ARM: dts: ls1021a: add sata node to dts

PATCH Superseded Yuantian.Tang at freescale.com 2 participants 2 messages Dec 2, 2015 – Dec 11, 2015 Device tree bindings

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Yuantian.Tang at freescale.com

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2015-12-02 07:16 UTC #0 lore raw

PATCH v3 1/1 ARM: dts: ls1021a: add sata node to dts

From: Tang Yuantian <[email protected]>

Added sata node to ls1021aqds and ls1021atwr board to support sata function.

Signed-off-by Tang Yuantian <[email protected]>

---
v3:
- refine the title and commit message
- added a status property so that sata can be controlled by board specific dts.
v2:
- put reg-names right after reg property

 arch/arm/boot/dts/ls1021a-qds.dts |  4 ++++
 arch/arm/boot/dts/ls1021a-twr.dts |  4 ++++
 arch/arm/boot/dts/ls1021a.dtsi    | 11 +++++++++++
 3 files changed, 19 insertions(+)

arch/arm/boot/dts/ls1021a-qds.dts +4 -0

index 0521e68..803cc54 100644
@@ -327,3 +327,7 @@
 &uart1 {
 	status = "okay";
 };
+
+&sata {
+	status = "okay";
+};

arch/arm/boot/dts/ls1021a-twr.dts +4 -0

index fbb89d1..62dec7c 100644
@@ -219,3 +219,7 @@
 &uart1 {
 	status = "okay";
 };
+
+&sata {
+	status = "okay";
+};

arch/arm/boot/dts/ls1021a.dtsi +11 -0

index 9430a99..da9bd7e 100644
@@ -143,6 +143,17 @@
 			status = "disabled";
 		};
 
+		sata: sata at 3200000 {
+			compatible = "fsl,ls1021a-ahci";
+			reg = <0x0 0x3200000 0x0 0x10000>,
+			      <0x0 0x20220520 0x0 0x4>;
+			reg-names = "ahci", "sata-ecc";
+			interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&platform_clk 1>;
+			dma-coherent;
+			status = "disabled";
+		};
+
 		scfg: scfg at 1570000 {
 			compatible = "fsl,ls1021a-scfg", "syscon";
 			reg = <0x0 0x1570000 0x0 0x10000>;

Signature · 1 line

2.1.0.27.g96db324

Shawn Guo

2015-12-11 14:41 UTC #1 lore raw

PATCH v3 1/1 ARM: dts: ls1021a: add sata node to dts

Quoted 24 lines · Yuantian.Tang at freescale.com

From: Tang Yuantian <[email protected]>
Added sata node to ls1021aqds and ls1021atwr board to support sata function.
Signed-off-by Tang Yuantian <[email protected]>
---
v3:
- refine the title and commit message
- added a status property so that sata can be controlled by board specific dts.
v2:
- put reg-names right after reg property
 arch/arm/boot/dts/ls1021a-qds.dts |  4 ++++
 arch/arm/boot/dts/ls1021a-twr.dts |  4 ++++
 arch/arm/boot/dts/ls1021a.dtsi    | 11 +++++++++++
 3 files changed, 19 insertions(+)
arch/arm/boot/dts/ls1021a-qds.dts +0 -0
index 0521e68..803cc54 100644

arch/arm/boot/dts/ls1021a-qds.dts line 333

Quoted 7 lines

arch/arm/boot/dts/ls1021a-qds.dts +4 -0

@@ -327,3 +327,7 @@
 &uart1 {
 	status = "okay";
 };
+
+&sata {
+	status = "okay";
+};

The labelled nodes are sorted alphabetically. Please keep the new addition sorted too.

arch/arm/boot/dts/ls1021a-twr.dts line 225

Quoted 12 lines

arch/arm/boot/dts/ls1021a-twr.dts +4 -0

index fbb89d1..62dec7c 100644
@@ -219,3 +219,7 @@
 &uart1 {
 	status = "okay";
 };
+
+&sata {
+	status = "okay";
+};

Ditto

Shawn

Quoted 26 lines

arch/arm/boot/dts/ls1021a.dtsi +11 -0

index 9430a99..da9bd7e 100644
@@ -143,6 +143,17 @@
 			status = "disabled";
 		};
 
+		sata: sata at 3200000 {
+			compatible = "fsl,ls1021a-ahci";
+			reg = <0x0 0x3200000 0x0 0x10000>,
+			      <0x0 0x20220520 0x0 0x4>;
+			reg-names = "ahci", "sata-ecc";
+			interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&platform_clk 1>;
+			dma-coherent;
+			status = "disabled";
+		};
+
 		scfg: scfg at 1570000 {
 			compatible = "fsl,ls1021a-scfg", "syscon";
 			reg = <0x0 0x1570000 0x0 0x10000>;

Signature · 1 line

2.1.0.27.g96db324