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arm64: dts: r8a7795: Add PSCI node

PATCH New Dirk Behme 6 participants 18 messages Dec 4, 2015 – Mar 16, 2016

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Device tree bindings SuperH Arm/RISC-V/Renesas architecture
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Dirk Behme

author
#0 lore raw

PATCH 1/3 arm64: dts: r8a7795: Add PSCI node

From: Gaku Inami <[email protected]>

Add PSCI node for r8a7795 SoC, and cpu node enable-method property is set to "psci".

Signed-off-by Gaku Inami <[email protected]>
Signed-off-by Takeshi Kihara <[email protected]>
Sigend-off-by Dirk Behme <[email protected]>

---
Note: This patch picked from

https://git.kernel.org/cgit/linux/kernel/git/horms/renesas-bsp.git/log/?h=v4.2/rcar-3.0.x

and rebased against

https://git.kernel.org/cgit/linux/kernel/git/geert/renesas-drivers.git/log/?h=topic/gen3-latest renesas-drivers-2015-12-01-v4.4-rc3

 arch/arm64/boot/dts/renesas/r8a7795.dtsi | 6 ++++++
 1 file changed, 6 insertions(+)
arch/arm64/boot/dts/renesas/r8a7795.dtsi +6 -0
index 816400c..5611597 100644
@@ -26,6 +26,11 @@
 		i2c6 = &i2c6;
 	};
 
+	psci {
+		compatible = "arm,psci-0.2";
+		method = "smc";
+	};
+
 	cpus {
 		#address-cells = <1>;
 		#size-cells = <0>;

@@ -35,6 +40,7 @@
 			compatible = "arm,cortex-a57", "arm,armv8";
 			reg = <0x0>;
 			device_type = "cpu";
+			enable-method = "psci";
 		};
 	};
Signature · 1 line
2.6.3
author
#1 lore raw

PATCH 2/3 arm64: dts: r8a7795: Add Cortex-A57 CPU cores

From: Gaku Inami <[email protected]>

Add Cortex-A57 CPU cores to r8a7795 SoC for a total of 4 x Cortex-A57.

Signed-off-by Gaku Inami <[email protected]>
Signed-off-by Takeshi Kihara <[email protected]>
Sigend-off-by Dirk Behme <[email protected]>

---

Note: This patch picked from

https://git.kernel.org/cgit/linux/kernel/git/horms/renesas-bsp.git/log/?h=v4.2/rcar-3.0.x

and rebased against

https://git.kernel.org/cgit/linux/kernel/git/geert/renesas-drivers.git/log/?h=topic/gen3-latest renesas-drivers-2015-12-01-v4.4-rc3

 arch/arm64/boot/dts/renesas/r8a7795.dtsi | 31 +++++++++++++++++++++++++------
 1 file changed, 25 insertions(+), 6 deletions(-)
arch/arm64/boot/dts/renesas/r8a7795.dtsi +25 -6
index 5611597..946a5bb 100644
@@ -35,13 +35,31 @@
 		#address-cells = <1>;
 		#size-cells = <0>;
 
-		/* 1 core only at this point */
 		a57_0: cpu at 0 {
 			compatible = "arm,cortex-a57", "arm,armv8";
 			reg = <0x0>;
 			device_type = "cpu";
 			enable-method = "psci";
 		};
+
+		a57_1: cpu at 1 {
+			compatible = "arm,cortex-a57","arm,armv8";
+			reg = <0x1>;
+			device_type = "cpu";
+			enable-method = "psci";
+		};
+		a57_2: cpu at 2 {
+			compatible = "arm,cortex-a57","arm,armv8";
+			reg = <0x2>;
+			device_type = "cpu";
+			enable-method = "psci";
+		};
+		a57_3: cpu at 3 {
+			compatible = "arm,cortex-a57","arm,armv8";
+			reg = <0x3>;
+			device_type = "cpu";
+			enable-method = "psci";
+		};
 	};
 
 	extal_clk: extal {

@@ -101,6 +119,7 @@
 	soc {
 		compatible = "simple-bus";
 		interrupt-parent = <&gic>;
+
 		#address-cells = <2>;
 		#size-cells = <2>;
 		ranges;

@@ -113,7 +132,7 @@
 			reg = <0x0 0xf1010000 0 0x1000>,
 			      <0x0 0xf1020000 0 0x2000>;
 			interrupts = <GIC_PPI 9
-					(GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>;
+					(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 		};
 
 		gpio0: gpio at e6050000 {

@@ -231,13 +250,13 @@
 		timer {
 			compatible = "arm,armv8-timer";
 			interrupts = <GIC_PPI 13
-					(GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
+					(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 				     <GIC_PPI 14
-					(GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
+					(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 				     <GIC_PPI 11
-					(GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
+					(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 				     <GIC_PPI 10
-					(GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;
+					(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
 		};
 
 		cpg: clock-controller at e6150000 {
Signature · 1 line
2.6.3
#3 lore raw

PATCH 2/3 arm64: dts: r8a7795: Add Cortex-A57 CPU cores

Quoted 10 lines · Simon Horman
Quoted 7 lines · Dirk Behme

From: Gaku Inami <[email protected]>

Add Cortex-A57 CPU cores to r8a7795 SoC for a total of 4 x Cortex-A57.

Signed-off-by Gaku Inami <[email protected]>
Signed-off-by Takeshi Kihara <[email protected]>
Sigend-off-by Dirk Behme <[email protected]>

Thanks, I have queued this up for v4.5.

I meant to test this earlier but somehow it slopped my mind.

With this patch applied I still only see one CPU brought up whereas I was expecting 4. Are more patches needed in order to get more CPUs operating?

I am using renesas-devel-20151214-v4.4-rc5 + the cpg-mmsr driver (v6). I built the kernel using the defconfig.

author
#4 lore raw

PATCH 2/3 arm64: dts: r8a7795: Add Cortex-A57 CPU cores

Quoted 10 lines · Simon Horman
Quoted 9 lines · Simon Horman
Quoted 7 lines · Dirk Behme

From: Gaku Inami <[email protected]>

Add Cortex-A57 CPU cores to r8a7795 SoC for a total of 4 x Cortex-A57.

Signed-off-by Gaku Inami <[email protected]>
Signed-off-by Takeshi Kihara <[email protected]>
Sigend-off-by Dirk Behme <[email protected]>
Quoted 7 lines
Quoted 1 line

Thanks, I have queued this up for v4.5.

I meant to test this earlier but somehow it slopped my mind.

With this patch applied I still only see one CPU brought up whereas I was expecting 4. Are more patches needed in order to get more CPUs operating?

Hmm, I don't think so (?).

I tested this with

https://github.com/dirkbehme/linux-renesas-rcar-gen3/commits/dirk/gen3-latest-update

and got (including the A53 patch)

...
ASID allocator initialised with 65536 entries

Detected PIPT I-cache on CPU1

CPU1: Booted secondary processor [411fd073]

Detected PIPT I-cache on CPU2

CPU2: Booted secondary processor [411fd073]

Detected PIPT I-cache on CPU3

CPU3: Booted secondary processor [411fd073]

Detected VIPT I-cache on CPU4

CPU features: enabling workaround for ARM erratum 845719

CPU4: Booted secondary processor [410fd034]

Detected VIPT I-cache on CPU5

CPU5: Booted secondary processor [410fd034]

Detected VIPT I-cache on CPU6

CPU6: Booted secondary processor [410fd034]

Detected VIPT I-cache on CPU7

CPU7: Booted secondary processor [410fd034]

Brought up 8 CPUs

SMP: Total of 8 processors activated.

CPU: All CPU(s) started at EL1
...

This is based on last weeks renesas-drivers-2015-12-08-v4.4-rc4 and besides the patches for SDHI/eMMC I don't think it contains anything additional regarding the number of CPU cores.

Best regards

Dirk

#5 lore raw

PATCH 2/3 arm64: dts: r8a7795: Add Cortex-A57 CPU cores

In reply to Simon Horman

Hi Simon,

Quoted 12 lines · Simon Horman
Quoted 10 lines · Simon Horman
Quoted 7 lines · Dirk Behme

From: Gaku Inami <[email protected]>

Add Cortex-A57 CPU cores to r8a7795 SoC for a total of 4 x Cortex-A57.

Signed-off-by Gaku Inami <[email protected]>
Signed-off-by Takeshi Kihara <[email protected]>
Sigend-off-by Dirk Behme <[email protected]>

Thanks, I have queued this up for v4.5.

Quoted 8 lines

I meant to test this earlier but somehow it slopped my mind.

With this patch applied I still only see one CPU brought up whereas I was expecting 4. Are more patches needed in order to get more CPUs operating?

I am using renesas-devel-20151214-v4.4-rc5 + the cpg-mmsr driver (v6). I built the kernel using the defconfig.

I can confirm I saw 4 CPUs online as soon as I had merged renesas-devel containing the above change into my tree (which was based on renesas-drivers-2015-12-08-v4.4-rc4 at that time).

I was surprised to see it was that simple to enable the 3 other cores ;-)

Gr{oetje,eeting}s,

Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert at linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds

maintainer
#6 lore raw

PATCH 2/3 arm64: dts: r8a7795: Add Cortex-A57 CPU cores

In reply to Simon Horman

Hi Simon,

Quoted 10 lines · Simon Horman
Quoted 7 lines · Dirk Behme

From: Gaku Inami <[email protected]>

Add Cortex-A57 CPU cores to r8a7795 SoC for a total of 4 x Cortex-A57.

Signed-off-by Gaku Inami <[email protected]>
Signed-off-by Takeshi Kihara <[email protected]>
Sigend-off-by Dirk Behme <[email protected]>

Thanks, I have queued this up for v4.5.

Thanks. May I ask if CPU hotplug is known to work? Also, which version of the boot loader stack is required?

Best,

/ magnus

author
#7 lore raw

PATCH 2/3 arm64: dts: r8a7795: Add Cortex-A57 CPU cores

Quoted 8 lines · Magnus Damm

Hi Simon,

Quoted 5 lines · Simon Horman
Quoted 4 lines · Dirk Behme

From: Gaku Inami <[email protected]>

Add Cortex-A57 CPU cores to r8a7795 SoC for a total of 4 x Cortex-A57.

Quoted 7 lines
Quoted 5 lines
Quoted 3 lines
Signed-off-by Gaku Inami <[email protected]>
Signed-off-by Takeshi Kihara <[email protected]>
Sigend-off-by Dirk Behme <[email protected]>

Thanks, I have queued this up for v4.5.

Thanks. May I ask if CPU hotplug is known to work?

I didn't test that.

Quoted 2 lines

Also, which version
of the boot loader stack is required?

I've the U-Boot / boot loader stack from BSP v3.0.2 on the board. I haven't tested v3.0.3, yet.

Best regards

Dirk

maintainer
#8 lore raw

PATCH 2/3 arm64: dts: r8a7795: Add Cortex-A57 CPU cores

Hi Dirk,

Quoted 17 lines · Dirk Behme
Quoted 16 lines · Magnus Damm

Hi Simon,

Quoted 12 lines · Simon Horman
Quoted 8 lines · Dirk Behme

From: Gaku Inami <[email protected]>

Add Cortex-A57 CPU cores to r8a7795 SoC for a total of 4 x Cortex-A57.

Signed-off-by Gaku Inami <[email protected]>
Signed-off-by Takeshi Kihara <[email protected]>
Sigend-off-by Dirk Behme <[email protected]>
Quoted 8 lines
Quoted 4 lines
Quoted 1 line

Thanks, I have queued this up for v4.5.

Thanks. May I ask if CPU hotplug is known to work?

I didn't test that.

Ok, no worries. I feel that there are various CPU related features that need a bit of testing to make sure support is stable enough to enable without causing issues for other on-going development.

CPU Hotplug is one of those, another is kernel command line options like maxcpus, and kexec would be good to have working as well. To make things a bit more complicated, there is a rather complicated software stack with trusted code installed by the boot loader, so there is a dependency on that as well. On earlier SoCs from previous generations there were issues with shared reset vectors and a watchdog, so SMP support may affect watchdog too...

Quoted 5 lines
Quoted 2 lines

Also, which version
of the boot loader stack is required?

I've the U-Boot / boot loader stack from BSP v3.0.2 on the board. I haven't tested v3.0.3, yet.

Thanks for sharing!

Cheers,

/ magnus

#9 lore raw

PATCH 2/3 arm64: dts: r8a7795: Add Cortex-A57 CPU cores

In reply to Dirk Behme

Hi Dirk,

Quoted 13 lines · Dirk Behme
Quoted 12 lines · Magnus Damm

Hi Simon,

Quoted 9 lines · Simon Horman
Quoted 7 lines · Dirk Behme

From: Gaku Inami <[email protected]>

Add Cortex-A57 CPU cores to r8a7795 SoC for a total of 4 x Cortex-A57.

Signed-off-by Gaku Inami <[email protected]>
Signed-off-by Takeshi Kihara <[email protected]>
Sigend-off-by Dirk Behme <[email protected]>
Quoted 6 lines
Quoted 3 lines
Quoted 1 line

Thanks, I have queued this up for v4.5.

Thanks. May I ask if CPU hotplug is known to work?

I didn't test that.

As a follow-up I am wondering if you subsequently observed CPU hotplug working. My recent testing on v4.5 indicates that it isn't working in my environment. It would be quite valuable to know if it has ever been known to work.

Quoted 6 lines
Quoted 2 lines

Also, which version
of the boot loader stack is required?

I've the U-Boot / boot loader stack from BSP v3.0.2 on the board. I haven't tested v3.0.3, yet.

For reference my environment is as follows:

    NOTICE:  BL2: R-Car H3 Loader Rev.1.0.1
    NOTICE:  BL2: DDR1600(rev.0.10)
    NOTICE:  BL2: DRAM Split is 4ch
    NOTICE:  BL2: QoS is Gfx Oriented(rev.0.24A)
    NOTICE:  BL2: v1.1(release):41099f4
    NOTICE:  BL2: Built : 11:47:26, Nov 19 2015
    NOTICE:  BL2: Normal boot
    NOTICE:  BL2: memdrv_block_read dst=0xe630e0b0 src=0x8180000 len=36(0x24)
    NOTICE:  BL2: memdrv_block_read dst=0x43f00000 src=0x8180400 len=3072(0xc00)
    NOTICE:  BL2: memdrv_block_read dst=0x44000000 src=0x81c0000 len=65536(0x10000)
    NOTICE:  BL2: memdrv_block_read dst=0x44100000 src=0x8200000 len=524288(0x80000)
    NOTICE:  BL2: memdrv_block_read dst=0x49000000 src=0x8640000 len=1048576(0x100000)
    U-Boot 2015.04 (Nov 19 2015 - 11:47:49)

    CPU: Renesas Electronics CPU rev 1.0
    Board: Salvator-X
    DRAM:  896 MiB
    MMC:   sh-sdhi: 0, sh-sdhi: 1, sh-sdhi: 2
    In:    serial
    Out:   serial
    Err:   serial
    Net:   ravb
#10 lore raw

PATCH 2/3 arm64: dts: r8a7795: Add Cortex-A57 CPU cores

Hi Simon, Dirk, Magnus,

Quoted 21 lines · Simon Horman

Hi Dirk,

Quoted 18 lines · Dirk Behme
Quoted 15 lines · Magnus Damm

Hi Simon,

Quoted 10 lines · Simon Horman
Quoted 7 lines · Dirk Behme

From: Gaku Inami <[email protected]>

Add Cortex-A57 CPU cores to r8a7795 SoC for a total of 4 x Cortex-A57.

Signed-off-by Gaku Inami <[email protected]>
Signed-off-by Takeshi Kihara <[email protected]>
Sigend-off-by Dirk Behme <[email protected]>

Thanks, I have queued this up for v4.5.

Thanks. May I ask if CPU hotplug is known to work?

Quoted 9 lines
Quoted 1 line

I didn't test that.

As a follow-up I am wondering if you subsequently observed CPU hotplug working. My recent testing on v4.5 indicates that it isn't working in my environment. It would be quite valuable to know if it has ever been known to work.

Quoted 2 lines
Quoted 2 lines

Also, which version
of the boot loader stack is required?

Yes. CPUHotplug will be supported in boot loader stack released by Dec 2015 and later.

Quoted 35 lines
Quoted 3 lines

I've the U-Boot / boot loader stack from BSP v3.0.2 on the board. I haven't tested v3.0.3, yet.

For reference my environment is as follows:

     NOTICE:  BL2: R-Car H3 Loader Rev.1.0.1
     NOTICE:  BL2: DDR1600(rev.0.10)
     NOTICE:  BL2: DRAM Split is 4ch
     NOTICE:  BL2: QoS is Gfx Oriented(rev.0.24A)
     NOTICE:  BL2: v1.1(release):41099f4
     NOTICE:  BL2: Built : 11:47:26, Nov 19 2015
     NOTICE:  BL2: Normal boot
     NOTICE:  BL2: memdrv_block_read dst=0xe630e0b0 src=0x8180000 len=36(0x24)
     NOTICE:  BL2: memdrv_block_read dst=0x43f00000 src=0x8180400 len=3072(0xc00)
     NOTICE:  BL2: memdrv_block_read dst=0x44000000 src=0x81c0000 len=65536(0x10000)
     NOTICE:  BL2: memdrv_block_read dst=0x44100000 src=0x8200000 len=524288(0x80000)
     NOTICE:  BL2: memdrv_block_read dst=0x49000000 src=0x8640000 len=1048576(0x100000)
     U-Boot 2015.04 (Nov 19 2015 - 11:47:49)

     CPU: Renesas Electronics CPU rev 1.0
     Board: Salvator-X
     DRAM:  896 MiB
     MMC:   sh-sdhi: 0, sh-sdhi: 1, sh-sdhi: 2
     In:    serial
     Out:   serial
     Err:   serial
     Net:   ravb

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Signature · 2 lines
Best regards,
KHIEM Nguyen
#11 lore raw

PATCH 2/3 arm64: dts: r8a7795: Add Cortex-A57 CPU cores

Quoted 31 lines · Khiem Nguyen

Hi Simon, Dirk, Magnus,

Quoted 28 lines · Simon Horman

Hi Dirk,

Quoted 13 lines · Dirk Behme
Quoted 12 lines · Magnus Damm

Hi Simon,

Quoted 9 lines · Simon Horman
Quoted 7 lines · Dirk Behme

From: Gaku Inami <[email protected]>

Add Cortex-A57 CPU cores to r8a7795 SoC for a total of 4 x Cortex-A57.

Signed-off-by Gaku Inami <[email protected]>
Signed-off-by Takeshi Kihara <[email protected]>
Sigend-off-by Dirk Behme <[email protected]>
Quoted 6 lines
Quoted 3 lines
Quoted 1 line

Thanks, I have queued this up for v4.5.

Thanks. May I ask if CPU hotplug is known to work?

I didn't test that.

As a follow-up I am wondering if you subsequently observed CPU hotplug working. My recent testing on v4.5 indicates that it isn't working in my environment. It would be quite valuable to know if it has ever been known to work.

Quoted 5 lines
Quoted 2 lines
Quoted 2 lines
Quoted 2 lines

Also, which version
of the boot loader stack is required?

Yes. CPUHotplug will be supported in boot loader stack released by Dec 2015 and later.

Thanks, that sounds positive.

As Dec 2015 has already passed I wonder if a boot loader stack that supports CPU Hotplug is currently available. Perhaps internally? If so I think it would be good to verify v4.5.

Quoted 40 lines
Quoted 34 lines
Quoted 2 lines

I've the U-Boot / boot loader stack from BSP v3.0.2 on the board. I haven't tested v3.0.3, yet.

For reference my environment is as follows:

    NOTICE:  BL2: R-Car H3 Loader Rev.1.0.1
    NOTICE:  BL2: DDR1600(rev.0.10)
    NOTICE:  BL2: DRAM Split is 4ch
    NOTICE:  BL2: QoS is Gfx Oriented(rev.0.24A)
    NOTICE:  BL2: v1.1(release):41099f4
    NOTICE:  BL2: Built : 11:47:26, Nov 19 2015
    NOTICE:  BL2: Normal boot
    NOTICE:  BL2: memdrv_block_read dst=0xe630e0b0 src=0x8180000 len=36(0x24)
    NOTICE:  BL2: memdrv_block_read dst=0x43f00000 src=0x8180400 len=3072(0xc00)
    NOTICE:  BL2: memdrv_block_read dst=0x44000000 src=0x81c0000 len=65536(0x10000)
    NOTICE:  BL2: memdrv_block_read dst=0x44100000 src=0x8200000 len=524288(0x80000)
    NOTICE:  BL2: memdrv_block_read dst=0x49000000 src=0x8640000 len=1048576(0x100000)
    U-Boot 2015.04 (Nov 19 2015 - 11:47:49)

    CPU: Renesas Electronics CPU rev 1.0
    Board: Salvator-X
    DRAM:  896 MiB
    MMC:   sh-sdhi: 0, sh-sdhi: 1, sh-sdhi: 2
    In:    serial
    Out:   serial
    Err:   serial
    Net:   ravb

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Signature · 2 lines
Best regards,
KHIEM Nguyen
author
#12 lore raw

PATCH 3/3 arm64: dts: r8a7795: Add pmu device nodes

In reply to Dirk Behme

From: Yoshifumi Hosoya <[email protected]>

Enabling the performance monitor unit on r8a7795.

Signed-off-by Masaru Nagai <[email protected]>
Signed-off-by Yoshifumi Hosoya <[email protected]>
Sigend-off-by Dirk Behme <[email protected]>

---
Note: This patch picked from

https://git.kernel.org/cgit/linux/kernel/git/horms/renesas-bsp.git/log/?h=v4.2/rcar-3.0.x

and rebased against

https://git.kernel.org/cgit/linux/kernel/git/geert/renesas-drivers.git/log/?h=topic/gen3-latest renesas-drivers-2015-12-01-v4.4-rc3

 arch/arm64/boot/dts/renesas/r8a7795.dtsi | 12 ++++++++++++
 1 file changed, 12 insertions(+)
arch/arm64/boot/dts/renesas/r8a7795.dtsi +12 -0
index 946a5bb..8113b71 100644
@@ -247,6 +247,18 @@
 			power-domains = <&cpg>;
 		};
 
+		pmu {
+			compatible = "arm,armv8-pmuv3";
+			interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-affinity = <&a57_0>,
+					     <&a57_1>,
+					     <&a57_2>,
+					     <&a57_3>;
+		};
+
 		timer {
 			compatible = "arm,armv8-timer";
 			interrupts = <GIC_PPI 13
Signature · 1 line
2.6.3
#14 lore raw

PATCH 3/3 arm64: dts: r8a7795: Add pmu device nodes

In reply to Dirk Behme
Quoted 24 lines · Dirk Behme

From: Yoshifumi Hosoya <[email protected]>

Enabling the performance monitor unit on r8a7795.

Signed-off-by Masaru Nagai <[email protected]>
Signed-off-by Yoshifumi Hosoya <[email protected]>
Sigend-off-by Dirk Behme <[email protected]>

---
Note: This patch picked from

https://git.kernel.org/cgit/linux/kernel/git/horms/renesas-bsp.git/log/?h=v4.2/rcar-3.0.x

and rebased against

https://git.kernel.org/cgit/linux/kernel/git/geert/renesas-drivers.git/log/?h=topic/gen3-latest renesas-drivers-2015-12-01-v4.4-rc3

  arch/arm64/boot/dts/renesas/r8a7795.dtsi | 12 ++++++++++++
  1 file changed, 12 insertions(+)
arch/arm64/boot/dts/renesas/r8a7795.dtsi +0 -0
index 946a5bb..8113b71 100644

arch/arm64/boot/dts/renesas/r8a7795.dtsi line 251

Quoted 5 lines
arch/arm64/boot/dts/renesas/r8a7795.dtsi +2 -0
@@ -247,6 +247,18 @@
  			power-domains = <&cpg>;
  		};
 
+		pmu {
+			compatible = "arm,armv8-pmuv3";

You can add more specific compatible "arm,cortex-a57-pmu" if it's Cortex A57.

Signature · 2 lines
Regards,
Sudeep
#15 lore raw

PATCH 3/3 arm64: dts: r8a7795: Add pmu device nodes

Quoted 33 lines · Sudeep Holla
Quoted 32 lines · Dirk Behme

From: Yoshifumi Hosoya <[email protected]>

Enabling the performance monitor unit on r8a7795.

Signed-off-by Masaru Nagai <[email protected]>
Signed-off-by Yoshifumi Hosoya <[email protected]>
Sigend-off-by Dirk Behme <[email protected]>

---
Note: This patch picked from

https://git.kernel.org/cgit/linux/kernel/git/horms/renesas-bsp.git/log/?h=v4.2/rcar-3.0.x

and rebased against

https://git.kernel.org/cgit/linux/kernel/git/geert/renesas-drivers.git/log/?h=topic/gen3-latest
renesas-drivers-2015-12-01-v4.4-rc3

  arch/arm64/boot/dts/renesas/r8a7795.dtsi | 12 ++++++++++++
  1 file changed, 12 insertions(+)
arch/arm64/boot/dts/renesas/r8a7795.dtsi +0 -0
index 946a5bb..8113b71 100644
@@ -247,6 +247,18 @@
                        power-domains = <&cpg>;
                };
Quoted 6 lines

arch/arm64/boot/dts/renesas/r8a7795.dtsi line 251

Quoted 2 lines
arch/arm64/boot/dts/renesas/r8a7795.dtsi +2 -0
+               pmu {
+                       compatible = "arm,armv8-pmuv3";

You can add more specific compatible "arm,cortex-a57-pmu" if it's Cortex A57.

Except that one is not documented.

Oh, it is. Someone mistyped the commas. Patch sent.

Gr{oetje,eeting}s,

Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert at linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds

#16 lore raw

PATCH 3/3 arm64: dts: r8a7795: Add pmu device nodes

Quoted 41 lines · Geert Uytterhoeven
Quoted 33 lines · Sudeep Holla
Quoted 32 lines · Dirk Behme

From: Yoshifumi Hosoya <[email protected]>

Enabling the performance monitor unit on r8a7795.

Signed-off-by Masaru Nagai <[email protected]>
Signed-off-by Yoshifumi Hosoya <[email protected]>
Sigend-off-by Dirk Behme <[email protected]>

---
Note: This patch picked from

https://git.kernel.org/cgit/linux/kernel/git/horms/renesas-bsp.git/log/?h=v4.2/rcar-3.0.x

and rebased against

https://git.kernel.org/cgit/linux/kernel/git/geert/renesas-drivers.git/log/?h=topic/gen3-latest
renesas-drivers-2015-12-01-v4.4-rc3

   arch/arm64/boot/dts/renesas/r8a7795.dtsi | 12 ++++++++++++
   1 file changed, 12 insertions(+)
arch/arm64/boot/dts/renesas/r8a7795.dtsi +0 -0
index 946a5bb..8113b71 100644
@@ -247,6 +247,18 @@
                         power-domains = <&cpg>;
                 };
Quoted 6 lines

arch/arm64/boot/dts/renesas/r8a7795.dtsi line 251

Quoted 2 lines
arch/arm64/boot/dts/renesas/r8a7795.dtsi +2 -0
+               pmu {
+                       compatible = "arm,armv8-pmuv3";

You can add more specific compatible "arm,cortex-a57-pmu" if it's Cortex A57.

Quoted 4 lines

Except that one is not documented.

Oh, it is. Someone mistyped the commas. Patch sent.

Ah right, nice catch. Thanks for the patch.

Signature · 2 lines
Regards,
Sudeep