clk: ti: Add support for dm814x ADPLL
Subsystems (3)
PATCH v4 1/1 clk: ti: Add support for dm814x ADPLL
On dm814x we have 13 ADPLLs with 3 to 4 outputs on each. The ADPLLs have several dividers and muxes controlled by a shared control register for each PLL.
Note that for the clocks to work as device drivers for booting on dm814x, this patch depends on "ARM: OMAP2+: Change core_initcall levels to postcore_initcall".
Also note that this patch does not implement clk_set_rate for the PLL, that will be posted later on when available.
---
If no more comments, Tero can you please apply into an immutable branch against v4.4-rc1 that I can merge in too?
Changes since v3:
- We want to create the clkdev entry for all clocks, not just outputs
- ti_adpll_wait_lock loops did not do the right thing
- We want to use CLK_GET_RATE_NOCACHE in ti_adpll_init_dco
--- .../devicetree/bindings/clock/ti/adpll.txt | 43 + drivers/clk/Kconfig | 1 + drivers/clk/ti/Kconfig | 6 + drivers/clk/ti/Makefile | 2 + drivers/clk/ti/adpll.c | 1004 ++++++++++++++++++++ drivers/clk/ti/clk-814x.c | 53 ++ 6 files changed, 1109 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/ti/adpll.txt create mode 100644 drivers/clk/ti/Kconfig create mode 100644 drivers/clk/ti/adpll.c
Documentation/devicetree/bindings/clock/ti/adpll.txt new file +43 -0
@@ -0,0 +1,43 @@ +Binding for Texas Instruments ADPLL clock. + +Binding status: Unstable - ABI compatibility may be broken in the future + +This binding uses the common clock binding[1]. It assumes a +register-mapped ADPLL with two to three selectable input clocks +and three to four children.. + +[1] Documentation/devicetree/bindings/clock/clock-bindings.txt + +Required properties: +- compatible : shall be one of "ti,dm814-adpll-s-clock" or + "ti,dm814-adpll-lj-clock" depending on the type of the ADPLL +- #clock-cells : from common clock binding; shall be set to 0. +- clocks : link phandles of parent clocks clkinp and clkinpulow, note + that the adpll-s-clock also has an optional clkinphif +- reg : address and length of the register set for controlling the ADPLL. + +Examples: + adpll_mpu_ck: adpll at 40 { + #clock-cells = <1>; + compatible = "ti,dm814-adpll-s-clock"; + reg = <0x40 0x40>; + clocks = <&devosc_ck &devosc_ck &devosc_ck>; + clock-names = "clkinp", "clkinpulow", "clkinphif"; + clock-indices = <0>, <1>, <2>, <3>; + clock-output-names = "481c5040.adpll.dcoclkldo", + "481c5040.adpll.clkout", + "481c5040.adpll.clkoutx2", + "481c5040.adpll.clkouthif"; + }; + + adpll_dsp_ck: adpll at 80 { + #clock-cells = <1>; + compatible = "ti,dm814-adpll-lj-clock"; + reg = <0x80 0x30>; + clocks = <&devosc_ck &devosc_ck>; + clock-names = "clkinp", "clkinpulow"; + clock-indices = <0>, <1>, <2>; + clock-output-names = "481c5080.adpll.dcoclkldo", + "481c5080.adpll.clkout", + "481c5080.adpll.clkoutldo"; + };
drivers/clk/Kconfig +1 -0
@@ -190,6 +190,7 @@ config COMMON_CLK_CDCE706 source "drivers/clk/bcm/Kconfig" source "drivers/clk/hisilicon/Kconfig" +source "drivers/clk/ti/Kconfig" source "drivers/clk/qcom/Kconfig" endmenu
drivers/clk/ti/Kconfig new file +6 -0
@@ -0,0 +1,6 @@ +config COMMON_CLK_TI_ADPLL + tristate "Clock driver for dm814x ADPLL" + depends on ARCH_OMAP2PLUS + default y if SOC_TI81XX + ---help--- + ADPLL clock driver for the dm814x SoC using common clock framework.
drivers/clk/ti/Makefile +2 -0
@@ -18,3 +18,5 @@ obj-$(CONFIG_SOC_AM43XX) += $(clk-common) dpll3xxx.o clk-43xx.o ifdef CONFIG_ATAGS obj-$(CONFIG_ARCH_OMAP3) += clk-3xxx-legacy.o endif + +obj-$(CONFIG_COMMON_CLK_TI_ADPLL) += adpll.o
drivers/clk/ti/adpll.c new file +1004 -0
1,004 lines not on this page · raw message
drivers/clk/ti/clk-814x.c +53 -0
72 lines not on this page · raw message
Signature · 1 line
2.6.2
PATCH v4 1/1 clk: ti: Add support for dm814x ADPLL
Quoted 17 lines · Tony Lindgren
On dm814x we have 13 ADPLLs with 3 to 4 outputs on each. The ADPLLs have several dividers and muxes controlled by a shared control register for each PLL.
Note that for the clocks to work as device drivers for booting on dm814x, this patch depends on "ARM: OMAP2+: Change
core_initcalllevels topostcore_initcall".Also note that this patch does not implement
clk_set_ratefor the PLL, that will be posted later on when available.Cc Michael Turquette <[email protected]>Cc Stephen Boyd <[email protected]>Cc Tero Kristo <[email protected]>Signed-off-by Tony Lindgren <[email protected]>---
Quoted 8 lines
If no more comments, Tero can you please apply into an immutable branch against v4.4-rc1 that I can merge in too?
Changes since v3:
- We want to create the clkdev entry for all clocks, not just outputs
-ti_adpll_wait_lockloops did not do the right thing
- We want to useCLK_GET_RATE_NOCACHEinti_adpll_init_dco
I have just one comment below still, once that is addressed:
Stephen / Michael, can you pick this up for next merge? I don't have anything else coming for the window this time, and I am probably going to be on vacation just nicely to not be able to push anything anyway.
<snip>
drivers/clk/ti/adpll.c line 600
Quoted 10 lines
drivers/clk/ti/adpll.c new file +10
-0+ +/* Warn if clkout or clkoutx2 try to set unavailable parent */ +static int ti_adpll_clkout_set_parent (struct clk_hw *hw,u8 index) +{ +struct ti_adpll_clkout_data *co =to_clkout (hw); +struct ti_adpll_data *d = co->adpll; + +if (ti_adpll_clock_is_bypass (d) != index) +return -EAGAIN ; +
I think this part is still somewhat weird. You are not doing anything useful in this function, so do you need to implement it at all? Just returning -EINVAL always might work also. EAGAIN is wrong return value anyway as it can pretty much never succeed.
-Tero
Quoted 3 lines
drivers/clk/ti/adpll.c new file +3
-0+return 0 ; +} +
<snip>
PATCH v4 1/1 clk: ti: Add support for dm814x ADPLL
Quoted 27 lines · Tero Kristo
Quoted 17 lines · Tony Lindgren
On dm814x we have 13 ADPLLs with 3 to 4 outputs on each. The ADPLLs have several dividers and muxes controlled by a shared control register for each PLL.
Note that for the clocks to work as device drivers for booting on dm814x, this patch depends on "ARM: OMAP2+: Change
core_initcalllevels topostcore_initcall".Also note that this patch does not implement
clk_set_ratefor the PLL, that will be posted later on when available.Cc Michael Turquette <[email protected]>Cc Stephen Boyd <[email protected]>Cc Tero Kristo <[email protected]>Signed-off-by Tony Lindgren <[email protected]>---
Quoted 8 lines
If no more comments, Tero can you please apply into an immutable branch against v4.4-rc1 that I can merge in too?
Changes since v3:
- We want to create the clkdev entry for all clocks, not just outputs
-ti_adpll_wait_lockloops did not do the right thing
- We want to useCLK_GET_RATE_NOCACHEinti_adpll_init_dco
Quoted 7 lines
I have just one comment below still, once that is addressed:
Conditionally-acked-by Tero Kristo <[email protected]>Stephen / Michael, can you pick this up for next merge? I don't have anything else coming for the window this time, and I am probably going to be on vacation just nicely to not be able to push anything anyway.
Also, I managed to remove the dependency to the dts changes. So there's no longer any need to set up an immutable branch for this patch.
Quoted 17 lines
<snip>
drivers/clk/ti/adpll.c line 600
Quoted 10 lines
drivers/clk/ti/adpll.c new file +10
-0+ +/* Warn if clkout or clkoutx2 try to set unavailable parent */ +static int ti_adpll_clkout_set_parent (struct clk_hw *hw,u8 index) +{ +struct ti_adpll_clkout_data *co =to_clkout (hw); +struct ti_adpll_data *d = co->adpll; + +if (ti_adpll_clock_is_bypass (d) != index) +return -EAGAIN ; +I think this part is still somewhat weird. You are not doing anything useful in this function, so do you need to implement it at all? Just returning
-EINVALalways might work also. EAGAIN is wrong return value anyway as it can pretty much never succeed.
OK thanks sounds good to me, I'll check it this after lunch.
Also noticed the do_div should be div64_u64 so v5 coming later today.
Regards,
Tony
PATCH v4 1/1 clk: ti: Add support for dm814x ADPLL
Quoted 30 lines · Tony Lindgren
Quoted 29 lines · Tero Kristo
Quoted 17 lines · Tony Lindgren
On dm814x we have 13 ADPLLs with 3 to 4 outputs on each. The ADPLLs have several dividers and muxes controlled by a shared control register for each PLL.
Note that for the clocks to work as device drivers for booting on dm814x, this patch depends on "ARM: OMAP2+: Change
core_initcalllevels topostcore_initcall".Also note that this patch does not implement
clk_set_ratefor the PLL, that will be posted later on when available.Cc Michael Turquette <[email protected]>Cc Stephen Boyd <[email protected]>Cc Tero Kristo <[email protected]>Signed-off-by Tony Lindgren <[email protected]>---
Quoted 8 lines
If no more comments, Tero can you please apply into an immutable branch against v4.4-rc1 that I can merge in too?
Changes since v3:
- We want to create the clkdev entry for all clocks, not just outputs
-ti_adpll_wait_lockloops did not do the right thing
- We want to useCLK_GET_RATE_NOCACHEinti_adpll_init_dcoI have just one comment below still, once that is addressed:
Quoted 8 lines
Quoted 5 lines
Conditionally-acked-by Tero Kristo <[email protected]>Stephen / Michael, can you pick this up for next merge? I don't have anything else coming for the window this time, and I am probably going to be on vacation just nicely to not be able to push anything anyway.
Also, I managed to remove the dependency to the dts changes. So there's no longer any need to set up an immutable branch for this patch.
Can you split the binding description into a separate patch and send it to the dt mailing list? Feel free to add my Ack to it.
Stephen and I are trying to not take that stuff anymore.
Regards,
Mike
Quoted 27 lines
Quoted 18 lines
<snip>
drivers/clk/ti/adpll.c line 600
Quoted 10 lines
drivers/clk/ti/adpll.c new file +10
-0+ +/* Warn if clkout or clkoutx2 try to set unavailable parent */ +static int ti_adpll_clkout_set_parent (struct clk_hw *hw,u8 index) +{ +struct ti_adpll_clkout_data *co =to_clkout (hw); +struct ti_adpll_data *d = co->adpll; + +if (ti_adpll_clock_is_bypass (d) != index) +return -EAGAIN ; +I think this part is still somewhat weird. You are not doing anything useful in this function, so do you need to implement it at all? Just returning
-EINVALalways might work also. EAGAIN is wrong return value anyway as it can pretty much never succeed.OK thanks sounds good to me, I'll check it this after lunch.
Also noticed the
do_divshould bediv64_u64so v5 coming later today.Regards,
Tony
PATCH v4 1/1 clk: ti: Add support for dm814x ADPLL
Quoted 37 lines · Michael Turquette
Quoted 36 lines · Tony Lindgren
Quoted 34 lines · Tero Kristo
Quoted 17 lines · Tony Lindgren
On dm814x we have 13 ADPLLs with 3 to 4 outputs on each. The ADPLLs have several dividers and muxes controlled by a shared control register for each PLL.
Note that for the clocks to work as device drivers for booting on dm814x, this patch depends on "ARM: OMAP2+: Change
core_initcalllevels topostcore_initcall".Also note that this patch does not implement
clk_set_ratefor the PLL, that will be posted later on when available.Cc Michael Turquette <[email protected]>Cc Stephen Boyd <[email protected]>Cc Tero Kristo <[email protected]>Signed-off-by Tony Lindgren <[email protected]>---
Quoted 8 lines
If no more comments, Tero can you please apply into an immutable branch against v4.4-rc1 that I can merge in too?
Changes since v3:
- We want to create the clkdev entry for all clocks, not just outputs
-ti_adpll_wait_lockloops did not do the right thing
- We want to useCLK_GET_RATE_NOCACHEinti_adpll_init_dcoI have just one comment below still, once that is addressed:
Conditionally-acked-by Tero Kristo <[email protected]>Stephen / Michael, can you pick this up for next merge? I don't have anything else coming for the window this time, and I am probably going to be on vacation just nicely to not be able to push anything anyway.
Quoted 5 lines
Quoted 2 lines
Also, I managed to remove the dependency to the dts changes. So there's no longer any need to set up an immutable branch for this patch.
Can you split the binding description into a separate patch and send it to the dt mailing list? Feel free to add my Ack to it.
OK will do thanks.
Quoted 1 line
Stephen and I are trying to not take that stuff anymore.
Sure, no problem.
Regards,
Tony