mips: add base support for atheros ath79 based SOCs

This patch enable work for ar933x SOC, tested on ar9331 board.

Signed-off-by Wills Wang <[email protected]>

arch/mips/config.mk +0 -0

 PLATFORM_CPPFLAGS += $(cpuflags-y)
 
 PLATFORM_CPPFLAGS += -D__MIPS__

(quoted diff) +0 -0

b/arch/mips/mach-ath79/ar933x/ddr_tap.S new file mode 100644 index 0000000..18c57de

arch/mips/mach-ath79/ar933x/ddr_tap.S new file +33 -0

@@ -0,0 +1,268 @@
+/*
+ * (C) Copyright 2015
+ * Wills Wang, <[email protected]>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <config.h>
+#include <asm/asm.h>
+#include <asm/regdef.h>
+#include <asm/mipsregs.h>
+#include <asm/addrspace.h>
+#include <asm/arch/ar71xx_regs.h>
+
+#define DRAM_K0(x)      KSEG0ADDR(x)
+#define DRAM_K1(x)      KSEG1ADDR(x)
+
+	.text
+	.set noreorder
+
+LEAF(ddr_tap_init)
+	/* Tap settings for the DDR */
+	li      t0, 0xffffffff
+	li      t1, DRAM_K0(0x500000)
+	sw      t0, 0x0(t1)
+	sw      t0, 0x4(t1)
+	sw      t0, 0x8(t1)
+	sw      t0, 0xc(t1)
+	nop
+	nop
+
+	li      t8, DRAM_K1(0x2000)
+	li      t0, 0x00

(quoted diff) +0 -0

b/arch/mips/mach-ath79/ar933x/lowlevel_init.S new file mode 100644 index 0000000..72509ca

arch/mips/mach-ath79/ar933x/lowlevel_init.S new file +84 -0

@@ -0,0 +1,460 @@
+/*
+ * (C) Copyright 2015
+ * Wills Wang, <[email protected]>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <config.h>
+#include <asm/asm.h>
+#include <asm/regdef.h>
+#include <asm/mipsregs.h>
+#include <asm/addrspace.h>
+#include <asm/arch/ar71xx_regs.h>
+
+#define SET_BIT(val, bit)   ((val) | (1 << (bit)))
+#define SET_PLL_PD(val)     SET_BIT(val, 30)
+#define AHB_DIV_TO_4(val)   SET_BIT(SET_BIT(val, 15), 16)
+#define PLL_BYPASS(val)     SET_BIT(val, 2)
+
+#define MK_PLL_CONF(divint, refdiv, range, outdiv) \
+     (((0x3F & divint) << 10) | \
+     ((0x1F & refdiv) << 16) | \
+     ((0x1 & range)   << 21) | \
+     ((0x7 & outdiv)  << 23) )
+
+#define MK_CLK_CNTL(cpudiv, ddrdiv, ahbdiv) \
+    (((0x3 & (cpudiv - 1)) << 5)  | \
+    ((0x3 & (ddrdiv - 1)) << 10) | \
+    ((0x3 & (ahbdiv - 1)) << 15) )
+
+/*
+ * PLL_CPU_CONFIG_VAL
+ *
+ * Bit30 is set (CPU_PLLPWD = 1 -> power down control for CPU PLL)
+ * After PLL configuration we need to clear this bit
+ *
+ * Values written into CPU PLL Configuration (CPU_PLL_CONFIG)
+ *
+ * bits 10..15  (6bit)  DIV_INT (Integer part of the DIV to CPU PLL)
+ *                      =>  32  (0x20)  VCOOUT = XTAL * DIV_INT
+ * bits 16..20  (5bit)  REFDIV  (Reference clock divider)
+ *                      =>  1   (0x1)   [Must start at values 1]
+ * bits 21      (1bit)  RANGE   (VCO frequency range of the CPU PLL)
+ *                      =>  0   (0x0)   [Doesn't impact clock values]
+ * bits 23..25  (3bit)  OUTDIV  (Ratio between VCO and PLL output)
+ *                      =>  1   (0x1)   [0 is illegal!]
+ *                              PLLOUT = VCOOUT * (1/2^OUTDIV)
+ */
+/* DIV_INT=32 (25MHz*32/2=400MHz), REFDIV=1, RANGE=0, OUTDIV=1 */
+#define PLL_CPU_CONFIG_VAL_40M  MK_PLL_CONF(20, 1, 0, 1)
+/* DIV_INT=20 (40MHz*20/2=400MHz), REFDIV=1, RANGE=0, OUTDIV=1 */
+#define PLL_CPU_CONFIG_VAL_25M  MK_PLL_CONF(32, 1, 0, 1)
+
+/*
+ * PLL_CLK_CONTROL_VAL
+ *
+ * In PLL_CLK_CONTROL_VAL bit 2 is set (BYPASS = 1 -> bypass PLL)
+ * After PLL configuration we need to clear this bit
+ *
+ * Values written into CPU Clock Control Register CLOCK_CONTROL
+ *
+ * bits 2       (1bit)  BYPASS (Bypass PLL. This defaults to 1 for test.
+ *                      Software must enable the CPU PLL for normal and
+ *                      then set this bit to 0)
+ * bits 5..6    (2bit)  CPU_POST_DIV    =>  0   (DEFAULT, Ratio = 1)
+ *                      CPU_CLK = PLLOUT / CPU_POST_DIV
+ * bits 10..11  (2bit)  DDR_POST_DIV    =>  0   (DEFAULT, Ratio = 1)
+ *                      DDR_CLK = PLLOUT / DDR_POST_DIV
+ * bits 15..16  (2bit)  AHB_POST_DIV    =>  1   (DEFAULT, Ratio = 2)
+ *                      AHB_CLK = PLLOUT / AHB_POST_DIV
+ *
+ */
+#define PLL_CLK_CONTROL_VAL MK_CLK_CNTL(1, 1, 2)
+
+    .text
+    .set noreorder
+
+LEAF(lowlevel_init)
+   /* These three WLAN_RESET will avoid original issue */
+    li      t3, 0x03
+1:
+    li      t0, KSEG1ADDR(AR71XX_RESET_BASE)
+    lw      t1, AR933X_RESET_REG_RESET_MODULE(t0)
+    ori     t1, t1, 0x0800

arch/mips/mach-ath79/cpu.c new file +21 -0

new file mode 100644
index 0000000..1f58877
@@ -0,0 +1,269 @@
+/*
+ * (C) Copyright 2015
+ * Wills Wang, <[email protected]>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/addrspace.h>
+#include <asm/types.h>
+#include <asm/arch/ath79.h>
+#include <asm/arch/ar71xx_regs.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+enum ath79_soc_type get_soc_type(void)
+{
+	enum ath79_soc_type soc = ATH79_SOC_UNKNOWN;
+	u32 id, major, minor;
+

arch/mips/mach-ath79/cpu.c new file +11 -0

+int print_cpuinfo(void)
+{
+	enum ath79_soc_type soc = ATH79_SOC_UNKNOWN;
+	char *chip = "????";
+	u32 id, major, minor;
+	u32 rev = 0;
+	u32 ver = 1;
+
+	id = readl(KSEG1ADDR(AR71XX_RESET_BASE + AR71XX_RESET_REG_REV_ID));
+	major = id & REV_ID_MAJOR_MASK;
+

arch/mips/mach-ath79/cpu.c new file +3 -0

+
+	return 0;
+}

arch/mips/mach-ath79/dram.c new file +15 -0

new file mode 100644
index 0000000..42539dc
@@ -0,0 +1,27 @@
+/*
+ * (C) Copyright 2015
+ * Wills Wang, <[email protected]>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/addrspace.h>
+#include <asm/arch/ddr.h>
+
+phys_size_t initdram(int board_type)
+{
+	uint8_t *addr, *p;
+	int i;

arch/mips/mach-ath79/dram.c new file +2 -0

+	return (phys_size_t)(p - addr);
+}

arch/mips/mach-ath79/reset.c new file +8 -0

new file mode 100644
index 0000000..0ace05d
@@ -0,0 +1,55 @@
+/*
+ * (C) Copyright 2015
+ * Wills Wang, <[email protected]>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>

arch/mips/mach-ath79/reset.c new file +21 -0

+DECLARE_GLOBAL_DATA_PTR;
+
+void _machine_restart(void)
+{
+	enum ath79_soc_type soc;
+	u32 val, reg = 0;
+
+	soc = get_soc_type();
+	if (soc_is_ar71xx(soc))
+		reg = AR71XX_RESET_REG_RESET_MODULE;
+	else if (soc_is_ar724x(soc))
+		reg = AR724X_RESET_REG_RESET_MODULE;
+	else if (soc_is_ar913x(soc))
+		reg = AR913X_RESET_REG_RESET_MODULE;
+	else if (soc_is_ar933x(soc))
+		reg = AR933X_RESET_REG_RESET_MODULE;
+	else if (soc_is_ar934x(soc))
+		reg = AR934X_RESET_REG_RESET_MODULE;
+	else if (soc_is_qca953x(soc))
+		reg = QCA953X_RESET_REG_RESET_MODULE;
+	else if (soc_is_qca955x(soc))

arch/mips/mach-ath79/reset.c new file +5 -0

+	}
+
+	while (1)
+		/* NOP */;
+}

Quoted 3 lines · Wills Wang

This patch enable work for ar933x SOC, tested on ar9331 board.

Signed-off-by Wills Wang <[email protected]>

[...]

arch/mips/config.mk cpuflags-$(CONFIG_CPU_MIPS32_R1) += -march=mips32 · line 40

Quoted 10 lines

arch/mips/config.mk +1 -3

index 3ebc202..fd50909 100644
@@ -39,6 +39,7 @@ cpuflags-$(CONFIG_CPU_MIPS32_R1) += -march=mips32
-Wa,-mips32 cpuflags-$(CONFIG_CPU_MIPS32_R2) += -march=mips32r2
-Wa,-mips32r2 cpuflags-$(CONFIG_CPU_MIPS64_R1) += -march=mips64
-Wa,-mips64
  cpuflags-$(CONFIG_CPU_MIPS64_R2) += -march=mips64r2 -Wa,-mips64r2
+cpuflags-$(CONFIG_ARCH_ATH79) += -mtune=24kc

You can just tune it for MIPS32_R2 , it will be compatible with older toolchains too. I don't think there is much benefit in being so explicit and using mips24kc tuning.

Quoted 3 lines

arch/mips/config.mk +0 -0

  PLATFORM_CPPFLAGS += $(cpuflags-y)
 
  PLATFORM_CPPFLAGS += -D__MIPS__

[...]

Quoted 39 lines

(quoted diff) +0 -0

b/arch/mips/mach-ath79/ar933x/ddr_tap.S new file mode 100644 index 0000000..18c57de

arch/mips/mach-ath79/ar933x/ddr_tap.S new file +33 -0

@@ -0,0 +1,268 @@
+/*
+ * (C) Copyright 2015
+ * Wills Wang, <[email protected]>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <config.h>
+#include <asm/asm.h>
+#include <asm/regdef.h>
+#include <asm/mipsregs.h>
+#include <asm/addrspace.h>
+#include <asm/arch/ar71xx_regs.h>
+
+#define DRAM_K0(x)      KSEG0ADDR(x)
+#define DRAM_K1(x)      KSEG1ADDR(x)
+
+	.text
+	.set noreorder
+
+LEAF(ddr_tap_init)
+	/* Tap settings for the DDR */
+	li      t0, 0xffffffff
+	li      t1, DRAM_K0(0x500000)
+	sw      t0, 0x0(t1)
+	sw      t0, 0x4(t1)
+	sw      t0, 0x8(t1)
+	sw      t0, 0xc(t1)
+	nop
+	nop
+
+	li      t8, DRAM_K1(0x2000)
+	li      t0, 0x00

arch/mips/mach-ath79/ar933x/ddr_tap.S line 43

Quoted 10 lines

arch/mips/mach-ath79/ar933x/ddr_tap.S new file +10 -0

+	li      t1, 0x100
+0:
+	andi    t2, t0, 0x03
+	li      t3, 0x00
+	bne     t2, t3,1f
+	 nop
+	li      t9, 0x00000000
+	sw      t9, 0x0(t8)
+	b       2f
+	 nop

Please rewrite this into C, I believe it should be pretty easy.

[...]

Quoted 93 lines

(quoted diff) +0 -0

b/arch/mips/mach-ath79/ar933x/lowlevel_init.S new file mode 100644 index 0000000..72509ca

arch/mips/mach-ath79/ar933x/lowlevel_init.S new file +87 -0

@@ -0,0 +1,460 @@
+/*
+ * (C) Copyright 2015
+ * Wills Wang, <[email protected]>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <config.h>
+#include <asm/asm.h>
+#include <asm/regdef.h>
+#include <asm/mipsregs.h>
+#include <asm/addrspace.h>
+#include <asm/arch/ar71xx_regs.h>
+
+#define SET_BIT(val, bit)   ((val) | (1 << (bit)))
+#define SET_PLL_PD(val)     SET_BIT(val, 30)
+#define AHB_DIV_TO_4(val)   SET_BIT(SET_BIT(val, 15), 16)
+#define PLL_BYPASS(val)     SET_BIT(val, 2)
+
+#define MK_PLL_CONF(divint, refdiv, range, outdiv) \
+     (((0x3F & divint) << 10) | \
+     ((0x1F & refdiv) << 16) | \
+     ((0x1 & range)   << 21) | \
+     ((0x7 & outdiv)  << 23) )
+
+#define MK_CLK_CNTL(cpudiv, ddrdiv, ahbdiv) \
+    (((0x3 & (cpudiv - 1)) << 5)  | \
+    ((0x3 & (ddrdiv - 1)) << 10) | \
+    ((0x3 & (ahbdiv - 1)) << 15) )
+
+/*
+ * PLL_CPU_CONFIG_VAL
+ *
+ * Bit30 is set (CPU_PLLPWD = 1 -> power down control for CPU PLL)
+ * After PLL configuration we need to clear this bit
+ *
+ * Values written into CPU PLL Configuration (CPU_PLL_CONFIG)
+ *
+ * bits 10..15  (6bit)  DIV_INT (Integer part of the DIV to CPU PLL)
+ *                      =>  32  (0x20)  VCOOUT = XTAL * DIV_INT
+ * bits 16..20  (5bit)  REFDIV  (Reference clock divider)
+ *                      =>  1   (0x1)   [Must start at values 1]
+ * bits 21      (1bit)  RANGE   (VCO frequency range of the CPU PLL)
+ *                      =>  0   (0x0)   [Doesn't impact clock values]
+ * bits 23..25  (3bit)  OUTDIV  (Ratio between VCO and PLL output)
+ *                      =>  1   (0x1)   [0 is illegal!]
+ *                              PLLOUT = VCOOUT * (1/2^OUTDIV)
+ */
+/* DIV_INT=32 (25MHz*32/2=400MHz), REFDIV=1, RANGE=0, OUTDIV=1 */
+#define PLL_CPU_CONFIG_VAL_40M  MK_PLL_CONF(20, 1, 0, 1)
+/* DIV_INT=20 (40MHz*20/2=400MHz), REFDIV=1, RANGE=0, OUTDIV=1 */
+#define PLL_CPU_CONFIG_VAL_25M  MK_PLL_CONF(32, 1, 0, 1)
+
+/*
+ * PLL_CLK_CONTROL_VAL
+ *
+ * In PLL_CLK_CONTROL_VAL bit 2 is set (BYPASS = 1 -> bypass PLL)
+ * After PLL configuration we need to clear this bit
+ *
+ * Values written into CPU Clock Control Register CLOCK_CONTROL
+ *
+ * bits 2       (1bit)  BYPASS (Bypass PLL. This defaults to 1 for test.
+ *                      Software must enable the CPU PLL for normal and
+ *                      then set this bit to 0)
+ * bits 5..6    (2bit)  CPU_POST_DIV    =>  0   (DEFAULT, Ratio = 1)
+ *                      CPU_CLK = PLLOUT / CPU_POST_DIV
+ * bits 10..11  (2bit)  DDR_POST_DIV    =>  0   (DEFAULT, Ratio = 1)
+ *                      DDR_CLK = PLLOUT / DDR_POST_DIV
+ * bits 15..16  (2bit)  AHB_POST_DIV    =>  1   (DEFAULT, Ratio = 2)
+ *                      AHB_CLK = PLLOUT / AHB_POST_DIV
+ *
+ */
+#define PLL_CLK_CONTROL_VAL MK_CLK_CNTL(1, 1, 2)
+
+    .text
+    .set noreorder
+
+LEAF(lowlevel_init)
+   /* These three WLAN_RESET will avoid original issue */
+    li      t3, 0x03
+1:
+    li      t0, KSEG1ADDR(AR71XX_RESET_BASE)
+    lw      t1, AR933X_RESET_REG_RESET_MODULE(t0)
+    ori     t1, t1, 0x0800
+    sw      t1, AR933X_RESET_REG_RESET_MODULE(t0)
+    nop
+    lw      t1, AR933X_RESET_REG_RESET_MODULE(t0)

arch/mips/mach-ath79/ar933x/lowlevel_init.S line 94

Quoted 7 lines

arch/mips/mach-ath79/ar933x/lowlevel_init.S new file +7 -0

+    li      t2, 0xfffff7ff
+    and     t1, t1, t2
+    sw      t1, AR933X_RESET_REG_RESET_MODULE(t0)
+    nop
+    addi    t3, t3, -1
+    bnez    t3, 1b
+     nop

This should be also easy to rewrite into C , right ?

[...]

Quoted 27 lines

arch/mips/mach-ath79/cpu.c new file +21 -0

new file mode 100644
index 0000000..1f58877
@@ -0,0 +1,269 @@
+/*
+ * (C) Copyright 2015
+ * Wills Wang, <[email protected]>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/addrspace.h>
+#include <asm/types.h>
+#include <asm/arch/ath79.h>
+#include <asm/arch/ar71xx_regs.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+enum ath79_soc_type get_soc_type(void)
+{
+	enum ath79_soc_type soc = ATH79_SOC_UNKNOWN;
+	u32 id, major, minor;
+

arch/mips/mach-ath79/cpu.c line 31

Quoted 10 lines

arch/mips/mach-ath79/cpu.c new file +10 -0

+	id = readl(KSEG1ADDR(AR71XX_RESET_BASE + AR71XX_RESET_REG_REV_ID));
+	major = id & REV_ID_MAJOR_MASK;
+
+	switch (major) {
+	case REV_ID_MAJOR_AR71XX:
+		minor = id & AR71XX_REV_ID_MINOR_MASK;
+		switch (minor) {
+		case AR71XX_REV_ID_MINOR_AR7130:
+			soc = ATH79_SOC_AR7130;
+			break;

I think you can convert this stuff into a table of sorts, so you won't have such a lengthy code:

struct {
	u32 major;
	u32 minor;
	enum soc;
} table[] {
	{ REV_ID_MAJOR_AR71XX, AR71XX_REV_ID_MINOR_AR7130, ATH79_SOC_AR7130 },
         ...
}

And just iterate over such table.

[...]

Quoted 11 lines

arch/mips/mach-ath79/cpu.c new file +11 -0

+int print_cpuinfo(void)
+{
+	enum ath79_soc_type soc = ATH79_SOC_UNKNOWN;
+	char *chip = "????";
+	u32 id, major, minor;
+	u32 rev = 0;
+	u32 ver = 1;
+
+	id = readl(KSEG1ADDR(AR71XX_RESET_BASE + AR71XX_RESET_REG_REV_ID));
+	major = id & REV_ID_MAJOR_MASK;
+

arch/mips/mach-ath79/cpu.c line 137

Quoted 10 lines

arch/mips/mach-ath79/cpu.c new file +10 -0

+	switch (major) {
+	case REV_ID_MAJOR_AR71XX:
+		minor = id & AR71XX_REV_ID_MINOR_MASK;
+		rev = id >> AR71XX_REV_ID_REVISION_SHIFT;
+		rev &= AR71XX_REV_ID_REVISION_MASK;
+		switch (minor) {
+		case AR71XX_REV_ID_MINOR_AR7130:
+			soc = ATH79_SOC_AR7130;
+			chip = "7130";
+			break;

DTTO here, use table lookup

[...]

Quoted 27 lines

arch/mips/mach-ath79/cpu.c new file +3 -0

+
+	return 0;
+}

arch/mips/mach-ath79/dram.c new file +18 -0

new file mode 100644
index 0000000..42539dc
@@ -0,0 +1,27 @@
+/*
+ * (C) Copyright 2015
+ * Wills Wang, <[email protected]>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/addrspace.h>
+#include <asm/arch/ddr.h>
+
+phys_size_t initdram(int board_type)
+{
+	uint8_t *addr, *p;
+	int i;
+
+	ddr_tap_init();
+	addr = (uint8_t *)KSEG1;

arch/mips/mach-ath79/dram.c line 25

Quoted 7 lines

arch/mips/mach-ath79/dram.c new file +7 -0

+	*addr = 0x77;
+	for (i = 0, p = addr; p < (uint8_t *)KSEG2; i++) {
+		p += 0x1000000;
+		*p = i;
+		if (*addr != 0x77)
+			break;
+	}

What is this and how does it work ?

Quoted 3 lines

arch/mips/mach-ath79/dram.c new file +2 -0

+	return (phys_size_t)(p - addr);
+}

[...]

Quoted 14 lines

arch/mips/mach-ath79/reset.c new file +8 -0

new file mode 100644
index 0000000..0ace05d
@@ -0,0 +1,55 @@
+/*
+ * (C) Copyright 2015
+ * Wills Wang, <[email protected]>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>

arch/mips/mach-ath79/reset.c line 18

Quoted 10 lines

arch/mips/mach-ath79/reset.c new file +10 -0

+#include <asm/io.h>
+#include <asm/addrspace.h>
+#include <asm/types.h>
+#include <asm/arch/ath79.h>
+#include <asm/arch/ar71xx_regs.h>
+
+#define REG_READ(b, o)      readl(KSEG1ADDR(b + o))
+#define REG_WRITE(b, o, v)  writel(v, KSEG1ADDR((b + o)))
+#define RST_READ(a)        REG_READ(AR71XX_RESET_BASE, a)
+#define RST_WRITE(a, v)    REG_WRITE(AR71XX_RESET_BASE, a, v)

Drop these.

Quoted 24 lines

arch/mips/mach-ath79/reset.c new file +24 -0

+DECLARE_GLOBAL_DATA_PTR;
+
+void _machine_restart(void)
+{
+	enum ath79_soc_type soc;
+	u32 val, reg = 0;
+
+	soc = get_soc_type();
+	if (soc_is_ar71xx(soc))
+		reg = AR71XX_RESET_REG_RESET_MODULE;
+	else if (soc_is_ar724x(soc))
+		reg = AR724X_RESET_REG_RESET_MODULE;
+	else if (soc_is_ar913x(soc))
+		reg = AR913X_RESET_REG_RESET_MODULE;
+	else if (soc_is_ar933x(soc))
+		reg = AR933X_RESET_REG_RESET_MODULE;
+	else if (soc_is_ar934x(soc))
+		reg = AR934X_RESET_REG_RESET_MODULE;
+	else if (soc_is_qca953x(soc))
+		reg = QCA953X_RESET_REG_RESET_MODULE;
+	else if (soc_is_qca955x(soc))
+		reg = QCA955X_RESET_REG_RESET_MODULE;
+	else if (soc_is_qca956x(soc))
+		reg = QCA956X_RESET_REG_RESET_MODULE;

arch/mips/mach-ath79/reset.c line 50

Quoted 7 lines

arch/mips/mach-ath79/reset.c new file +7 -0

+	else
+		puts("Reset register not defined for this SOC\n");
+
+	if (reg) {
+		val = RST_READ(reg);
+		val |= AR71XX_RESET_FULL_CHIP;
+		RST_WRITE(reg, val);

setbits_le32() please.

Quoted 5 lines

arch/mips/mach-ath79/reset.c new file +5 -0

+	}
+
+	while (1)
+		/* NOP */;
+}

Quoted 18 lines

Quoted 17 lines

arch/mips/mach-ath79/ar933x/lowlevel_init.S new file +17 -0

+LEAF(lowlevel_init)
+   /* These three WLAN_RESET will avoid original issue */
+    li      t3, 0x03
+1:
+    li      t0, KSEG1ADDR(AR71XX_RESET_BASE)
+    lw      t1, AR933X_RESET_REG_RESET_MODULE(t0)
+    ori     t1, t1, 0x0800
+    sw      t1, AR933X_RESET_REG_RESET_MODULE(t0)
+    nop
+    lw      t1, AR933X_RESET_REG_RESET_MODULE(t0)
+    li      t2, 0xfffff7ff
+    and     t1, t1, t2
+    sw      t1, AR933X_RESET_REG_RESET_MODULE(t0)
+    nop
+    addi    t3, t3, -1
+    bnez    t3, 1b
+     nop

Quoted 1 line

This should be also easy to rewrite into C , right ?

C runtime environment is not available.
C stack is not ready before DDR has initialized.

Quoted 8 lines

Quoted 8 lines

arch/mips/mach-ath79/dram.c new file +8 -0

+phys_size_t initdram(int board_type)
+{
+	uint8_t *addr, *p;
+	int i;
+
+	ddr_tap_init();
+	addr = (uint8_t *)KSEG1;
+	*addr = 0x77;

Quoted 8 lines

arch/mips/mach-ath79/dram.c line 25

Quoted 6 lines

arch/mips/mach-ath79/dram.c new file +6 -0

+	for (i = 0, p = addr; p < (uint8_t *)KSEG2; i++) {
+		p += 0x1000000;
+		*p = i;
+		if (*addr != 0x77)
+			break;
+	}

What is this and how does it work ?

Physical memory was mapped circularly for this chip.

Quoted 3 lines

Quoted 2 lines

arch/mips/mach-ath79/dram.c new file +2 -0

+	return (phys_size_t)(p - addr);
+}

Quoted 6 lines

arch/mips/mach-ath79/reset.c line 50

Quoted 4 lines

arch/mips/mach-ath79/reset.c new file +4 -0

+	if (reg) {
+		val = RST_READ(reg);
+		val |= AR71XX_RESET_FULL_CHIP;
+		RST_WRITE(reg, val);

setbits_le32() please.

Macro setbits_le32() is not available for MIPS architecture.

Other, I don't think there is better in being so explicit and using little-endian.

On Thursday, December 24, 2015 at 02:51:06 PM, Wills Wang wrote:

[...]

Quoted 17 lines

Quoted 17 lines

Quoted 17 lines

arch/mips/mach-ath79/ar933x/lowlevel_init.S new file +17 -0

+LEAF(lowlevel_init)
+   /* These three WLAN_RESET will avoid original issue */
+    li      t3, 0x03
+1:
+    li      t0, KSEG1ADDR(AR71XX_RESET_BASE)
+    lw      t1, AR933X_RESET_REG_RESET_MODULE(t0)
+    ori     t1, t1, 0x0800
+    sw      t1, AR933X_RESET_REG_RESET_MODULE(t0)
+    nop
+    lw      t1, AR933X_RESET_REG_RESET_MODULE(t0)
+    li      t2, 0xfffff7ff
+    and     t1, t1, t2
+    sw      t1, AR933X_RESET_REG_RESET_MODULE(t0)
+    nop
+    addi    t3, t3, -1
+    bnez    t3, 1b
+     nop

Quoted 3 lines

Quoted 1 line

This should be also easy to rewrite into C , right ?

C runtime environment is not available.
C stack is not ready before DDR has initialized.

Just point the stack into a locked cacheline or some onchip RAM and there you have a C runtime. That should be pretty easy :)

[...]

Quoted 15 lines

Quoted 7 lines

Quoted 7 lines

arch/mips/mach-ath79/dram.c new file +7 -0

+phys_size_t initdram(int board_type)
+{
+	uint8_t *addr, *p;
+	int i;
+
+	ddr_tap_init();
+	addr = (uint8_t *)KSEG1;

Quoted 8 lines

arch/mips/mach-ath79/dram.c line 25

Quoted 7 lines

arch/mips/mach-ath79/dram.c new file +7 -0

+	*addr = 0x77;
+	for (i = 0, p = addr; p < (uint8_t *)KSEG2; i++) {
+		p += 0x1000000;
+		*p = i;
+		if (*addr != 0x77)
+			break;
+	}

What is this and how does it work ?

Quoted 1 line

Physical memory was mapped circularly for this chip.

Can you please expand on that ? I am not as deep in this chip as you are, so please explain it to me in a bit more detail.

Quoted 2 lines

Quoted 2 lines

Quoted 2 lines

arch/mips/mach-ath79/dram.c new file +2 -0

+	return (phys_size_t)(p - addr);
+}

[...]

Quoted 5 lines

Quoted 5 lines

arch/mips/mach-ath79/reset.c line 50

Quoted 4 lines

arch/mips/mach-ath79/reset.c new file +4 -0

+	if (reg) {
+		val = RST_READ(reg);
+		val |= AR71XX_RESET_FULL_CHIP;
+		RST_WRITE(reg, val);

setbits_le32() please.

Quoted 1 line

Macro setbits_le32() is not available for MIPS architecture.

You can always add them :)

Quoted 2 lines

Other, I don't think there is better in being so explicit and using little-endian.

I believe your register accesses should have correct endianness exactly beause mips can be both endian.

Quoted 24 lines · Marek Vasut

On Thursday, December 24, 2015 at 02:51:06 PM, Wills Wang wrote:

[...]

Quoted 20 lines

Quoted 19 lines

Quoted 7 lines

arch/mips/mach-ath79/ar933x/lowlevel_init.S new file +7 -0

+LEAF(lowlevel_init)
+   /* These three WLAN_RESET will avoid original issue */
+    li      t3, 0x03
+1:
+    li      t0, KSEG1ADDR(AR71XX_RESET_BASE)
+    lw      t1, AR933X_RESET_REG_RESET_MODULE(t0)
+    ori     t1, t1, 0x0800

arch/mips/mach-ath79/ar933x/lowlevel_init.S line 94

Quoted 10 lines

arch/mips/mach-ath79/ar933x/lowlevel_init.S new file +10 -0

+    sw      t1, AR933X_RESET_REG_RESET_MODULE(t0)
+    nop
+    lw      t1, AR933X_RESET_REG_RESET_MODULE(t0)
+    li      t2, 0xfffff7ff
+    and     t1, t1, t2
+    sw      t1, AR933X_RESET_REG_RESET_MODULE(t0)
+    nop
+    addi    t3, t3, -1
+    bnez    t3, 1b
+     nop

This should be also easy to rewrite into C , right ?

Quoted 5 lines

Quoted 2 lines

C runtime environment is not available.
C stack is not ready before DDR has initialized.

Just point the stack into a locked cacheline or some onchip RAM and there you have a C runtime. That should be pretty easy :)

How to lock cacheline?

My guess is that cache memory may be use to map SPI flash at 0x9f000000 by ROM code.

Quoted 19 lines

[...]

Quoted 17 lines

Quoted 16 lines

Quoted 4 lines

arch/mips/mach-ath79/dram.c new file +4 -0

+phys_size_t initdram(int board_type)
+{
+	uint8_t *addr, *p;
+	int i;

arch/mips/mach-ath79/dram.c line 25

Quoted 10 lines

arch/mips/mach-ath79/dram.c new file +10 -0

+
+	ddr_tap_init();
+	addr = (uint8_t *)KSEG1;
+	*addr = 0x77;
+	for (i = 0, p = addr; p < (uint8_t *)KSEG2; i++) {
+		p += 0x1000000;
+		*p = i;
+		if (*addr != 0x77)
+			break;
+	}

What is this and how does it work ?

Quoted 4 lines

Quoted 1 line

Physical memory was mapped circularly for this chip.

Can you please expand on that ? I am not as deep in this chip as you are, so please explain it to me in a bit more detail.

Quoted 16 lines

Quoted 2 lines

Quoted 2 lines

Quoted 2 lines

arch/mips/mach-ath79/dram.c new file +2 -0

+	return (phys_size_t)(p - addr);
+}

[...]

Quoted 8 lines

Quoted 6 lines

arch/mips/mach-ath79/reset.c line 50

Quoted 4 lines

arch/mips/mach-ath79/reset.c new file +4 -0

+	if (reg) {
+		val = RST_READ(reg);
+		val |= AR71XX_RESET_FULL_CHIP;
+		RST_WRITE(reg, val);

setbits_le32() please.

Macro setbits_le32() is not available for MIPS architecture.

You can always add them :)

Quoted 5 lines

Quoted 2 lines

Other, I don't think there is better in being so explicit and using little-endian.

I believe your register accesses should have correct endianness exactly beause mips can be both endian.

What is the advantage of using setbits_le32()?

Quoted 22 lines · Wills Wang

Quoted 21 lines · Marek Vasut

On Thursday, December 24, 2015 at 02:51:06 PM, Wills Wang wrote:

[...]

Quoted 17 lines

Quoted 17 lines

Quoted 17 lines

arch/mips/mach-ath79/ar933x/lowlevel_init.S new file +17 -0

+LEAF(lowlevel_init)
+   /* These three WLAN_RESET will avoid original issue */
+    li      t3, 0x03
+1:
+    li      t0, KSEG1ADDR(AR71XX_RESET_BASE)
+    lw      t1, AR933X_RESET_REG_RESET_MODULE(t0)
+    ori     t1, t1, 0x0800
+    sw      t1, AR933X_RESET_REG_RESET_MODULE(t0)
+    nop
+    lw      t1, AR933X_RESET_REG_RESET_MODULE(t0)
+    li      t2, 0xfffff7ff
+    and     t1, t1, t2
+    sw      t1, AR933X_RESET_REG_RESET_MODULE(t0)
+    nop
+    addi    t3, t3, -1
+    bnez    t3, 1b
+     nop

Quoted 6 lines

Quoted 5 lines

Quoted 3 lines

Quoted 1 line

This should be also easy to rewrite into C , right ?

C runtime environment is not available.
C stack is not ready before DDR has initialized.

Just point the stack into a locked cacheline or some onchip RAM and there you have a C runtime. That should be pretty easy :)

How to lock cacheline?

You'd have to check the MIPS core manual, I don't know the details, sorry.

Quoted 2 lines

My guess is that cache memory may be use to map SPI flash at 0x9f000000 by ROM code.

The SPI flash is an IP block which just maps the SPI NOR into the address space, it doesn't use the CPU cache at all.

Maybe you don't even need to lock cachelines though, the AR9331 should have some internal SRAM, so just use that for stack. Do you have a proper datasheet for the Atheros MIPS chips ? I have some 320 pages datasheet for AR9331.

Quoted 17 lines

Quoted 17 lines

[...]

Quoted 15 lines

Quoted 15 lines

Quoted 4 lines

arch/mips/mach-ath79/dram.c new file +4 -0

+phys_size_t initdram(int board_type)
+{
+	uint8_t *addr, *p;
+	int i;

arch/mips/mach-ath79/dram.c line 25

Quoted 10 lines

arch/mips/mach-ath79/dram.c new file +10 -0

+
+	ddr_tap_init();
+	addr = (uint8_t *)KSEG1;
+	*addr = 0x77;
+	for (i = 0, p = addr; p < (uint8_t *)KSEG2; i++) {
+		p += 0x1000000;
+		*p = i;
+		if (*addr != 0x77)
+			break;
+	}

What is this and how does it work ?

Quoted 3 lines

Quoted 3 lines

Quoted 1 line

Physical memory was mapped circularly for this chip.

Can you please expand on that ? I am not as deep in this chip as you are, so please explain it to me in a bit more detail.

Well ... ?

Quoted 17 lines

Quoted 17 lines

Quoted 3 lines

Quoted 3 lines

Quoted 3 lines

arch/mips/mach-ath79/dram.c new file +2 -0

+	return (phys_size_t)(p - addr);
+}

[...]

Quoted 6 lines

Quoted 5 lines

arch/mips/mach-ath79/reset.c line 50

Quoted 4 lines

arch/mips/mach-ath79/reset.c new file +4 -0

+	if (reg) {
+		val = RST_READ(reg);
+		val |= AR71XX_RESET_FULL_CHIP;
+		RST_WRITE(reg, val);

setbits_le32() please.

Macro setbits_le32() is not available for MIPS architecture.

You can always add them :)

Quoted 2 lines

Other, I don't think there is better in being so explicit and using little-endian.

I believe your register accesses should have correct endianness exactly beause mips can be both endian.

Quoted 1 line

What is the advantage of using setbits_le32()?

You don't have these constant repeating patterns of:

var = read()
var |= BIT
write(var)

It makes things a bit less confusing.

Best regards,
Marek Vasut

Quoted 7 lines

The SPI flash is an IP block which just maps the SPI NOR into the address space, it doesn't use the CPU cache at all.

Maybe you don't even need to lock cachelines though, the AR9331 should have some internal SRAM, so just use that for stack. Do you have a proper datasheet for the Atheros MIPS chips ? I have some 320 pages datasheet for AR9331.

I don't find any description about internal SRAM in public datasheet. About mapping SPI flash, there is a doubt, who fetch the instruction from the SPI Nor flash to CPU pipe line when chip boot from SPI flash? I guess that ROM code handle cache exception and load instruction/date from SPI flash into cache.

Quoted 19 lines

Quoted 19 lines

Quoted 19 lines

[...]

Quoted 17 lines

Quoted 16 lines

Quoted 4 lines

(quoted diff) +4 -0

+phys_size_t initdram(int board_type)
+{
+	uint8_t *addr, *p;
+	int i;

Review

Quoted 10 lines

(quoted diff) +10 -0

+
+	ddr_tap_init();
+	addr = (uint8_t *)KSEG1;
+	*addr = 0x77;
+	for (i = 0, p = addr; p < (uint8_t *)KSEG2; i++) {
+		p += 0x1000000;
+		*p = i;
+		if (*addr != 0x77)
+			break;
+	}

What is this and how does it work ?

Quoted 6 lines

Quoted 4 lines

Quoted 4 lines

Quoted 1 line

Physical memory was mapped circularly for this chip.

Can you please expand on that ? I am not as deep in this chip as you are, so please explain it to me in a bit more detail.

Well ... ?

There is 64MB DDR on my board, the 64MB memory was mapped circularly into 0x00000000-0x03ffffff, 0x04000000-0x07ffffff, 0x08000000-0x0bffffff,... the address 0x00000000, 0x04000000 and 0x08000000 was mapped to the same physical memory. their corresponding KSEG1 address is 0xA0000000, 0xA4000000,
0xA8000000, when write a value into 0xA0000000, we can read the same value from address 0xA4000000 and 0xA8000000.

Quoted 26 lines

Quoted 16 lines

Quoted 16 lines

Quoted 2 lines

Quoted 2 lines

Quoted 2 lines

(quoted diff) +2 -0

+	return (phys_size_t)(p - addr);
+}

[...]

Quoted 8 lines

Quoted 6 lines

Review

Quoted 4 lines

(quoted diff) +4 -0

+	if (reg) {
+		val = RST_READ(reg);
+		val |= AR71XX_RESET_FULL_CHIP;
+		RST_WRITE(reg, val);

setbits_le32() please.

Macro setbits_le32() is not available for MIPS architecture.

You can always add them :)

Quoted 7 lines

Quoted 5 lines

Quoted 2 lines

Other, I don't think there is better in being so explicit and using little-endian.

I believe your register accesses should have correct endianness exactly beause mips can be both endian.

What is the advantage of using setbits_le32()?

You don't have these constant repeating patterns of:

Quoted 5 lines

var = read()
var |= BIT
write(var)

It makes things a bit less confusing.

ok, AR9331 use big-endian.

On Saturday, December 26, 2015 at 04:48:57 PM, Wills Wang wrote:

[...]

Quoted 8 lines

Quoted 7 lines

The SPI flash is an IP block which just maps the SPI NOR into the address space, it doesn't use the CPU cache at all.

Maybe you don't even need to lock cachelines though, the AR9331 should have some internal SRAM, so just use that for stack. Do you have a proper datasheet for the Atheros MIPS chips ? I have some 320 pages datasheet for AR9331.

Quoted 5 lines

I don't find any description about internal SRAM in public datasheet. About mapping SPI flash, there is a doubt, who fetch the instruction from the SPI Nor flash to CPU pipe line when chip boot from SPI flash? I guess that ROM code handle cache exception and load instruction/date from SPI flash into cache.

I just pulled out the SPI NOR from the Arduino Yun I have here and connected an FPGA with SPI NOR emulator in there. All the chip does is it issues the fastread opcode to the SPI NOR when it boots. It does the same thing if you access the 0x9f000000..0x9fxxxxxx address range from the ancient U-Boot 1.1.x.

My impression is that the SPI NOR controller in the chip does a mapping between the SPI NOR and the memory mapped access to the 0x9fxxxxxx range. There is no caching involved in that, all of this is done internally in the SPI NOR block.

The mips24kc core should support locking cache lines , so if the SRAM is not available, this would have to do.

Quoted 22 lines · Marek Vasut

On Saturday, December 26, 2015 at 04:48:57 PM, Wills Wang wrote:

[...]

Quoted 7 lines

Quoted 7 lines

The SPI flash is an IP block which just maps the SPI NOR into the address space, it doesn't use the CPU cache at all.

Maybe you don't even need to lock cachelines though, the AR9331 should have some internal SRAM, so just use that for stack. Do you have a proper datasheet for the Atheros MIPS chips ? I have some 320 pages datasheet for AR9331.

Quoted 5 lines

I don't find any description about internal SRAM in public datasheet. About mapping SPI flash, there is a doubt, who fetch the instruction from the SPI Nor flash to CPU pipe line when chip boot from SPI flash? I guess that ROM code handle cache exception and load instruction/date from SPI flash into cache.

I just pulled out the SPI NOR from the Arduino Yun I have here and connected an FPGA with SPI NOR emulator in there. All the chip does is it issues the fastread opcode to the SPI NOR when it boots. It does the same thing if you access the 0x9f000000..0x9fxxxxxx address range from the ancient U-Boot 1.1.x.

Quoted 7 lines

My impression is that the SPI NOR controller in the chip does a mapping between the SPI NOR and the memory mapped access to the 0x9fxxxxxx range. There is no caching involved in that, all of this is done internally in the SPI NOR block.

The mips24kc core should support locking cache lines , so if the SRAM is not available, this would have to do.

Ha, look at this [1]. risk @ #openwrt-devel at freenode pointed this location out (thanks!)

[1] https://github.com/pepe2k/u-boot_mod/blob/master/u-
boot/cpu/mips/start.S#L652

Best regards,
Marek Vasut

WASP is ar9341.

Quoted 33 lines · Marek Vasut

Quoted 31 lines · Wills Wang

[...]

Quoted 8 lines

Quoted 7 lines

The SPI flash is an IP block which just maps the SPI NOR into the address space, it doesn't use the CPU cache at all.

Maybe you don't even need to lock cachelines though, the AR9331 should have some internal SRAM, so just use that for stack. Do you have a proper datasheet for the Atheros MIPS chips ? I have some 320 pages datasheet for AR9331.

Quoted 5 lines

I don't find any description about internal SRAM in public datasheet. About mapping SPI flash, there is a doubt, who fetch the instruction from the SPI Nor flash to CPU pipe line when chip boot from SPI flash? I guess that ROM code handle cache exception and load instruction/date from SPI flash into cache.

I just pulled out the SPI NOR from the Arduino Yun I have here and connected an FPGA with SPI NOR emulator in there. All the chip does is it issues the fastread opcode to the SPI NOR when it boots. It does the same thing if you access the 0x9f000000..0x9fxxxxxx address range from the ancient U-Boot 1.1.x.

My impression is that the SPI NOR controller in the chip does a mapping between the SPI NOR and the memory mapped access to the 0x9fxxxxxx range. There is no caching involved in that, all of this is done internally in the SPI NOR block.

The mips24kc core should support locking cache lines , so if the SRAM is not available, this would have to do.

Quoted 8 lines

Ha, look at this [1]. risk @ #openwrt-devel at freenode pointed this location out (thanks!)

[1] https://github.com/pepe2k/u-boot_mod/blob/master/u-
boot/cpu/mips/start.S#L652

Best regards,
Marek Vasut

Quoted 1 line · Wills Wang

WASP is ar9341.

Please do not top post.

Did you try if the memory is accessible on your platform ? AR9331 I have here has the SRAM at 0xbd007000 , just like that machine in [1] .

Quoted 5 lines · Marek Vasut

Quoted 1 line · Wills Wang

WASP is ar9341.

Please do not top post.

Quoted 2 lines

Did you try if the memory is accessible on your platform ? AR9331 I have here has the SRAM at 0xbd007000 , just like that machine in [1] .

I found there is a memory segment at 0xbd000000...0xbd007fff. it's independent of DDR physical memory, can be read and wrote, but hardware can't boot up if don't execute lowlevel_init.S when define CONFIG_SYS_INIT_SP_ADDR=0xbd007000 to set C stack into SRAM.

Quoted 5 lines · Wills Wang

Quoted 4 lines · Marek Vasut

Quoted 1 line · Wills Wang

WASP is ar9341.

Please do not top post.

Quoted 6 lines

Quoted 2 lines

Did you try if the memory is accessible on your platform ? AR9331 I have here has the SRAM at 0xbd007000 , just like that machine in [1] .

I found there is a memory segment at 0xbd000000...0xbd007fff. it's independent of DDR physical memory, can be read and wrote, but hardware can't boot up if don't execute lowlevel_init.S when define CONFIG_SYS_INIT_SP_ADDR=0xbd007000 to set C stack into SRAM.

Stack grows down, so of course if you put stack at the beginning of SRAM, that cannot work ;-) Put it at the end , 0xbd008000.

Best regards,
Marek Vasut

Quoted 15 lines · Marek Vasut

Quoted 13 lines · Wills Wang

Quoted 7 lines · Marek Vasut

Quoted 1 line · Wills Wang

WASP is ar9341.

Please do not top post.

Did you try if the memory is accessible on your platform ? AR9331 I have here has the SRAM at 0xbd007000 , just like that machine in [1] .

I found there is a memory segment at 0xbd000000...0xbd007fff. it's independent of DDR physical memory, can be read and wrote, but hardware can't boot up if don't execute lowlevel_init.S when define CONFIG_SYS_INIT_SP_ADDR=0xbd007000 to set C stack into SRAM.

Quoted 2 lines

Stack grows down, so of course if you put stack at the beginning of SRAM, that cannot work ;-) Put it at the end , 0xbd008000.

This memory segment was mapped circularly at 0xbd000000...0xbdffffff.

Quoted 9 lines · Wills Wang

Quoted 8 lines · Marek Vasut

Quoted 7 lines · Wills Wang

Quoted 6 lines · Marek Vasut

Quoted 1 line · Wills Wang

WASP is ar9341.

Please do not top post.

Did you try if the memory is accessible on your platform ? AR9331 I have here has the SRAM at 0xbd007000 , just like that machine in [1] .

Quoted 7 lines

Quoted 6 lines

Quoted 4 lines

I found there is a memory segment at 0xbd000000...0xbd007fff. it's independent of DDR physical memory, can be read and wrote, but hardware can't boot up if don't execute lowlevel_init.S when define CONFIG_SYS_INIT_SP_ADDR=0xbd007000 to set C stack into SRAM.

Stack grows down, so of course if you put stack at the beginning of SRAM, that cannot work ;-) Put it at the end , 0xbd008000.

This memory segment was mapped circularly at 0xbd000000...0xbdffffff.

So is this area at 0xbd008000 usable for stack or not ?

Best regards,
Marek Vasut

Quoted 21 lines · Marek Vasut

Quoted 20 lines · Wills Wang

Quoted 18 lines · Marek Vasut

Quoted 6 lines · Wills Wang

Quoted 5 lines · Marek Vasut

Quoted 1 line · Wills Wang

WASP is ar9341.

Please do not top post.

Quoted 8 lines

Quoted 3 lines

Did you try if the memory is accessible on your platform ? AR9331 I have here has the SRAM at 0xbd007000 , just like that machine in [1] .

I found there is a memory segment at 0xbd000000...0xbd007fff. it's independent of DDR physical memory, can be read and wrote, but hardware can't boot up if don't execute lowlevel_init.S when define CONFIG_SYS_INIT_SP_ADDR=0xbd007000 to set C stack into SRAM.

Stack grows down, so of course if you put stack at the beginning of SRAM, that cannot work ;-) Put it at the end , 0xbd008000.

Quoted 3 lines

Quoted 1 line

This memory segment was mapped circularly at 0xbd000000...0xbdffffff.

So is this area at 0xbd008000 usable for stack or not ?

Same times board can boot up, but in a very unstable. i use the following setting:

#define CONFIG_SYS_INIT_RAM_ADDR 0xbd000000

#define CONFIG_SYS_INIT_RAM_SIZE (32 * SZ_1K)

#define CONFIG_SYS_INIT_SP_OFFSET \
(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_ADDR \
(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)

Quoted 16 lines · Wills Wang

Quoted 15 lines · Marek Vasut

Quoted 14 lines · Wills Wang

Quoted 13 lines · Marek Vasut

Quoted 12 lines · Wills Wang

Quoted 7 lines · Marek Vasut

Quoted 1 line · Wills Wang

WASP is ar9341.

Please do not top post.

Did you try if the memory is accessible on your platform ? AR9331 I have here has the SRAM at 0xbd007000 , just like that machine in [1] .

I found there is a memory segment at 0xbd000000...0xbd007fff. it's independent of DDR physical memory, can be read and wrote, but hardware can't boot up if don't execute lowlevel_init.S when define CONFIG_SYS_INIT_SP_ADDR=0xbd007000 to set C stack into SRAM.

Quoted 8 lines

Quoted 4 lines

Quoted 3 lines

Quoted 2 lines

Stack grows down, so of course if you put stack at the beginning of SRAM, that cannot work ;-) Put it at the end , 0xbd008000.

This memory segment was mapped circularly at 0xbd000000...0xbdffffff.

So is this area at 0xbd008000 usable for stack or not ?

Same times board can boot up, but in a very unstable. i use the following setting:

#define CONFIG_SYS_INIT_RAM_ADDR 0xbd000000

Should be 0xbd007000

Quoted 1 line

#define CONFIG_SYS_INIT_RAM_SIZE (32 * SZ_1K)

Should be 4 KiB large.

Quoted 4 lines

#define CONFIG_SYS_INIT_SP_OFFSET \
(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_ADDR \
(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)

Did you investigate why the board has problems ?

Best regards,
Marek Vasut

Quoted 42 lines · Marek Vasut

Quoted 22 lines · Wills Wang

Quoted 21 lines · Marek Vasut

Quoted 20 lines · Wills Wang

Quoted 18 lines · Marek Vasut

Quoted 6 lines · Wills Wang

Quoted 5 lines · Marek Vasut

Quoted 1 line · Wills Wang

WASP is ar9341.

Please do not top post.

Quoted 8 lines

Quoted 3 lines

Did you try if the memory is accessible on your platform ? AR9331 I have here has the SRAM at 0xbd007000 , just like that machine in
[1] .

I found there is a memory segment at 0xbd000000...0xbd007fff. it's independent of DDR physical memory, can be read and wrote, but hardware can't boot up if don't execute lowlevel_init.S when define CONFIG_SYS_INIT_SP_ADDR=0xbd007000 to set C stack into SRAM.

Stack grows down, so of course if you put stack at the beginning of SRAM, that cannot work ;-) Put it at the end , 0xbd008000.

Quoted 8 lines

Quoted 3 lines

Quoted 1 line

This memory segment was mapped circularly at 0xbd000000...0xbdffffff.

So is this area at 0xbd008000 usable for stack or not ?

Same times board can boot up, but in a very unstable. i use the following setting:

#define CONFIG_SYS_INIT_RAM_ADDR 0xbd000000

Should be 0xbd007000

Quoted 1 line

#define CONFIG_SYS_INIT_RAM_SIZE (32 * SZ_1K)

Should be 4 KiB large.

Quoted 4 lines

#define CONFIG_SYS_INIT_SP_OFFSET \

(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)

Quoted 5 lines

Quoted 3 lines

#define CONFIG_SYS_INIT_SP_ADDR \

(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)

Did you investigate why the board has problems ?

"lowlevel_init.S" can't be dropped.

Quoted 38 lines · Wills Wang

Quoted 37 lines · Marek Vasut

Quoted 16 lines · Wills Wang

Quoted 15 lines · Marek Vasut

Quoted 14 lines · Wills Wang

Quoted 13 lines · Marek Vasut

Quoted 12 lines · Wills Wang

Quoted 7 lines · Marek Vasut

Quoted 1 line · Wills Wang

WASP is ar9341.

Please do not top post.

Did you try if the memory is accessible on your platform ? AR9331 I have here has the SRAM at 0xbd007000 , just like that machine in
[1] .

I found there is a memory segment at 0xbd000000...0xbd007fff. it's independent of DDR physical memory, can be read and wrote, but hardware can't boot up if don't execute lowlevel_init.S when define CONFIG_SYS_INIT_SP_ADDR=0xbd007000 to set C stack into SRAM.

Quoted 8 lines

Quoted 4 lines

Quoted 3 lines

Quoted 2 lines

Stack grows down, so of course if you put stack at the beginning of SRAM, that cannot work ;-) Put it at the end , 0xbd008000.

This memory segment was mapped circularly at 0xbd000000...0xbdffffff.

So is this area at 0xbd008000 usable for stack or not ?

Same times board can boot up, but in a very unstable. i use the following setting:

#define CONFIG_SYS_INIT_RAM_ADDR 0xbd000000

Should be 0xbd007000

Quoted 1 line

#define CONFIG_SYS_INIT_RAM_SIZE (32 * SZ_1K)

Should be 4 KiB large.

Quoted 7 lines

#define CONFIG_SYS_INIT_SP_OFFSET \

(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)

#define CONFIG_SYS_INIT_SP_ADDR \

(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)

Quoted 2 lines

Quoted 1 line

Did you investigate why the board has problems ?

"lowlevel_init.S" can't be dropped.

Thank you very much for all the effort you put into investigating and explaining why this SRAM area cannot be used ... not. From my side, consider this patch to be NAKed.

Best regards,
Marek Vasut

Quoted 8 lines

Quoted 1 line

"lowlevel_init.S" can't be dropped.

Thank you very much for all the effort you put into investigating and explaining why this SRAM area cannot be used ... not. From my side, consider this patch to be NAKed.

Best regards,
Marek Vasut

"lowlevel_init.S" can't be entirely dropped, there are three main reasons for this.

1. Chip has an original issue, need reset "WLAN" three times to avoid it when power up.

2. Need reset RTC and force to wake MAC, or chip can't work .

3. Need initialise PLL clock for CPU/DDR/AHB, the default clock is 25MHz, the interval from
power-up to printout is about 5s.

So, assembler code could not be avoided even using SRAM for c stack.

Now that chipmaker don't open SRAM of this chip and recommend DDR for initial stack, i think
that using DDR should be more consolidated.

On Monday, December 28, 2015 at 12:17:41 PM, Wills Wang wrote:
[...]

Quoted 9 lines

Quoted 7 lines

Quoted 1 line

"lowlevel_init.S" can't be dropped.

Thank you very much for all the effort you put into investigating and explaining why this SRAM area cannot be used ... not. From my side, consider this patch to be NAKed.

Best regards,
Marek Vasut

"lowlevel_init.S" can't be entirely dropped, there are three main reasons for this.

Right, so I checked how these are performed and whether these can or cannot be done from C code.

Quoted 2 lines

1. Chip has an original issue, need reset "WLAN" three times to avoid it when power up.

26 /* These three wlan reset will avoid original issue, 27 so full chip reset isn't needed here. */

  28     set_reg(0xb806001c, 0x00c06b30)
  29     nop
  30     set_reg(0xb806001c, 0x00c06330)
  31     nop
  32     set_reg(0xb806001c, 0x00c06b30)
  33     nop
  34     set_reg(0xb806001c, 0x00c06330)
  35     nop
  36 reset_wlan:
  37     set_reg(0xb806001c, 0x00c06b30)
  38     nop
  39     set_reg(0xb806001c, 0x00c06330)
  40     nop

Yes, these can be done from C code.

Quoted 1 line

2. Need reset RTC and force to wake MAC, or chip can't work .

73 /* RTC reset */

  74     set_reg(0x1810704c, 0x00000003)
  75     nop
  76     nop
  77     set_reg(0x18107040, 0x00000000)
  78     nop
  79     nop
  80     set_reg(0x18107040, 0x00000001)
  81     nop

DTTO.

Quoted 3 lines

3. Need initialise PLL clock for CPU/DDR/AHB, the default clock is 25MHz, the interval from
power-up to printout is about 5s.

The PLL configuration is again a set of writes to some random registers. This can again be done from the C code.

Quoted 1 line

So, assembler code could not be avoided even using SRAM for c stack.

I am not convinced, see above. Please show me where exactly is the assembly code imperative. I simply do not see it.

Quoted 3 lines

Now that chipmaker don't open SRAM of this chip and recommend DDR for initial stack, i think
that using DDR should be more consolidated.

I do not care what the chip maker says unless there is an explicit explanation why they require that. Most often, these sorts of "limitations" are in place only because the chipmaker has incompetent software engineers.

So I would like to see either the SRAM or locked cacheline used for stack and then lowlevel init converted into proper C code unless there is an explicit explanation why this can not be done. And by explicit I mean for example a snippet of code which cannot be converted into C code. Note that asm volatile can still be used to contain such small bits of assembler code if needed be.

Best regards,
Marek Vasut

On Monday, December 28, 2015 at 12:17:41 PM, Wills Wang wrote:
[...]

Quoted 9 lines

Quoted 7 lines

Quoted 1 line

"lowlevel_init.S" can't be dropped.

Thank you very much for all the effort you put into investigating and explaining why this SRAM area cannot be used ... not. From my side, consider this patch to be NAKed.

Best regards,
Marek Vasut

"lowlevel_init.S" can't be entirely dropped, there are three main reasons for this.

Right, so I checked how these are performed and whether these can or cannot be done from C code.

Quoted 2 lines

1. Chip has an original issue, need reset "WLAN" three times to avoid it when power up.

26 /* These three wlan reset will avoid original issue, 27 so full chip reset isn't needed here. */

  28     set_reg(0xb806001c, 0x00c06b30)
  29     nop
  30     set_reg(0xb806001c, 0x00c06330)
  31     nop
  32     set_reg(0xb806001c, 0x00c06b30)
  33     nop
  34     set_reg(0xb806001c, 0x00c06330)
  35     nop
  36 reset_wlan:
  37     set_reg(0xb806001c, 0x00c06b30)
  38     nop
  39     set_reg(0xb806001c, 0x00c06330)
  40     nop

Yes, these can be done from C code.

Quoted 1 line

2. Need reset RTC and force to wake MAC, or chip can't work .

73 /* RTC reset */

  74     set_reg(0x1810704c, 0x00000003)
  75     nop
  76     nop
  77     set_reg(0x18107040, 0x00000000)
  78     nop
  79     nop
  80     set_reg(0x18107040, 0x00000001)
  81     nop

DTTO.

Quoted 3 lines

3. Need initialise PLL clock for CPU/DDR/AHB, the default clock is 25MHz, the interval from
power-up to printout is about 5s.

The PLL configuration is again a set of writes to some random registers. This can again be done from the C code.

Quoted 1 line

So, assembler code could not be avoided even using SRAM for c stack.

I am not convinced, see above. Please show me where exactly is the assembly code imperative. I simply do not see it.

Quoted 3 lines

Now that chipmaker don't open SRAM of this chip and recommend DDR for initial stack, i think
that using DDR should be more consolidated.

I do not care what the chip maker says unless there is an explicit explanation why they require that. Most often, these sorts of "limitations" are in place only because the chipmaker has incompetent software engineers.

So I would like to see either the SRAM or locked cacheline used for stack and then lowlevel init converted into proper C code unless there is an explicit explanation why this can not be done. And by explicit I mean for example a snippet of code which cannot be converted into C code. Note that asm volatile can still be used to contain such small bits of assembler code if needed be.

Best regards,
Marek Vasut

Quoted 81 lines · Marek Vasut

On Monday, December 28, 2015 at 12:17:41 PM, Wills Wang wrote:
[...]

Quoted 11 lines

Quoted 8 lines

Quoted 1 line

"lowlevel_init.S" can't be dropped.

Thank you very much for all the effort you put into investigating and explaining why this SRAM area cannot be used ... not. From my side, consider this patch to be NAKed.

Best regards,
Marek Vasut

"lowlevel_init.S" can't be entirely dropped, there are three main reasons for this.

Right, so I checked how these are performed and whether these can or cannot be done from C code.

Quoted 3 lines

1. Chip has an original issue, need reset "WLAN" three times to avoid it when power up.

26 /* These three wlan reset will avoid original issue, 27 so full chip reset isn't needed here. */

  28     set_reg(0xb806001c, 0x00c06b30)
  29     nop
  30     set_reg(0xb806001c, 0x00c06330)
  31     nop
  32     set_reg(0xb806001c, 0x00c06b30)
  33     nop
  34     set_reg(0xb806001c, 0x00c06330)
  35     nop
  36 reset_wlan:
  37     set_reg(0xb806001c, 0x00c06b30)
  38     nop
  39     set_reg(0xb806001c, 0x00c06330)
  40     nop

Yes, these can be done from C code.

Quoted 2 lines

2. Need reset RTC and force to wake MAC, or chip can't work .

73 /* RTC reset */

  74     set_reg(0x1810704c, 0x00000003)
  75     nop
  76     nop
  77     set_reg(0x18107040, 0x00000000)
  78     nop
  79     nop
  80     set_reg(0x18107040, 0x00000001)
  81     nop

DTTO.

Quoted 3 lines

3. Need initialise PLL clock for CPU/DDR/AHB, the default clock is 25MHz, the interval from
power-up to printout is about 5s.

The PLL configuration is again a set of writes to some random registers. This can again be done from the C code.

Quoted 1 line

So, assembler code could not be avoided even using SRAM for c stack.

I am not convinced, see above. Please show me where exactly is the assembly code imperative. I simply do not see it.

Quoted 3 lines

Now that chipmaker don't open SRAM of this chip and recommend DDR for initial stack, i think
that using DDR should be more consolidated.

I do not care what the chip maker says unless there is an explicit explanation why they require that. Most often, these sorts of "limitations" are in place only because the chipmaker has incompetent software engineers.

So I would like to see either the SRAM or locked cacheline used for stack and then lowlevel init converted into proper C code unless there is an explicit explanation why this can not be done. And by explicit I mean for example a snippet of code which cannot be converted into C code. Note that asm volatile can still be used to contain such small bits of assembler code if needed be.

Quoted 2 lines

Best regards,
Marek Vasut

I made a series of tries in this, i configure initial stack in SRAM and convert
these code to c, and put them in arch_cpu_init(the first available c entry), but
hardware don't work. if i keep the above three points(RESET/RTC/PLL) in lowlevel_init, put other code in arch_cpu_init, board work fine.

Quoted 85 lines · Marek Vasut

Quoted 81 lines · Wills Wang

[...]

Quoted 11 lines

Quoted 8 lines

Quoted 1 line

"lowlevel_init.S" can't be dropped.

Thank you very much for all the effort you put into investigating and explaining why this SRAM area cannot be used ... not. From my side, consider this patch to be NAKed.

Best regards,
Marek Vasut

"lowlevel_init.S" can't be entirely dropped, there are three main reasons for this.

Right, so I checked how these are performed and whether these can or cannot be done from C code.

Quoted 3 lines

1. Chip has an original issue, need reset "WLAN" three times to avoid it when power up.

26 /* These three wlan reset will avoid original issue, 27 so full chip reset isn't needed here. */

  28     set_reg(0xb806001c, 0x00c06b30)
  29     nop
  30     set_reg(0xb806001c, 0x00c06330)
  31     nop
  32     set_reg(0xb806001c, 0x00c06b30)
  33     nop
  34     set_reg(0xb806001c, 0x00c06330)
  35     nop
  36 reset_wlan:
  37     set_reg(0xb806001c, 0x00c06b30)
  38     nop
  39     set_reg(0xb806001c, 0x00c06330)
  40     nop

Yes, these can be done from C code.

Quoted 2 lines

2. Need reset RTC and force to wake MAC, or chip can't work .

73 /* RTC reset */

  74     set_reg(0x1810704c, 0x00000003)
  75     nop
  76     nop
  77     set_reg(0x18107040, 0x00000000)
  78     nop
  79     nop
  80     set_reg(0x18107040, 0x00000001)
  81     nop

DTTO.

Quoted 3 lines

3. Need initialise PLL clock for CPU/DDR/AHB, the default clock is 25MHz, the interval from
power-up to printout is about 5s.

The PLL configuration is again a set of writes to some random registers. This can again be done from the C code.

Quoted 1 line

So, assembler code could not be avoided even using SRAM for c stack.

I am not convinced, see above. Please show me where exactly is the assembly code imperative. I simply do not see it.

Quoted 3 lines

Now that chipmaker don't open SRAM of this chip and recommend DDR for initial stack, i think
that using DDR should be more consolidated.

I do not care what the chip maker says unless there is an explicit explanation why they require that. Most often, these sorts of "limitations" are in place only because the chipmaker has incompetent software engineers.

So I would like to see either the SRAM or locked cacheline used for stack and then lowlevel init converted into proper C code unless there is an explicit explanation why this can not be done. And by explicit I mean for example a snippet of code which cannot be converted into C code. Note that asm volatile can still be used to contain such small bits of assembler code if needed be.

Quoted 2 lines

Best regards,
Marek Vasut

Quoted 6 lines

I made a series of tries in this, i configure initial stack in SRAM and convert
these code to c, and put them in arch_cpu_init(the first available c entry), but
hardware don't work. if i keep the above three points(RESET/RTC/PLL) in lowlevel_init, put other code in arch_cpu_init, board work fine.

So let me ask the question again -- why does the C code not work ? Did you investigate the reason why does the C code not work ?

Can you share the change you did to convert things to C code ? There might be a bug in that too ...

Am 28.12.2015 um 16:52 schrieb Marek Vasut:

Quoted 96 lines · Wills Wang

Quoted 85 lines · Marek Vasut

Quoted 81 lines · Wills Wang

[...]

Quoted 11 lines

Quoted 8 lines

Quoted 1 line

"lowlevel_init.S" can't be dropped.

Thank you very much for all the effort you put into investigating and explaining why this SRAM area cannot be used ... not. From my side, consider this patch to be NAKed.

Best regards,
Marek Vasut

"lowlevel_init.S" can't be entirely dropped, there are three main reasons for this.

Right, so I checked how these are performed and whether these can or cannot be done from C code.

Quoted 3 lines

1. Chip has an original issue, need reset "WLAN" three times to avoid it when power up.

26 /* These three wlan reset will avoid original issue, 27 so full chip reset isn't needed here. */

  28     set_reg(0xb806001c, 0x00c06b30)
  29     nop
  30     set_reg(0xb806001c, 0x00c06330)
  31     nop
  32     set_reg(0xb806001c, 0x00c06b30)
  33     nop
  34     set_reg(0xb806001c, 0x00c06330)
  35     nop
  36 reset_wlan:
  37     set_reg(0xb806001c, 0x00c06b30)
  38     nop
  39     set_reg(0xb806001c, 0x00c06330)
  40     nop

Yes, these can be done from C code.

Quoted 2 lines

2. Need reset RTC and force to wake MAC, or chip can't work .

73 /* RTC reset */

  74     set_reg(0x1810704c, 0x00000003)
  75     nop
  76     nop
  77     set_reg(0x18107040, 0x00000000)
  78     nop
  79     nop
  80     set_reg(0x18107040, 0x00000001)
  81     nop

DTTO.

Quoted 3 lines

3. Need initialise PLL clock for CPU/DDR/AHB, the default clock is 25MHz, the interval from
power-up to printout is about 5s.

The PLL configuration is again a set of writes to some random registers. This can again be done from the C code.

Quoted 1 line

So, assembler code could not be avoided even using SRAM for c stack.

I am not convinced, see above. Please show me where exactly is the assembly code imperative. I simply do not see it.

Quoted 3 lines

Now that chipmaker don't open SRAM of this chip and recommend DDR for initial stack, i think
that using DDR should be more consolidated.

I do not care what the chip maker says unless there is an explicit explanation why they require that. Most often, these sorts of "limitations" are in place only because the chipmaker has incompetent software engineers.

So I would like to see either the SRAM or locked cacheline used for stack and then lowlevel init converted into proper C code unless there is an explicit explanation why this can not be done. And by explicit I mean for example a snippet of code which cannot be converted into C code. Note that asm volatile can still be used to contain such small bits of assembler code if needed be.

Quoted 2 lines

Best regards,
Marek Vasut

Quoted 6 lines

I made a series of tries in this, i configure initial stack in SRAM and convert
these code to c, and put them in arch_cpu_init(the first available c entry), but
hardware don't work. if i keep the above three points(RESET/RTC/PLL) in lowlevel_init, put other code in arch_cpu_init, board work fine.

So let me ask the question again -- why does the C code not work ? Did you investigate the reason why does the C code not work ?

Quoted 2 lines

Can you share the change you did to convert things to C code ? There might be a bug in that too ...

it is not a matter of C or assembly, but of the init sequence currently implemented on MIPS. The main purpose of lowlevel_init() is to initialize memory controllers and DRAM. This has to be done in assembly because we have no C runtime environment available at that point.

Also compiling U-Boot as PIC requires to enable MIPS ABI function calls in gcc (-mabicalls). This always creates function prologues and epilogues which are utilizing the stack pointer. Thus we cannot simply convert all lowlevel_init functions to C.

Moving code from lowlevel_init to arch_cpu_init or elsewhere will not work because that code runs too late then. Simply moving the stack to SRAM will also not help because lowlevel_init runs before the stack is available.

Before Wills can convert his code to C, we need to rework the init sequence in start.S. But that is out of the scope of this patch series. I will try to prepare some patches in the next days. The SRAM part should be easy. But the cache line lock need some more work and testing.

In the meantime Wills could send a new patch series, which addresses all other issues except lowlevel_init. The function ddr_tap_init can be already converted to C because it is called from init_dram where a C runtime environment is available. So we could have at least a working patch series and could finalize the review of the other patches. After I have updated u-boot-mips/next branch, Wills can rebase and convert lowlevel_init to C.

Quoted 22 lines · Marek Vasut

Quoted 21 lines · Wills Wang

Quoted 20 lines · Marek Vasut

Quoted 18 lines · Wills Wang

Quoted 6 lines · Marek Vasut

Quoted 5 lines · Wills Wang

Quoted 1 line

WASP is ar9341.

Please do not top post.

Quoted 8 lines

Quoted 3 lines

Did you try if the memory is accessible on your platform ? AR9331 I have here has the SRAM at 0xbd007000 , just like that machine in [1] .

I found there is a memory segment at 0xbd000000...0xbd007fff. it's independent of DDR physical memory, can be read and wrote, but hardware can't boot up if don't execute lowlevel_init.S when define CONFIG_SYS_INIT_SP_ADDR=0xbd007000 to set C stack into SRAM.

Stack grows down, so of course if you put stack at the beginning of SRAM, that cannot work ;-) Put it at the end , 0xbd008000.

Quoted 8 lines

Quoted 3 lines

Quoted 1 line

This memory segment was mapped circularly at 0xbd000000...0xbdffffff.

So is this area at 0xbd008000 usable for stack or not ?

Same times board can boot up, but in a very unstable. i use the following setting:

#define CONFIG_SYS_INIT_RAM_ADDR 0xbd000000

Should be 0xbd007000

Quoted 1 line

#define CONFIG_SYS_INIT_RAM_SIZE (32 * SZ_1K)

Should be 4 KiB large.

Quoted 4 lines

#define CONFIG_SYS_INIT_SP_OFFSET \
(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_ADDR \
(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)

Did you investigate why the board has problems ?

Am 27.12.2015 um 12:04 schrieb Marek Vasut:

Quoted 40 lines · Wills Wang

Quoted 22 lines · Marek Vasut

Quoted 21 lines · Wills Wang

Quoted 20 lines · Marek Vasut

Quoted 18 lines · Wills Wang

Quoted 6 lines · Marek Vasut

Quoted 5 lines · Wills Wang

Quoted 1 line

WASP is ar9341.

Please do not top post.

Quoted 8 lines

Quoted 3 lines

Did you try if the memory is accessible on your platform ? AR9331 I have here has the SRAM at 0xbd007000 , just like that machine in
[1] .

I found there is a memory segment at 0xbd000000...0xbd007fff. it's independent of DDR physical memory, can be read and wrote, but hardware can't boot up if don't execute lowlevel_init.S when define CONFIG_SYS_INIT_SP_ADDR=0xbd007000 to set C stack into SRAM.

Stack grows down, so of course if you put stack at the beginning of SRAM, that cannot work ;-) Put it at the end , 0xbd008000.

Quoted 8 lines

Quoted 3 lines

Quoted 1 line

This memory segment was mapped circularly at 0xbd000000...0xbdffffff.

So is this area at 0xbd008000 usable for stack or not ?

Same times board can boot up, but in a very unstable. i use the following setting:

#define CONFIG_SYS_INIT_RAM_ADDR 0xbd000000

Should be 0xbd007000

Quoted 1 line

#define CONFIG_SYS_INIT_RAM_SIZE (32 * SZ_1K)

Should be 4 KiB large.

Quoted 2 lines

#define CONFIG_SYS_INIT_SP_OFFSET \

Quoted 7 lines

Quoted 5 lines

(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)

#define CONFIG_SYS_INIT_SP_ADDR \

(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)

Did you investigate why the board has problems ?

according to the description above by Wills those three defines setup the values correctly for start.S:

#define CONFIG_SYS_INIT_RAM_ADDR 0xbd000000
#define CONFIG_SYS_INIT_RAM_SIZE (32 * SZ_1K)
#define CONFIG_SYS_INIT_SP_ADDR \
(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE)

The stack pointer will then be set to the end of the SRAM area with a 16 Byte alignment. The resulting address should be 0xbd007ff0. From this address, the size of gd_t and CONFIG_SYS_MALLOC_F_LEN will be subtracted. The remaining space is available for the initial stack.

Which value did you chose for CONFIG_SYS_MALLOC_F_LEN? It must be big enough to satisfy all malloc requests by the DM stack and small enough to fit in 32k minus stack size and gd_t size.

Important note: do net set CONFIG_SKIP_LOWLEVEL_INIT yet because that leaves you without initialized RAM or caches. If the setup does not work yet, you likely need to init some extra bits to make the SRAM working.

Am 27.12.2015 um 12:04 schrieb Marek Vasut:

Quoted 27 lines · Wills Wang

Quoted 16 lines · Marek Vasut

Quoted 15 lines · Wills Wang

Quoted 14 lines · Marek Vasut

Quoted 13 lines · Wills Wang

Quoted 12 lines · Marek Vasut

Quoted 7 lines · Wills Wang

Quoted 1 line

WASP is ar9341.

Please do not top post.

Did you try if the memory is accessible on your platform ? AR9331 I have here has the SRAM at 0xbd007000 , just like that machine in [1] .

I found there is a memory segment at 0xbd000000...0xbd007fff. it's independent of DDR physical memory, can be read and wrote, but hardware can't boot up if don't execute lowlevel_init.S when define CONFIG_SYS_INIT_SP_ADDR=0xbd007000 to set C stack into SRAM.

Quoted 8 lines

Quoted 4 lines

Quoted 3 lines

Quoted 2 lines

Stack grows down, so of course if you put stack at the beginning of SRAM, that cannot work ;-) Put it at the end , 0xbd008000.

This memory segment was mapped circularly at 0xbd000000...0xbdffffff.

So is this area at 0xbd008000 usable for stack or not ?

Same times board can boot up, but in a very unstable. i use the following setting:

#define CONFIG_SYS_INIT_RAM_ADDR 0xbd000000

Should be 0xbd007000

Quoted 9 lines

Quoted 1 line

#define CONFIG_SYS_INIT_RAM_SIZE (32 * SZ_1K)

Should be 4 KiB large.

Quoted 4 lines

#define CONFIG_SYS_INIT_SP_OFFSET \
(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_ADDR \
(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)

Did you investigate why the board has problems ?

according to the description above by Wills those three defines setup the values correctly for start.S:

#define CONFIG_SYS_INIT_RAM_ADDR 0xbd000000
#define CONFIG_SYS_INIT_RAM_SIZE (32 * SZ_1K)
#define CONFIG_SYS_INIT_SP_ADDR \
(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE)

The stack pointer will then be set to the end of the SRAM area with a 16 Byte alignment. The resulting address should be 0xbd007ff0. From this address, the size of gd_t and CONFIG_SYS_MALLOC_F_LEN will be subtracted. The remaining space is available for the initial stack.

Which value did you chose for CONFIG_SYS_MALLOC_F_LEN? It must be big enough to satisfy all malloc requests by the DM stack and small enough to fit in 32k minus stack size and gd_t size.

Important note: do net set CONFIG_SKIP_LOWLEVEL_INIT yet because that leaves you without initialized RAM or caches. If the setup does not work yet, you likely need to init some extra bits to make the SRAM working.

drivers/serial/serial_ar933x.c new file +54 -0

+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct ar933x_serial_baudrate{
+	u32 baudrate;
+	u32 scale;
+	u32 step;
+};
+
+const struct ar933x_serial_baudrate baudrate_table_40mhz[] = {
+/*  baudrate,   scale,  step */
+	{600,       255,    503},
+	{1200,      249,    983},
+	{2400,      167,    1321},
+	{4800,      87,     1384},
+	{9600,      45,     1447},
+	{14400,     53,     2548},
+	{19200,     22,     1447},
+	{28800,     26,     2548},
+	{38400,     28,     3649},
+	{56000,     7,      1468},
+	{57600,     34,     6606},
+	{115200,    28,     10947},
+	{128000,    6,      2936},
+	{153600,    18,     9563},
+	{230400,    16,     12834},
+	{250000,    4,      4096},
+	{256000,    6,      5872},
+	{460800,    7,      12079},
+	{576000,    4,      9437},
+	{921600,    3,      12079},
+	{1000000,   2,      9830},
+	{1152000,   2,      11324},
+	{1500000,   0,      4915},
+	{2000000,   0,      6553},
+ };
+
+const struct ar933x_serial_baudrate baudrate_table_25mhz[] = {
+/*  baudrate,   scale,  step */
+	{600,       255,    805},
+	{1200,      209,    1321},
+	{2400,      104,    1321},
+	{4800,      54,     1384},
+	{9600,      78,     3976},
+	{14400,     98,     7474},
+	{19200,     55,     5637},
+	{28800,     77,     11777},
+	{38400,     36,     7449},
+	{56000,     4,      1468},
+	{57600,     35,     10871},
+	{115200,    20,     12683},
+	{128000,    11,     8053},
+	{153600,    9,      8053},
+	{230400,    9,      12079},

drivers/serial/serial_ar933x.c new file +5 -0

+static int ar933x_serial_init(void)
+{
+	u32 val;
+
+	/*

drivers/serial/serial_ar933x.c new file +19 -0

+
+	/*
+	 * UART controller configuration:
+	 * - no DMA
+	 * - no interrupt
+	 * - DCE mode
+	 * - no flow control
+	 * - set RX ready oride
+	 * - set TX ready oride
+	 */
+	val = AR933X_UART_CS_TX_READY_ORIDE | AR933X_UART_CS_RX_READY_ORIDE
+		| (AR933X_UART_CS_IF_MODE_DCE << AR933X_UART_CS_IF_MODE_S);
+	ar933x_write(AR933X_UART_BASE, AR933X_UART_CS_REG, val);
+	return 0;
+}
+
+#ifdef CONFIG_DM_SERIAL
+static int ar933x_serial_setbrg(struct udevice *dev, int baudrate)
+{

drivers/serial/serial_ar933x.c new file +8 -0

+	if (val & AR933X_BOOTSTRAP_REF_CLK_40) {
+		baudrate_table = baudrate_table_40mhz;
+		baudrate_table_size = ARRAY_SIZE(baudrate_table_40mhz);
+		scale = (40000000 / (16 * baudrate)) - 1;
+		step = 8192;
+	} else {
+		baudrate_table = baudrate_table_25mhz;
+		baudrate_table_size = ARRAY_SIZE(baudrate_table_25mhz);

drivers/serial/serial_ar933x.c new file +9 -0

+	val |= ((step & AR933X_UART_CLOCK_STEP_M)
+			<< AR933X_UART_CLOCK_STEP_S);
+	ar933x_write(AR933X_UART_BASE, AR933X_UART_CLOCK_REG, val);
+#ifdef CONFIG_DM_SERIAL
+	return 0;
+#endif
+}
+
+#ifdef CONFIG_DM_SERIAL

drivers/serial/serial_ar933x.c new file +9 -0

+
+	data  = (u32)c | AR933X_UART_DATA_TX_CSR;
+	ar933x_write(AR933X_UART_BASE, AR933X_UART_DATA_REG, data);
+#ifdef CONFIG_DM_SERIAL
+	return 0;
+#endif
+}
+
+#ifdef CONFIG_DM_SERIAL

drivers/serial/serial_ar933x.c new file +34 -0

+
+	data = ar933x_read(AR933X_UART_BASE, AR933X_UART_DATA_REG);
+	ar933x_write(AR933X_UART_BASE, AR933X_UART_DATA_REG, AR933X_UART_DATA_RX_CSR);
+	return data & AR933X_UART_DATA_TX_RX_MASK;
+}
+
+#ifdef CONFIG_DM_SERIAL
+static int ar933x_serial_pending(struct udevice *dev, bool input)
+{
+	u32 data;
+
+	data = ar933x_read(AR933X_UART_BASE, AR933X_UART_DATA_REG);
+	if (input)
+		return (data & AR933X_UART_DATA_RX_CSR) ? 1 : 0;
+	else
+		return (data & AR933X_UART_DATA_TX_CSR) ? 0 : 1;
+}
+
+static int ar933x_serial_probe(struct udevice *dev)
+{
+	ar933x_serial_init();
+	return 0;
+}
+
+static const struct dm_serial_ops ar933x_serial_ops = {
+	.putc = ar933x_serial_putc,
+	.pending = ar933x_serial_pending,
+	.getc = ar933x_serial_getc,
+	.setbrg = ar933x_serial_setbrg,
+};
+
+static const struct udevice_id ar933x_serial_ids[] = {
+	{ .compatible = "ath79,ar933x-uart" },
+	{ }

Hi Wills,

Is there any reason that you need to support pre-DM serial driver? It should be safe to support DM only. You may add debug_uart support which might be helpful during debug. The ops for DM serial is different to pre-DM though the name look similar. Please see the comments below.

I worked on mips before I moved to nios very long ago (20 yr). And nios2 mostly followed mips.

I understand there is not device tree control for u-boot on mips yet. But I added it to nios2 recently. It might be worthy if you could add it to mips. You may find the dts binding on Linux kernel. And please add dts binding to doc/ and you might copy them from Linux kernel.

drivers/serial/serial_ar933x.c line 16

Quoted 10 lines

drivers/serial/serial_ar933x.c new file +10 -0

+
+#include <common.h>
+#include <serial.h>
+#include <dm.h>
+#include <errno.h>
+#include <asm/io.h>
+#include <asm/addrspace.h>
+#include <asm/types.h>
+#include <asm/arch/ar71xx_regs.h>
+#include <asm/arch/ar933x_uart.h>

Please sort the sequence of header files inclusion.

Quoted 54 lines

drivers/serial/serial_ar933x.c new file +54 -0

+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct ar933x_serial_baudrate{
+    u32 baudrate;
+    u32 scale;
+    u32 step;
+};
+
+const struct ar933x_serial_baudrate baudrate_table_40mhz[] = {
+/*  baudrate,   scale,  step */
+    {600,       255,    503},
+    {1200,      249,    983},
+    {2400,      167,    1321},
+    {4800,      87,     1384},
+    {9600,      45,     1447},
+    {14400,     53,     2548},
+    {19200,     22,     1447},
+    {28800,     26,     2548},
+    {38400,     28,     3649},
+    {56000,     7,      1468},
+    {57600,     34,     6606},
+    {115200,    28,     10947},
+    {128000,    6,      2936},
+    {153600,    18,     9563},
+    {230400,    16,     12834},
+    {250000,    4,      4096},
+    {256000,    6,      5872},
+    {460800,    7,      12079},
+    {576000,    4,      9437},
+    {921600,    3,      12079},
+    {1000000,   2,      9830},
+    {1152000,   2,      11324},
+    {1500000,   0,      4915},
+    {2000000,   0,      6553},
+ };
+
+const struct ar933x_serial_baudrate baudrate_table_25mhz[] = {
+/*  baudrate,   scale,  step */
+    {600,       255,    805},
+    {1200,      209,    1321},
+    {2400,      104,    1321},
+    {4800,      54,     1384},
+    {9600,      78,     3976},
+    {14400,     98,     7474},
+    {19200,     55,     5637},
+    {28800,     77,     11777},
+    {38400,     36,     7449},
+    {56000,     4,      1468},
+    {57600,     35,     10871},
+    {115200,    20,     12683},
+    {128000,    11,     8053},
+    {153600,    9,      8053},
+    {230400,    9,      12079},

drivers/serial/serial_ar933x.c line 80

Quoted 10 lines

drivers/serial/serial_ar933x.c new file +10 -0

+    {250000,    6,      9175},
+    {256000,    5,      8053},
+    {460800,    4,      12079},
+    {576000,    3,      12079},
+    {921600,    1,      9663},
+    {1000000,   1,      10485},
+    {1152000,   1,      12079},
+    {1500000,   0,      7864},
+    {2000000,   0,      10485},
+};

The requirement of u-boot is much simpler than Linux kernel. For the uart header, you should include only the macros that the driver really used. Or you can add it to the driver directly without the additional header file. The same rule applies to the baudrate tables. You need only some practical rates, not every possible one.

drivers/serial/serial_ar933x.c line 91

Quoted 11 lines

drivers/serial/serial_ar933x.c new file +11 -0

+
+static inline u32 ar933x_read(u32 base, u32 offset)
+{
+    return readl(KSEG1ADDR(base + offset));
+}
+
+static inline void ar933x_write(u32 base, u32 offset, u32 val)
+{
+    writel(val, KSEG1ADDR(base + offset));
+}
+

For the KSEG1ADDR mapping, which Marek also mentioned, I would suggest rework map_physmem() in asm/io.h on mips to map K1 kernel space, which is very similar to ioremap() on Linux kernel. So that you don't need to map it for every IO.

plat->regs = map_physmem(dev_get_addr(dev),
sizeof(...),
MAP_NOCACHE);

Quoted 5 lines

drivers/serial/serial_ar933x.c new file +5 -0

+static int ar933x_serial_init(void)
+{
+    u32 val;
+
+    /*

drivers/serial/serial_ar933x.c line 106

Quoted 10 lines

drivers/serial/serial_ar933x.c new file +10 -0

+     * Set GPIO10 (UART_SO) as output and enable UART,
+     * BIT(15) in GPIO_FUNCTION_1 register must be written with 1
+     */
+    val = ar933x_read(AR71XX_GPIO_BASE, AR71XX_GPIO_REG_OE);
+    val |= BIT(10);
+    ar933x_write(AR71XX_GPIO_BASE, AR71XX_GPIO_REG_OE, val);
+
+    val = ar933x_read(AR71XX_GPIO_BASE, AR71XX_GPIO_REG_FUNC);
+    val |= (AR933X_GPIO_FUNC_UART_EN | BIT(15));
+    ar933x_write(AR71XX_GPIO_BASE, AR71XX_GPIO_REG_FUNC, val);

These might go to the pinctrl driver or board initialization.

Quoted 19 lines

drivers/serial/serial_ar933x.c new file +19 -0

+
+    /*
+     * UART controller configuration:
+     * - no DMA
+     * - no interrupt
+     * - DCE mode
+     * - no flow control
+     * - set RX ready oride
+     * - set TX ready oride
+     */
+    val = AR933X_UART_CS_TX_READY_ORIDE | AR933X_UART_CS_RX_READY_ORIDE
+        | (AR933X_UART_CS_IF_MODE_DCE << AR933X_UART_CS_IF_MODE_S);
+    ar933x_write(AR933X_UART_BASE, AR933X_UART_CS_REG, val);
+    return 0;
+}
+
+#ifdef CONFIG_DM_SERIAL
+static int ar933x_serial_setbrg(struct udevice *dev, int baudrate)
+{

drivers/serial/serial_ar933x.c line 135

Quoted 10 lines

drivers/serial/serial_ar933x.c new file +10 -0

+#else
+static void ar933x_serial_setbrg(void)
+{
+    int baudrate = gd->baudrate;
+#endif
+    u32 val, scale, step;
+    const struct ar933x_serial_baudrate *baudrate_table;
+    int i, baudrate_table_size;
+
+    val = ar933x_read(AR71XX_RESET_BASE, AR933X_RESET_REG_BOOTSTRAP);

This can go to some clock rate in board info during board initialization.

Quoted 8 lines

drivers/serial/serial_ar933x.c new file +8 -0

+    if (val & AR933X_BOOTSTRAP_REF_CLK_40) {
+        baudrate_table = baudrate_table_40mhz;
+        baudrate_table_size = ARRAY_SIZE(baudrate_table_40mhz);
+        scale = (40000000 / (16 * baudrate)) - 1;
+        step = 8192;
+    } else {
+        baudrate_table = baudrate_table_25mhz;
+        baudrate_table_size = ARRAY_SIZE(baudrate_table_25mhz);

drivers/serial/serial_ar933x.c line 153

Quoted 10 lines

drivers/serial/serial_ar933x.c new file +10 -0

+        scale = (25000000 / (16 * baudrate)) - 1;
+        step = 8192;
+    }
+
+    for (i = 0; i < baudrate_table_size; i++) {
+        if (baudrate_table[i].baudrate == gd->baudrate) {
+            scale = baudrate_table[i].scale;
+            step = baudrate_table[i].step;
+        }
+    }

What happens if not found?

drivers/serial/serial_ar933x.c line 156

Quoted 4 lines

drivers/serial/serial_ar933x.c new file +3 -0

+
+    val  = ((scale & AR933X_UART_CLOCK_SCALE_M)
+            << AR933X_UART_CLOCK_SCALE_S);

The outer parenthesis is not needed.

Quoted 9 lines

drivers/serial/serial_ar933x.c new file +9 -0

+    val |= ((step & AR933X_UART_CLOCK_STEP_M)
+            << AR933X_UART_CLOCK_STEP_S);
+    ar933x_write(AR933X_UART_BASE, AR933X_UART_CLOCK_REG, val);
+#ifdef CONFIG_DM_SERIAL
+    return 0;
+#endif
+}
+
+#ifdef CONFIG_DM_SERIAL

drivers/serial/serial_ar933x.c line 175

Quoted 10 lines

drivers/serial/serial_ar933x.c new file +10 -0

+static int ar933x_serial_putc(struct udevice *dev, const char c)
+#else
+static void ar933x_serial_putc(const char c)
+#endif
+{
+    u32 data;
+
+    if (c == '\n')
+#ifdef CONFIG_DM_SERIAL
+        ar933x_serial_putc(dev, '\r');

Not needed for DM serial.

drivers/serial/serial_ar933x.c line 181

Quoted 6 lines

drivers/serial/serial_ar933x.c new file +6 -0

+#else
+        ar933x_serial_putc('\r');
+#endif
+    do {
+        data = ar933x_read(AR933X_UART_BASE, AR933X_UART_DATA_REG);
+    } while (!(data & AR933X_UART_DATA_TX_CSR));

Return -EAGAIN if not ready for DM serial.

Quoted 9 lines

drivers/serial/serial_ar933x.c new file +9 -0

+
+    data  = (u32)c | AR933X_UART_DATA_TX_CSR;
+    ar933x_write(AR933X_UART_BASE, AR933X_UART_DATA_REG, data);
+#ifdef CONFIG_DM_SERIAL
+    return 0;
+#endif
+}
+
+#ifdef CONFIG_DM_SERIAL

drivers/serial/serial_ar933x.c line 200

Quoted 10 lines

drivers/serial/serial_ar933x.c new file +10 -0

+static int ar933x_serial_getc(struct udevice *dev)
+#else
+static int ar933x_serial_getc(void)
+#endif
+{
+    u32 data;
+
+    do {
+        data = ar933x_read(AR933X_UART_BASE, AR933X_UART_DATA_REG);
+    } while (!(data & AR933X_UART_DATA_RX_CSR));

Return -EAGAIN if no data available for DM serial.

Quoted 41 lines

drivers/serial/serial_ar933x.c new file +3 -0

+
+    data = ar933x_read(AR933X_UART_BASE, AR933X_UART_DATA_REG);
+    ar933x_write(AR933X_UART_BASE, AR933X_UART_DATA_REG, 

AR933X_UART_DATA_RX_CSR);

drivers/serial/serial_ar933x.c new file +37 -0

+    return data & AR933X_UART_DATA_TX_RX_MASK;
+}
+
+#ifdef CONFIG_DM_SERIAL
+static int ar933x_serial_pending(struct udevice *dev, bool input)
+{
+    u32 data;
+
+    data = ar933x_read(AR933X_UART_BASE, AR933X_UART_DATA_REG);
+    if (input)
+        return (data & AR933X_UART_DATA_RX_CSR) ? 1 : 0;
+    else
+        return (data & AR933X_UART_DATA_TX_CSR) ? 0 : 1;
+}
+
+static int ar933x_serial_probe(struct udevice *dev)
+{
+    ar933x_serial_init();
+    return 0;
+}
+
+static const struct dm_serial_ops ar933x_serial_ops = {
+    .putc = ar933x_serial_putc,
+    .pending = ar933x_serial_pending,
+    .getc = ar933x_serial_getc,
+    .setbrg = ar933x_serial_setbrg,
+};
+
+static const struct udevice_id ar933x_serial_ids[] = {
+    { .compatible = "ath79,ar933x-uart" },
+    { }
+};
+
+U_BOOT_DRIVER(serial_ar933x) = {
+    .name   = "serial_ar933x",
+    .id = UCLASS_SERIAL,
+    .of_match = ar933x_serial_ids,

drivers/serial/serial_ar933x.c line 244

Quoted 4 lines

drivers/serial/serial_ar933x.c new file +4 -0

+    .probe = ar933x_serial_probe,
+    .ops    = &ar933x_serial_ops,
+    .flags = DM_FLAG_PRE_RELOC,
+};

I understand there might be only a single UART on the ar9331. But it might be better to bind the reg address with U_BOOT_DEVICE() and platform data, or better dts.

Thanks.

Best regards,
Thomas

Quoted 8 lines · Thomas Chou

Hi Wills,

Is there any reason that you need to support pre-DM serial driver? It should be safe to support DM only. You may add debug_uart support which might be helpful during debug. The ops for DM serial is different to pre-DM though the name look similar. Please see the comments below.

I will remove the code about pre-DM serial driver.

Quoted 3 lines

I worked on mips before I moved to nios very long ago (20 yr). And nios2 mostly followed mips.

Quoted 5 lines

I understand there is not device tree control for u-boot on mips yet. But I added it to nios2 recently. It might be worthy if you could add it to mips. You may find the dts binding on Linux kernel. And please add dts binding to doc/ and you might copy them from Linux kernel.

I has taken a long time to add base device tree for this patch, but i can't get the driver serial number if don't specify explicitly "aliases" section in dts file. but It seems to not need for ARM device.

Quoted 1 line

Quoted 1 line

+

Quoted 100 lines

drivers/serial/serial_ar933x.c line 16

Quoted 9 lines

drivers/serial/serial_ar933x.c new file +9 -0

+#include <common.h>
+#include <serial.h>
+#include <dm.h>
+#include <errno.h>
+#include <asm/io.h>
+#include <asm/addrspace.h>
+#include <asm/types.h>
+#include <asm/arch/ar71xx_regs.h>
+#include <asm/arch/ar933x_uart.h>

Please sort the sequence of header files inclusion.

Quoted 54 lines

drivers/serial/serial_ar933x.c new file +54 -0

+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct ar933x_serial_baudrate{
+    u32 baudrate;
+    u32 scale;
+    u32 step;
+};
+
+const struct ar933x_serial_baudrate baudrate_table_40mhz[] = {
+/*  baudrate,   scale,  step */
+    {600,       255,    503},
+    {1200,      249,    983},
+    {2400,      167,    1321},
+    {4800,      87,     1384},
+    {9600,      45,     1447},
+    {14400,     53,     2548},
+    {19200,     22,     1447},
+    {28800,     26,     2548},
+    {38400,     28,     3649},
+    {56000,     7,      1468},
+    {57600,     34,     6606},
+    {115200,    28,     10947},
+    {128000,    6,      2936},
+    {153600,    18,     9563},
+    {230400,    16,     12834},
+    {250000,    4,      4096},
+    {256000,    6,      5872},
+    {460800,    7,      12079},
+    {576000,    4,      9437},
+    {921600,    3,      12079},
+    {1000000,   2,      9830},
+    {1152000,   2,      11324},
+    {1500000,   0,      4915},
+    {2000000,   0,      6553},
+ };
+
+const struct ar933x_serial_baudrate baudrate_table_25mhz[] = {
+/*  baudrate,   scale,  step */
+    {600,       255,    805},
+    {1200,      209,    1321},
+    {2400,      104,    1321},
+    {4800,      54,     1384},
+    {9600,      78,     3976},
+    {14400,     98,     7474},
+    {19200,     55,     5637},
+    {28800,     77,     11777},
+    {38400,     36,     7449},
+    {56000,     4,      1468},
+    {57600,     35,     10871},
+    {115200,    20,     12683},
+    {128000,    11,     8053},
+    {153600,    9,      8053},
+    {230400,    9,      12079},

drivers/serial/serial_ar933x.c line 80

Quoted 10 lines

drivers/serial/serial_ar933x.c new file +10 -0

+    {250000,    6,      9175},
+    {256000,    5,      8053},
+    {460800,    4,      12079},
+    {576000,    3,      12079},
+    {921600,    1,      9663},
+    {1000000,   1,      10485},
+    {1152000,   1,      12079},
+    {1500000,   0,      7864},
+    {2000000,   0,      10485},
+};

The requirement of u-boot is much simpler than Linux kernel. For the uart header, you should include only the macros that the driver really used. Or you can add it to the driver directly without the additional header file. The same rule applies to the baudrate tables. You need only some practical rates, not every possible one.

drivers/serial/serial_ar933x.c line 91

Quoted 11 lines

drivers/serial/serial_ar933x.c new file +11 -0

+
+static inline u32 ar933x_read(u32 base, u32 offset)
+{
+    return readl(KSEG1ADDR(base + offset));
+}
+
+static inline void ar933x_write(u32 base, u32 offset, u32 val)
+{
+    writel(val, KSEG1ADDR(base + offset));
+}
+

For the KSEG1ADDR mapping, which Marek also mentioned, I would suggest rework map_physmem() in asm/io.h on mips to map K1 kernel space, which is very similar to ioremap() on Linux kernel. So that you don't need to map it for every IO.

Quoted 4 lines

plat->regs = map_physmem(dev_get_addr(dev),
sizeof(...),
MAP_NOCACHE);

In MIPS, function "map_physmem" is empty.

Quoted 69 lines

Quoted 5 lines

drivers/serial/serial_ar933x.c new file +5 -0

+static int ar933x_serial_init(void)
+{
+    u32 val;
+
+    /*

drivers/serial/serial_ar933x.c line 106

Quoted 10 lines

drivers/serial/serial_ar933x.c new file +10 -0

+     * Set GPIO10 (UART_SO) as output and enable UART,
+     * BIT(15) in GPIO_FUNCTION_1 register must be written with 1
+     */
+    val = ar933x_read(AR71XX_GPIO_BASE, AR71XX_GPIO_REG_OE);
+    val |= BIT(10);
+    ar933x_write(AR71XX_GPIO_BASE, AR71XX_GPIO_REG_OE, val);
+
+    val = ar933x_read(AR71XX_GPIO_BASE, AR71XX_GPIO_REG_FUNC);
+    val |= (AR933X_GPIO_FUNC_UART_EN | BIT(15));
+    ar933x_write(AR71XX_GPIO_BASE, AR71XX_GPIO_REG_FUNC, val);

These might go to the pinctrl driver or board initialization.

Quoted 19 lines

drivers/serial/serial_ar933x.c new file +19 -0

+
+    /*
+     * UART controller configuration:
+     * - no DMA
+     * - no interrupt
+     * - DCE mode
+     * - no flow control
+     * - set RX ready oride
+     * - set TX ready oride
+     */
+    val = AR933X_UART_CS_TX_READY_ORIDE | AR933X_UART_CS_RX_READY_ORIDE
+        | (AR933X_UART_CS_IF_MODE_DCE << AR933X_UART_CS_IF_MODE_S);
+    ar933x_write(AR933X_UART_BASE, AR933X_UART_CS_REG, val);
+    return 0;
+}
+
+#ifdef CONFIG_DM_SERIAL
+static int ar933x_serial_setbrg(struct udevice *dev, int baudrate)
+{

drivers/serial/serial_ar933x.c line 135

Quoted 10 lines

drivers/serial/serial_ar933x.c new file +10 -0

+#else
+static void ar933x_serial_setbrg(void)
+{
+    int baudrate = gd->baudrate;
+#endif
+    u32 val, scale, step;
+    const struct ar933x_serial_baudrate *baudrate_table;
+    int i, baudrate_table_size;
+
+    val = ar933x_read(AR71XX_RESET_BASE, AR933X_RESET_REG_BOOTSTRAP);

This can go to some clock rate in board info during board initialization.

Quoted 8 lines

drivers/serial/serial_ar933x.c new file +8 -0

+    if (val & AR933X_BOOTSTRAP_REF_CLK_40) {
+        baudrate_table = baudrate_table_40mhz;
+        baudrate_table_size = ARRAY_SIZE(baudrate_table_40mhz);
+        scale = (40000000 / (16 * baudrate)) - 1;
+        step = 8192;
+    } else {
+        baudrate_table = baudrate_table_25mhz;
+        baudrate_table_size = ARRAY_SIZE(baudrate_table_25mhz);

drivers/serial/serial_ar933x.c line 153

Quoted 10 lines

drivers/serial/serial_ar933x.c new file +10 -0

+        scale = (25000000 / (16 * baudrate)) - 1;
+        step = 8192;
+    }
+
+    for (i = 0; i < baudrate_table_size; i++) {
+        if (baudrate_table[i].baudrate == gd->baudrate) {
+            scale = baudrate_table[i].scale;
+            step = baudrate_table[i].step;
+        }
+    }

Quoted 1 line

What happens if not found?

"scale" and "step" was initialized by "if...else" statement above.

Quoted 101 lines

drivers/serial/serial_ar933x.c line 156

Quoted 4 lines

drivers/serial/serial_ar933x.c new file +3 -0

+
+    val  = ((scale & AR933X_UART_CLOCK_SCALE_M)
+            << AR933X_UART_CLOCK_SCALE_S);

The outer parenthesis is not needed.

Quoted 9 lines

drivers/serial/serial_ar933x.c new file +9 -0

+    val |= ((step & AR933X_UART_CLOCK_STEP_M)
+            << AR933X_UART_CLOCK_STEP_S);
+    ar933x_write(AR933X_UART_BASE, AR933X_UART_CLOCK_REG, val);
+#ifdef CONFIG_DM_SERIAL
+    return 0;
+#endif
+}
+
+#ifdef CONFIG_DM_SERIAL

drivers/serial/serial_ar933x.c line 175

Quoted 10 lines

drivers/serial/serial_ar933x.c new file +10 -0

+static int ar933x_serial_putc(struct udevice *dev, const char c)
+#else
+static void ar933x_serial_putc(const char c)
+#endif
+{
+    u32 data;
+
+    if (c == '\n')
+#ifdef CONFIG_DM_SERIAL
+        ar933x_serial_putc(dev, '\r');

Not needed for DM serial.

drivers/serial/serial_ar933x.c line 181

Quoted 6 lines

drivers/serial/serial_ar933x.c new file +6 -0

+#else
+        ar933x_serial_putc('\r');
+#endif
+    do {
+        data = ar933x_read(AR933X_UART_BASE, AR933X_UART_DATA_REG);
+    } while (!(data & AR933X_UART_DATA_TX_CSR));

Return -EAGAIN if not ready for DM serial.

Quoted 9 lines

drivers/serial/serial_ar933x.c new file +9 -0

+
+    data  = (u32)c | AR933X_UART_DATA_TX_CSR;
+    ar933x_write(AR933X_UART_BASE, AR933X_UART_DATA_REG, data);
+#ifdef CONFIG_DM_SERIAL
+    return 0;
+#endif
+}
+
+#ifdef CONFIG_DM_SERIAL

drivers/serial/serial_ar933x.c line 200

Quoted 10 lines

drivers/serial/serial_ar933x.c new file +10 -0

+static int ar933x_serial_getc(struct udevice *dev)
+#else
+static int ar933x_serial_getc(void)
+#endif
+{
+    u32 data;
+
+    do {
+        data = ar933x_read(AR933X_UART_BASE, AR933X_UART_DATA_REG);
+    } while (!(data & AR933X_UART_DATA_RX_CSR));

Return -EAGAIN if no data available for DM serial.

Quoted 41 lines

drivers/serial/serial_ar933x.c new file +3 -0

+
+    data = ar933x_read(AR933X_UART_BASE, AR933X_UART_DATA_REG);
+    ar933x_write(AR933X_UART_BASE, AR933X_UART_DATA_REG,

AR933X_UART_DATA_RX_CSR);

drivers/serial/serial_ar933x.c new file +37 -0

+    return data & AR933X_UART_DATA_TX_RX_MASK;
+}
+
+#ifdef CONFIG_DM_SERIAL
+static int ar933x_serial_pending(struct udevice *dev, bool input)
+{
+    u32 data;
+
+    data = ar933x_read(AR933X_UART_BASE, AR933X_UART_DATA_REG);
+    if (input)
+        return (data & AR933X_UART_DATA_RX_CSR) ? 1 : 0;
+    else
+        return (data & AR933X_UART_DATA_TX_CSR) ? 0 : 1;
+}
+
+static int ar933x_serial_probe(struct udevice *dev)
+{
+    ar933x_serial_init();
+    return 0;
+}
+
+static const struct dm_serial_ops ar933x_serial_ops = {
+    .putc = ar933x_serial_putc,
+    .pending = ar933x_serial_pending,
+    .getc = ar933x_serial_getc,
+    .setbrg = ar933x_serial_setbrg,
+};
+
+static const struct udevice_id ar933x_serial_ids[] = {
+    { .compatible = "ath79,ar933x-uart" },
+    { }
+};
+
+U_BOOT_DRIVER(serial_ar933x) = {
+    .name   = "serial_ar933x",
+    .id = UCLASS_SERIAL,
+    .of_match = ar933x_serial_ids,

Quoted 9 lines

drivers/serial/serial_ar933x.c line 244

Quoted 4 lines

drivers/serial/serial_ar933x.c new file +4 -0

+    .probe = ar933x_serial_probe,
+    .ops    = &ar933x_serial_ops,
+    .flags = DM_FLAG_PRE_RELOC,
+};

I understand there might be only a single UART on the ar9331. But it might be better to bind the reg address with U_BOOT_DEVICE() and platform data, or better dts.

The pinctrl and clock drvier is not ready, there is no way to operate clock and gpio resister if use address from device tree.

Signed-off-by Wills Wang <[email protected]>

---

Changes in v3: None
Changes in v2: None

 drivers/serial/Makefile        |   1 +
 drivers/serial/serial_ar933x.c | 274 +++++++++++++++++++++++++++++++++++++++++
 2 files changed, 275 insertions(+)
 create mode 100644 drivers/serial/serial_ar933x.c

drivers/serial/Makefile +1 -0

index dd87147..9a7ad89 100644
@@ -17,6 +17,7 @@ endif
 
 obj-$(CONFIG_ALTERA_UART) += altera_uart.o
 obj-$(CONFIG_ALTERA_JTAG_UART) += altera_jtag_uart.o
+obj-$(CONFIG_AR933X_SERIAL) += serial_ar933x.o
 obj-$(CONFIG_ARM_DCC) += arm_dcc.o
 obj-$(CONFIG_ATMEL_USART) += atmel_usart.o
 obj-$(CONFIG_EFI_APP) += serial_efi.o

drivers/serial/serial_ar933x.c new file +165 -0

new file mode 100644
index 0000000..6c0d726
@@ -0,0 +1,274 @@
+/*
+ * (C) Copyright 2015
+ * Wills Wang, <[email protected]>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <serial.h>
+#include <dm.h>
+#include <errno.h>
+#include <asm/io.h>
+#include <asm/addrspace.h>
+#include <asm/types.h>
+#include <asm/arch/ar71xx_regs.h>
+#include <asm/arch/ar933x_uart.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct ar933x_serial_baudrate{
+       u32 baudrate;
+       u32 scale;
+       u32 step;
+};
+
+const struct ar933x_serial_baudrate baudrate_table_40mhz[] = {
+/*  baudrate,   scale,  step */
+       {600,       255,    503},
+       {1200,      249,    983},
+       {2400,      167,    1321},
+       {4800,      87,     1384},
+       {9600,      45,     1447},
+       {14400,     53,     2548},
+       {19200,     22,     1447},
+       {28800,     26,     2548},
+       {38400,     28,     3649},
+       {56000,     7,      1468},
+       {57600,     34,     6606},
+       {115200,    28,     10947},
+       {128000,    6,      2936},
+       {153600,    18,     9563},
+       {230400,    16,     12834},
+       {250000,    4,      4096},
+       {256000,    6,      5872},
+       {460800,    7,      12079},
+       {576000,    4,      9437},
+       {921600,    3,      12079},
+       {1000000,   2,      9830},
+       {1152000,   2,      11324},
+       {1500000,   0,      4915},
+       {2000000,   0,      6553},
+ };
+
+const struct ar933x_serial_baudrate baudrate_table_25mhz[] = {
+/*  baudrate,   scale,  step */
+       {600,       255,    805},
+       {1200,      209,    1321},
+       {2400,      104,    1321},
+       {4800,      54,     1384},
+       {9600,      78,     3976},
+       {14400,     98,     7474},
+       {19200,     55,     5637},
+       {28800,     77,     11777},
+       {38400,     36,     7449},
+       {56000,     4,      1468},
+       {57600,     35,     10871},
+       {115200,    20,     12683},
+       {128000,    11,     8053},
+       {153600,    9,      8053},
+       {230400,    9,      12079},
+       {250000,    6,      9175},
+       {256000,    5,      8053},
+       {460800,    4,      12079},
+       {576000,    3,      12079},
+       {921600,    1,      9663},
+       {1000000,   1,      10485},
+       {1152000,   1,      12079},
+       {1500000,   0,      7864},
+       {2000000,   0,      10485},
+};
+
+static inline u32 ar933x_read(u32 base, u32 offset)
+{
+       return readl(KSEG1ADDR(base + offset));
+}
+
+static inline void ar933x_write(u32 base, u32 offset, u32 val)
+{
+       writel(val, KSEG1ADDR(base + offset));
+}
+
+static int ar933x_serial_init(void)
+{
+       u32 val;
+
+       /*
+        * Set GPIO10 (UART_SO) as output and enable UART,
+        * BIT(15) in GPIO_FUNCTION_1 register must be written with 1
+        */
+       val = ar933x_read(AR71XX_GPIO_BASE, AR71XX_GPIO_REG_OE);
+       val |= BIT(10);
+       ar933x_write(AR71XX_GPIO_BASE, AR71XX_GPIO_REG_OE, val);
+
+       val = ar933x_read(AR71XX_GPIO_BASE, AR71XX_GPIO_REG_FUNC);
+       val |= (AR933X_GPIO_FUNC_UART_EN | BIT(15));
+       ar933x_write(AR71XX_GPIO_BASE, AR71XX_GPIO_REG_FUNC, val);
+
+       /*
+        * UART controller configuration:
+        * - no DMA
+        * - no interrupt
+        * - DCE mode
+        * - no flow control
+        * - set RX ready oride
+        * - set TX ready oride
+        */
+       val = AR933X_UART_CS_TX_READY_ORIDE | AR933X_UART_CS_RX_READY_ORIDE
+               | (AR933X_UART_CS_IF_MODE_DCE << AR933X_UART_CS_IF_MODE_S);
+       ar933x_write(AR933X_UART_BASE, AR933X_UART_CS_REG, val);
+       return 0;
+}
+
+#ifdef CONFIG_DM_SERIAL
+static int ar933x_serial_setbrg(struct udevice *dev, int baudrate)
+{
+#else
+static void ar933x_serial_setbrg(void)
+{
+       int baudrate = gd->baudrate;
+#endif
+       u32 val, scale, step;
+       const struct ar933x_serial_baudrate *baudrate_table;
+       int i, baudrate_table_size;
+
+       val = ar933x_read(AR71XX_RESET_BASE, AR933X_RESET_REG_BOOTSTRAP);
+       if (val & AR933X_BOOTSTRAP_REF_CLK_40) {
+               baudrate_table = baudrate_table_40mhz;
+               baudrate_table_size = ARRAY_SIZE(baudrate_table_40mhz);
+               scale = (40000000 / (16 * baudrate)) - 1;
+               step = 8192;
+       } else {
+               baudrate_table = baudrate_table_25mhz;
+               baudrate_table_size = ARRAY_SIZE(baudrate_table_25mhz);
+               scale = (25000000 / (16 * baudrate)) - 1;
+               step = 8192;
+       }
+
+       for (i = 0; i < baudrate_table_size; i++) {
+               if (baudrate_table[i].baudrate == gd->baudrate) {
+                       scale = baudrate_table[i].scale;
+                       step = baudrate_table[i].step;
+               }
+       }
+
+       val  = ((scale & AR933X_UART_CLOCK_SCALE_M)
+                       << AR933X_UART_CLOCK_SCALE_S);
+       val |= ((step & AR933X_UART_CLOCK_STEP_M)
+                       << AR933X_UART_CLOCK_STEP_S);
+       ar933x_write(AR933X_UART_BASE, AR933X_UART_CLOCK_REG, val);
+#ifdef CONFIG_DM_SERIAL
+       return 0;
+#endif
+}
+
+#ifdef CONFIG_DM_SERIAL