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arm: cache: Implement cache range check for v7

PATCH New Marek Vasut 3 participants 8 messages Jul 27, 2015 – Jan 25, 2016 Arm (32-bit)

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Marek Vasut

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#0 lore raw

PATCH 1/1 arm: cache: Implement cache range check for v7

Add code to aid tracking down cache alignment issues. In case DEBUG is defined in the cache.c, this code will check alignment of each attempt to flush/invalidate data cache and print a warning if the alignment is incorrect. If DEBUG is not defined, this code is optimized out.

Signed-off-by Marek Vasut <[email protected]>
Cc Dinh Nguyen <[email protected]>
Cc Albert Aribaud <[email protected]>
Cc Tom Rini <[email protected]>
---
 arch/arm/cpu/armv7/cache_v7.c | 21 +++++++++++++++++++++
 1 file changed, 21 insertions(+)
arch/arm/cpu/armv7/cache_v7.c +21 -0
index e8ee875..84431bb 100644
@@ -16,6 +16,23 @@
 #define ARMV7_DCACHE_CLEAN_INVAL_RANGE	4
 
 #ifndef CONFIG_SYS_DCACHE_OFF
+static int check_cache_range(unsigned long start, unsigned long stop)
+{
+	int ok = 1;
+
+	if (start & (CONFIG_SYS_CACHELINE_SIZE - 1))
+		ok = 0;
+
+	if (stop & (CONFIG_SYS_CACHELINE_SIZE - 1))
+		ok = 0;
+
+	if (!ok)
+		debug("CACHE: Misaligned operation at range [%08lx, %08lx]\n",
+			start, stop);
+
+	return ok;
+}
+
 /*
  * Write the level and type you want to Cache Size Selection Register(CSSELR)
  * to get size details from Current Cache Size ID Register(CCSIDR)

@@ -257,6 +274,8 @@ void flush_dcache_all(void)
  */
 void invalidate_dcache_range(unsigned long start, unsigned long stop)
 {
+	check_cache_range(start, stop);
+
 	v7_dcache_maint_range(start, stop, ARMV7_DCACHE_INVAL_RANGE);
 
 	v7_outer_cache_inval_range(start, stop);

@@ -269,6 +288,8 @@ void invalidate_dcache_range(unsigned long start, unsigned long stop)
  */
 void flush_dcache_range(unsigned long start, unsigned long stop)
 {
+	check_cache_range(start, stop);
+
 	v7_dcache_maint_range(start, stop, ARMV7_DCACHE_CLEAN_INVAL_RANGE);
 
 	v7_outer_cache_flush_range(start, stop);
Signature · 1 line
2.1.4
author
#1 lore raw

PATCH 1/1 arm: cache: Implement cache range check for v7

Quoted 10 lines · Marek Vasut

Add code to aid tracking down cache alignment issues. In case DEBUG is defined in the cache.c, this code will check alignment of each attempt to flush/invalidate data cache and print a warning if the alignment is incorrect. If DEBUG is not defined, this code is optimized out.

Signed-off-by Marek Vasut <[email protected]>
Cc Dinh Nguyen <[email protected]>
Cc Albert Aribaud <[email protected]>
Cc Tom Rini <[email protected]>

Bump ? Is this patch useful or shall it be dropped ?

Quoted 44 lines
 arch/arm/cpu/armv7/cache_v7.c | 21 +++++++++++++++++++++
 1 file changed, 21 insertions(+)
arch/arm/cpu/armv7/cache_v7.c +17 -0
index e8ee875..84431bb 100644
@@ -16,6 +16,23 @@
 #define ARMV7_DCACHE_CLEAN_INVAL_RANGE	4
 
 #ifndef CONFIG_SYS_DCACHE_OFF
+static int check_cache_range(unsigned long start, unsigned long stop)
+{
+	int ok = 1;
+
+	if (start & (CONFIG_SYS_CACHELINE_SIZE - 1))
+		ok = 0;
+
+	if (stop & (CONFIG_SYS_CACHELINE_SIZE - 1))
+		ok = 0;
+
+	if (!ok)
+		debug("CACHE: Misaligned operation at range [%08lx, %08lx]\n",
+			start, stop);
+
+	return ok;
+}
+
 /*
  * Write the level and type you want to Cache Size Selection

Register(CSSELR) * to get size details from Current Cache Size ID Register(CCSIDR) @@ -257,6 +274,8 @@ void flush_dcache_all(void)
*/
void invalidate_dcache_range(unsigned long start, unsigned long stop) {

arch/arm/cpu/armv7/cache_v7.c +2 -0
+	check_cache_range(start, stop);
+
 	v7_dcache_maint_range(start, stop, ARMV7_DCACHE_INVAL_RANGE);
 
 	v7_outer_cache_inval_range(start, stop);

@@ -269,6 +288,8 @@ void invalidate_dcache_range(unsigned long start,

unsigned long stop) */
void flush_dcache_range(unsigned long start, unsigned long stop) {

arch/arm/cpu/armv7/cache_v7.c void invalidate_dcache_range(unsigned long start, unsigned long stop) · line 295

Quoted 5 lines
arch/arm/cpu/armv7/cache_v7.c +2 -0
+	check_cache_range(start, stop);
+
 	v7_dcache_maint_range(start, stop, ARMV7_DCACHE_CLEAN_INVAL_RANGE);
 
 	v7_outer_cache_flush_range(start, stop);

Best regards,
Marek Vasut

author
#2 lore raw

PATCH 1/1 arm: cache: Implement cache range check for v7

In reply to Marek Vasut
Quoted 10 lines · Marek Vasut

Add code to aid tracking down cache alignment issues. In case DEBUG is defined in the cache.c, this code will check alignment of each attempt to flush/invalidate data cache and print a warning if the alignment is incorrect. If DEBUG is not defined, this code is optimized out.

Signed-off-by Marek Vasut <[email protected]>
Cc Dinh Nguyen <[email protected]>
Cc Albert Aribaud <[email protected]>
Cc Tom Rini <[email protected]>

Bump ?

Quoted 44 lines
 arch/arm/cpu/armv7/cache_v7.c | 21 +++++++++++++++++++++
 1 file changed, 21 insertions(+)
arch/arm/cpu/armv7/cache_v7.c +17 -0
index e8ee875..84431bb 100644
@@ -16,6 +16,23 @@
 #define ARMV7_DCACHE_CLEAN_INVAL_RANGE	4
 
 #ifndef CONFIG_SYS_DCACHE_OFF
+static int check_cache_range(unsigned long start, unsigned long stop)
+{
+	int ok = 1;
+
+	if (start & (CONFIG_SYS_CACHELINE_SIZE - 1))
+		ok = 0;
+
+	if (stop & (CONFIG_SYS_CACHELINE_SIZE - 1))
+		ok = 0;
+
+	if (!ok)
+		debug("CACHE: Misaligned operation at range [%08lx, %08lx]\n",
+			start, stop);
+
+	return ok;
+}
+
 /*
  * Write the level and type you want to Cache Size Selection

Register(CSSELR) * to get size details from Current Cache Size ID Register(CCSIDR) @@ -257,6 +274,8 @@ void flush_dcache_all(void)
*/
void invalidate_dcache_range(unsigned long start, unsigned long stop) {

arch/arm/cpu/armv7/cache_v7.c +2 -0
+	check_cache_range(start, stop);
+
 	v7_dcache_maint_range(start, stop, ARMV7_DCACHE_INVAL_RANGE);
 
 	v7_outer_cache_inval_range(start, stop);

@@ -269,6 +288,8 @@ void invalidate_dcache_range(unsigned long start,

unsigned long stop) */
void flush_dcache_range(unsigned long start, unsigned long stop) {

arch/arm/cpu/armv7/cache_v7.c void invalidate_dcache_range(unsigned long start, unsigned long stop) · line 295

Quoted 5 lines
arch/arm/cpu/armv7/cache_v7.c +2 -0
+	check_cache_range(start, stop);
+
 	v7_dcache_maint_range(start, stop, ARMV7_DCACHE_CLEAN_INVAL_RANGE);
 
 	v7_outer_cache_flush_range(start, stop);

Best regards,
Marek Vasut

author
#3 lore raw

PATCH 1/1 arm: cache: Implement cache range check for v7

Quoted 7 lines · Marek Vasut
Quoted 6 lines · Marek Vasut

Add code to aid tracking down cache alignment issues. In case DEBUG is defined in the cache.c, this code will check alignment of each attempt to flush/invalidate data cache and print a warning if the alignment is incorrect. If DEBUG is not defined, this code is optimized out.

Quoted 6 lines
Quoted 4 lines
Signed-off-by Marek Vasut <[email protected]>
Cc Dinh Nguyen <[email protected]>
Cc Albert Aribaud <[email protected]>
Cc Tom Rini <[email protected]>

Bump ?

Bump ?

Quoted 65 lines
Quoted 56 lines
 arch/arm/cpu/armv7/cache_v7.c | 21 +++++++++++++++++++++
 1 file changed, 21 insertions(+)
(quoted diff) +0 -0

b/arch/arm/cpu/armv7/cache_v7.c index e8ee875..84431bb 100644

arch/arm/cpu/armv7/cache_v7.c +17 -0
@@ -16,6 +16,23 @@
 
 #define ARMV7_DCACHE_CLEAN_INVAL_RANGE	4
 
 #ifndef CONFIG_SYS_DCACHE_OFF
 
+static int check_cache_range(unsigned long start, unsigned long stop)
+{
+	int ok = 1;
+
+	if (start & (CONFIG_SYS_CACHELINE_SIZE - 1))
+		ok = 0;
+
+	if (stop & (CONFIG_SYS_CACHELINE_SIZE - 1))
+		ok = 0;
+
+	if (!ok)
+		debug("CACHE: Misaligned operation at range [%08lx, %08lx]\n",
+			start, stop);
+
+	return ok;
+}
+

/*

* Write the level and type you want to Cache Size Selection

Register(CSSELR) * to get size details from Current Cache Size ID Register(CCSIDR) @@ -257,6 +274,8 @@ void flush_dcache_all(void)

*/

void invalidate_dcache_range(unsigned long start, unsigned long stop) {

arch/arm/cpu/armv7/cache_v7.c +2 -0
+	check_cache_range(start, stop);
+
 
 	v7_dcache_maint_range(start, stop, ARMV7_DCACHE_INVAL_RANGE);
 
 	v7_outer_cache_inval_range(start, stop);

@@ -269,6 +288,8 @@ void invalidate_dcache_range(unsigned long start,

unsigned long stop) */

void flush_dcache_range(unsigned long start, unsigned long stop) {

arch/arm/cpu/armv7/cache_v7.c void invalidate_dcache_range(unsigned long start, unsigned long stop) · line 295

Quoted 6 lines
arch/arm/cpu/armv7/cache_v7.c +2 -0
+	check_cache_range(start, stop);
+
 
 	v7_dcache_maint_range(start, stop, ARMV7_DCACHE_CLEAN_INVAL_RANGE);
 
 	v7_outer_cache_flush_range(start, stop);

Best regards,
Marek Vasut

author
#4 lore raw

PATCH 1/1 arm: cache: Implement cache range check for v7

Quoted 8 lines · Marek Vasut
Quoted 7 lines · Marek Vasut
Quoted 6 lines · Marek Vasut

Add code to aid tracking down cache alignment issues. In case DEBUG is defined in the cache.c, this code will check alignment of each attempt to flush/invalidate data cache and print a warning if the alignment is incorrect. If DEBUG is not defined, this code is optimized out.

Quoted 8 lines
Quoted 6 lines
Quoted 4 lines
Signed-off-by Marek Vasut <[email protected]>
Cc Dinh Nguyen <[email protected]>
Cc Albert Aribaud <[email protected]>
Cc Tom Rini <[email protected]>

Bump ?

Bump ?

Bump #3 ?

Quoted 59 lines
Quoted 59 lines
Quoted 59 lines
 arch/arm/cpu/armv7/cache_v7.c | 21 +++++++++++++++++++++
 1 file changed, 21 insertions(+)
(quoted diff) +0 -0

b/arch/arm/cpu/armv7/cache_v7.c index e8ee875..84431bb 100644

arch/arm/cpu/armv7/cache_v7.c +17 -0
@@ -16,6 +16,23 @@
 
 #define ARMV7_DCACHE_CLEAN_INVAL_RANGE	4
 
 #ifndef CONFIG_SYS_DCACHE_OFF
 
+static int check_cache_range(unsigned long start, unsigned long stop)
+{
+	int ok = 1;
+
+	if (start & (CONFIG_SYS_CACHELINE_SIZE - 1))
+		ok = 0;
+
+	if (stop & (CONFIG_SYS_CACHELINE_SIZE - 1))
+		ok = 0;
+
+	if (!ok)
+		debug("CACHE: Misaligned operation at range [%08lx, %08lx]\n",
+			start, stop);
+
+	return ok;
+}
+

/*

* Write the level and type you want to Cache Size Selection

Register(CSSELR) * to get size details from Current Cache Size ID Register(CCSIDR) @@ -257,6 +274,8 @@ void flush_dcache_all(void)

*/

void invalidate_dcache_range(unsigned long start, unsigned long stop) {

arch/arm/cpu/armv7/cache_v7.c +2 -0
+	check_cache_range(start, stop);
+
 
 	v7_dcache_maint_range(start, stop, ARMV7_DCACHE_INVAL_RANGE);
 
 	v7_outer_cache_inval_range(start, stop);

@@ -269,6 +288,8 @@ void invalidate_dcache_range(unsigned long start,

unsigned long stop) */

void flush_dcache_range(unsigned long start, unsigned long stop) {

arch/arm/cpu/armv7/cache_v7.c +2 -0
+	check_cache_range(start, stop);
+
Quoted 6 lines
Quoted 6 lines

arch/arm/cpu/armv7/cache_v7.c void invalidate_dcache_range(unsigned long start, unsigned long stop) · line 295

Quoted 3 lines
arch/arm/cpu/armv7/cache_v7.c +0 -0
 	v7_dcache_maint_range(start, stop, ARMV7_DCACHE_CLEAN_INVAL_RANGE);
 
 	v7_outer_cache_flush_range(start, stop);

Best regards,
Marek Vasut

Best regards,
Marek Vasut

author
#5 lore raw

PATCH 1/1 arm: cache: Implement cache range check for v7

Quoted 14 lines · Marek Vasut
Quoted 13 lines · Marek Vasut
Quoted 12 lines · Marek Vasut
Quoted 10 lines · Marek Vasut

Add code to aid tracking down cache alignment issues. In case DEBUG is defined in the cache.c, this code will check alignment of each attempt to flush/invalidate data cache and print a warning if the alignment is incorrect. If DEBUG is not defined, this code is optimized out.

Signed-off-by Marek Vasut <[email protected]>
Cc Dinh Nguyen <[email protected]>
Cc Albert Aribaud <[email protected]>
Cc Tom Rini <[email protected]>
Quoted 5 lines
Quoted 3 lines
Quoted 1 line

Bump ?

Bump ?

Bump #3 ?

Bump #4 ?

Quoted 13 lines
Quoted 13 lines
Quoted 13 lines
Quoted 13 lines
 arch/arm/cpu/armv7/cache_v7.c | 21 +++++++++++++++++++++
 1 file changed, 21 insertions(+)
(quoted diff) +0 -0

b/arch/arm/cpu/armv7/cache_v7.c index e8ee875..84431bb 100644

arch/arm/cpu/armv7/cache_v7.c +0 -0
@@ -16,6 +16,23 @@
 
 #define ARMV7_DCACHE_CLEAN_INVAL_RANGE	4
 
 #ifndef CONFIG_SYS_DCACHE_OFF
Quoted 12 lines
Quoted 4 lines
Quoted 4 lines
Quoted 4 lines
arch/arm/cpu/armv7/cache_v7.c +3 -0
+static int check_cache_range(unsigned long start, unsigned long
 stop) +{
+	int ok = 1;
+
Quoted 8 lines
Quoted 8 lines

arch/arm/cpu/armv7/cache_v7.c

Quoted 8 lines
arch/arm/cpu/armv7/cache_v7.c +8 -0
+	if (start & (CONFIG_SYS_CACHELINE_SIZE - 1))
+		ok = 0;
+
+	if (stop & (CONFIG_SYS_CACHELINE_SIZE - 1))
+		ok = 0;
+
+	if (!ok)
+		debug("CACHE: Misaligned operation at range [%08lx,

%08lx]\n",

Quoted 28 lines
Quoted 28 lines
Quoted 28 lines
Quoted 28 lines
arch/arm/cpu/armv7/cache_v7.c +5 -0
+			start, stop);
+
+	return ok;
+}
+
 
 /*
 
  * Write the level and type you want to Cache Size Selection

Register(CSSELR) * to get size details from Current Cache Size ID Register(CCSIDR) @@ -257,6 +274,8 @@ void flush_dcache_all(void)

*/

void invalidate_dcache_range(unsigned long start, unsigned long stop) {

arch/arm/cpu/armv7/cache_v7.c +2 -0
+	check_cache_range(start, stop);
+
 
 	v7_dcache_maint_range(start, stop, ARMV7_DCACHE_INVAL_RANGE);
 
 	v7_outer_cache_inval_range(start, stop);

@@ -269,6 +288,8 @@ void invalidate_dcache_range(unsigned long start,

unsigned long stop) */

Quoted 7 lines
Quoted 7 lines
Quoted 7 lines

arch/arm/cpu/armv7/cache_v7.c void flush_dcache_all(void)

Quoted 7 lines

void flush_dcache_range(unsigned long start, unsigned long stop) {

arch/arm/cpu/armv7/cache_v7.c +2 -0
+	check_cache_range(start, stop);
+
 
 	v7_dcache_maint_range(start, stop,

ARMV7_DCACHE_CLEAN_INVAL_RANGE);

Quoted 8 lines
Quoted 5 lines
Quoted 5 lines
Quoted 2 lines

v7_outer_cache_flush_range(start, stop);

Best regards,
Marek Vasut

Best regards,
Marek Vasut

Best regards,
Marek Vasut

#6 lore raw

PATCH 1/1 arm: cache: Implement cache range check for v7

Quoted 15 lines · Marek Vasut
Quoted 14 lines · Marek Vasut
Quoted 13 lines · Marek Vasut
Quoted 12 lines · Marek Vasut
Quoted 10 lines · Marek Vasut

Add code to aid tracking down cache alignment issues. In case DEBUG is defined in the cache.c, this code will check alignment of each attempt to flush/invalidate data cache and print a warning if the alignment is incorrect. If DEBUG is not defined, this code is optimized out.

Signed-off-by Marek Vasut <[email protected]>
Cc Dinh Nguyen <[email protected]>
Cc Albert Aribaud <[email protected]>
Cc Tom Rini <[email protected]>
Quoted 7 lines
Quoted 5 lines
Quoted 3 lines
Quoted 1 line

Bump ?

Bump ?

Bump #3 ?

Bump #4 ?

Albert?

Quoted 77 lines
Quoted 13 lines
Quoted 13 lines
Quoted 13 lines
Quoted 13 lines
 arch/arm/cpu/armv7/cache_v7.c | 21 +++++++++++++++++++++
 1 file changed, 21 insertions(+)
(quoted diff) +0 -0

b/arch/arm/cpu/armv7/cache_v7.c index e8ee875..84431bb 100644

arch/arm/cpu/armv7/cache_v7.c +0 -0
@@ -16,6 +16,23 @@
 
 #define ARMV7_DCACHE_CLEAN_INVAL_RANGE	4
 
 #ifndef CONFIG_SYS_DCACHE_OFF
Quoted 12 lines
Quoted 4 lines
Quoted 4 lines
Quoted 4 lines
arch/arm/cpu/armv7/cache_v7.c +3 -0
+static int check_cache_range(unsigned long start, unsigned long
 stop) +{
+	int ok = 1;
+
Quoted 8 lines
Quoted 8 lines

arch/arm/cpu/armv7/cache_v7.c

Quoted 8 lines
arch/arm/cpu/armv7/cache_v7.c +8 -0
+	if (start & (CONFIG_SYS_CACHELINE_SIZE - 1))
+		ok = 0;
+
+	if (stop & (CONFIG_SYS_CACHELINE_SIZE - 1))
+		ok = 0;
+
+	if (!ok)
+		debug("CACHE: Misaligned operation at range [%08lx,

%08lx]\n",

Quoted 28 lines
Quoted 28 lines
Quoted 28 lines
Quoted 28 lines
arch/arm/cpu/armv7/cache_v7.c +5 -0
+			start, stop);
+
+	return ok;
+}
+
 
 /*
 
  * Write the level and type you want to Cache Size Selection

Register(CSSELR) * to get size details from Current Cache Size ID Register(CCSIDR) @@ -257,6 +274,8 @@ void flush_dcache_all(void)

*/

void invalidate_dcache_range(unsigned long start, unsigned long stop) {

arch/arm/cpu/armv7/cache_v7.c +2 -0
+	check_cache_range(start, stop);
+
 
 	v7_dcache_maint_range(start, stop, ARMV7_DCACHE_INVAL_RANGE);
 
 	v7_outer_cache_inval_range(start, stop);

@@ -269,6 +288,8 @@ void invalidate_dcache_range(unsigned long start,

unsigned long stop) */

Quoted 7 lines
Quoted 7 lines
Quoted 7 lines

arch/arm/cpu/armv7/cache_v7.c void flush_dcache_all(void)

Quoted 7 lines

void flush_dcache_range(unsigned long start, unsigned long stop) {

arch/arm/cpu/armv7/cache_v7.c +2 -0
+	check_cache_range(start, stop);
+
 
 	v7_dcache_maint_range(start, stop,

ARMV7_DCACHE_CLEAN_INVAL_RANGE);

Quoted 8 lines
Quoted 5 lines
Quoted 5 lines
Quoted 2 lines

v7_outer_cache_flush_range(start, stop);

Best regards,
Marek Vasut

Best regards,
Marek Vasut

Best regards,
Marek Vasut
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Signature · 8 lines
Tom
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#7 lore raw

PATCH 1/1 arm: cache: Implement cache range check for v7

Hello Tom,

Quoted 18 lines · Tom Rini
Quoted 17 lines · Marek Vasut
Quoted 16 lines · Marek Vasut
Quoted 15 lines · Marek Vasut
Quoted 13 lines · Marek Vasut
Quoted 10 lines · Marek Vasut

Add code to aid tracking down cache alignment issues. In case DEBUG is defined in the cache.c, this code will check alignment of each attempt to flush/invalidate data cache and print a warning if the alignment is incorrect. If DEBUG is not defined, this code is optimized out.

Signed-off-by Marek Vasut <[email protected]>
Cc Dinh Nguyen <[email protected]>
Cc Albert Aribaud <[email protected]>
Cc Tom Rini <[email protected]>

Bump ?

Quoted 7 lines
Quoted 5 lines
Quoted 3 lines
Quoted 1 line

Bump ?

Bump #3 ?

Bump #4 ?

Albert?

Sorry. Applied to u-boot-arm/master, thanks.

Amicalement,

Signature · 1 line
Albert.