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armv7: add cacheline sizes where missing

PATCH New Albert ARIBAUD 3 participants 4 messages Jan 26, 2016 – Jan 27, 2016

Subsystems (3)
Arm/Microchip (AT91) SoC support Arm/RISC-V/Renesas architecture Arm/versatile express platform
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Albert ARIBAUD

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#0 lore raw

PATCH 1/1 armv7: add cacheline sizes where missing

Some armv7 targets are missing a cache line size declaration. In preparation for "arm: cache: Implement cache range check for v7" patch, add these declarations with the appropriate value for the target's SoC or CPU.

Signed-off-by Albert ARIBAUD <[email protected]>

---

 include/configs/am3517_crane.h      | 2 ++
 include/configs/am3517_evm.h        | 2 ++
 include/configs/at91-sama5_common.h | 2 ++
 include/configs/bcm_ep_board.h      | 1 +
 include/configs/cm_t35.h            | 2 ++
 include/configs/cm_t3517.h          | 2 ++
 include/configs/colibri_vf.h        | 2 ++
 include/configs/kzm9g.h             | 2 ++
 include/configs/nokia_rx51.h        | 2 ++
 include/configs/pcm052.h            | 2 ++
 include/configs/rcar-gen2-common.h  | 2 ++
 include/configs/rk3036_common.h     | 2 ++
 include/configs/rk3288_common.h     | 2 ++
 include/configs/s5p_goni.h          | 2 ++
 include/configs/smdkc100.h          | 2 ++
 include/configs/tao3530.h           | 2 ++
 include/configs/ti814x_evm.h        | 2 ++
 include/configs/ti816x_evm.h        | 2 ++
 include/configs/ti_omap3_common.h   | 5 +++++
 include/configs/tricorder.h         | 2 ++
 include/configs/vexpress_common.h   | 2 ++
 include/configs/vf610twr.h          | 2 ++
 22 files changed, 46 insertions(+)
include/configs/am3517_crane.h +2 -0
index 4ed8e00..3cc2874 100644
@@ -13,6 +13,8 @@
 #ifndef __CONFIG_H
 #define __CONFIG_H
 
+#define CONFIG_SYS_CACHELINE_SIZE	64
+
 /*
  * High Level Configuration Options
  */
include/configs/am3517_evm.h +2 -0
index 23457d6..4547d7f 100644
@@ -13,6 +13,8 @@
 #ifndef __CONFIG_H
 #define __CONFIG_H
 
+#define CONFIG_SYS_CACHELINE_SIZE	64
+
 /*
  * High Level Configuration Options
  */
include/configs/at91-sama5_common.h +2 -0
index 9db4a4f..7b06601 100644
@@ -12,6 +12,8 @@
 
 #include <asm/hardware.h>
 
+#define CONFIG_SYS_CACHELINE_SIZE	64
+
 #define CONFIG_SYS_TEXT_BASE		0x26f00000
 
 /* ARM asynchronous clock */
include/configs/bcm_ep_board.h +1 -0
index 305864f..1d4869b 100644
@@ -11,6 +11,7 @@
 
 #define CONFIG_SKIP_LOWLEVEL_INIT
 
+#define CONFIG_SYS_CACHELINE_SIZE	64
 
 /*
  * Memory configuration
include/configs/cm_t35.h +2 -0
index 2dc745e..24ae14d 100644
@@ -17,6 +17,8 @@
 #ifndef __CONFIG_H
 #define __CONFIG_H
 
+#define CONFIG_SYS_CACHELINE_SIZE	64
+
 /*
  * High Level Configuration Options
  */
include/configs/cm_t3517.h +2 -0
index 0aefec8..7a07de4 100644
@@ -10,6 +10,8 @@
 #ifndef __CONFIG_H
 #define __CONFIG_H
 
+#define CONFIG_SYS_CACHELINE_SIZE	64
+
 /*
  * High Level Configuration Options
  */
include/configs/colibri_vf.h +2 -0
index 5aed3a5..dd44462 100644
@@ -12,6 +12,8 @@
 #ifndef __CONFIG_H
 #define __CONFIG_H
 
+#define CONFIG_SYS_CACHELINE_SIZE	32
+
 #include <asm/arch/imx-regs.h>
 
 #define CONFIG_VF610
include/configs/kzm9g.h +2 -0
index 94b0f03..d5cbb33 100644
@@ -10,6 +10,8 @@
 
 #undef DEBUG
 
+#define CONFIG_SYS_CACHELINE_SIZE	32
+
 #define CONFIG_SH73A0
 #define CONFIG_KZM_A9_GT
 #define CONFIG_RMOBILE_BOARD_STRING	"KMC KZM-A9-GT"
include/configs/nokia_rx51.h +2 -0
index b11e43a..5c41405 100644
@@ -19,6 +19,8 @@
 #ifndef __CONFIG_H
 #define __CONFIG_H
 
+#define CONFIG_SYS_CACHELINE_SIZE 64
+
 /*
  * High Level Configuration Options
  */
include/configs/pcm052.h +2 -0
index 891bdb0..2628dfa 100644
@@ -9,6 +9,8 @@
 #ifndef __CONFIG_H
 #define __CONFIG_H
 
+#define CONFIG_SYS_CACHELINE_SIZE	32
+
 #include <asm/arch/imx-regs.h>
 
 #define CONFIG_VF610
include/configs/rcar-gen2-common.h +2 -0
index f0a3a18..f750b53 100644
@@ -9,6 +9,8 @@
 #ifndef __RCAR_GEN2_COMMON_H
 #define __RCAR_GEN2_COMMON_H
 
+#define CONFIG_SYS_CACHELINE_SIZE 64
+
 #include <asm/arch/rmobile.h>
 
 #define CONFIG_CMD_DFL
include/configs/rk3036_common.h +2 -0
index d22ea74..368d046 100644
@@ -6,6 +6,8 @@
 #ifndef __CONFIG_RK3036_COMMON_H
 #define __CONFIG_RK3036_COMMON_H
 
+#define CONFIG_SYS_CACHELINE_SIZE	32
+
 #include <asm/arch/hardware.h>
 
 #define CONFIG_SYS_NO_FLASH
include/configs/rk3288_common.h +2 -0
index ebf1ab0..427ac4b 100644
@@ -7,6 +7,8 @@
 #ifndef __CONFIG_RK3288_COMMON_H
 #define __CONFIG_RK3288_COMMON_H
 
+#define CONFIG_SYS_CACHELINE_SIZE	64
+
 #include <asm/arch/hardware.h>
 
 #define CONFIG_SYS_NO_FLASH
include/configs/s5p_goni.h +2 -0
index 8f65d7e..f92c23d 100644
@@ -17,6 +17,8 @@
 #define CONFIG_S5PC110		1	/* which is in a S5PC110 */
 #define CONFIG_MACH_GONI	1	/* working with Goni */
 
+#define CONFIG_SYS_CACHELINE_SIZE	64
+
 #include <linux/sizes.h>
 #include <asm/arch/cpu.h>		/* get chip and board defs */
include/configs/smdkc100.h +2 -0
index c36e444..db79e54 100644
@@ -12,6 +12,8 @@
 #ifndef __CONFIG_H
 #define __CONFIG_H
 
+#define CONFIG_SYS_CACHELINE_SIZE	64
+
 /*
  * High Level Configuration Options
  * (easy to change)
include/configs/tao3530.h +2 -0
index c1bd179..d5aba70 100644
@@ -13,6 +13,8 @@
 #ifndef __CONFIG_H
 #define __CONFIG_H
 
+#define CONFIG_SYS_CACHELINE_SIZE	64
+
 /*
  * High Level Configuration Options
  */
include/configs/ti814x_evm.h +2 -0
index e726040..3d0498d 100644
@@ -16,6 +16,8 @@
 #ifndef __CONFIG_TI814X_EVM_H
 #define __CONFIG_TI814X_EVM_H
 
+#define CONFIG_SYS_CACHELINE_SIZE	64
+
 #define CONFIG_TI81XX
 #define CONFIG_TI814X
 #define CONFIG_SYS_NO_FLASH
include/configs/ti816x_evm.h +2 -0
index ba652ca..533fae7 100644
@@ -10,6 +10,8 @@
 #ifndef __CONFIG_TI816X_EVM_H
 #define __CONFIG_TI816X_EVM_H
 
+#define CONFIG_SYS_CACHELINE_SIZE	64
+
 #define CONFIG_TI81XX
 #define CONFIG_TI816X
 #define CONFIG_SYS_NO_FLASH
include/configs/ti_omap3_common.h +5 -0
index 02fdcdc..6a4868c 100644
@@ -14,6 +14,11 @@
 #ifndef __CONFIG_TI_OMAP3_COMMON_H__
 #define __CONFIG_TI_OMAP3_COMMON_H__
 
+/*
+ * High Level Configuration Options
+ */
+
+#define CONFIG_SYS_CACHELINE_SIZE	64
 
 #include <asm/arch/cpu.h>
 #include <asm/arch/omap.h>
include/configs/tricorder.h +2 -0
index f5f5324..2ec2f01 100644
@@ -16,6 +16,8 @@
 #ifndef __CONFIG_H
 #define __CONFIG_H
 
+#define CONFIG_SYS_CACHELINE_SIZE	64
+
 /* High Level Configuration Options */
 #define CONFIG_SYS_THUMB_BUILD
 #define CONFIG_OMAP			/* in a TI OMAP core */
include/configs/vexpress_common.h +2 -0
index cec510c..d78ca0b 100644
@@ -118,6 +118,8 @@
 #define CONFIG_SYS_MEMTEST_START	V2M_BASE
 #define CONFIG_SYS_MEMTEST_END		0x20000000
 
+#define CONFIG_SYS_CACHELINE_SIZE	64
+
 #define CONFIG_CMDLINE_TAG		1	/* enable passing of ATAGs */
 #define CONFIG_SETUP_MEMORY_TAGS	1
 #define CONFIG_SYS_L2CACHE_OFF		1
include/configs/vf610twr.h +2 -0
index dcfafaf..d100f73 100644
@@ -9,6 +9,8 @@
 #ifndef __CONFIG_H
 #define __CONFIG_H
 
+#define CONFIG_SYS_CACHELINE_SIZE	32
+
 #include <asm/arch/imx-regs.h>
 
 #define CONFIG_VF610
Signature · 1 line
2.5.0
#1 lore raw

PATCH 1/1 armv7: add cacheline sizes where missing

Quoted 6 lines · Albert ARIBAUD

Some armv7 targets are missing a cache line size declaration. In preparation for "arm: cache: Implement cache range check for v7" patch, add these declarations with the appropriate value for the target's SoC or CPU.

Signed-off-by Albert ARIBAUD <[email protected]>

For the TI boards:

Reviewed-by Tom Rini <[email protected]>
Signature · 8 lines
Tom
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#2 lore raw

PATCH 1/1 armv7: add cacheline sizes where missing

In reply to Albert ARIBAUD
Quoted 6 lines · Albert ARIBAUD

Some armv7 targets are missing a cache line size declaration. In preparation for "arm: cache: Implement cache range check for v7" patch, add these declarations with the appropriate value for the target's SoC or CPU.

Signed-off-by Albert ARIBAUD <[email protected]>

[...]

include/configs/at91-sama5_common.h line 19

Quoted 13 lines
(quoted diff) +0 -0

b/include/configs/at91-sama5_common.h index 9db4a4f..7b06601 100644

include/configs/at91-sama5_common.h +2 -0
@@ -12,6 +12,8 @@
 
 #include <asm/hardware.h>
 
+#define CONFIG_SYS_CACHELINE_SIZE	64
+
 #define CONFIG_SYS_TEXT_BASE		0x26f00000
 
 /* ARM asynchronous clock */

I think SAMA5 is CortexA5 and that has 32B cachelines.

Best regards,
Marek Vasut

author
#3 lore raw

PATCH 1/1 armv7: add cacheline sizes where missing

Hello Marek,

Quoted 18 lines · Marek Vasut
Quoted 6 lines · Albert ARIBAUD

Some armv7 targets are missing a cache line size declaration. In preparation for "arm: cache: Implement cache range check for v7" patch, add these declarations with the appropriate value for the target's SoC or CPU.

Signed-off-by Albert ARIBAUD <[email protected]>

[...]

Quoted 8 lines
(quoted diff) +0 -0

b/include/configs/at91-sama5_common.h index 9db4a4f..7b06601 100644

include/configs/at91-sama5_common.h +0 -0
@@ -12,6 +12,8 @@
 
 #include <asm/hardware.h>
Quoted 7 lines

include/configs/at91-sama5_common.h line 19

Quoted 5 lines
include/configs/at91-sama5_common.h +2 -0
+#define CONFIG_SYS_CACHELINE_SIZE	64
+
 #define CONFIG_SYS_TEXT_BASE		0x26f00000
 
 /* ARM asynchronous clock */

I think SAMA5 is CortexA5 and that has 32B cachelines.

Correct. V2 incoming.

Quoted 2 lines

Best regards,
Marek Vasut

Amicalement,

Signature · 1 line
Albert.