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Add support for imx6qp

PATCH New Bai Ping 3 participants 13 messages Dec 15, 2015 – Jan 28, 2016

Subsystems (7)
Device tree bindings Arm (32-bit) Arm sub-architectures Arm i.MX and Layerscape +3 more subsystems
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Bai Ping

author
#0 lore raw

v2 cover Add support for imx6qp

This patchset add basic support for i.MX6Quad Plus SOC.

change for v2:
-- address commnet from Fabio Estevam, split the dts
into three patch:
dts for imx6qp soc; dts for imx6qp-sabresd
and dts for imx6qp-sabreauto
-- fix a typo in commit, the chip name should be i.MX6Quad Plus

Bai Ping (5):
ARM: dts: imx: Add basic dts support for imx6qp SOC
ARM: dts: imx: Add basic dts support for imx6qp-sabresd
ARM: dts: imx: Add basic dts support for imx6qp-sabreauto
clk: imx: Add clock support for imx6qp
ARM: imx: Add msl code support for imx6qp

 arch/arm/boot/dts/Makefile                |   2 +
 arch/arm/boot/dts/imx6q.dtsi              |   2 +-
 arch/arm/boot/dts/imx6qdl-sabresd.dtsi    |   1 +
 arch/arm/boot/dts/imx6qp-sabreauto.dts    |  67 +++++++++++++
 arch/arm/boot/dts/imx6qp-sabresd.dts      |  59 +++++++++++
 arch/arm/boot/dts/imx6qp.dtsi             | 157 ++++++++++++++++++++++++++++++
 arch/arm/mach-imx/anatop.c                |   5 +-
 arch/arm/mach-imx/mach-imx6q.c            |   8 +-
 drivers/clk/imx/clk-imx6q.c               | 132 ++++++++++++++++++++-----
 include/dt-bindings/clock/imx6qdl-clock.h |  16 ++-
 10 files changed, 417 insertions(+), 32 deletions(-)
 create mode 100644 arch/arm/boot/dts/imx6qp-sabreauto.dts
 create mode 100644 arch/arm/boot/dts/imx6qp-sabresd.dts
 create mode 100644 arch/arm/boot/dts/imx6qp.dtsi
Signature · 1 line
1.9.1
author
#1 lore raw

PATCH v2 1/5 ARM: dts: imx: Add basic dts support for imx6qp SOC

The i.MX6Quad Plus processor is an high performance SOC of i.MX6 family. It has enhanced graphics performance and increased overall memory bandwidth compared to i.MX6Q. Most of the design are same as i.MX6Quad/Dual, so code for i.MX6Quad can be resued by this chip. The revision number is identied as i.MX6Q Rev2.0, but actually it is a new chip, as we did many change to the overall architecture.

This patch adds basic dtsi file support for the new i.MX6Quad Plus processor.

Signed-off-by Bai Ping <[email protected]>
---
 arch/arm/boot/dts/imx6q.dtsi              |   2 +-
 arch/arm/boot/dts/imx6qp.dtsi             | 157 ++++++++++++++++++++++++++++++
 include/dt-bindings/clock/imx6qdl-clock.h |  16 ++-
 3 files changed, 173 insertions(+), 2 deletions(-)
 create mode 100644 arch/arm/boot/dts/imx6qp.dtsi
arch/arm/boot/dts/imx6q.dtsi +1 -1
index a266a56..e26d0fd 100644
@@ -22,7 +22,7 @@
 		#address-cells = <1>;
 		#size-cells = <0>;
 
-		cpu at 0 {
+		cpu0: cpu at 0 {
 			compatible = "arm,cortex-a9";
 			device_type = "cpu";
 			reg = <0>;
arch/arm/boot/dts/imx6qp.dtsi new file +157 -0

157 lines not on this page · raw message

include/dt-bindings/clock/imx6qdl-clock.h +15 -1
index 77985cc..2905033 100644
@@ -255,6 +255,20 @@
 #define IMX6QDL_CLK_CAAM_ACLK			242
 #define IMX6QDL_CLK_CAAM_IPG			243
 #define IMX6QDL_CLK_SPDIF_GCLK			244
-#define IMX6QDL_CLK_END				245
+#define IMX6QDL_CLK_UART_SEL			245
+#define IMX6QDL_CLK_IPG_PER_SEL			246
+#define IMX6QDL_CLK_ECSPI_SEL			247
+#define IMX6QDL_CLK_CAN_SEL			248
+#define IMX6QDL_CLK_MMDC_CH1_AXI_CG		249
+#define IMX6QDL_CLK_PRE0			250
+#define IMX6QDL_CLK_PRE1			251
+#define IMX6QDL_CLK_PRE2			252
+#define IMX6QDL_CLK_PRE3			253
+#define IMX6QDL_CLK_PRG0_AXI			254
+#define IMX6QDL_CLK_PRG1_AXI			255
+#define IMX6QDL_CLK_PRG0_APB			256
+#define IMX6QDL_CLK_PRG1_APB			257
+#define IMX6QDL_CLK_PRE_AXI			258
+#define IMX6QDL_CLK_END				259
 
 #endif /* __DT_BINDINGS_CLOCK_IMX6QDL_H */
Signature · 1 line
1.9.1
#2 lore raw

PATCH v2 1/5 ARM: dts: imx: Add basic dts support for imx6qp SOC

Quoted 36 lines · Bai Ping

The i.MX6Quad Plus processor is an high performance SOC of i.MX6 family. It has enhanced graphics performance and increased overall memory bandwidth compared to i.MX6Q. Most of the design are same as i.MX6Quad/Dual, so code for i.MX6Quad can be resued by this chip. The revision number is identied as i.MX6Q Rev2.0, but actually it is a new chip, as we did many change to the overall architecture.

This patch adds basic dtsi file support for the new i.MX6Quad Plus processor.

Signed-off-by Bai Ping <[email protected]>
---
 arch/arm/boot/dts/imx6q.dtsi              |   2 +-
 arch/arm/boot/dts/imx6qp.dtsi             | 157 ++++++++++++++++++++++++++++++
 include/dt-bindings/clock/imx6qdl-clock.h |  16 ++-
 3 files changed, 173 insertions(+), 2 deletions(-)
 create mode 100644 arch/arm/boot/dts/imx6qp.dtsi
arch/arm/boot/dts/imx6q.dtsi +1 -1
index a266a56..e26d0fd 100644
@@ -22,7 +22,7 @@
 		#address-cells = <1>;
 		#size-cells = <0>;
 
-		cpu at 0 {
+		cpu0: cpu at 0 {
 			compatible = "arm,cortex-a9";
 			device_type = "cpu";
 			reg = <0>;
arch/arm/boot/dts/imx6qp.dtsi new file +0 -0
new file mode 100644
index 0000000..e43751f

arch/arm/boot/dts/imx6qp.dtsi line 6

Quoted 6 lines
arch/arm/boot/dts/imx6qp.dtsi new file +6 -0
@@ -0,0 +1,157 @@
+/*
+ * Copyright 2015 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.

For new dts files, we suggest to use GPL/X11 dual license to consider non-Linux users. You can grep "dual-licensed" in arch/arm/boot/dts to find a plenty of examples.

arch/arm/boot/dts/imx6qp.dtsi line 9

Quoted 3 lines
arch/arm/boot/dts/imx6qp.dtsi new file +3 -0
+ *
+ */
+

Do you not need to include "imx6qdl.dtsi" here?

arch/arm/boot/dts/imx6qp.dtsi line 21

Quoted 12 lines
arch/arm/boot/dts/imx6qp.dtsi new file +12 -0
+/ {
+	aliases {
+		pre0 = &pre1;
+		pre1 = &pre2;
+		pre2 = &pre3;
+		pre3 = &pre4;
+		prg0 = &prg1;
+		prg1 = &prg2;
+	};
+
+	soc {
+		ocram_2: sram at 00940000 {

The label can just be ocram2.

arch/arm/boot/dts/imx6qp.dtsi line 27

Quoted 6 lines
arch/arm/boot/dts/imx6qp.dtsi new file +6 -0
+			compatible = "mmio-sram";
+			reg = <0x00940000 0x20000>;
+			clocks = <&clks IMX6QDL_CLK_OCRAM>;
+		};
+
+		ocram_3: sram at 00960000 {

ocram3

Quoted 23 lines
arch/arm/boot/dts/imx6qp.dtsi new file +23 -0
+			compatible = "mmio-sram";
+			reg = <0x00960000 0x20000>;
+			clocks = <&clks IMX6QDL_CLK_OCRAM>;
+		};
+
+		pcie: pcie at 0x01000000 {
+			compatible = "fsl,imx6qp-pcie", "snps,dw-pcie";
+			reg = <0x01ffc000 0x4000>, <0x01f00000 0x80000>;
+			reg-names = "dbi", "config";
+			#address-cells = <3>;
+			#size-cells = <2>;
+			device_type = "pci";
+			ranges = <0x81000000 0 0          0x01f80000 0 0x00010000 /* downstream I/O */
+				  0x82000000 0 0x01000000 0x01000000 0 0x00f00000>; /* non-prefetchable memory */
+			num-lanes = <1>;
+			interrupts = <0 120 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "msi";
+			#interrupt-cells = <1>;
+			interrupt-map-mask = <0 0 0 0x7>;
+			interrupt-map = <0 0 0 1 &intc 0 123 IRQ_TYPE_LEVEL_HIGH>,
+					<0 0 0 2 &intc 0 122 IRQ_TYPE_LEVEL_HIGH>,
+					<0 0 0 3 &intc 0 121 IRQ_TYPE_LEVEL_HIGH>,
+					<0 0 0 4 &intc 0 120 IRQ_TYPE_LEVEL_HIGH>;

arch/arm/boot/dts/imx6qp.dtsi line 60

Quoted 10 lines
arch/arm/boot/dts/imx6qp.dtsi new file +10 -0
+			clocks = <&clks IMX6QDL_CLK_PCIE_REF_125M>,
+				 <&clks IMX6QDL_CLK_SATA_REF_100M>,
+				 <&clks IMX6QDL_CLK_LVDS1_GATE>, <&clks IMX6QDL_CLK_PCIE_AXI>;
+			clock-names = "pcie_phy", "ref_100m", "pcie_bus", "pcie";
+			status = "disabled";
+		};
+
+		aips-bus at 02100000 { /* AIPS2 */
+			pre1: pre at 021c8000 {
+				compatible = "fsl,imx6q-pre";

Is there already a device tree binding and driver for this block in upstream kernel? I do not accepted any unestablished device.

Quoted 26 lines
arch/arm/boot/dts/imx6qp.dtsi new file +26 -0
+				reg = <0x021c8000 0x1000>;
+				clocks = <&clks IMX6QDL_CLK_PRE0>;
+				interrupts = <0 90 IRQ_TYPE_EDGE_RISING>;
+				ocram = <&ocram_2>;
+				status = "disabled";
+			};
+
+			pre2: pre at 021c9000 {
+				compatible = "fsl,imx6q-pre";
+				reg = <0x021c9000 0x1000>;
+				clocks = <&clks IMX6QDL_CLK_PRE1>;
+				interrupts = <0 97 IRQ_TYPE_EDGE_RISING>;
+				ocram = <&ocram_2>;
+				status = "disabled";
+			};
+
+			pre3: pre at 021ca000 {
+				compatible = "fsl,imx6q-pre";
+				reg = <0x021ca000 0x1000>;
+				clocks = <&clks IMX6QDL_CLK_PRE2>;
+				interrupts = <0 98 IRQ_TYPE_EDGE_RISING>;
+				ocram = <&ocram_3>;
+				status = "disabled";
+			};
+
+			pre4: pre at 021cb000 {

arch/arm/boot/dts/imx6qp.dtsi line 96

Quoted 10 lines
arch/arm/boot/dts/imx6qp.dtsi new file +10 -0
+				compatible = "fsl,imx6q-pre";
+				reg = <0x021cb000 0x1000>;
+				clocks = <&clks IMX6QDL_CLK_PRE3>;
+				interrupts = <0 99 IRQ_TYPE_EDGE_RISING>;
+				ocram = <&ocram_3>;
+				status = "disabled";
+			};
+
+			prg1: prg at 021cc000 {
+				compatible = "fsl,imx6q-prg";

Ditto

include/dt-bindings/clock/imx6qdl-clock.h

Quoted 65 lines
arch/arm/boot/dts/imx6qp.dtsi new file +61 -0
+				reg = <0x021cc000 0x1000>;
+				clocks = <&clks IMX6QDL_CLK_PRG0_AXI>,
+					 <&clks IMX6QDL_CLK_PRG0_APB>;
+				clock-names = "axi", "apb";
+				gpr = <&gpr>;
+				status = "disabled";
+			};
+
+			prg2: prg at 021cd000 {
+				compatible = "fsl,imx6q-prg";
+				reg = <0x021cd000 0x1000>;
+				clocks = <&clks IMX6QDL_CLK_PRG1_AXI>,
+					 <&clks IMX6QDL_CLK_PRG1_APB>;
+				clock-names = "axi", "apb";
+				gpr = <&gpr>;
+				status = "disabled";
+			};
+		};
+
+		ipu1: ipu at 02400000 {
+			compatible = "fsl,imx6qp-ipu", "fsl,imx6q-ipu";
+			clocks = <&clks IMX6QDL_CLK_IPU1>,
+				 <&clks IMX6QDL_CLK_IPU1_DI0>, <&clks IMX6QDL_CLK_IPU1_DI1>,
+				 <&clks IMX6QDL_CLK_IPU1_DI0_SEL>, <&clks IMX6QDL_CLK_IPU1_DI1_SEL>,
+				 <&clks IMX6QDL_CLK_LDB_DI0_PODF>, <&clks IMX6QDL_CLK_LDB_DI1_PODF>,
+				 <&clks IMX6QDL_CLK_PRG0_APB>;
+			clock-names = "bus",
+				      "di0", "di1",
+				      "di0_sel", "di1_sel",
+				      "ldb_di0", "ldb_di1", "prg";
+		};
+
+		ipu2: ipu at 02800000 {
+			compatible = "fsl,imx6qp-ipu", "fsl,imx6q-ipu";
+			clocks = <&clks IMX6QDL_CLK_IPU2>,
+				 <&clks IMX6QDL_CLK_IPU2_DI0>, <&clks IMX6QDL_CLK_IPU2_DI1>,
+				 <&clks IMX6QDL_CLK_IPU2_DI0_SEL>, <&clks IMX6QDL_CLK_IPU2_DI1_SEL>,
+				 <&clks IMX6QDL_CLK_LDB_DI0_PODF>, <&clks IMX6QDL_CLK_LDB_DI1_PODF>,
+				 <&clks IMX6QDL_CLK_PRG1_APB>;
+			clock-names = "bus",
+				      "di0", "di1",
+				      "di0_sel", "di1_sel",
+				      "ldb_di0", "ldb_di1", "prg";
+		};
+
+		sata: sata at 02200000 {
+			compatible = "fsl,imx6qp-ahci";
+			reg = <0x02200000 0x4000>;
+			interrupts = <0 39 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&clks IMX6QDL_CLK_SATA>,
+				 <&clks IMX6QDL_CLK_SATA_REF_100M>,
+				 <&clks IMX6QDL_CLK_AHB>;
+			clock-names = "sata", "sata_ref", "ahb";
+			status = "disabled";
+		};
+	};
+};
+
+&ldb {
+	compatible = "fsl,imx6qp-ldb", "fsl,imx6q-ldb", "fsl,imx53-ldb";
+};
include/dt-bindings/clock/imx6qdl-clock.h +0 -0
index 77985cc..2905033 100644

This file should be updated in the patch that updates clock driver. Only after these new clocks get supported by clock driver, you can use them in device tree.

Shawn

Quoted 26 lines
include/dt-bindings/clock/imx6qdl-clock.h +15 -1
@@ -255,6 +255,20 @@
 #define IMX6QDL_CLK_CAAM_ACLK			242
 #define IMX6QDL_CLK_CAAM_IPG			243
 #define IMX6QDL_CLK_SPDIF_GCLK			244
-#define IMX6QDL_CLK_END				245
+#define IMX6QDL_CLK_UART_SEL			245
+#define IMX6QDL_CLK_IPG_PER_SEL			246
+#define IMX6QDL_CLK_ECSPI_SEL			247
+#define IMX6QDL_CLK_CAN_SEL			248
+#define IMX6QDL_CLK_MMDC_CH1_AXI_CG		249
+#define IMX6QDL_CLK_PRE0			250
+#define IMX6QDL_CLK_PRE1			251
+#define IMX6QDL_CLK_PRE2			252
+#define IMX6QDL_CLK_PRE3			253
+#define IMX6QDL_CLK_PRG0_AXI			254
+#define IMX6QDL_CLK_PRG1_AXI			255
+#define IMX6QDL_CLK_PRG0_APB			256
+#define IMX6QDL_CLK_PRG1_APB			257
+#define IMX6QDL_CLK_PRE_AXI			258
+#define IMX6QDL_CLK_END				259
 
 #endif /* __DT_BINDINGS_CLOCK_IMX6QDL_H */
Signature · 1 line
1.9.1
#3 lore raw

PATCH v2 1/5 ARM: dts: imx: Add basic dts support for imx6qp SOC

Quoted 54 lines

-----Original Message-----
From: Shawn Guo [mailto:shawnguo at kernel.org]
Sent: 2016?1?28? 15:43
To: b51503 at freescale.com
Cc: kernel at pengutronix.de; pawel.moll at arm.com; robh+dt at kernel.org; mturquette at baylibre.com; sboyd at codeaurora.org; linux-arm- kernel at lists.infradead.org; linux-clk at vger.kernel.org; devicetree at vger.kernel.org
Subject: Re: [PATCH v2 1/5] ARM: dts: imx: Add basic dts support for imx6qp SOC

Quoted 7 lines · Bai Ping

The i.MX6Quad Plus processor is an high performance SOC of i.MX6 family. It has enhanced graphics performance and increased overall memory bandwidth compared to i.MX6Q. Most of the design are same as i.MX6Quad/Dual, so code for i.MX6Quad can be resued by this chip. The revision number is identied as i.MX6Q Rev2.0, but actually it is a new chip, as we did many change to the overall architecture.

Quoted 6 lines

This patch adds basic dtsi file support for the new i.MX6Quad Plus processor.

Signed-off-by Bai Ping <[email protected]>
---
 arch/arm/boot/dts/imx6q.dtsi              |   2 +-
 arch/arm/boot/dts/imx6qp.dtsi             | 157

++++++++++++++++++++++++++++++

Quoted 26 lines
 include/dt-bindings/clock/imx6qdl-clock.h |  16 ++-
 3 files changed, 173 insertions(+), 2 deletions(-)  create mode

100644 arch/arm/boot/dts/imx6qp.dtsi

(quoted diff) +0 -0

b/arch/arm/boot/dts/imx6q.dtsi index a266a56..e26d0fd 100644

arch/arm/boot/dts/imx6q.dtsi +1 -1
@@ -22,7 +22,7 @@
 		#address-cells = <1>;
 		#size-cells = <0>;
 
-		cpu at 0 {
+		cpu0: cpu at 0 {
 			compatible = "arm,cortex-a9";
 			device_type = "cpu";
 			reg = <0>;
(quoted diff) +0 -0

b/arch/arm/boot/dts/imx6qp.dtsi new file mode 100644 index 0000000..e43751f

arch/arm/boot/dts/imx6qp.dtsi new file +3 -0
@@ -0,0 +1,157 @@
+/*
+ * Copyright 2015 Freescale Semiconductor, Inc.
+ *
Quoted 9 lines

arch/arm/boot/dts/imx6qp.dtsi line 6

Quoted 4 lines
arch/arm/boot/dts/imx6qp.dtsi new file +4 -0
+ * This program is free software; you can redistribute it and/or
+modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.

For new dts files, we suggest to use GPL/X11 dual license to consider non-Linux users. You can grep "dual-licensed" in arch/arm/boot/dts to find a plenty of examples.

ok, I will fix this in patch V3.

Quoted 6 lines

arch/arm/boot/dts/imx6qp.dtsi line 9

Quoted 3 lines
arch/arm/boot/dts/imx6qp.dtsi new file +3 -0
+ *
+ */
+

Do you not need to include "imx6qdl.dtsi" here?

Quoted 15 lines

arch/arm/boot/dts/imx6qp.dtsi line 21

Quoted 12 lines
arch/arm/boot/dts/imx6qp.dtsi new file +12 -0
+/ {
+	aliases {
+		pre0 = &pre1;
+		pre1 = &pre2;
+		pre2 = &pre3;
+		pre3 = &pre4;
+		prg0 = &prg1;
+		prg1 = &prg2;
+	};
+
+	soc {
+		ocram_2: sram at 00940000 {

The label can just be ocram2.

ok, thanks for you suggest.

Quoted 44 lines

arch/arm/boot/dts/imx6qp.dtsi line 27

Quoted 6 lines
arch/arm/boot/dts/imx6qp.dtsi new file +6 -0
+			compatible = "mmio-sram";
+			reg = <0x00940000 0x20000>;
+			clocks = <&clks IMX6QDL_CLK_OCRAM>;
+		};
+
+		ocram_3: sram at 00960000 {

ocram3

arch/arm/boot/dts/imx6qp.dtsi

Quoted 13 lines
arch/arm/boot/dts/imx6qp.dtsi new file +13 -0
+			compatible = "mmio-sram";
+			reg = <0x00960000 0x20000>;
+			clocks = <&clks IMX6QDL_CLK_OCRAM>;
+		};
+
+		pcie: pcie at 0x01000000 {
+			compatible = "fsl,imx6qp-pcie", "snps,dw-pcie";
+			reg = <0x01ffc000 0x4000>, <0x01f00000 0x80000>;
+			reg-names = "dbi", "config";
+			#address-cells = <3>;
+			#size-cells = <2>;
+			device_type = "pci";
+			ranges = <0x81000000 0 0          0x01f80000 0 0x00010000

/* downstream I/O */

arch/arm/boot/dts/imx6qp.dtsi line 42

Quoted 1 line
arch/arm/boot/dts/imx6qp.dtsi new file +1 -0
+				  0x82000000 0 0x01000000 0x01000000 0

0x00f00000>; /* non-prefetchable memory */

arch/arm/boot/dts/imx6qp.dtsi

Quoted 6 lines
arch/arm/boot/dts/imx6qp.dtsi new file +6 -0
+			num-lanes = <1>;
+			interrupts = <0 120 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "msi";
+			#interrupt-cells = <1>;
+			interrupt-map-mask = <0 0 0 0x7>;
+			interrupt-map = <0 0 0 1 &intc 0 123

IRQ_TYPE_LEVEL_HIGH>,

arch/arm/boot/dts/imx6qp.dtsi line 49

Quoted 1 line
arch/arm/boot/dts/imx6qp.dtsi new file +1 -0
+					<0 0 0 2 &intc 0 122

IRQ_TYPE_LEVEL_HIGH>,

arch/arm/boot/dts/imx6qp.dtsi line 50

Quoted 1 line
arch/arm/boot/dts/imx6qp.dtsi new file +1 -0
+					<0 0 0 3 &intc 0 121

IRQ_TYPE_LEVEL_HIGH>,

arch/arm/boot/dts/imx6qp.dtsi line 51

Quoted 1 line
arch/arm/boot/dts/imx6qp.dtsi new file +1 -0
+					<0 0 0 4 &intc 0 120

IRQ_TYPE_LEVEL_HIGH>;

arch/arm/boot/dts/imx6qp.dtsi

Quoted 3 lines
arch/arm/boot/dts/imx6qp.dtsi new file +3 -0
+			clocks = <&clks IMX6QDL_CLK_PCIE_REF_125M>,
+				 <&clks IMX6QDL_CLK_SATA_REF_100M>,
+				 <&clks IMX6QDL_CLK_LVDS1_GATE>, <&clks

IMX6QDL_CLK_PCIE_AXI>;

arch/arm/boot/dts/imx6qp.dtsi line 55

Quoted 1 line
arch/arm/boot/dts/imx6qp.dtsi new file +1 -0
+			clock-names = "pcie_phy", "ref_100m", "pcie_bus",

"pcie";

Quoted 10 lines

arch/arm/boot/dts/imx6qp.dtsi line 60

Quoted 6 lines
arch/arm/boot/dts/imx6qp.dtsi new file +6 -0
+			status = "disabled";
+		};
+
+		aips-bus at 02100000 { /* AIPS2 */
+			pre1: pre at 021c8000 {
+				compatible = "fsl,imx6q-pre";

Is there already a device tree binding and driver for this block in upstream kernel? I do not accepted any unestablished device.

No driver available in upstream kernel, I will remove these node in patch V3.

Quoted 106 lines
Quoted 26 lines
arch/arm/boot/dts/imx6qp.dtsi new file +26 -0
+				reg = <0x021c8000 0x1000>;
+				clocks = <&clks IMX6QDL_CLK_PRE0>;
+				interrupts = <0 90 IRQ_TYPE_EDGE_RISING>;
+				ocram = <&ocram_2>;
+				status = "disabled";
+			};
+
+			pre2: pre at 021c9000 {
+				compatible = "fsl,imx6q-pre";
+				reg = <0x021c9000 0x1000>;
+				clocks = <&clks IMX6QDL_CLK_PRE1>;
+				interrupts = <0 97 IRQ_TYPE_EDGE_RISING>;
+				ocram = <&ocram_2>;
+				status = "disabled";
+			};
+
+			pre3: pre at 021ca000 {
+				compatible = "fsl,imx6q-pre";
+				reg = <0x021ca000 0x1000>;
+				clocks = <&clks IMX6QDL_CLK_PRE2>;
+				interrupts = <0 98 IRQ_TYPE_EDGE_RISING>;
+				ocram = <&ocram_3>;
+				status = "disabled";
+			};
+
+			pre4: pre at 021cb000 {

arch/arm/boot/dts/imx6qp.dtsi line 96

Quoted 10 lines
arch/arm/boot/dts/imx6qp.dtsi new file +10 -0
+				compatible = "fsl,imx6q-pre";
+				reg = <0x021cb000 0x1000>;
+				clocks = <&clks IMX6QDL_CLK_PRE3>;
+				interrupts = <0 99 IRQ_TYPE_EDGE_RISING>;
+				ocram = <&ocram_3>;
+				status = "disabled";
+			};
+
+			prg1: prg at 021cc000 {
+				compatible = "fsl,imx6q-prg";

Ditto

Quoted 13 lines
arch/arm/boot/dts/imx6qp.dtsi new file +13 -0
+				reg = <0x021cc000 0x1000>;
+				clocks = <&clks IMX6QDL_CLK_PRG0_AXI>,
+					 <&clks IMX6QDL_CLK_PRG0_APB>;
+				clock-names = "axi", "apb";
+				gpr = <&gpr>;
+				status = "disabled";
+			};
+
+			prg2: prg at 021cd000 {
+				compatible = "fsl,imx6q-prg";
+				reg = <0x021cd000 0x1000>;
+				clocks = <&clks IMX6QDL_CLK_PRG1_AXI>,
+					 <&clks IMX6QDL_CLK_PRG1_APB>;

arch/arm/boot/dts/imx6qp.dtsi

Quoted 10 lines
arch/arm/boot/dts/imx6qp.dtsi new file +10 -0
+				clock-names = "axi", "apb";
+				gpr = <&gpr>;
+				status = "disabled";
+			};
+		};
+
+		ipu1: ipu at 02400000 {
+			compatible = "fsl,imx6qp-ipu", "fsl,imx6q-ipu";
+			clocks = <&clks IMX6QDL_CLK_IPU1>,
+				 <&clks IMX6QDL_CLK_IPU1_DI0>, <&clks

IMX6QDL_CLK_IPU1_DI1>,

arch/arm/boot/dts/imx6qp.dtsi line 121

Quoted 1 line
arch/arm/boot/dts/imx6qp.dtsi new file +1 -0
+				 <&clks IMX6QDL_CLK_IPU1_DI0_SEL>, <&clks

IMX6QDL_CLK_IPU1_DI1_SEL>,

arch/arm/boot/dts/imx6qp.dtsi line 122

Quoted 1 line
arch/arm/boot/dts/imx6qp.dtsi new file +1 -0
+				 <&clks IMX6QDL_CLK_LDB_DI0_PODF>, <&clks

IMX6QDL_CLK_LDB_DI1_PODF>,

arch/arm/boot/dts/imx6qp.dtsi

Quoted 11 lines
arch/arm/boot/dts/imx6qp.dtsi new file +11 -0
+				 <&clks IMX6QDL_CLK_PRG0_APB>;
+			clock-names = "bus",
+				      "di0", "di1",
+				      "di0_sel", "di1_sel",
+				      "ldb_di0", "ldb_di1", "prg";
+		};
+
+		ipu2: ipu at 02800000 {
+			compatible = "fsl,imx6qp-ipu", "fsl,imx6q-ipu";
+			clocks = <&clks IMX6QDL_CLK_IPU2>,
+				 <&clks IMX6QDL_CLK_IPU2_DI0>, <&clks

IMX6QDL_CLK_IPU2_DI1>,

arch/arm/boot/dts/imx6qp.dtsi line 134

Quoted 1 line
arch/arm/boot/dts/imx6qp.dtsi new file +1 -0
+				 <&clks IMX6QDL_CLK_IPU2_DI0_SEL>, <&clks

IMX6QDL_CLK_IPU2_DI1_SEL>,

arch/arm/boot/dts/imx6qp.dtsi line 135

Quoted 1 line
arch/arm/boot/dts/imx6qp.dtsi new file +1 -0
+				 <&clks IMX6QDL_CLK_LDB_DI0_PODF>, <&clks

IMX6QDL_CLK_LDB_DI1_PODF>,

Quoted 23 lines
arch/arm/boot/dts/imx6qp.dtsi new file +22 -0
+				 <&clks IMX6QDL_CLK_PRG1_APB>;
+			clock-names = "bus",
+				      "di0", "di1",
+				      "di0_sel", "di1_sel",
+				      "ldb_di0", "ldb_di1", "prg";
+		};
+
+		sata: sata at 02200000 {
+			compatible = "fsl,imx6qp-ahci";
+			reg = <0x02200000 0x4000>;
+			interrupts = <0 39 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&clks IMX6QDL_CLK_SATA>,
+				 <&clks IMX6QDL_CLK_SATA_REF_100M>,
+				 <&clks IMX6QDL_CLK_AHB>;
+			clock-names = "sata", "sata_ref", "ahb";
+			status = "disabled";
+		};
+	};
+};
+
+&ldb {
+	compatible = "fsl,imx6qp-ldb", "fsl,imx6q-ldb", "fsl,imx53-ldb"; };
(quoted diff) +0 -0
Quoted 9 lines

include/dt-bindings/clock/imx6qdl-clock.h

Quoted 4 lines

b/include/dt-bindings/clock/imx6qdl-clock.h
index 77985cc..2905033 100644

include/dt-bindings/clock/imx6qdl-clock.h +0 -0

This file should be updated in the patch that updates clock driver. Only after these new clocks get supported by clock driver, you can use them in device tree.

ok, thanks for you review.

Quoted 28 lines

Shawn

Quoted 26 lines
include/dt-bindings/clock/imx6qdl-clock.h +15 -2
@@ -255,6 +255,20 @@
 #define IMX6QDL_CLK_CAAM_ACLK			242
 #define IMX6QDL_CLK_CAAM_IPG			243
 #define IMX6QDL_CLK_SPDIF_GCLK			244
-#define IMX6QDL_CLK_END				245
+#define IMX6QDL_CLK_UART_SEL			245
+#define IMX6QDL_CLK_IPG_PER_SEL			246
+#define IMX6QDL_CLK_ECSPI_SEL			247
+#define IMX6QDL_CLK_CAN_SEL			248
+#define IMX6QDL_CLK_MMDC_CH1_AXI_CG		249
+#define IMX6QDL_CLK_PRE0			250
+#define IMX6QDL_CLK_PRE1			251
+#define IMX6QDL_CLK_PRE2			252
+#define IMX6QDL_CLK_PRE3			253
+#define IMX6QDL_CLK_PRG0_AXI			254
+#define IMX6QDL_CLK_PRG1_AXI			255
+#define IMX6QDL_CLK_PRG0_APB			256
+#define IMX6QDL_CLK_PRG1_APB			257
+#define IMX6QDL_CLK_PRE_AXI			258
+#define IMX6QDL_CLK_END				259
 
 #endif /* __DT_BINDINGS_CLOCK_IMX6QDL_H */
--

1.9.1

author
#4 lore raw

PATCH v2 2/5 ARM: dts: imx: Add basic dts support for imx6qp-sabresd

In reply to Bai Ping

The patch adds dts file for imx6qp-sabresd board.

Signed-off-by Bai Ping <[email protected]>
---
 arch/arm/boot/dts/Makefile             |  1 +
 arch/arm/boot/dts/imx6qdl-sabresd.dtsi |  1 +
 arch/arm/boot/dts/imx6qp-sabresd.dts   | 59 ++++++++++++++++++++++++++++++++++
 3 files changed, 61 insertions(+)
 create mode 100644 arch/arm/boot/dts/imx6qp-sabresd.dts
arch/arm/boot/dts/Makefile +1 -0
index 36d8133..dfba765 100644
@@ -302,6 +302,7 @@ dtb-$(CONFIG_SOC_IMX6Q) += \
 	imx6dl-sabreauto.dtb \
 	imx6dl-sabrelite.dtb \
 	imx6dl-sabresd.dtb \
+	imx6qp-sabresd.dtb \
 	imx6dl-tx6dl-comtft.dtb \
 	imx6dl-tx6u-801x.dtb \
 	imx6dl-tx6u-811x.dtb \
arch/arm/boot/dts/imx6qdl-sabresd.dtsi +1 -0
index a6d445c..f65f57b 100644
@@ -238,6 +238,7 @@
 				regulator-max-microvolt = <3300000>;
 				regulator-boot-on;
 				regulator-always-on;
+				regulator-ramp-delay = <6250>;
 			};
 
 			sw3a_reg: sw3a {
arch/arm/boot/dts/imx6qp-sabresd.dts new file +59 -0

59 lines not on this page · raw message

Signature · 1 line
1.9.1
#5 lore raw

PATCH v2 2/5 ARM: dts: imx: Add basic dts support for imx6qp-sabresd

Quoted 15 lines · Bai Ping

The patch adds dts file for imx6qp-sabresd board.

Signed-off-by Bai Ping <[email protected]>
---
 arch/arm/boot/dts/Makefile             |  1 +
 arch/arm/boot/dts/imx6qdl-sabresd.dtsi |  1 +
 arch/arm/boot/dts/imx6qp-sabresd.dts   | 59 ++++++++++++++++++++++++++++++++++
 3 files changed, 61 insertions(+)
 create mode 100644 arch/arm/boot/dts/imx6qp-sabresd.dts
arch/arm/boot/dts/Makefile +0 -0
index 36d8133..dfba765 100644

arch/arm/boot/dts/Makefile dtb-$(CONFIG_SOC_IMX6Q) += \ · line 305

Quoted 4 lines
arch/arm/boot/dts/Makefile +1 -0
@@ -302,6 +302,7 @@ dtb-$(CONFIG_SOC_IMX6Q) += \
 	imx6dl-sabreauto.dtb \
 	imx6dl-sabrelite.dtb \
 	imx6dl-sabresd.dtb \
+	imx6qp-sabresd.dtb \

Please keep the list sort alphabetically. That said, imx6qp-sabresd.dtb should be added after imx6q-* ones.

arch/arm/boot/dts/imx6qdl-sabresd.dtsi line 241

Quoted 12 lines
arch/arm/boot/dts/Makefile +0 -0
 	imx6dl-tx6dl-comtft.dtb \
 	imx6dl-tx6u-801x.dtb \
 	imx6dl-tx6u-811x.dtb \
arch/arm/boot/dts/imx6qdl-sabresd.dtsi +1 -0
index a6d445c..f65f57b 100644
@@ -238,6 +238,7 @@
 				regulator-max-microvolt = <3300000>;
 				regulator-boot-on;
 				regulator-always-on;
+				regulator-ramp-delay = <6250>;

So this change applies to imx6q and imx6dl sabresd as well?

Quoted 9 lines
arch/arm/boot/dts/imx6qdl-sabresd.dtsi +0 -0
 			};
 
 			sw3a_reg: sw3a {
arch/arm/boot/dts/imx6qp-sabresd.dts new file +0 -0
new file mode 100644
index 0000000..c3ab2b6

arch/arm/boot/dts/imx6qp-sabresd.dts line 10

Quoted 10 lines
arch/arm/boot/dts/imx6qp-sabresd.dts new file +10 -0
@@ -0,0 +1,59 @@
+/*
+ * Copyright (C) 2015 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include "imx6q-sabresd.dts"
+#include "imx6qp.dtsi"

Ah, that's why you do not include "imx6qdl.dtsi" in imx6qp.dtsi. I have a question with this approach. How people should write his imx6qp board dts file, if his board never has an imx6q version?

arch/arm/boot/dts/imx6qp-sabresd.dts line 22

Quoted 12 lines
arch/arm/boot/dts/imx6qp-sabresd.dts new file +12 -0
+
+/ {
+	model = "Freescale i.MX6 Quad Plus SABRE Smart Device Board";
+	compatible = "fsl,imx6qp-sabresd", "fsl,imx6qp";
+};
+
+&cpu0 {
+	arm-supply = <&sw2_reg>;
+};
+
+&iomuxc {
+	imx6qdl-sabresd {

Since commit 5fcdf6a7ed95 (pinctrl: imx: Allow parsing DT without function nodes), this additional container node can just be saved.

Shawn

Quoted 46 lines
arch/arm/boot/dts/imx6qp-sabresd.dts new file +37 -0
+		pinctrl_usdhc2: usdhc2grp {
+			fsl,pins = <
+				MX6QDL_PAD_SD2_CMD__SD2_CMD		0x17059
+				MX6QDL_PAD_SD2_CLK__SD2_CLK		0x10071
+				MX6QDL_PAD_SD2_DAT0__SD2_DATA0		0x17059
+				MX6QDL_PAD_SD2_DAT1__SD2_DATA1		0x17059
+				MX6QDL_PAD_SD2_DAT2__SD2_DATA2		0x17059
+				MX6QDL_PAD_SD2_DAT3__SD2_DATA3		0x17059
+				MX6QDL_PAD_NANDF_D4__SD2_DATA4		0x17059
+				MX6QDL_PAD_NANDF_D5__SD2_DATA5		0x17059
+				MX6QDL_PAD_NANDF_D6__SD2_DATA6		0x17059
+				MX6QDL_PAD_NANDF_D7__SD2_DATA7		0x17059
+			>;
+		};
+
+		pinctrl_usdhc3: usdhc3grp {
+			fsl,pins = <
+				MX6QDL_PAD_SD3_CMD__SD3_CMD		0x17059
+				MX6QDL_PAD_SD3_CLK__SD3_CLK		0x10071
+				MX6QDL_PAD_SD3_DAT0__SD3_DATA0		0x17059
+				MX6QDL_PAD_SD3_DAT1__SD3_DATA1		0x17059
+				MX6QDL_PAD_SD3_DAT2__SD3_DATA2		0x17059
+				MX6QDL_PAD_SD3_DAT3__SD3_DATA3		0x17059
+				MX6QDL_PAD_SD3_DAT4__SD3_DATA4		0x17059
+				MX6QDL_PAD_SD3_DAT5__SD3_DATA5		0x17059
+				MX6QDL_PAD_SD3_DAT6__SD3_DATA6		0x17059
+				MX6QDL_PAD_SD3_DAT7__SD3_DATA7		0x17059
+			>;
+		};
+	};
+};
+
+&pcie {
+	power-on-gpio = <&gpio3 19 0>;
+	reset-gpio = <&gpio7 12 0>;
+	status = "okay";
+};
Signature · 7 lines
1.9.1


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel at lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
#6 lore raw

PATCH v2 2/5 ARM: dts: imx: Add basic dts support for imx6qp-sabresd

Quoted 38 lines

-----Original Message-----
From: Shawn Guo [mailto:shawnguo at kernel.org]
Sent: 2016?1?28? 15:54
To: b51503 at freescale.com
Cc: kernel at pengutronix.de; devicetree at vger.kernel.org; pawel.moll at arm.com; mturquette at baylibre.com; sboyd at codeaurora.org; robh+dt at kernel.org; linux-clk at vger.kernel.org; linux-arm- kernel at lists.infradead.org
Subject: Re: [PATCH v2 2/5] ARM: dts: imx: Add basic dts support for imx6qp- sabresd

Quoted 7 lines · Bai Ping

The patch adds dts file for imx6qp-sabresd board.

Signed-off-by Bai Ping <[email protected]>
---
 arch/arm/boot/dts/Makefile             |  1 +
 arch/arm/boot/dts/imx6qdl-sabresd.dtsi |  1 +
 arch/arm/boot/dts/imx6qp-sabresd.dts   | 59

++++++++++++++++++++++++++++++++++

arch/arm/boot/dts/Makefile dtb-$(CONFIG_SOC_IMX6Q) += \ · line 305

Quoted 12 lines
 3 files changed, 61 insertions(+)
 create mode 100644 arch/arm/boot/dts/imx6qp-sabresd.dts
arch/arm/boot/dts/Makefile +1 -0
index 36d8133..dfba765 100644
@@ -302,6 +302,7 @@ dtb-$(CONFIG_SOC_IMX6Q) += \
 	imx6dl-sabreauto.dtb \
 	imx6dl-sabrelite.dtb \
 	imx6dl-sabresd.dtb \
+	imx6qp-sabresd.dtb \

Please keep the list sort alphabetically. That said, imx6qp-sabresd.dtb should be added after imx6q-* ones.

Quoted 16 lines

arch/arm/boot/dts/imx6qdl-sabresd.dtsi line 241

Quoted 13 lines
arch/arm/boot/dts/Makefile +0 -0
 	imx6dl-tx6dl-comtft.dtb \
 	imx6dl-tx6u-801x.dtb \
 	imx6dl-tx6u-811x.dtb \
arch/arm/boot/dts/imx6qdl-sabresd.dtsi +1 -0
index a6d445c..f65f57b 100644
@@ -238,6 +238,7 @@
 				regulator-max-microvolt = <3300000>;
 				regulator-boot-on;
 				regulator-always-on;
+				regulator-ramp-delay = <6250>;

So this change applies to imx6q and imx6dl sabresd as well?

Yes, this change applies to imx6q and imx6dl sabresd.

Quoted 17 lines
Quoted 17 lines
arch/arm/boot/dts/imx6qdl-sabresd.dtsi +0 -0
 			};
 
 			sw3a_reg: sw3a {
arch/arm/boot/dts/imx6qp-sabresd.dts new file +7 -0
new file mode 100644
index 0000000..c3ab2b6
@@ -0,0 +1,59 @@
+/*
+ * Copyright (C) 2015 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
Quoted 9 lines

arch/arm/boot/dts/imx6qp-sabresd.dts line 10

Quoted 4 lines
arch/arm/boot/dts/imx6qp-sabresd.dts new file +4 -0
+ */
+
+#include "imx6q-sabresd.dts"
+#include "imx6qp.dtsi"

Ah, that's why you do not include "imx6qdl.dtsi" in imx6qp.dtsi. I have a question with this approach. How people should write his imx6qp board dts file, if his board never has an imx6q version?

Sure, it is a problem, include the imx6qdl.dtsi in imx6qp.dtsi is more reasonable.

Quoted 83 lines

arch/arm/boot/dts/imx6qp-sabresd.dts line 22

Quoted 11 lines
arch/arm/boot/dts/imx6qp-sabresd.dts new file +11 -0
+
+/ {
+	model = "Freescale i.MX6 Quad Plus SABRE Smart Device Board";
+	compatible = "fsl,imx6qp-sabresd", "fsl,imx6qp"; };
+
+&cpu0 {
+	arm-supply = <&sw2_reg>;
+};
+
+&iomuxc {
+	imx6qdl-sabresd {

Since commit 5fcdf6a7ed95 (pinctrl: imx: Allow parsing DT without function nodes), this additional container node can just be saved.

Shawn

arch/arm/boot/dts/imx6qp-sabresd.dts

Quoted 3 lines
arch/arm/boot/dts/imx6qp-sabresd.dts new file +3 -0
+		pinctrl_usdhc2: usdhc2grp {
+			fsl,pins = <
+				MX6QDL_PAD_SD2_CMD__SD2_CMD

	0x17059

arch/arm/boot/dts/imx6qp-sabresd.dts line 26

Quoted 1 line
arch/arm/boot/dts/imx6qp-sabresd.dts new file +1 -0
+				MX6QDL_PAD_SD2_CLK__SD2_CLK

	0x10071

arch/arm/boot/dts/imx6qp-sabresd.dts line 27

Quoted 1 line
arch/arm/boot/dts/imx6qp-sabresd.dts new file +1 -0
+				MX6QDL_PAD_SD2_DAT0__SD2_DATA0

	0x17059

arch/arm/boot/dts/imx6qp-sabresd.dts line 28

Quoted 1 line
arch/arm/boot/dts/imx6qp-sabresd.dts new file +1 -0
+				MX6QDL_PAD_SD2_DAT1__SD2_DATA1

	0x17059

arch/arm/boot/dts/imx6qp-sabresd.dts line 29

Quoted 1 line
arch/arm/boot/dts/imx6qp-sabresd.dts new file +1 -0
+				MX6QDL_PAD_SD2_DAT2__SD2_DATA2

	0x17059

arch/arm/boot/dts/imx6qp-sabresd.dts line 30

Quoted 1 line
arch/arm/boot/dts/imx6qp-sabresd.dts new file +1 -0
+				MX6QDL_PAD_SD2_DAT3__SD2_DATA3

	0x17059

arch/arm/boot/dts/imx6qp-sabresd.dts line 31

Quoted 1 line
arch/arm/boot/dts/imx6qp-sabresd.dts new file +1 -0
+				MX6QDL_PAD_NANDF_D4__SD2_DATA4

	0x17059

arch/arm/boot/dts/imx6qp-sabresd.dts line 32

Quoted 1 line
arch/arm/boot/dts/imx6qp-sabresd.dts new file +1 -0
+				MX6QDL_PAD_NANDF_D5__SD2_DATA5

	0x17059

arch/arm/boot/dts/imx6qp-sabresd.dts line 33

Quoted 1 line
arch/arm/boot/dts/imx6qp-sabresd.dts new file +1 -0
+				MX6QDL_PAD_NANDF_D6__SD2_DATA6

	0x17059

arch/arm/boot/dts/imx6qp-sabresd.dts line 34

Quoted 1 line
arch/arm/boot/dts/imx6qp-sabresd.dts new file +1 -0
+				MX6QDL_PAD_NANDF_D7__SD2_DATA7

	0x17059

arch/arm/boot/dts/imx6qp-sabresd.dts

Quoted 6 lines
arch/arm/boot/dts/imx6qp-sabresd.dts new file +6 -0
+			>;
+		};
+
+		pinctrl_usdhc3: usdhc3grp {
+			fsl,pins = <
+				MX6QDL_PAD_SD3_CMD__SD3_CMD

	0x17059

arch/arm/boot/dts/imx6qp-sabresd.dts line 41

Quoted 1 line
arch/arm/boot/dts/imx6qp-sabresd.dts new file +1 -0
+				MX6QDL_PAD_SD3_CLK__SD3_CLK

	0x10071

arch/arm/boot/dts/imx6qp-sabresd.dts line 42

Quoted 1 line
arch/arm/boot/dts/imx6qp-sabresd.dts new file +1 -0
+				MX6QDL_PAD_SD3_DAT0__SD3_DATA0

	0x17059

arch/arm/boot/dts/imx6qp-sabresd.dts line 43

Quoted 1 line
arch/arm/boot/dts/imx6qp-sabresd.dts new file +1 -0
+				MX6QDL_PAD_SD3_DAT1__SD3_DATA1

	0x17059

arch/arm/boot/dts/imx6qp-sabresd.dts line 44

Quoted 1 line
arch/arm/boot/dts/imx6qp-sabresd.dts new file +1 -0
+				MX6QDL_PAD_SD3_DAT2__SD3_DATA2

	0x17059

arch/arm/boot/dts/imx6qp-sabresd.dts line 45

Quoted 1 line
arch/arm/boot/dts/imx6qp-sabresd.dts new file +1 -0
+				MX6QDL_PAD_SD3_DAT3__SD3_DATA3

	0x17059

arch/arm/boot/dts/imx6qp-sabresd.dts line 46

Quoted 1 line
arch/arm/boot/dts/imx6qp-sabresd.dts new file +1 -0
+				MX6QDL_PAD_SD3_DAT4__SD3_DATA4

	0x17059

arch/arm/boot/dts/imx6qp-sabresd.dts line 47

Quoted 1 line
arch/arm/boot/dts/imx6qp-sabresd.dts new file +1 -0
+				MX6QDL_PAD_SD3_DAT5__SD3_DATA5

	0x17059

arch/arm/boot/dts/imx6qp-sabresd.dts line 48

Quoted 1 line
arch/arm/boot/dts/imx6qp-sabresd.dts new file +1 -0
+				MX6QDL_PAD_SD3_DAT6__SD3_DATA6

	0x17059

arch/arm/boot/dts/imx6qp-sabresd.dts line 49

Quoted 1 line
arch/arm/boot/dts/imx6qp-sabresd.dts new file +1 -0
+				MX6QDL_PAD_SD3_DAT7__SD3_DATA7

	0x17059
Quoted 19 lines
arch/arm/boot/dts/imx6qp-sabresd.dts new file +10 -1
+			>;
+		};
+	};
+};
+
+&pcie {
+	power-on-gpio = <&gpio3 19 0>;
+	reset-gpio = <&gpio7 12 0>;
+	status = "okay";
+};
--

1.9.1

_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel at lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

author
#7 lore raw

PATCH v2 3/5 ARM: dts: imx: Add basic dts support for imx6qp-sabreauto

In reply to Bai Ping

This patch adds basic dts file for imx6qp-sabreauto board.

Signed-off-by Bai Ping <[email protected]>
---
 arch/arm/boot/dts/Makefile             |  1 +
 arch/arm/boot/dts/imx6qp-sabreauto.dts | 67 ++++++++++++++++++++++++++++++++++
 2 files changed, 68 insertions(+)
 create mode 100644 arch/arm/boot/dts/imx6qp-sabreauto.dts
arch/arm/boot/dts/Makefile +1 -0
index dfba765..7996a51 100644
@@ -329,6 +329,7 @@ dtb-$(CONFIG_SOC_IMX6Q) += \
 	imx6q-phytec-pbab01.dtb \
 	imx6q-rex-pro.dtb \
 	imx6q-sabreauto.dtb \
+	imx6qp-sabreauto.dtb \
 	imx6q-sabrelite.dtb \
 	imx6q-sabresd.dtb \
 	imx6q-sbc6x.dtb \
arch/arm/boot/dts/imx6qp-sabreauto.dts new file +67 -0

67 lines not on this page · raw message

Signature · 1 line
1.9.1
#8 lore raw

PATCH v2 3/5 ARM: dts: imx: Add basic dts support for imx6qp-sabreauto

Quoted 14 lines · Bai Ping

This patch adds basic dts file for imx6qp-sabreauto board.

Signed-off-by Bai Ping <[email protected]>
---
 arch/arm/boot/dts/Makefile             |  1 +
 arch/arm/boot/dts/imx6qp-sabreauto.dts | 67 ++++++++++++++++++++++++++++++++++
 2 files changed, 68 insertions(+)
 create mode 100644 arch/arm/boot/dts/imx6qp-sabreauto.dts
arch/arm/boot/dts/Makefile +0 -0
index dfba765..7996a51 100644

arch/arm/boot/dts/Makefile dtb-$(CONFIG_SOC_IMX6Q) += \ · line 332

Quoted 4 lines
arch/arm/boot/dts/Makefile +1 -0
@@ -329,6 +329,7 @@ dtb-$(CONFIG_SOC_IMX6Q) += \
 	imx6q-phytec-pbab01.dtb \
 	imx6q-rex-pro.dtb \
 	imx6q-sabreauto.dtb \
+	imx6qp-sabreauto.dtb \

This order is incorrect either.

Quoted 9 lines
arch/arm/boot/dts/Makefile +0 -0
 	imx6q-sabrelite.dtb \
 	imx6q-sabresd.dtb \
 	imx6q-sbc6x.dtb \
arch/arm/boot/dts/imx6qp-sabreauto.dts new file +0 -0
new file mode 100644
index 0000000..b24aae6

arch/arm/boot/dts/imx6qp-sabreauto.dts line 6

Quoted 6 lines
arch/arm/boot/dts/imx6qp-sabreauto.dts new file +6 -0
@@ -0,0 +1,67 @@
+/*
+ * Copyright (C) 2015 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.

GPL/X11 dual license please.

arch/arm/boot/dts/imx6qp-sabreauto.dts line 19

Quoted 13 lines
arch/arm/boot/dts/imx6qp-sabreauto.dts new file +13 -0
+ */
+
+#include "imx6q-sabreauto.dts"
+#include "imx6qp.dtsi"
+
+/ {
+	model = "Freescale i.MX6 Quad Plus SABRE Automotive Board";
+	compatible = "fsl,imx6qp-sabreauto", "fsl,imx6qp";
+};
+
+
+&fec {
+	pinctrl-assert-gpios = <&max7322 0 GPIO_ACTIVE_HIGH>;

Upstream kernel doesn't have this property.

Shawn

Quoted 52 lines
arch/arm/boot/dts/imx6qp-sabreauto.dts new file +48 -0
+};
+
+&i2c2 {
+	max7322: gpio at 68 {
+		compatible = "maxim,max7322";
+		reg = <0x68>;
+		gpio-controller;
+		#gpio-cells = <2>;
+	};
+};
+
+&iomuxc {
+	imx6qdl-sabreauto {
+		pinctrl_enet: enetgrp {
+			fsl,pins = <
+				MX6QDL_PAD_KEY_COL1__ENET_MDIO          0x1b0b0
+				MX6QDL_PAD_KEY_COL2__ENET_MDC           0x1b0b0
+				MX6QDL_PAD_RGMII_TXC__RGMII_TXC         0x1b018
+				MX6QDL_PAD_RGMII_TD0__RGMII_TD0         0x1b018
+				MX6QDL_PAD_RGMII_TD1__RGMII_TD1         0x1b018
+				MX6QDL_PAD_RGMII_TD2__RGMII_TD2         0x1b018
+				MX6QDL_PAD_RGMII_TD3__RGMII_TD3         0x1b018
+				MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL   0x1b018
+				MX6QDL_PAD_RGMII_RXC__RGMII_RXC         0x1b018
+				MX6QDL_PAD_RGMII_RD0__RGMII_RD0         0x1b018
+				MX6QDL_PAD_RGMII_RD1__RGMII_RD1         0x1b018
+				MX6QDL_PAD_RGMII_RD2__RGMII_RD2         0x1b018
+				MX6QDL_PAD_RGMII_RD3__RGMII_RD3         0x1b018
+				MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL   0x1b018
+				MX6QDL_PAD_GPIO_16__ENET_REF_CLK        0x4001b0a8
+				MX6QDL_PAD_GPIO_6__ENET_IRQ		0x000b1
+			>;
+		};
+	};
+};
+
+&pcie {
+	reset-gpio = <&max7310_c 5 GPIO_ACTIVE_LOW>;
+	status = "okay";
+};
+
+&sata {
+	status = "okay";
+};
+
+&vgen3_reg {
+	regulator-always-on;
+};
Signature · 1 line
1.9.1
author
#9 lore raw

PATCH v2 4/5 clk: imx: Add clock support for imx6qp

In reply to Bai Ping

most of the clock tree structures on i.MX6QP are same as on i.MX6Q. there still some difference between these two SOCs. Compared to the i.MX6Q, the differences of clocks on i.MX6QP is mainly on:

1. UART clk root
2. IPG_PER clk,
3. ENFC
4. ECSPI
5. CAN_SEL
6. CSCMR1 register fixup issue
7. LDB clock
8. GPU2D clock
9 MMDC_CH1_AXI gate ...

Signed-off-by Bai Ping <[email protected]>
---
 drivers/clk/imx/clk-imx6q.c | 132 +++++++++++++++++++++++++++++++++++---------
 1 file changed, 105 insertions(+), 27 deletions(-)
drivers/clk/imx/clk-imx6q.c +105 -27
index f0efc6f..02e1818 100644
@@ -34,7 +34,9 @@ static const char *periph2_sels[]	= { "periph2_pre", "periph2_clk2", };
 static const char *axi_sels[]		= { "periph", "pll2_pfd2_396m", "periph", "pll3_pfd1_540m", };
 static const char *audio_sels[]	= { "pll4_audio_div", "pll3_pfd2_508m", "pll3_pfd3_454m", "pll3_usb_otg", };
 static const char *gpu_axi_sels[]	= { "axi", "ahb", };
+static const char *pre_axi_sels[]	= { "axi", "ahb", };
 static const char *gpu2d_core_sels[]	= { "axi", "pll3_usb_otg", "pll2_pfd0_352m", "pll2_pfd2_396m", };
+static const char *gpu2d_core_sels_2[]	= { "mmdc_ch0_axi", "pll3_usb_otg", "pll2_pfd1_594m", "pll3_pfd0_720m",};
 static const char *gpu3d_core_sels[]	= { "mmdc_ch0_axi", "pll3_usb_otg", "pll2_pfd1_594m", "pll2_pfd2_396m", };
 static const char *gpu3d_shader_sels[] = { "mmdc_ch0_axi", "pll3_usb_otg", "pll2_pfd1_594m", "pll3_pfd0_720m", };
 static const char *ipu_sels[]		= { "mmdc_ch0_axi", "pll2_pfd2_396m", "pll3_120m", "pll3_pfd1_540m", };

@@ -44,15 +46,24 @@ static const char *ipu1_di0_sels[]	= { "ipu1_di0_pre", "dummy", "dummy", "ldb_di
 static const char *ipu1_di1_sels[]	= { "ipu1_di1_pre", "dummy", "dummy", "ldb_di0", "ldb_di1", };
 static const char *ipu2_di0_sels[]	= { "ipu2_di0_pre", "dummy", "dummy", "ldb_di0", "ldb_di1", };
 static const char *ipu2_di1_sels[]	= { "ipu2_di1_pre", "dummy", "dummy", "ldb_di0", "ldb_di1", };
+static const char *ipu1_di0_sels_2[]	= { "ipu1_di0_pre", "dummy", "dummy", "ldb_di0_podf", "ldb_di1_podf", };
+static const char *ipu1_di1_sels_2[]	= { "ipu1_di1_pre", "dummy", "dummy", "ldb_di0_podf", "ldb_di1_podf", };
+static const char *ipu2_di0_sels_2[]	= { "ipu2_di0_pre", "dummy", "dummy", "ldb_di0_podf", "ldb_di1_podf", };
+static const char *ipu2_di1_sels_2[]	= { "ipu2_di1_pre", "dummy", "dummy", "ldb_di0_podf", "ldb_di1_podf", };
 static const char *hsi_tx_sels[]	= { "pll3_120m", "pll2_pfd2_396m", };
 static const char *pcie_axi_sels[]	= { "axi", "ahb", };
 static const char *ssi_sels[]		= { "pll3_pfd2_508m", "pll3_pfd3_454m", "pll4_audio_div", };
 static const char *usdhc_sels[]	= { "pll2_pfd2_396m", "pll2_pfd0_352m", };
 static const char *enfc_sels[]	= { "pll2_pfd0_352m", "pll2_bus", "pll3_usb_otg", "pll2_pfd2_396m", };
+static const char *enfc_sels_2[] = {"pll2_pfd0_352m", "pll2_bus", "pll3_usb_otg", "pll2_pfd2_396m", "pll3_pfd3_454m", "dummy", };
 static const char *eim_sels[]		= { "pll2_pfd2_396m", "pll3_usb_otg", "axi", "pll2_pfd0_352m", };
 static const char *eim_slow_sels[]      = { "axi", "pll3_usb_otg", "pll2_pfd2_396m", "pll2_pfd0_352m", };
 static const char *vdo_axi_sels[]	= { "axi", "ahb", };
 static const char *vpu_axi_sels[]	= { "axi", "pll2_pfd2_396m", "pll2_pfd0_352m", };
+static const char *uart_sels[] = { "pll3_80m", "osc", };
+static const char *ipg_per_sels[] = { "ipg", "osc", };
+static const char *ecspi_sels[] = { "pll3_60m", "osc", };
+static const char *can_sels[] = { "pll3_60m", "osc", "pll3_80m", };
 static const char *cko1_sels[]	= { "pll3_usb_otg", "pll2_bus", "pll1_sys", "pll5_video_div",
 				    "dummy", "axi", "enfc", "ipu1_di0", "ipu1_di1", "ipu2_di0",
 				    "ipu2_di1", "ahb", "ipg", "ipg_per", "ckil", "pll4_audio_div", };

@@ -121,12 +132,19 @@ static unsigned int share_count_ssi2;
 static unsigned int share_count_ssi3;
 static unsigned int share_count_mipi_core_cfg;
 static unsigned int share_count_spdif;
+static unsigned int share_count_prg0;
+static unsigned int share_count_prg1;
 
 static inline int clk_on_imx6q(void)
 {
 	return of_machine_is_compatible("fsl,imx6q");
 }
 
+static inline int clk_on_imx6qp(void)
+{
+	return of_machine_is_compatible("fsl,imx6qp");
+}
+
 static inline int clk_on_imx6dl(void)
 {
 	return of_machine_is_compatible("fsl,imx6dl");

@@ -265,7 +283,7 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
 	clk[IMX6QDL_CLK_TWD]       = imx_clk_fixed_factor("twd",       "arm",            1, 2);
 	clk[IMX6QDL_CLK_GPT_3M]    = imx_clk_fixed_factor("gpt_3m",    "osc",            1, 8);
 	clk[IMX6QDL_CLK_VIDEO_27M] = imx_clk_fixed_factor("video_27m", "pll3_pfd1_540m", 1, 20);
-	if (clk_on_imx6dl()) {
+	if (clk_on_imx6dl() || clk_on_imx6qp()) {
 		clk[IMX6QDL_CLK_GPU2D_AXI] = imx_clk_fixed_factor("gpu2d_axi", "mmdc_ch0_axi_podf", 1, 1);
 		clk[IMX6QDL_CLK_GPU3D_AXI] = imx_clk_fixed_factor("gpu3d_axi", "mmdc_ch0_axi_podf", 1, 1);
 	}

@@ -294,7 +312,15 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
 		clk[IMX6QDL_CLK_GPU2D_AXI]        = imx_clk_mux("gpu2d_axi",        base + 0x18, 0,  1, gpu_axi_sels,      ARRAY_SIZE(gpu_axi_sels));
 		clk[IMX6QDL_CLK_GPU3D_AXI]        = imx_clk_mux("gpu3d_axi",        base + 0x18, 1,  1, gpu_axi_sels,      ARRAY_SIZE(gpu_axi_sels));
 	}
-	clk[IMX6QDL_CLK_GPU2D_CORE_SEL]   = imx_clk_mux("gpu2d_core_sel",   base + 0x18, 16, 2, gpu2d_core_sels,   ARRAY_SIZE(gpu2d_core_sels));
+	if (clk_on_imx6qp()) {
+		clk[IMX6QDL_CLK_CAN_SEL]   = imx_clk_mux("can_sel",	base + 0x20, 8,  2, can_sels, ARRAY_SIZE(can_sels));
+		clk[IMX6QDL_CLK_ECSPI_SEL] = imx_clk_mux("ecspi_sel",	base + 0x38, 18, 1, ecspi_sels,  ARRAY_SIZE(ecspi_sels));
+		clk[IMX6QDL_CLK_IPG_PER_SEL] = imx_clk_mux("ipg_per_sel", base + 0x1c, 6, 1, ipg_per_sels, ARRAY_SIZE(ipg_per_sels));
+		clk[IMX6QDL_CLK_UART_SEL] = imx_clk_mux("uart_sel", base + 0x24, 6, 1, uart_sels, ARRAY_SIZE(uart_sels));
+		clk[IMX6QDL_CLK_GPU2D_CORE_SEL] = imx_clk_mux("gpu2d_core_sel", base + 0x18, 16, 2, gpu2d_core_sels_2, ARRAY_SIZE(gpu2d_core_sels_2));
+	} else {
+		clk[IMX6QDL_CLK_GPU2D_CORE_SEL] = imx_clk_mux("gpu2d_core_sel",   base + 0x18, 16, 2, gpu2d_core_sels,   ARRAY_SIZE(gpu2d_core_sels));
+	}
 	clk[IMX6QDL_CLK_GPU3D_CORE_SEL]   = imx_clk_mux("gpu3d_core_sel",   base + 0x18, 4,  2, gpu3d_core_sels,   ARRAY_SIZE(gpu3d_core_sels));
 	clk[IMX6QDL_CLK_GPU3D_SHADER_SEL] = imx_clk_mux("gpu3d_shader_sel", base + 0x18, 8,  2, gpu3d_shader_sels, ARRAY_SIZE(gpu3d_shader_sels));
 	clk[IMX6QDL_CLK_IPU1_SEL]         = imx_clk_mux("ipu1_sel",         base + 0x3c, 9,  2, ipu_sels,          ARRAY_SIZE(ipu_sels));

@@ -305,22 +331,40 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
 	clk[IMX6QDL_CLK_IPU1_DI1_PRE_SEL] = imx_clk_mux_flags("ipu1_di1_pre_sel", base + 0x34, 15, 3, ipu_di_pre_sels,   ARRAY_SIZE(ipu_di_pre_sels), CLK_SET_RATE_PARENT);
 	clk[IMX6QDL_CLK_IPU2_DI0_PRE_SEL] = imx_clk_mux_flags("ipu2_di0_pre_sel", base + 0x38, 6,  3, ipu_di_pre_sels,   ARRAY_SIZE(ipu_di_pre_sels), CLK_SET_RATE_PARENT);
 	clk[IMX6QDL_CLK_IPU2_DI1_PRE_SEL] = imx_clk_mux_flags("ipu2_di1_pre_sel", base + 0x38, 15, 3, ipu_di_pre_sels,   ARRAY_SIZE(ipu_di_pre_sels), CLK_SET_RATE_PARENT);
-	clk[IMX6QDL_CLK_IPU1_DI0_SEL]     = imx_clk_mux_flags("ipu1_di0_sel",     base + 0x34, 0,  3, ipu1_di0_sels,     ARRAY_SIZE(ipu1_di0_sels), CLK_SET_RATE_PARENT);
-	clk[IMX6QDL_CLK_IPU1_DI1_SEL]     = imx_clk_mux_flags("ipu1_di1_sel",     base + 0x34, 9,  3, ipu1_di1_sels,     ARRAY_SIZE(ipu1_di1_sels), CLK_SET_RATE_PARENT);
-	clk[IMX6QDL_CLK_IPU2_DI0_SEL]     = imx_clk_mux_flags("ipu2_di0_sel",     base + 0x38, 0,  3, ipu2_di0_sels,     ARRAY_SIZE(ipu2_di0_sels), CLK_SET_RATE_PARENT);
-	clk[IMX6QDL_CLK_IPU2_DI1_SEL]     = imx_clk_mux_flags("ipu2_di1_sel",     base + 0x38, 9,  3, ipu2_di1_sels,     ARRAY_SIZE(ipu2_di1_sels), CLK_SET_RATE_PARENT);
 	clk[IMX6QDL_CLK_HSI_TX_SEL]       = imx_clk_mux("hsi_tx_sel",       base + 0x30, 28, 1, hsi_tx_sels,       ARRAY_SIZE(hsi_tx_sels));
 	clk[IMX6QDL_CLK_PCIE_AXI_SEL]     = imx_clk_mux("pcie_axi_sel",     base + 0x18, 10, 1, pcie_axi_sels,     ARRAY_SIZE(pcie_axi_sels));
-	clk[IMX6QDL_CLK_SSI1_SEL]         = imx_clk_fixup_mux("ssi1_sel",   base + 0x1c, 10, 2, ssi_sels,          ARRAY_SIZE(ssi_sels), imx_cscmr1_fixup);
-	clk[IMX6QDL_CLK_SSI2_SEL]         = imx_clk_fixup_mux("ssi2_sel",   base + 0x1c, 12, 2, ssi_sels,          ARRAY_SIZE(ssi_sels), imx_cscmr1_fixup);
-	clk[IMX6QDL_CLK_SSI3_SEL]         = imx_clk_fixup_mux("ssi3_sel",   base + 0x1c, 14, 2, ssi_sels,          ARRAY_SIZE(ssi_sels), imx_cscmr1_fixup);
-	clk[IMX6QDL_CLK_USDHC1_SEL]       = imx_clk_fixup_mux("usdhc1_sel", base + 0x1c, 16, 1, usdhc_sels,        ARRAY_SIZE(usdhc_sels), imx_cscmr1_fixup);
-	clk[IMX6QDL_CLK_USDHC2_SEL]       = imx_clk_fixup_mux("usdhc2_sel", base + 0x1c, 17, 1, usdhc_sels,        ARRAY_SIZE(usdhc_sels), imx_cscmr1_fixup);
-	clk[IMX6QDL_CLK_USDHC3_SEL]       = imx_clk_fixup_mux("usdhc3_sel", base + 0x1c, 18, 1, usdhc_sels,        ARRAY_SIZE(usdhc_sels), imx_cscmr1_fixup);
-	clk[IMX6QDL_CLK_USDHC4_SEL]       = imx_clk_fixup_mux("usdhc4_sel", base + 0x1c, 19, 1, usdhc_sels,        ARRAY_SIZE(usdhc_sels), imx_cscmr1_fixup);
-	clk[IMX6QDL_CLK_ENFC_SEL]         = imx_clk_mux("enfc_sel",         base + 0x2c, 16, 2, enfc_sels,         ARRAY_SIZE(enfc_sels));
-	clk[IMX6QDL_CLK_EIM_SEL]          = imx_clk_fixup_mux("eim_sel",      base + 0x1c, 27, 2, eim_sels,        ARRAY_SIZE(eim_sels), imx_cscmr1_fixup);
-	clk[IMX6QDL_CLK_EIM_SLOW_SEL]     = imx_clk_fixup_mux("eim_slow_sel", base + 0x1c, 29, 2, eim_slow_sels,   ARRAY_SIZE(eim_slow_sels), imx_cscmr1_fixup);
+	if (clk_on_imx6qp()) {
+		clk[IMX6QDL_CLK_IPU1_DI0_SEL]     = imx_clk_mux_flags("ipu1_di0_sel",     base + 0x34, 0,  3, ipu1_di0_sels_2,     ARRAY_SIZE(ipu1_di0_sels_2), CLK_SET_RATE_PARENT);
+		clk[IMX6QDL_CLK_IPU1_DI1_SEL]     = imx_clk_mux_flags("ipu1_di1_sel",     base + 0x34, 9,  3, ipu1_di1_sels_2,     ARRAY_SIZE(ipu1_di1_sels_2), CLK_SET_RATE_PARENT);
+		clk[IMX6QDL_CLK_IPU2_DI0_SEL]     = imx_clk_mux_flags("ipu2_di0_sel",     base + 0x38, 0,  3, ipu2_di0_sels_2,     ARRAY_SIZE(ipu2_di0_sels_2), CLK_SET_RATE_PARENT);
+		clk[IMX6QDL_CLK_IPU2_DI1_SEL]     = imx_clk_mux_flags("ipu2_di1_sel",     base + 0x38, 9,  3, ipu2_di1_sels_2,     ARRAY_SIZE(ipu2_di1_sels_2), CLK_SET_RATE_PARENT);
+		clk[IMX6QDL_CLK_SSI1_SEL]         = imx_clk_mux("ssi1_sel",   base + 0x1c, 10, 2, ssi_sels,          ARRAY_SIZE(ssi_sels));
+		clk[IMX6QDL_CLK_SSI2_SEL]         = imx_clk_mux("ssi2_sel",   base + 0x1c, 12, 2, ssi_sels,          ARRAY_SIZE(ssi_sels));
+		clk[IMX6QDL_CLK_SSI3_SEL]         = imx_clk_mux("ssi3_sel",   base + 0x1c, 14, 2, ssi_sels,          ARRAY_SIZE(ssi_sels));
+		clk[IMX6QDL_CLK_USDHC1_SEL]       = imx_clk_mux("usdhc1_sel", base + 0x1c, 16, 1, usdhc_sels,        ARRAY_SIZE(usdhc_sels));
+		clk[IMX6QDL_CLK_USDHC2_SEL]       = imx_clk_mux("usdhc2_sel", base + 0x1c, 17, 1, usdhc_sels,        ARRAY_SIZE(usdhc_sels));
+		clk[IMX6QDL_CLK_USDHC3_SEL]       = imx_clk_mux("usdhc3_sel", base + 0x1c, 18, 1, usdhc_sels,        ARRAY_SIZE(usdhc_sels));
+		clk[IMX6QDL_CLK_USDHC4_SEL]       = imx_clk_mux("usdhc4_sel", base + 0x1c, 19, 1, usdhc_sels,        ARRAY_SIZE(usdhc_sels));
+		clk[IMX6QDL_CLK_ENFC_SEL]         = imx_clk_mux("enfc_sel",         base + 0x2c, 15, 3, enfc_sels_2,         ARRAY_SIZE(enfc_sels_2));
+		clk[IMX6QDL_CLK_EIM_SEL]          = imx_clk_mux("eim_sel",      base + 0x1c, 27, 2, eim_sels,        ARRAY_SIZE(eim_sels));
+		clk[IMX6QDL_CLK_EIM_SLOW_SEL]     = imx_clk_mux("eim_slow_sel", base + 0x1c, 29, 2, eim_slow_sels,   ARRAY_SIZE(eim_slow_sels));
+		clk[IMX6QDL_CLK_PRE_AXI]	  = imx_clk_mux("pre_axi",	base + 0x18, 1,  1, pre_axi_sels,    ARRAY_SIZE(pre_axi_sels));
+	} else {
+		clk[IMX6QDL_CLK_IPU1_DI0_SEL]     = imx_clk_mux_flags("ipu1_di0_sel",     base + 0x34, 0,  3, ipu1_di0_sels,     ARRAY_SIZE(ipu1_di0_sels), CLK_SET_RATE_PARENT);
+		clk[IMX6QDL_CLK_IPU1_DI1_SEL]     = imx_clk_mux_flags("ipu1_di1_sel",     base + 0x34, 9,  3, ipu1_di1_sels,     ARRAY_SIZE(ipu1_di1_sels), CLK_SET_RATE_PARENT);
+		clk[IMX6QDL_CLK_IPU2_DI0_SEL]     = imx_clk_mux_flags("ipu2_di0_sel",     base + 0x38, 0,  3, ipu2_di0_sels,     ARRAY_SIZE(ipu2_di0_sels), CLK_SET_RATE_PARENT);
+		clk[IMX6QDL_CLK_IPU2_DI1_SEL]     = imx_clk_mux_flags("ipu2_di1_sel",     base + 0x38, 9,  3, ipu2_di1_sels,     ARRAY_SIZE(ipu2_di1_sels), CLK_SET_RATE_PARENT);
+		clk[IMX6QDL_CLK_SSI1_SEL]         = imx_clk_fixup_mux("ssi1_sel",   base + 0x1c, 10, 2, ssi_sels,          ARRAY_SIZE(ssi_sels), imx_cscmr1_fixup);
+		clk[IMX6QDL_CLK_SSI2_SEL]         = imx_clk_fixup_mux("ssi2_sel",   base + 0x1c, 12, 2, ssi_sels,          ARRAY_SIZE(ssi_sels), imx_cscmr1_fixup);
+		clk[IMX6QDL_CLK_SSI3_SEL]         = imx_clk_fixup_mux("ssi3_sel",   base + 0x1c, 14, 2, ssi_sels,          ARRAY_SIZE(ssi_sels), imx_cscmr1_fixup);
+		clk[IMX6QDL_CLK_USDHC1_SEL]       = imx_clk_fixup_mux("usdhc1_sel", base + 0x1c, 16, 1, usdhc_sels,        ARRAY_SIZE(usdhc_sels), imx_cscmr1_fixup);
+		clk[IMX6QDL_CLK_USDHC2_SEL]       = imx_clk_fixup_mux("usdhc2_sel", base + 0x1c, 17, 1, usdhc_sels,        ARRAY_SIZE(usdhc_sels), imx_cscmr1_fixup);
+		clk[IMX6QDL_CLK_USDHC3_SEL]       = imx_clk_fixup_mux("usdhc3_sel", base + 0x1c, 18, 1, usdhc_sels,        ARRAY_SIZE(usdhc_sels), imx_cscmr1_fixup);
+		clk[IMX6QDL_CLK_USDHC4_SEL]       = imx_clk_fixup_mux("usdhc4_sel", base + 0x1c, 19, 1, usdhc_sels,        ARRAY_SIZE(usdhc_sels), imx_cscmr1_fixup);
+		clk[IMX6QDL_CLK_ENFC_SEL]         = imx_clk_mux("enfc_sel",         base + 0x2c, 16, 2, enfc_sels,         ARRAY_SIZE(enfc_sels));
+		clk[IMX6QDL_CLK_EIM_SEL]          = imx_clk_fixup_mux("eim_sel",      base + 0x1c, 27, 2, eim_sels,        ARRAY_SIZE(eim_sels), imx_cscmr1_fixup);
+		clk[IMX6QDL_CLK_EIM_SLOW_SEL]     = imx_clk_fixup_mux("eim_slow_sel", base + 0x1c, 29, 2, eim_slow_sels,   ARRAY_SIZE(eim_slow_sels), imx_cscmr1_fixup);
+	}
 	clk[IMX6QDL_CLK_VDO_AXI_SEL]      = imx_clk_mux("vdo_axi_sel",      base + 0x18, 11, 1, vdo_axi_sels,      ARRAY_SIZE(vdo_axi_sels));
 	clk[IMX6QDL_CLK_VPU_AXI_SEL]      = imx_clk_mux("vpu_axi_sel",      base + 0x18, 14, 2, vpu_axi_sels,      ARRAY_SIZE(vpu_axi_sels));
 	clk[IMX6QDL_CLK_CKO1_SEL]         = imx_clk_mux("cko1_sel",         base + 0x60, 0,  4, cko1_sels,         ARRAY_SIZE(cko1_sels));

@@ -335,23 +379,33 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
 	clk[IMX6QDL_CLK_PERIPH_CLK2]      = imx_clk_divider("periph_clk2",      "periph_clk2_sel",   base + 0x14, 27, 3);
 	clk[IMX6QDL_CLK_PERIPH2_CLK2]     = imx_clk_divider("periph2_clk2",     "periph2_clk2_sel",  base + 0x14, 0,  3);
 	clk[IMX6QDL_CLK_IPG]              = imx_clk_divider("ipg",              "ahb",               base + 0x14, 8,  2);
-	clk[IMX6QDL_CLK_IPG_PER]          = imx_clk_fixup_divider("ipg_per",    "ipg",               base + 0x1c, 0,  6, imx_cscmr1_fixup);
 	clk[IMX6QDL_CLK_ESAI_PRED]        = imx_clk_divider("esai_pred",        "esai_sel",          base + 0x28, 9,  3);
 	clk[IMX6QDL_CLK_ESAI_PODF]        = imx_clk_divider("esai_podf",        "esai_pred",         base + 0x28, 25, 3);
 	clk[IMX6QDL_CLK_ASRC_PRED]        = imx_clk_divider("asrc_pred",        "asrc_sel",          base + 0x30, 12, 3);
 	clk[IMX6QDL_CLK_ASRC_PODF]        = imx_clk_divider("asrc_podf",        "asrc_pred",         base + 0x30, 9,  3);
 	clk[IMX6QDL_CLK_SPDIF_PRED]       = imx_clk_divider("spdif_pred",       "spdif_sel",         base + 0x30, 25, 3);
 	clk[IMX6QDL_CLK_SPDIF_PODF]       = imx_clk_divider("spdif_podf",       "spdif_pred",        base + 0x30, 22, 3);
-	clk[IMX6QDL_CLK_CAN_ROOT]         = imx_clk_divider("can_root",         "pll3_60m",          base + 0x20, 2,  6);
-	clk[IMX6QDL_CLK_ECSPI_ROOT]       = imx_clk_divider("ecspi_root",       "pll3_60m",          base + 0x38, 19, 6);
+	if (clk_on_imx6qp()) {
+		clk[IMX6QDL_CLK_IPG_PER] = imx_clk_divider("ipg_per", "ipg_per_sel", base + 0x1c, 0, 6);
+		clk[IMX6QDL_CLK_ECSPI_ROOT] = imx_clk_divider("ecspi_root", "ecspi_sel", base + 0x38, 19, 6);
+		clk[IMX6QDL_CLK_CAN_ROOT] = imx_clk_divider("can_root", "can_sel", base + 0x20, 2, 6);
+		clk[IMX6QDL_CLK_UART_SERIAL_PODF] = imx_clk_divider("uart_serial_podf", "uart_sel", base + 0x24, 0, 6);
+		clk[IMX6QDL_CLK_LDB_DI0_DIV_3_5] = imx_clk_fixed_factor("ldb_di0_div_3_5", "ldb_di0", 2, 7);
+		clk[IMX6QDL_CLK_LDB_DI1_DIV_3_5] = imx_clk_fixed_factor("ldb_di1_div_3_5", "ldb_di1", 2, 7);
+	} else {
+		clk[IMX6QDL_CLK_ECSPI_ROOT] = imx_clk_divider("ecspi_root", "pll3_60m", base + 0x38, 19, 6);
+		clk[IMX6QDL_CLK_CAN_ROOT] = imx_clk_divider("can_root", "pll3_60", base + 0x20, 2, 6);
+		clk[IMX6QDL_CLK_IPG_PER] = imx_clk_fixup_divider("ipg_per", "ipg", base + 0x1c, 0, 6, imx_cscmr1_fixup);
+		clk[IMX6QDL_CLK_UART_SERIAL_PODF] = imx_clk_divider("uart_serial_podf", "pll3_80m",          base + 0x24, 0,  6);
+		clk[IMX6QDL_CLK_LDB_DI0_DIV_3_5] = imx_clk_fixed_factor("ldb_di0_div_3_5", "ldb_di0_sel", 2, 7);
+		clk[IMX6QDL_CLK_LDB_DI1_DIV_3_5] = imx_clk_fixed_factor("ldb_di1_div_3_5", "ldb_di1_sel", 2, 7);
+	}
 	clk[IMX6QDL_CLK_GPU2D_CORE_PODF]  = imx_clk_divider("gpu2d_core_podf",  "gpu2d_core_sel",    base + 0x18, 23, 3);
 	clk[IMX6QDL_CLK_GPU3D_CORE_PODF]  = imx_clk_divider("gpu3d_core_podf",  "gpu3d_core_sel",    base + 0x18, 26, 3);
 	clk[IMX6QDL_CLK_GPU3D_SHADER]     = imx_clk_divider("gpu3d_shader",     "gpu3d_shader_sel",  base + 0x18, 29, 3);
 	clk[IMX6QDL_CLK_IPU1_PODF]        = imx_clk_divider("ipu1_podf",        "ipu1_sel",          base + 0x3c, 11, 3);
 	clk[IMX6QDL_CLK_IPU2_PODF]        = imx_clk_divider("ipu2_podf",        "ipu2_sel",          base + 0x3c, 16, 3);
-	clk[IMX6QDL_CLK_LDB_DI0_DIV_3_5]  = imx_clk_fixed_factor("ldb_di0_div_3_5", "ldb_di0_sel", 2, 7);
 	clk[IMX6QDL_CLK_LDB_DI0_PODF]     = imx_clk_divider_flags("ldb_di0_podf", "ldb_di0_div_3_5", base + 0x20, 10, 1, 0);
-	clk[IMX6QDL_CLK_LDB_DI1_DIV_3_5]  = imx_clk_fixed_factor("ldb_di1_div_3_5", "ldb_di1_sel", 2, 7);
 	clk[IMX6QDL_CLK_LDB_DI1_PODF]     = imx_clk_divider_flags("ldb_di1_podf", "ldb_di1_div_3_5", base + 0x20, 11, 1, 0);
 	clk[IMX6QDL_CLK_IPU1_DI0_PRE]     = imx_clk_divider("ipu1_di0_pre",     "ipu1_di0_pre_sel",  base + 0x34, 3,  3);
 	clk[IMX6QDL_CLK_IPU1_DI1_PRE]     = imx_clk_divider("ipu1_di1_pre",     "ipu1_di1_pre_sel",  base + 0x34, 12, 3);

@@ -364,15 +418,19 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
 	clk[IMX6QDL_CLK_SSI2_PODF]        = imx_clk_divider("ssi2_podf",        "ssi2_pred",         base + 0x2c, 0,  6);
 	clk[IMX6QDL_CLK_SSI3_PRED]        = imx_clk_divider("ssi3_pred",        "ssi3_sel",          base + 0x28, 22, 3);
 	clk[IMX6QDL_CLK_SSI3_PODF]        = imx_clk_divider("ssi3_podf",        "ssi3_pred",         base + 0x28, 16, 6);
-	clk[IMX6QDL_CLK_UART_SERIAL_PODF] = imx_clk_divider("uart_serial_podf", "pll3_80m",          base + 0x24, 0,  6);
 	clk[IMX6QDL_CLK_USDHC1_PODF]      = imx_clk_divider("usdhc1_podf",      "usdhc1_sel",        base + 0x24, 11, 3);
 	clk[IMX6QDL_CLK_USDHC2_PODF]      = imx_clk_divider("usdhc2_podf",      "usdhc2_sel",        base + 0x24, 16, 3);
 	clk[IMX6QDL_CLK_USDHC3_PODF]      = imx_clk_divider("usdhc3_podf",      "usdhc3_sel",        base + 0x24, 19, 3);
 	clk[IMX6QDL_CLK_USDHC4_PODF]      = imx_clk_divider("usdhc4_podf",      "usdhc4_sel",        base + 0x24, 22, 3);
 	clk[IMX6QDL_CLK_ENFC_PRED]        = imx_clk_divider("enfc_pred",        "enfc_sel",          base + 0x2c, 18, 3);
 	clk[IMX6QDL_CLK_ENFC_PODF]        = imx_clk_divider("enfc_podf",        "enfc_pred",         base + 0x2c, 21, 6);
-	clk[IMX6QDL_CLK_EIM_PODF]         = imx_clk_fixup_divider("eim_podf",   "eim_sel",           base + 0x1c, 20, 3, imx_cscmr1_fixup);
-	clk[IMX6QDL_CLK_EIM_SLOW_PODF]    = imx_clk_fixup_divider("eim_slow_podf", "eim_slow_sel",   base + 0x1c, 23, 3, imx_cscmr1_fixup);
+	if (clk_on_imx6qp()) {
+		clk[IMX6QDL_CLK_EIM_PODF]         = imx_clk_divider("eim_podf",   "eim_sel",           base + 0x1c, 20, 3);
+		clk[IMX6QDL_CLK_EIM_SLOW_PODF]    = imx_clk_divider("eim_slow_podf", "eim_slow_sel",   base + 0x1c, 23, 3);
+	} else {
+		clk[IMX6QDL_CLK_EIM_PODF]         = imx_clk_fixup_divider("eim_podf",   "eim_sel",           base + 0x1c, 20, 3, imx_cscmr1_fixup);
+		clk[IMX6QDL_CLK_EIM_SLOW_PODF]    = imx_clk_fixup_divider("eim_slow_podf", "eim_slow_sel",   base + 0x1c, 23, 3, imx_cscmr1_fixup);
+	}
 	clk[IMX6QDL_CLK_VPU_AXI_PODF]     = imx_clk_divider("vpu_axi_podf",     "vpu_axi_sel",       base + 0x24, 25, 3);
 	clk[IMX6QDL_CLK_CKO1_PODF]        = imx_clk_divider("cko1_podf",        "cko1_sel",          base + 0x60, 4,  3);
 	clk[IMX6QDL_CLK_CKO2_PODF]        = imx_clk_divider("cko2_podf",        "cko2_sel",          base + 0x60, 21, 3);

@@ -380,7 +438,12 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
 	/*                                                        name                 parent_name    reg        shift width busy: reg, shift */
 	clk[IMX6QDL_CLK_AXI]               = imx_clk_busy_divider("axi",               "axi_sel",     base + 0x14, 16,  3,   base + 0x48, 0);
 	clk[IMX6QDL_CLK_MMDC_CH0_AXI_PODF] = imx_clk_busy_divider("mmdc_ch0_axi_podf", "periph",      base + 0x14, 19,  3,   base + 0x48, 4);
-	clk[IMX6QDL_CLK_MMDC_CH1_AXI_PODF] = imx_clk_busy_divider("mmdc_ch1_axi_podf", "periph2",     base + 0x14, 3,   3,   base + 0x48, 2);
+	if (clk_on_imx6qp()) {
+		clk[IMX6QDL_CLK_MMDC_CH1_AXI_CG] = imx_clk_gate("mmdc_ch1_axi_cg", "periph2", base + 0x4, 18);
+		clk[IMX6QDL_CLK_MMDC_CH1_AXI_PODF] = imx_clk_busy_divider("mmdc_ch1_axi_podf", "mmdc_ch1_axi_cg", base + 0x14, 3, 3, base + 0x48, 2);
+	} else {
+		clk[IMX6QDL_CLK_MMDC_CH1_AXI_PODF] = imx_clk_busy_divider("mmdc_ch1_axi_podf", "periph2",     base + 0x14, 3,   3,   base + 0x48, 2);
+	}
 	clk[IMX6QDL_CLK_ARM]               = imx_clk_busy_divider("arm",               "pll1_sw",     base + 0x10, 0,   3,   base + 0x48, 16);
 	clk[IMX6QDL_CLK_AHB]               = imx_clk_busy_divider("ahb",               "periph",      base + 0x14, 10,  3,   base + 0x48, 1);
 

@@ -432,8 +495,13 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
 	clk[IMX6QDL_CLK_IPU1_DI1]     = imx_clk_gate2("ipu1_di1",      "ipu1_di1_sel",      base + 0x74, 4);
 	clk[IMX6QDL_CLK_IPU2]         = imx_clk_gate2("ipu2",          "ipu2_podf",         base + 0x74, 6);
 	clk[IMX6QDL_CLK_IPU2_DI0]     = imx_clk_gate2("ipu2_di0",      "ipu2_di0_sel",      base + 0x74, 8);
-	clk[IMX6QDL_CLK_LDB_DI0]      = imx_clk_gate2("ldb_di0",       "ldb_di0_podf",      base + 0x74, 12);
-	clk[IMX6QDL_CLK_LDB_DI1]      = imx_clk_gate2("ldb_di1",       "ldb_di1_podf",      base + 0x74, 14);
+	if (clk_on_imx6qp()) {
+		clk[IMX6QDL_CLK_LDB_DI0]      = imx_clk_gate2("ldb_di0",       "ldb_di0_sel",      base + 0x74, 12);
+		clk[IMX6QDL_CLK_LDB_DI1]      = imx_clk_gate2("ldb_di1",       "ldb_di1_sel",      base + 0x74, 14);
+	} else {
+		clk[IMX6QDL_CLK_LDB_DI0]      = imx_clk_gate2("ldb_di0",       "ldb_di0_podf",      base + 0x74, 12);
+		clk[IMX6QDL_CLK_LDB_DI1]      = imx_clk_gate2("ldb_di1",       "ldb_di1_podf",      base + 0x74, 14);
+	}
 	clk[IMX6QDL_CLK_IPU2_DI1]     = imx_clk_gate2("ipu2_di1",      "ipu2_di1_sel",      base + 0x74, 10);
 	clk[IMX6QDL_CLK_HSI_TX]       = imx_clk_gate2_shared("hsi_tx", "hsi_tx_podf",       base + 0x74, 16, &share_count_mipi_core_cfg);
 	clk[IMX6QDL_CLK_MIPI_CORE_CFG] = imx_clk_gate2_shared("mipi_core_cfg", "video_27m", base + 0x74, 16, &share_count_mipi_core_cfg);

@@ -482,6 +550,16 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
 	clk[IMX6QDL_CLK_EIM_SLOW]     = imx_clk_gate2("eim_slow",      "eim_slow_podf",     base + 0x80, 10);
 	clk[IMX6QDL_CLK_VDO_AXI]      = imx_clk_gate2("vdo_axi",       "vdo_axi_sel",       base + 0x80, 12);
 	clk[IMX6QDL_CLK_VPU_AXI]      = imx_clk_gate2("vpu_axi",       "vpu_axi_podf",      base + 0x80, 14);
+	if (clk_on_imx6qp()) {
+		clk[IMX6QDL_CLK_PRE0] = imx_clk_gate2("pre0",	       "pre_axi",	    base + 0x80, 16);
+		clk[IMX6QDL_CLK_PRE1] = imx_clk_gate2("pre1",	       "pre_axi",	    base + 0x80, 18);
+		clk[IMX6QDL_CLK_PRE2] = imx_clk_gate2("pre2",	       "pre_axi",         base + 0x80, 20);
+		clk[IMX6QDL_CLK_PRE3] = imx_clk_gate2("pre3",	       "pre_axi",	    base + 0x80, 22);
+		clk[IMX6QDL_CLK_PRG0_AXI] = imx_clk_gate2_shared("prg0_axi",  "ipu1_podf",  base + 0x80, 24, &share_count_prg0);
+		clk[IMX6QDL_CLK_PRG1_AXI] = imx_clk_gate2_shared("prg1_axi",  "ipu2_podf",  base + 0x80, 26, &share_count_prg1);
+		clk[IMX6QDL_CLK_PRG0_APB] = imx_clk_gate2_shared("prg0_apb",  "ipg",	    base + 0x80, 24, &share_count_prg0);
+		clk[IMX6QDL_CLK_PRG1_APB] = imx_clk_gate2_shared("prg1_apb",  "ipg",	    base + 0x80, 26, &share_count_prg1);
+	}
 	clk[IMX6QDL_CLK_CKO1]         = imx_clk_gate("cko1",           "cko1_podf",         base + 0x60, 7);
 	clk[IMX6QDL_CLK_CKO2]         = imx_clk_gate("cko2",           "cko2_podf",         base + 0x60, 24);
Signature · 1 line
1.9.1
author
#10 lore raw

PATCH v2 5/5 ARM: imx: Add msl code support for imx6qp

In reply to Bai Ping

The i.MX6QP is a different SOC, but internally we treate it as i.MX6Q Rev_2.0 to maximum the code reusability. The chip silicon number we read from the ANADIG_DIGPROG is 0x630100. This patch add code to identify it as i.MX6QP Rev_1.0 when print out the silicon version.

Signed-off-by Bai Ping <[email protected]>
---
 arch/arm/mach-imx/anatop.c     | 5 ++++-
 arch/arm/mach-imx/mach-imx6q.c | 8 ++++++--
 2 files changed, 10 insertions(+), 3 deletions(-)
arch/arm/mach-imx/anatop.c +4 -1
index 231bb25..9622763 100644
@@ -129,7 +129,10 @@ void __init imx_init_revision_from_anatop(void)
 
 	switch (digprog & 0xff) {
 	case 0:
-		revision = IMX_CHIP_REVISION_1_0;
+		if (digprog >> 8 & 0x01)
+			revision = IMX_CHIP_REVISION_2_0;
+		else
+			revision = IMX_CHIP_REVISION_1_0;
 		break;
 	case 1:
 		revision = IMX_CHIP_REVISION_1_1;
arch/arm/mach-imx/mach-imx6q.c +6 -2
index 3878494b..cb27d56 100644
@@ -266,8 +266,11 @@ static void __init imx6q_init_machine(void)
 {
 	struct device *parent;
 
-	imx_print_silicon_rev(cpu_is_imx6dl() ? "i.MX6DL" : "i.MX6Q",
-			      imx_get_soc_revision());
+	if (cpu_is_imx6q() && imx_get_soc_revision() == IMX_CHIP_REVISION_2_0)
+		imx_print_silicon_rev("i.MX6QP", IMX_CHIP_REVISION_1_0);
+	else
+		imx_print_silicon_rev(cpu_is_imx6dl() ? "i.MX6DL" : "i.MX6Q",
+				imx_get_soc_revision());
 
 	parent = imx_soc_device_init();
 	if (parent == NULL)

@@ -399,6 +402,7 @@ static void __init imx6q_init_irq(void)
 static const char * const imx6q_dt_compat[] __initconst = {
 	"fsl,imx6dl",
 	"fsl,imx6q",
+	"fsl,imx6qp",
 	NULL,
 };
Signature · 1 line
1.9.1
#11 lore raw

PATCH v2 5/5 ARM: imx: Add msl code support for imx6qp

Quoted 17 lines · Bai Ping

The i.MX6QP is a different SOC, but internally we treate it as i.MX6Q Rev_2.0 to maximum the code reusability. The chip silicon number we read from the ANADIG_DIGPROG is 0x630100. This patch add code to identify it as i.MX6QP Rev_1.0 when print out the silicon version.

Signed-off-by Bai Ping <[email protected]>
---
 arch/arm/mach-imx/anatop.c     | 5 ++++-
 arch/arm/mach-imx/mach-imx6q.c | 8 ++++++--
 2 files changed, 10 insertions(+), 3 deletions(-)
arch/arm/mach-imx/anatop.c +0 -0
index 231bb25..9622763 100644

arch/arm/mach-imx/anatop.c void __init imx_init_revision_from_anatop(void) · line 135

Quoted 8 lines
arch/arm/mach-imx/anatop.c +4 -1
@@ -129,7 +129,10 @@ void __init imx_init_revision_from_anatop(void)
 
 	switch (digprog & 0xff) {
 	case 0:
-		revision = IMX_CHIP_REVISION_1_0;
+		if (digprog >> 8 & 0x01)
+			revision = IMX_CHIP_REVISION_2_0;
+		else
+			revision = IMX_CHIP_REVISION_1_0;

Please at least add some comment here to help us remember that this is a trick we play for i.MX6QP.

Shawn

Quoted 33 lines
arch/arm/mach-imx/anatop.c +0 -0
 		break;
 	case 1:
 		revision = IMX_CHIP_REVISION_1_1;
arch/arm/mach-imx/mach-imx6q.c +6 -2
index 3878494b..cb27d56 100644
@@ -266,8 +266,11 @@ static void __init imx6q_init_machine(void)
 {
 	struct device *parent;
 
-	imx_print_silicon_rev(cpu_is_imx6dl() ? "i.MX6DL" : "i.MX6Q",
-			      imx_get_soc_revision());
+	if (cpu_is_imx6q() && imx_get_soc_revision() == IMX_CHIP_REVISION_2_0)
+		imx_print_silicon_rev("i.MX6QP", IMX_CHIP_REVISION_1_0);
+	else
+		imx_print_silicon_rev(cpu_is_imx6dl() ? "i.MX6DL" : "i.MX6Q",
+				imx_get_soc_revision());
 
 	parent = imx_soc_device_init();
 	if (parent == NULL)

@@ -399,6 +402,7 @@ static void __init imx6q_init_irq(void)
 static const char * const imx6q_dt_compat[] __initconst = {
 	"fsl,imx6dl",
 	"fsl,imx6q",
+	"fsl,imx6qp",
 	NULL,
 };
Signature · 1 line
1.9.1
#12 lore raw

PATCH v2 5/5 ARM: imx: Add msl code support for imx6qp

Quoted 30 lines

-----Original Message-----
From: Shawn Guo [mailto:shawnguo at kernel.org]
Sent: 2016?1?28? 16:11
To: b51503 at freescale.com
Cc: kernel at pengutronix.de; pawel.moll at arm.com; robh+dt at kernel.org; mturquette at baylibre.com; sboyd at codeaurora.org; linux-arm- kernel at lists.infradead.org; linux-clk at vger.kernel.org; devicetree at vger.kernel.org
Subject: Re: [PATCH v2 5/5] ARM: imx: Add msl code support for imx6qp

Quoted 17 lines · Bai Ping

The i.MX6QP is a different SOC, but internally we treate it as i.MX6Q Rev_2.0 to maximum the code reusability. The chip silicon number we read from the ANADIG_DIGPROG is 0x630100. This patch add code to identify it as i.MX6QP Rev_1.0 when print out the silicon version.

Signed-off-by Bai Ping <[email protected]>
---
 arch/arm/mach-imx/anatop.c     | 5 ++++-
 arch/arm/mach-imx/mach-imx6q.c | 8 ++++++--
 2 files changed, 10 insertions(+), 3 deletions(-)
arch/arm/mach-imx/anatop.c +0 -0
index 231bb25..9622763 100644
@@ -129,7 +129,10 @@ void __init imx_init_revision_from_anatop(void)
Quoted 11 lines

arch/arm/mach-imx/anatop.c void __init imx_init_revision_from_anatop(void) · line 135

Quoted 7 lines
arch/arm/mach-imx/anatop.c +4 -1
 	switch (digprog & 0xff) {
 	case 0:
-		revision = IMX_CHIP_REVISION_1_0;
+		if (digprog >> 8 & 0x01)
+			revision = IMX_CHIP_REVISION_2_0;
+		else
+			revision = IMX_CHIP_REVISION_1_0;

Please at least add some comment here to help us remember that this is a trick we play for i.MX6QP.

Will address this in patch V3. Thanks for your review.

Quoted 35 lines

Shawn

arch/arm/mach-imx/mach-imx6q.c static void __init imx6q_init_machine(void) { · line 268

Quoted 13 lines
arch/arm/mach-imx/anatop.c +0 -0
 		break;
 	case 1:
 		revision = IMX_CHIP_REVISION_1_1;
(quoted diff) +0 -0

b/arch/arm/mach-imx/mach-imx6q.c index 3878494b..cb27d56 100644

arch/arm/mach-imx/mach-imx6q.c +1 -2
@@ -266,8 +266,11 @@ static void __init imx6q_init_machine(void)  {
 	struct device *parent;
 
-	imx_print_silicon_rev(cpu_is_imx6dl() ? "i.MX6DL" : "i.MX6Q",
-			      imx_get_soc_revision());
+	if (cpu_is_imx6q() && imx_get_soc_revision() ==

IMX_CHIP_REVISION_2_0)

Quoted 19 lines
arch/arm/mach-imx/mach-imx6q.c +5 -1
+		imx_print_silicon_rev("i.MX6QP", IMX_CHIP_REVISION_1_0);
+	else
+		imx_print_silicon_rev(cpu_is_imx6dl() ? "i.MX6DL" : "i.MX6Q",
+				imx_get_soc_revision());
 
 	parent = imx_soc_device_init();
 	if (parent == NULL)

@@ -399,6 +402,7 @@ static void __init imx6q_init_irq(void)  static
 const char * const imx6q_dt_compat[] __initconst = {
 	"fsl,imx6dl",
 	"fsl,imx6q",
+	"fsl,imx6qp",
 	NULL,
 };
 
--

1.9.1