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ARM: dts: imx7d: add arch timer

PATCH New Frank Li 3 participants 6 messages Jan 5, 2016 – Jan 28, 2016

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Device tree bindings Arm (32-bit) Arm sub-architectures Arm i.MX and Layerscape
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Frank Li

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#0 lore raw

PATCH v2 1/4 ARM: dts: imx7d: add arch timer

From: Frank Li <[email protected]>

Since uboot v2016.01-rc2, which supported basic psci for i.mx7d. So imx7d's second core can be enabled by psci.

Without arch timer, every timer event will be boardcasted to each core. arch timer has local timer irq for each core.

Signed-off-by Frank Li <[email protected]>

---

Change from v1 to v2:
* refine commit message show the relationship between smp and arch timer

 arch/arm/boot/dts/imx7d.dtsi | 9 +++++++++
 1 file changed, 9 insertions(+)
arch/arm/boot/dts/imx7d.dtsi +9 -0
index 489604a..a621af6 100644
@@ -119,6 +119,15 @@
 		clock-output-names = "osc";
 	};
 
+	timer {
+		compatible = "arm,armv7-timer";
+		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
+		interrupt-parent = <&intc>;
+	};
+
 	etr at 30086000 {
 		compatible = "arm,coresight-tmc", "arm,primecell";
 		reg = <0x30086000 0x1000>;
Signature · 1 line
2.5.2
author maintainer
#1 lore raw

PATCH v2 2/4 ARM: imx: select HAVE_ARM_ARCH_TIMER if selected i.MX7D

From: Frank Li <[email protected]>

i.MX7D Supported ARCH Timer.

Signed-off-by Frank Li <[email protected]>

---
Change from v1 to v2:
Sort config

 arch/arm/mach-imx/Kconfig | 1 +
 1 file changed, 1 insertion(+)
arch/arm/mach-imx/Kconfig +1 -0
index 0ac180f..43ff3cd 100644
@@ -561,6 +561,7 @@ config SOC_IMX7D
 	bool "i.MX7 Dual support"
 	select PINCTRL_IMX7D
 	select ARM_GIC
+	select HAVE_ARM_ARCH_TIMER
 	select HAVE_IMX_ANATOP
 	select HAVE_IMX_MMDC
 	help
Signature · 1 line
2.5.2
author maintainer
#2 lore raw

PATCH v2 3/4 ARM: imx: config: enable psci default

In reply to Frank Li

From: Frank Li <[email protected]>

i.MX7D uboot support psci firmware.
Enabled psci default.

Signed-off-by Frank Li <[email protected]>

---
Change from v1 to v2:
arm to "ARM"

 arch/arm/configs/imx_v6_v7_defconfig | 1 +
 1 file changed, 1 insertion(+)
arch/arm/configs/imx_v6_v7_defconfig +1 -0
index 2d5253d..1e792ef 100644
@@ -47,6 +47,7 @@ CONFIG_PCI=y
 CONFIG_PCI_MSI=y
 CONFIG_PCI_IMX6=y
 CONFIG_SMP=y
+CONFIG_ARM_PSCI=y
 CONFIG_PREEMPT_VOLUNTARY=y
 CONFIG_AEABI=y
 CONFIG_HIGHMEM=y
Signature · 1 line
2.5.2
author maintainer
#3 lore raw

PATCH v2 4/4 ARM: imx7d: correct chip version information

In reply to Frank Li

From: Frank Li <[email protected]>

The commond 'cat /sys/devices/soc0/revision' can
show correct soc version information.

"unknow revision" message in imx_print_silicon_rev() will never work for digprog.

Signed-off-by Frank Li <[email protected]>

---
Change from v1 to v2:
fix grammer issues in comments.

 arch/arm/mach-imx/anatop.c | 9 ++++++++-
 1 file changed, 8 insertions(+), 1 deletion(-)
arch/arm/mach-imx/anatop.c +8 -1
index 231bb25..bd3555e 100644
@@ -151,7 +151,14 @@ void __init imx_init_revision_from_anatop(void)
 		revision = IMX_CHIP_REVISION_1_5;
 		break;
 	default:
-		revision = IMX_CHIP_REVISION_UNKNOWN;
+		/*
+		 * Fail back to return raw register value instead of 0xff.
+		 * It will be easy to know version information in SOC if it
+		 * can't be recognized by known version. And some chip's (i.MX7D)
+		 * digprog value match linux version format, so it needn't map
+		 * again and we can use register value directly.
+		 */
+		revision = digprog & 0xff;
 	}
 
 	mxc_set_cpu_type(digprog >> 16 & 0xff);
Signature · 1 line
2.5.2
#4 lore raw

PATCH v2 1/4 ARM: dts: imx7d: add arch timer

In reply to Frank Li
Quoted 10 lines · Frank Li

From: Frank Li <[email protected]>

Since uboot v2016.01-rc2, which supported basic psci for i.mx7d. So imx7d's second core can be enabled by psci.

Without arch timer, every timer event will be boardcasted to each core. arch timer has local timer irq for each core.

Signed-off-by Frank Li <[email protected]>

---

Ping

Quoted 30 lines

Change from v1 to v2:
* refine commit message show the relationship between smp and arch timer

 arch/arm/boot/dts/imx7d.dtsi | 9 +++++++++
 1 file changed, 9 insertions(+)
arch/arm/boot/dts/imx7d.dtsi +9 -1
index 489604a..a621af6 100644
@@ -119,6 +119,15 @@
                clock-output-names = "osc";
        };
 
+       timer {
+               compatible = "arm,armv7-timer";
+               interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+                            <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+                            <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+                            <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
+               interrupt-parent = <&intc>;
+       };
+
        etr at 30086000 {
                compatible = "arm,coresight-tmc", "arm,primecell";
                reg = <0x30086000 0x1000>;
--

2.5.2

Applied
#5 lore raw

PATCH v2 1/4 ARM: dts: imx7d: add arch timer

In reply to Frank Li
Quoted 9 lines · Frank Li

From: Frank Li <[email protected]>

Since uboot v2016.01-rc2, which supported basic psci for i.mx7d. So imx7d's second core can be enabled by psci.

Without arch timer, every timer event will be boardcasted to each core. arch timer has local timer irq for each core.

Signed-off-by Frank Li <[email protected]>

Applied all, thanks.