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clk: xgene: Add SoC and PMD PLL clocks with v2 hardware

PATCH New Loc Ho 2 participants 10 messages Jan 20, 2016 – Jan 30, 2016

Subsystems (3)
Device tree bindings Common clk Applied micro (apm) x-gene device tree support
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Loc Ho

author
#0 lore raw

v2 cover clk: xgene: Add SoC and PMD PLL clocks with v2 hardware

Add APM X-Gene SoC and PCP PLL clocks support for v2 hardware.

v2:
* Move the detection of the HW version to compatible string
* Update APM X-Gene clock node binding documentation for v2 hardware
* Update Merlin DT clock node to reflect v2 SoC/PCP PLL hardware
* Fix some minor coding indentation issue with existent code

--
Loc Ho (3):
Documentation: Update APM X-Gene clock binding for v2 hardware
clk: xgene: Add SoC and PMD PLL clocks with v2 hardware
arm64: Update the Merlin DT PCP PLL clock node for v2 hardware

 Documentation/devicetree/bindings/clock/xgene.txt |    2 +
 arch/arm64/boot/dts/apm/apm-shadowcat.dtsi        |    2 +-
 drivers/clk/clk-xgene.c                           |  103 +++++++++++++--------
 3 files changed, 69 insertions(+), 38 deletions(-)
author
#1 lore raw

PATCH v2 1/3 Documentation: Update APM X-Gene clock binding for v2 hardware

Update APM X-Gene clock binding documentation for SoC and PCP PLL for v2 hardware.

Signed-off-by Loc Ho <[email protected]>
---
 Documentation/devicetree/bindings/clock/xgene.txt |    2 ++
 1 files changed, 2 insertions(+), 0 deletions(-)
Documentation/devicetree/bindings/clock/xgene.txt +2 -0
index 1c4ef77..3fe3169 100644
@@ -9,6 +9,8 @@ Required properties:
 	"apm,xgene-socpll-clock" - for a X-Gene SoC PLL clock
 	"apm,xgene-pcppll-clock" - for a X-Gene PCP PLL clock
 	"apm,xgene-device-clock" - for a X-Gene device clock
+	"apm,xgene-socpll-v2-clock" - for a X-Gene SoC PLL v2 clock
+	"apm,xgene-pcppll-v2-clock" - for a X-Gene PCP PLL v2 clock
 
 Required properties for SoC or PCP PLL clocks:
 - reg : shall be the physical PLL register address for the pll clock.
Signature · 1 line
1.7.1
Applied
#2 lore raw

PATCH v2 1/3 Documentation: Update APM X-Gene clock binding for v2 hardware

Quoted 5 lines · Loc Ho

Update APM X-Gene clock binding documentation for SoC and PCP PLL for v2 hardware.

Signed-off-by Loc Ho <[email protected]>

---

Applied to clk-next

Signature · 2 lines
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
author
#3 lore raw

PATCH v2 2/3 clk: xgene: Add SoC and PMD PLL clocks with v2 hardware

In reply to Loc Ho

Add X-Gene SoC and PMD PLL clocks support for v2 hardware. X-Gene SoC v2 and above use an slightly different SoC and PMD PLL hardware logic.

Signed-off-by Loc Ho <[email protected]>
---
 drivers/clk/clk-xgene.c |  103 ++++++++++++++++++++++++++++++-----------------
 1 files changed, 66 insertions(+), 37 deletions(-)
drivers/clk/clk-xgene.c +66 -37
index 10224b0..266d573 100644
@@ -29,7 +29,9 @@
 #include <linux/of_address.h>
 
 /* Register SCU_PCPPLL bit fields */
-#define N_DIV_RD(src)			(((src) & 0x000001ff))
+#define N_DIV_RD(src)			((src) & 0x000001ff)
+#define SC_N_DIV_RD(src)		((src) & 0x0000007f)
+#define SC_OUTDIV2(src)			(((src) & 0x00000100) >> 8)
 
 /* Register SCU_SOCPLL bit fields */
 #define CLKR_RD(src)			(((src) & 0x07000000)>>24)

@@ -63,6 +65,7 @@ struct xgene_clk_pll {
 	spinlock_t	*lock;
 	u32		pll_offset;
 	enum xgene_pll_type	type;
+	int		version;
 };
 
 #define to_xgene_clk_pll(_hw) container_of(_hw, struct xgene_clk_pll, hw)

@@ -92,27 +95,37 @@ static unsigned long xgene_clk_pll_recalc_rate(struct clk_hw *hw,
 
 	pll = xgene_clk_read(pllclk->reg + pllclk->pll_offset);
 
-	if (pllclk->type == PLL_TYPE_PCP) {
-		/*
-		 * PLL VCO = Reference clock * NF
-		 * PCP PLL = PLL_VCO / 2
-		 */
-		nout = 2;
-		fvco = parent_rate * (N_DIV_RD(pll) + 4);
+	if (pllclk->version <= 1) {
+		if (pllclk->type == PLL_TYPE_PCP) {
+			/*
+			* PLL VCO = Reference clock * NF
+			* PCP PLL = PLL_VCO / 2
+			*/
+			nout = 2;
+			fvco = parent_rate * (N_DIV_RD(pll) + 4);
+		} else {
+			/*
+			* Fref = Reference Clock / NREF;
+			* Fvco = Fref * NFB;
+			* Fout = Fvco / NOUT;
+			*/
+			nref = CLKR_RD(pll) + 1;
+			nout = CLKOD_RD(pll) + 1;
+			nfb = CLKF_RD(pll);
+			fref = parent_rate / nref;
+			fvco = fref * nfb;
+		}
 	} else {
 		/*
-		 * Fref = Reference Clock / NREF;
-		 * Fvco = Fref * NFB;
-		 * Fout = Fvco / NOUT;
+		 * fvco = Reference clock * FBDIVC
+		 * PLL freq = fvco / NOUT
 		 */
-		nref = CLKR_RD(pll) + 1;
-		nout = CLKOD_RD(pll) + 1;
-		nfb = CLKF_RD(pll);
-		fref = parent_rate / nref;
-		fvco = fref * nfb;
+		nout = SC_OUTDIV2(pll) ? 2 : 3;
+		fvco = parent_rate * SC_N_DIV_RD(pll);
 	}
-	pr_debug("%s pll recalc rate %ld parent %ld\n", clk_hw_get_name(hw),
-		fvco / nout, parent_rate);
+	pr_debug("%s pll recalc rate %ld parent %ld version %d\n",
+		 clk_hw_get_name(hw), fvco / nout, parent_rate,
+		 pllclk->version);
 
 	return fvco / nout;
 }

@@ -125,7 +138,7 @@ static const struct clk_ops xgene_clk_pll_ops = {
 static struct clk *xgene_register_clk_pll(struct device *dev,
 	const char *name, const char *parent_name,
 	unsigned long flags, void __iomem *reg, u32 pll_offset,
-	u32 type, spinlock_t *lock)
+	u32 type, spinlock_t *lock, int version)
 {
 	struct xgene_clk_pll *apmclk;
 	struct clk *clk;

@@ -144,6 +157,7 @@ static struct clk *xgene_register_clk_pll(struct device *dev,
 	init.parent_names = parent_name ? &parent_name : NULL;
 	init.num_parents = parent_name ? 1 : 0;
 
+	apmclk->version = version;
 	apmclk->reg = reg;
 	apmclk->lock = lock;
 	apmclk->pll_offset = pll_offset;

@@ -160,26 +174,37 @@ static struct clk *xgene_register_clk_pll(struct device *dev,
 	return clk;
 }
 
+static int xgene_pllclk_version(struct device_node *np)
+{
+	if (of_device_is_compatible(np, "apm,xgene-socpll-clock"))
+		return 1;
+	if (of_device_is_compatible(np, "apm,xgene-pcppll-clock"))
+		return 1;
+	return 2;
+}
+
 static void xgene_pllclk_init(struct device_node *np, enum xgene_pll_type pll_type)
 {
-        const char *clk_name = np->full_name;
-        struct clk *clk;
-        void __iomem *reg;
+	const char *clk_name = np->full_name;
+	struct clk *clk;
+	void __iomem *reg;
+	int version = xgene_pllclk_version(np);
 
-        reg = of_iomap(np, 0);
-        if (reg == NULL) {
-                pr_err("Unable to map CSR register for %s\n", np->full_name);
-                return;
-        }
-        of_property_read_string(np, "clock-output-names", &clk_name);
-        clk = xgene_register_clk_pll(NULL,
-                        clk_name, of_clk_get_parent_name(np, 0),
-                        CLK_IS_ROOT, reg, 0, pll_type, &clk_lock);
-        if (!IS_ERR(clk)) {
-                of_clk_add_provider(np, of_clk_src_simple_get, clk);
-                clk_register_clkdev(clk, clk_name, NULL);
-                pr_debug("Add %s clock PLL\n", clk_name);
-        }
+	reg = of_iomap(np, 0);
+	if (reg == NULL) {
+		pr_err("Unable to map CSR register for %s\n", np->full_name);
+		return;
+	}
+	of_property_read_string(np, "clock-output-names", &clk_name);
+	clk = xgene_register_clk_pll(NULL,
+			clk_name, of_clk_get_parent_name(np, 0),
+			CLK_IS_ROOT, reg, 0, pll_type, &clk_lock,
+			version);
+	if (!IS_ERR(clk)) {
+		of_clk_add_provider(np, of_clk_src_simple_get, clk);
+		clk_register_clkdev(clk, clk_name, NULL);
+		pr_debug("Add %s clock PLL\n", clk_name);
+	}
 }
 
 static void xgene_socpllclk_init(struct device_node *np)

@@ -460,7 +485,7 @@ static void __init xgene_devclk_init(struct device_node *np)
 		rc = of_address_to_resource(np, i, &res);
 		if (rc != 0) {
 			if (i == 0) {
-				pr_err("no DTS register for %s\n", 
+				pr_err("no DTS register for %s\n",
 					np->full_name);
 				return;
 			}

@@ -518,4 +543,8 @@ err:
 
 CLK_OF_DECLARE(xgene_socpll_clock, "apm,xgene-socpll-clock", xgene_socpllclk_init);
 CLK_OF_DECLARE(xgene_pcppll_clock, "apm,xgene-pcppll-clock", xgene_pcppllclk_init);
+CLK_OF_DECLARE(xgene_socpll_v2_clock, "apm,xgene-socpll-v2-clock",
+	       xgene_socpllclk_init);
+CLK_OF_DECLARE(xgene_pcppll_v2_clock, "apm,xgene-pcppll-v2-clock",
+	       xgene_pcppllclk_init);
 CLK_OF_DECLARE(xgene_dev_clock, "apm,xgene-device-clock", xgene_devclk_init);
Signature · 1 line
1.7.1
#4 lore raw

PATCH v2 2/3 clk: xgene: Add SoC and PMD PLL clocks with v2 hardware

Quoted 6 lines · Loc Ho

Add X-Gene SoC and PMD PLL clocks support for v2 hardware. X-Gene SoC v2 and above use an slightly different SoC and PMD PLL hardware logic.

Signed-off-by Loc Ho <[email protected]>

---

It's not from this patch, but I notice that we have a return inside a void function in this file...

---8<---
From: Stephen Boyd <[email protected]>
Subject: [PATCH] clk: xgene: Remove return from void function

This function doesn't return anything because it's void. Drop the return statement.

Cc Loc Ho <[email protected]>
Signed-off-by Stephen Boyd <[email protected]>
---
 drivers/clk/clk-xgene.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)
drivers/clk/clk-xgene.c +1 -1
index 266d573b9134..bd7156baa08b 100644
@@ -50,7 +50,7 @@ static inline u32 xgene_clk_read(void __iomem *csr)
 
 static inline void xgene_clk_write(u32 data, void __iomem *csr)
 {
-	return writel_relaxed(data, csr);
+	writel_relaxed(data, csr);
 }
 
 /* PLL Clock */
Signature · 2 lines
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
author
#5 lore raw

PATCH v2 2/3 clk: xgene: Add SoC and PMD PLL clocks with v2 hardware

Hi Stephen & All,

Quoted 29 lines · Stephen Boyd
Quoted 6 lines · Loc Ho

Add X-Gene SoC and PMD PLL clocks support for v2 hardware. X-Gene SoC v2 and above use an slightly different SoC and PMD PLL hardware logic.

Signed-off-by Loc Ho <[email protected]>

---

It's not from this patch, but I notice that we have a return inside a void function in this file...

---8<---
From: Stephen Boyd <[email protected]>
Subject: [PATCH] clk: xgene: Remove return from void function

This function doesn't return anything because it's void. Drop the return statement.

Cc Loc Ho <[email protected]>
Signed-off-by Stephen Boyd <[email protected]>
---
 drivers/clk/clk-xgene.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)
drivers/clk/clk-xgene.c +0 -0
index 266d573b9134..bd7156baa08b 100644

drivers/clk/clk-xgene.c static inline u32 xgene_clk_read(void __iomem *csr) · line 56

Quoted 8 lines
drivers/clk/clk-xgene.c +1 -1
@@ -50,7 +50,7 @@ static inline u32 xgene_clk_read(void __iomem *csr)
 
 static inline void xgene_clk_write(u32 data, void __iomem *csr)
 {
-       return writel_relaxed(data, csr);
+       writel_relaxed(data, csr);
 }
 
 /* PLL Clock */

Thanks for spotting this. Was my original patch for v2 X-Gene HW pulled in an specify GIT tree? I don't see it in the clk GIT master.

-Loc

Applied
#6 lore raw

PATCH v2 2/3 clk: xgene: Add SoC and PMD PLL clocks with v2 hardware

In reply to Loc Ho
Quoted 6 lines · Loc Ho

Add X-Gene SoC and PMD PLL clocks support for v2 hardware. X-Gene SoC v2 and above use an slightly different SoC and PMD PLL hardware logic.

Signed-off-by Loc Ho <[email protected]>

---

Applied to clk-next

Signature · 2 lines
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
author
#7 lore raw

PATCH v2 3/3 arm64: Update Merlin DT PCP PLL clock node for v2 hardware

In reply to Loc Ho

Update Merlin DT PCP PLL clock node to reflect compatible string change to reflect v2 hardware.

Signed-off-by Loc Ho <[email protected]>
---
 arch/arm64/boot/dts/apm/apm-shadowcat.dtsi |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)
arch/arm64/boot/dts/apm/apm-shadowcat.dtsi +1 -1
index 5d87a3d..83d293e 100644
@@ -224,7 +224,7 @@
 			};
 
 			socpll: socpll at 17000120 {
-				compatible = "apm,xgene-socpll-clock";
+				compatible = "apm,xgene-socpll-v2-clock";
 				#clock-cells = <1>;
 				clocks = <&refclk 0>;
 				reg = <0x0 0x17000120 0x0 0x1000>;
Signature · 1 line
1.7.1
#8 lore raw

PATCH v2 3/3 arm64: Update Merlin DT PCP PLL clock node for v2 hardware

Quoted 5 lines · Loc Ho

Update Merlin DT PCP PLL clock node to reflect compatible string change to reflect v2 hardware.

Signed-off-by Loc Ho <[email protected]>

---

Please take this through arm-soc.

Signature · 2 lines
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
author
#9 lore raw

PATCH v2 3/3 arm64: Update Merlin DT PCP PLL clock node for v2 hardware

Hi Stephen,

Quoted 8 lines · Stephen Boyd
Quoted 5 lines · Loc Ho

Update Merlin DT PCP PLL clock node to reflect compatible string change to reflect v2 hardware.

Signed-off-by Loc Ho <[email protected]>

---

Please take this through arm-soc.

I will ask Duc Dang to put this into APM xgene-next GIT for Arnd or Olof next pull.

-Loc