clk: sunxi: factors: Add missing recalc pointer copy

Remove the fixed dividers from the PLL6 driver to be able to have a reusable driver that can be used across several SoCs that share the same controller, but don't have the same set of dividers for this clock, and to also be reused multiple times in the same SoC, since we're droping the clock name.

Signed-off-by Maxime Ripard <[email protected]>

---
Changes from v2
- Rebased and converted over to the new factors refactoring. Fixed the retrieved rate

 arch/arm/boot/dts/sun6i-a31.dtsi     | 36 ++++++++++++++++++------------------
 arch/arm/boot/dts/sun8i-a23-a33.dtsi | 25 +++++++++++++++++--------
 arch/arm/boot/dts/sun8i-a23.dtsi     |  2 +-
 arch/arm/boot/dts/sun8i-a33.dtsi     |  4 ++--
 arch/arm/boot/dts/sun8i-h3.dtsi      | 36 ++++++++++++++++++------------------
 drivers/clk/sunxi/clk-sunxi.c        | 32 ++++++++++++++++----------------
 6 files changed, 72 insertions(+), 63 deletions(-)

Remove the fixed dividers from the PLL6 driver to be able to have a reusable driver that can be used across several SoCs that share the same controller, but don't have the same set of dividers for this clock, and to also be reused multiple times in the same SoC, since we're droping the clock name.

Signed-off-by Maxime Ripard <[email protected]>

---
Changes from v2
- Rebased and converted over to the new factors refactoring. Fixed the retrieved rate

 arch/arm/boot/dts/sun6i-a31.dtsi     | 36 ++++++++++++++++++------------------
 arch/arm/boot/dts/sun8i-a23-a33.dtsi | 25 +++++++++++++++++--------
 arch/arm/boot/dts/sun8i-a23.dtsi     |  2 +-
 arch/arm/boot/dts/sun8i-a33.dtsi     |  4 ++--
 arch/arm/boot/dts/sun8i-h3.dtsi      | 36 ++++++++++++++++++------------------
 drivers/clk/sunxi/clk-sunxi.c        | 32 ++++++++++++++++----------------
 6 files changed, 72 insertions(+), 63 deletions(-)

arch/arm/boot/dts/sun8i-h3.dtsi +12 -12

index 1524130e43c9..19aadf47027d 100644
@@ -121,27 +121,27 @@
 		};
 
 		pll6: clk at 01c20028 {
-			#clock-cells = <1>;
+			#clock-cells = <0>;
 			compatible = "allwinner,sun6i-a31-pll6-clk";
 			reg = <0x01c20028 0x4>;
 			clocks = <&osc24M>;
-			clock-output-names = "pll6", "pll6x2";
+			clock-output-names = "pll6";
 		};
 
-		pll6d2: pll6d2_clk {
+		pll6x2: pll6x2_clk {
 			#clock-cells = <0>;
 			compatible = "fixed-factor-clock";
-			clock-div = <2>;
-			clock-mult = <1>;
-			clocks = <&pll6 0>;
-			clock-output-names = "pll6d2";
+			clock-div = <1>;
+			clock-mult = <2>;
+			clocks = <&pll6>;
+			clock-output-names = "pll6-2x";
 		};
 
-		/* dummy clock until pll6 can be reused */
-		pll8: pll8_clk {
+		pll8: clk at 01c20044 {
 			#clock-cells = <0>;
-			compatible = "fixed-clock";
-			clock-frequency = <1>;
+			compatible = "allwinner,sun6i-a31-pll6-clk";
+			reg = <0x01c20044 0x4>;
+			clocks = <&osc24M>;
 			clock-output-names = "pll8";
 		};
 

@@ -165,7 +165,7 @@
 			#clock-cells = <0>;
 			compatible = "allwinner,sun6i-a31-ahb1-clk";
 			reg = <0x01c20054 0x4>;
-			clocks = <&osc32k>, <&osc24M>, <&axi>, <&pll6 0>;
+			clocks = <&osc32k>, <&osc24M>, <&axi>, <&pll6>;
 			clock-output-names = "ahb1";
 		};
 

Hi,

Quoted 20 lines · Maxime Ripard

Remove the fixed dividers from the PLL6 driver to be able to have a reusable driver that can be used across several SoCs that share the same controller, but don't have the same set of dividers for this clock, and to also be reused multiple times in the same SoC, since we're droping the clock name.

Signed-off-by Maxime Ripard <[email protected]>

---
Changes from v2
- Rebased and converted over to the new factors refactoring. Fixed the retrieved rate

 arch/arm/boot/dts/sun6i-a31.dtsi     | 36 ++++++++++++++++++------------------
 arch/arm/boot/dts/sun8i-a23-a33.dtsi | 25 +++++++++++++++++--------
 arch/arm/boot/dts/sun8i-a23.dtsi     |  2 +-
 arch/arm/boot/dts/sun8i-a33.dtsi     |  4 ++--
 arch/arm/boot/dts/sun8i-h3.dtsi      | 36 ++++++++++++++++++------------------
 drivers/clk/sunxi/clk-sunxi.c        | 32 ++++++++++++++++----------------
 6 files changed, 72 insertions(+), 63 deletions(-)

[...]

Quoted 52 lines

arch/arm/boot/dts/sun8i-h3.dtsi +12 -12

index 1524130e43c9..19aadf47027d 100644
@@ -121,27 +121,27 @@
              };
 
              pll6: clk at 01c20028 {
-                     #clock-cells = <1>;
+                     #clock-cells = <0>;
                      compatible = "allwinner,sun6i-a31-pll6-clk";
                      reg = <0x01c20028 0x4>;
                      clocks = <&osc24M>;
-                     clock-output-names = "pll6", "pll6x2";
+                     clock-output-names = "pll6";
              };
 
-             pll6d2: pll6d2_clk {
+             pll6x2: pll6x2_clk {
                      #clock-cells = <0>;
                      compatible = "fixed-factor-clock";
-                     clock-div = <2>;
-                     clock-mult = <1>;
-                     clocks = <&pll6 0>;
-                     clock-output-names = "pll6d2";
+                     clock-div = <1>;
+                     clock-mult = <2>;
+                     clocks = <&pll6>;
+                     clock-output-names = "pll6-2x";
              };
 
-             /* dummy clock until pll6 can be reused */
-             pll8: pll8_clk {
+             pll8: clk at 01c20044 {
                      #clock-cells = <0>;
-                     compatible = "fixed-clock";
-                     clock-frequency = <1>;
+                     compatible = "allwinner,sun6i-a31-pll6-clk";
+                     reg = <0x01c20044 0x4>;
+                     clocks = <&osc24M>;
                      clock-output-names = "pll8";
              };
 

@@ -165,7 +165,7 @@
                      #clock-cells = <0>;
                      compatible = "allwinner,sun6i-a31-ahb1-clk";
                      reg = <0x01c20054 0x4>;
-                     clocks = <&osc32k>, <&osc24M>, <&axi>, <&pll6 0>;
+                     clocks = <&osc32k>, <&osc24M>, <&axi>, <&pll6>;
                      clock-output-names = "ahb1";
              };
 

arch/arm/boot/dts/sun8i-h3.dtsi line 176

Quoted 6 lines

arch/arm/boot/dts/sun8i-h3.dtsi +1 -1

@@ -173,7 +173,7 @@
                      #clock-cells = <0>;
                      compatible = "allwinner,sun8i-h3-ahb2-clk";
                      reg = <0x01c2005c 0x4>;
-                     clocks = <&ahb1>, <&pll6d2>;
+                     clocks = <&ahb1>, <&pll6>;

According to the datasheet AHB2 really has PLL6 / 2 as parent, not PLL6 directly.

Quoted 9 lines

arch/arm/boot/dts/sun8i-h3.dtsi line 176

Quoted 6 lines

arch/arm/boot/dts/sun8i-h3.dtsi +1 -1

@@ -173,7 +173,7 @@
                      #clock-cells = <0>;
                      compatible = "allwinner,sun8i-h3-ahb2-clk";
                      reg = <0x01c2005c 0x4>;
-                     clocks = <&ahb1>, <&pll6d2>;
+                     clocks = <&ahb1>, <&pll6>;

According to the datasheet AHB2 really has PLL6 / 2 as parent, not PLL6 directly.

Thanks for the save. So we should keep pll6d2_clk.

Remove the fixed dividers from the PLL6 driver to be able to have a reusable driver that can be used across several SoCs that share the same controller, but don't have the same set of dividers for this clock, and to also be reused multiple times in the same SoC, since we're droping the clock name.

Signed-off-by Maxime Ripard <[email protected]>

---
Changes from v2
- Rebased and converted over to the new factors refactoring. Fixed the retrieved rate

 arch/arm/boot/dts/sun6i-a31.dtsi     | 36 ++++++++++++++++++------------------
 arch/arm/boot/dts/sun8i-a23-a33.dtsi | 25 +++++++++++++++++--------
 arch/arm/boot/dts/sun8i-a23.dtsi     |  2 +-
 arch/arm/boot/dts/sun8i-a33.dtsi     |  4 ++--
 arch/arm/boot/dts/sun8i-h3.dtsi      | 36 ++++++++++++++++++------------------
 drivers/clk/sunxi/clk-sunxi.c        | 32 ++++++++++++++++----------------
 6 files changed, 72 insertions(+), 63 deletions(-)

Quoted 12 lines · On Thu, 28 Jan 2016 20:22:38 +0100 Maxime Ripard…

Remove the fixed dividers from the PLL6 driver to be able to have a reusable driver that can be used across several SoCs that share the same controller, but don't have the same set of dividers for this clock, and to also be reused multiple times in the same SoC, since we're droping the clock name.

Signed-off-by Maxime Ripard <[email protected]>

---
Changes from v2
- Rebased and converted over to the new factors refactoring. Fixed the retrieved rate

Quoted 7 lines

 arch/arm/boot/dts/sun6i-a31.dtsi     | 36 ++++++++++++++++++------------------
 arch/arm/boot/dts/sun8i-a23-a33.dtsi | 25 +++++++++++++++++--------
 arch/arm/boot/dts/sun8i-a23.dtsi     |  2 +-
 arch/arm/boot/dts/sun8i-a33.dtsi     |  4 ++--
 arch/arm/boot/dts/sun8i-h3.dtsi      | 36 ++++++++++++++++++------------------
 drivers/clk/sunxi/clk-sunxi.c        | 32 ++++++++++++++++----------------
 6 files changed, 72 insertions(+), 63 deletions(-)

Hi Maxime,

Do you know that the DT definitions cannot be changed when they are in the mainline kernel?

Also, for the H3 PLL periph1 (aka PLL8), why didn't you create a 'pll8x2' clock with 'pll8' as a divider?

Quoted 8 lines · Jean-Francois Moine

Quoted 5 lines · On Thu, 28 Jan 2016 20:22:38 +0100 Maxime Ripard…

Remove the fixed dividers from the PLL6 driver to be able to have a reusable driver that can be used across several SoCs that share the same controller, but don't have the same set of dividers for this clock, and to also be reused multiple times in the same SoC, since we're droping the clock name.

Quoted 4 lines

Hi Maxime,

Do you know that the DT definitions cannot be changed when they are in the mainline kernel?

This rule varies depending on who you talk to. :)

Quoted 2 lines

Also, for the H3 PLL periph1 (aka PLL8), why didn't you create a 'pll8x2' clock with 'pll8' as a divider?

If it's used, it can be added later. No need to bloat the DT.

Quoted 12 lines · On Thu, 28 Jan 2016 20:22:38 +0100 Maxime Ripard…

Remove the fixed dividers from the PLL6 driver to be able to have a reusable driver that can be used across several SoCs that share the same controller, but don't have the same set of dividers for this clock, and to also be reused multiple times in the same SoC, since we're droping the clock name.

Signed-off-by Maxime Ripard <[email protected]>

---
Changes from v2
- Rebased and converted over to the new factors refactoring. Fixed the retrieved rate

Quoted 7 lines

 arch/arm/boot/dts/sun6i-a31.dtsi     | 36 ++++++++++++++++++------------------
 arch/arm/boot/dts/sun8i-a23-a33.dtsi | 25 +++++++++++++++++--------
 arch/arm/boot/dts/sun8i-a23.dtsi     |  2 +-
 arch/arm/boot/dts/sun8i-a33.dtsi     |  4 ++--
 arch/arm/boot/dts/sun8i-h3.dtsi      | 36 ++++++++++++++++++------------------
 drivers/clk/sunxi/clk-sunxi.c        | 32 ++++++++++++++++----------------
 6 files changed, 72 insertions(+), 63 deletions(-)

Hi Maxime,

Do you know that the DT definitions cannot be changed when they are in the mainline kernel?

Also, for the H3 PLL periph1 (aka PLL8), why didn't you create a 'pll8x2' clock with 'pll8' as a divider?

Quoted 2 lines

Also, for the H3 PLL periph1 (aka PLL8), why didn't you create a 'pll8x2' clock with 'pll8' as a divider?

No one seems to use it. We can always add it later in a separate patch when someone will.

Remove the fixed dividers from the PLL6 driver to be able to have a reusable driver that can be used across several SoCs that share the same controller, but don't have the same set of dividers for this clock, and to also be reused multiple times in the same SoC, since we're droping the clock name.

No one seems to use it. We can always add it later in a separate patch when someone will.

Quoted 5 lines · On Mon, 1 Feb 2016 21:17:54 +0100 Maxime Ripard…

Quoted 2 lines

Also, for the H3 PLL periph1 (aka PLL8), why didn't you create a 'pll8x2' clock with 'pll8' as a divider?

No one seems to use it. We can always add it later in a separate patch when someone will.

Well, then, I don't understand. The pll periph/peripheral/periph0, aka PLL6 works well for many SoCs and there is no need to change its DT definition.

In the patch header, you wrote:

Quoted 5 lines

Remove the fixed dividers from the PLL6 driver to be able to have a reusable driver that can be used across several SoCs that share the same controller, but don't have the same set of dividers for this clock, and to also be reused multiple times in the same SoC, since we're droping the clock name.

then, for the H3, you do
(the comment should be "until pll8 can be reused"),

Quoted 5 lines

arch/arm/boot/dts/sun8i-h3.dtsi +1 -3

-		/* dummy clock until pll6 can be reused */
-		pll8: pll8_clk {
+		pll8: clk at 01c20044 {
 			#clock-cells = <0>;
-			compatible = "fixed-clock";

arch/arm/boot/dts/sun8i-h3.dtsi line 146

Quoted 6 lines

arch/arm/boot/dts/sun8i-h3.dtsi +3 -1

-			clock-frequency = <1>;
+			compatible = "allwinner,sun6i-a31-pll6-clk";
+			reg = <0x01c20044 0x4>;
+			clocks = <&osc24M>;
 			clock-output-names = "pll8";
 		};

that is, you add the PLL8, don't you?

And, further, you change the MMC clocks:

arch/arm/boot/dts/sun8i-h3.dtsi line 249

Quoted 9 lines

arch/arm/boot/dts/sun8i-h3.dtsi +1 -1

@@ -243,7 +243,7 @@
 			#clock-cells = <1>;
 			compatible = "allwinner,sun4i-a10-mmc-clk";
 			reg = <0x01c20088 0x4>;
-			clocks = <&osc24M>, <&pll6 0>, <&pll8>;
+			clocks = <&osc24M>, <&pll6>, <&pll8>;
 			clock-output-names = "mmc0",
 					     "mmc0_output",
 					     "mmc0_sample";

where the PLL8 is already used.

So, how can you say

Quoted 2 lines

No one seems to use it. We can always add it later in a separate patch when someone will.

Commit 4a9b2abc213e ("clk: sunxi: factors: Support custom formulas") was introducing a custom recalc function. However, the pointer was never filled, which was making the whole thing unused.

Signed-off-by Maxime Ripard <[email protected]>

---
 drivers/clk/sunxi/clk-factors.c | 1 +
 1 file changed, 1 insertion(+)

drivers/clk/sunxi/clk-factors.c +1 -1

index e480a6bcf1f6..6e97f46c0c37 100644
@@ -212,6 +212,7 @@ struct clk *sunxi_factors_register(struct device_node *node,
        factors->reg = reg;
        factors->config = data->table;
        factors->get_factors = data->getter;
+       factors->recalc = data->recalc;
        factors->lock = lock;
 
        /* Add a gate if this factor clock can be gated */
--

2.6.4

Quoted 4 lines · Maxime Ripard

Commit 4a9b2abc213e ("clk: sunxi: factors: Support custom formulas") was introducing a custom recalc function. However, the pointer was never filled, which was making the whole thing unused.

Quoted 1 line

Signed-off-by Maxime Ripard <[email protected]>

(facepalm)

Acked-by Chen-Yu Tsai <[email protected]>

Can you squash it into the original?