mips: add base support for QCA/Atheros ath79 SOCs

Signed-off-by Wills Wang <[email protected]>

---

Changes in v7:
- Use setbits_32
- Fix include path for SoC specific headers

Changes in v6:
- Move ar933x as separate patch
- Add get_bootstrap in reset.c
- Use map_physmem instead of KSEG1ADDR
- Add arch_cpu_init for detect SOC type for early

arch/mips/mach-ath79/Kconfig new file +4 -0

+config SYS_SOC
+	default "ath79"
+
+endmenu

arch/mips/mach-ath79/Makefile new file +7 -0

new file mode 100644
index 0000000..6203cf0
@@ -0,0 +1,7 @@
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y += reset.o
+obj-y += cpu.o
+obj-y += dram.o

arch/mips/mach-ath79/cpu.c new file +12 -0

new file mode 100644
index 0000000..d8910a0
@@ -0,0 +1,203 @@
+/*
+ * Copyright (C) 2015-2016 Wills Wang <[email protected]>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/addrspace.h>
+#include <asm/types.h>
+#include <mach/ath79.h>
+#include <mach/ar71xx_regs.h>

arch/mips/mach-ath79/cpu.c new file +39 -0

+	{ATH79_SOC_AR7240,      "7240"},
+	{ATH79_SOC_AR7242,      "7242"},
+	{ATH79_SOC_AR9130,      "9130"},
+	{ATH79_SOC_AR9132,      "9132"},
+	{ATH79_SOC_AR9330,      "9330"},
+	{ATH79_SOC_AR9331,      "9331"},
+	{ATH79_SOC_AR9341,      "9341"},
+	{ATH79_SOC_AR9342,      "9342"},
+	{ATH79_SOC_AR9344,      "9344"},
+	{ATH79_SOC_QCA9533,     "9533"},
+	{ATH79_SOC_QCA9556,     "9556"},
+	{ATH79_SOC_QCA9558,     "9558"},
+	{ATH79_SOC_TP9343,      "9343"},
+	{ATH79_SOC_QCA9561,     "9561"},
+};
+
+int arch_cpu_init(void)
+{
+	void __iomem *base;
+	enum ath79_soc_type soc = ATH79_SOC_UNKNOWN;
+	u32 id, major, minor;
+	u32 rev = 0;
+	u32 ver = 1;
+
+	base = map_physmem(AR71XX_RESET_BASE, AR71XX_RESET_SIZE,
+			   MAP_NOCACHE);
+
+	id = readl(base + AR71XX_RESET_REG_REV_ID);
+	major = id & REV_ID_MAJOR_MASK;
+
+	switch (major) {
+	case REV_ID_MAJOR_AR71XX:
+		minor = id & AR71XX_REV_ID_MINOR_MASK;
+		rev = id >> AR71XX_REV_ID_REVISION_SHIFT;
+		rev &= AR71XX_REV_ID_REVISION_MASK;
+		switch (minor) {
+		case AR71XX_REV_ID_MINOR_AR7130:
+			soc = ATH79_SOC_AR7130;
+			break;

arch/mips/mach-ath79/cpu.c new file +4 -0

+	case REV_ID_MAJOR_AR7240:
+		soc = ATH79_SOC_AR7240;
+		rev = id & AR71XX_REV_ID_REVISION_MASK;
+		break;

(quoted diff) +0 -0

b/arch/mips/mach-ath79/include/mach/ar71xx_regs.h new file mode 100644 index 0000000..5e80eaf

arch/mips/mach-ath79/include/mach/ar71xx_regs.h new file +9 -0

@@ -0,0 +1,1187 @@
+/*
+ * Atheros AR71XX/AR724X/AR913X SoC register definitions
+ *
+ * Copyright (C) 2015-2016 Wills Wang <[email protected]>
+ * Copyright (C) 2010-2011 Jaiganesh Narayanan <[email protected]>
+ * Copyright (C) 2008-2010 Gabor Juhos <[email protected]>
+ * Copyright (C) 2008 Imre Kaloz <[email protected]>
+ *
+ * SPDX-License-Identifier:     GPL-2.0+

arch/mips/mach-ath79/include/mach/ar71xx_regs.h new file +2 -0

+#endif
+#endif

On Saturday, January 16, 2016 at 07:13:47 PM, Wills Wang wrote:

Commit message is missing.

Quoted 12 lines

Signed-off-by Wills Wang <[email protected]>

---

Changes in v7:
- Use setbits_32
- Fix include path for SoC specific headers

Changes in v6:
- Move ar933x as separate patch
- Add get_bootstrap in reset.c
- Use map_physmem instead of KSEG1ADDR
- Add arch_cpu_init for detect SOC type for early

[...]

arch/mips/mach-ath79/Kconfig line 5

Quoted 11 lines

arch/mips/mach-ath79/Kconfig new file +5 -0

new file mode 100644
index 0000000..df84876
@@ -0,0 +1,10 @@
+menu "QCA/Athroes 7xxx/9xxx platforms"
+	depends on ARCH_ATH79
+
+config SYS_VENDOR
+	default "ath79"

Vendor should be atheros I believe.

Quoted 38 lines

arch/mips/mach-ath79/Kconfig new file +4 -0

+config SYS_SOC
+	default "ath79"
+
+endmenu

arch/mips/mach-ath79/Makefile new file +7 -0

new file mode 100644
index 0000000..6203cf0
@@ -0,0 +1,7 @@
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y += reset.o
+obj-y += cpu.o
+obj-y += dram.o

arch/mips/mach-ath79/cpu.c new file +15 -0

new file mode 100644
index 0000000..d8910a0
@@ -0,0 +1,203 @@
+/*
+ * Copyright (C) 2015-2016 Wills Wang <[email protected]>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/addrspace.h>
+#include <asm/types.h>
+#include <mach/ath79.h>
+#include <mach/ar71xx_regs.h>
+
+struct ath79_soc_desc {
+	enum ath79_soc_type soc;

arch/mips/mach-ath79/cpu.c line 22

Quoted 7 lines

arch/mips/mach-ath79/cpu.c new file +7 -0

+	const char *chip;
+};
+
+static struct ath79_soc_desc desc[] = {
+	{ATH79_SOC_AR7130,      "7130"},
+	{ATH79_SOC_AR7141,      "7141"},
+	{ATH79_SOC_AR7161,      "7161"},

Just curious, were 7161 chips ever tested ?

Quoted 42 lines

arch/mips/mach-ath79/cpu.c new file +42 -0

+	{ATH79_SOC_AR7240,      "7240"},
+	{ATH79_SOC_AR7242,      "7242"},
+	{ATH79_SOC_AR9130,      "9130"},
+	{ATH79_SOC_AR9132,      "9132"},
+	{ATH79_SOC_AR9330,      "9330"},
+	{ATH79_SOC_AR9331,      "9331"},
+	{ATH79_SOC_AR9341,      "9341"},
+	{ATH79_SOC_AR9342,      "9342"},
+	{ATH79_SOC_AR9344,      "9344"},
+	{ATH79_SOC_QCA9533,     "9533"},
+	{ATH79_SOC_QCA9556,     "9556"},
+	{ATH79_SOC_QCA9558,     "9558"},
+	{ATH79_SOC_TP9343,      "9343"},
+	{ATH79_SOC_QCA9561,     "9561"},
+};
+
+int arch_cpu_init(void)
+{
+	void __iomem *base;
+	enum ath79_soc_type soc = ATH79_SOC_UNKNOWN;
+	u32 id, major, minor;
+	u32 rev = 0;
+	u32 ver = 1;
+
+	base = map_physmem(AR71XX_RESET_BASE, AR71XX_RESET_SIZE,
+			   MAP_NOCACHE);
+
+	id = readl(base + AR71XX_RESET_REG_REV_ID);
+	major = id & REV_ID_MAJOR_MASK;
+
+	switch (major) {
+	case REV_ID_MAJOR_AR71XX:
+		minor = id & AR71XX_REV_ID_MINOR_MASK;
+		rev = id >> AR71XX_REV_ID_REVISION_SHIFT;
+		rev &= AR71XX_REV_ID_REVISION_MASK;
+		switch (minor) {
+		case AR71XX_REV_ID_MINOR_AR7130:
+			soc = ATH79_SOC_AR7130;
+			break;
+
+		case AR71XX_REV_ID_MINOR_AR7141:
+			soc = ATH79_SOC_AR7141;

arch/mips/mach-ath79/cpu.c line 71

Quoted 7 lines

arch/mips/mach-ath79/cpu.c new file +7 -0

+			break;
+
+		case AR71XX_REV_ID_MINOR_AR7161:
+			soc = ATH79_SOC_AR7161;
+			break;
+		}
+		break;

This could easily be a lookup-table instead of such big switch statement.

Quoted 4 lines

arch/mips/mach-ath79/cpu.c new file +4 -0

+	case REV_ID_MAJOR_AR7240:
+		soc = ATH79_SOC_AR7240;
+		rev = id & AR71XX_REV_ID_REVISION_MASK;
+		break;

[...]

Quoted 18 lines

(quoted diff) +0 -0

b/arch/mips/mach-ath79/include/mach/ar71xx_regs.h new file mode 100644 index 0000000..5e80eaf

arch/mips/mach-ath79/include/mach/ar71xx_regs.h new file +12 -0

@@ -0,0 +1,1187 @@
+/*
+ * Atheros AR71XX/AR724X/AR913X SoC register definitions
+ *
+ * Copyright (C) 2015-2016 Wills Wang <[email protected]>
+ * Copyright (C) 2010-2011 Jaiganesh Narayanan <[email protected]>
+ * Copyright (C) 2008-2010 Gabor Juhos <[email protected]>
+ * Copyright (C) 2008 Imre Kaloz <[email protected]>
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#ifndef __ASM_MACH_AR71XX_REGS_H

arch/mips/mach-ath79/include/mach/ar71xx_regs.h line 19

Quoted 7 lines

arch/mips/mach-ath79/include/mach/ar71xx_regs.h new file +7 -0

+#define __ASM_MACH_AR71XX_REGS_H
+
+#ifndef __ASSEMBLY__
+#include <linux/bitops.h>
+#else
+#ifndef BIT
+#define BIT(nr)                 (1 << (nr))

Linux defines the macro as (1ul << (nr))

Quoted 2 lines

arch/mips/mach-ath79/include/mach/ar71xx_regs.h new file +2 -0

+#endif
+#endif

[...]

Quoted 19 lines · Marek Vasut

On Saturday, January 16, 2016 at 07:13:47 PM, Wills Wang wrote:

Commit message is missing.

Quoted 12 lines

Signed-off-by Wills Wang <[email protected]>

---

Changes in v7:
- Use setbits_32
- Fix include path for SoC specific headers

Changes in v6:
- Move ar933x as separate patch
- Add get_bootstrap in reset.c
- Use map_physmem instead of KSEG1ADDR
- Add arch_cpu_init for detect SOC type for early

[...]

Quoted 13 lines

arch/mips/mach-ath79/Kconfig line 5

Quoted 11 lines

arch/mips/mach-ath79/Kconfig new file +5 -0

new file mode 100644
index 0000000..df84876
@@ -0,0 +1,10 @@
+menu "QCA/Athroes 7xxx/9xxx platforms"
+	depends on ARCH_ATH79
+
+config SYS_VENDOR
+	default "ath79"

Vendor should be atheros I believe.

Now atheros was merged into qualcomm, ap121 and ap143, one belongs to atheros and the other to qualcomm.

Quoted 39 lines

Quoted 39 lines

arch/mips/mach-ath79/Kconfig new file +4 -0

+config SYS_SOC
+	default "ath79"
+
+endmenu

(quoted diff) +0 -0

b/arch/mips/mach-ath79/Makefile new file mode 100644 index 0000000..6203cf0

arch/mips/mach-ath79/Makefile new file +7 -0

@@ -0,0 +1,7 @@
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y += reset.o
+obj-y += cpu.o
+obj-y += dram.o

arch/mips/mach-ath79/cpu.c new file +16 -0

new file mode 100644
index 0000000..d8910a0
@@ -0,0 +1,203 @@
+/*
+ * Copyright (C) 2015-2016 Wills Wang <[email protected]>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/addrspace.h>
+#include <asm/types.h>
+#include <mach/ath79.h>
+#include <mach/ar71xx_regs.h>
+
+struct ath79_soc_desc {
+	enum ath79_soc_type soc;
+	const char *chip;

Quoted 8 lines

arch/mips/mach-ath79/cpu.c line 22

Quoted 6 lines

arch/mips/mach-ath79/cpu.c new file +6 -0

+};
+
+static struct ath79_soc_desc desc[] = {
+	{ATH79_SOC_AR7130,      "7130"},
+	{ATH79_SOC_AR7141,      "7141"},
+	{ATH79_SOC_AR7161,      "7161"},

Just curious, were 7161 chips ever tested ?

These id rules are verified by kernel and openwrt project, Of course, we can also remove support for these chips that faded out the market.

Quoted 43 lines

Quoted 43 lines

arch/mips/mach-ath79/cpu.c new file +43 -0

+	{ATH79_SOC_AR7240,      "7240"},
+	{ATH79_SOC_AR7242,      "7242"},
+	{ATH79_SOC_AR9130,      "9130"},
+	{ATH79_SOC_AR9132,      "9132"},
+	{ATH79_SOC_AR9330,      "9330"},
+	{ATH79_SOC_AR9331,      "9331"},
+	{ATH79_SOC_AR9341,      "9341"},
+	{ATH79_SOC_AR9342,      "9342"},
+	{ATH79_SOC_AR9344,      "9344"},
+	{ATH79_SOC_QCA9533,     "9533"},
+	{ATH79_SOC_QCA9556,     "9556"},
+	{ATH79_SOC_QCA9558,     "9558"},
+	{ATH79_SOC_TP9343,      "9343"},
+	{ATH79_SOC_QCA9561,     "9561"},
+};
+
+int arch_cpu_init(void)
+{
+	void __iomem *base;
+	enum ath79_soc_type soc = ATH79_SOC_UNKNOWN;
+	u32 id, major, minor;
+	u32 rev = 0;
+	u32 ver = 1;
+
+	base = map_physmem(AR71XX_RESET_BASE, AR71XX_RESET_SIZE,
+			   MAP_NOCACHE);
+
+	id = readl(base + AR71XX_RESET_REG_REV_ID);
+	major = id & REV_ID_MAJOR_MASK;
+
+	switch (major) {
+	case REV_ID_MAJOR_AR71XX:
+		minor = id & AR71XX_REV_ID_MINOR_MASK;
+		rev = id >> AR71XX_REV_ID_REVISION_SHIFT;
+		rev &= AR71XX_REV_ID_REVISION_MASK;
+		switch (minor) {
+		case AR71XX_REV_ID_MINOR_AR7130:
+			soc = ATH79_SOC_AR7130;
+			break;
+
+		case AR71XX_REV_ID_MINOR_AR7141:
+			soc = ATH79_SOC_AR7141;
+			break;

Quoted 8 lines

arch/mips/mach-ath79/cpu.c line 71

Quoted 6 lines

arch/mips/mach-ath79/cpu.c new file +6 -0

+
+		case AR71XX_REV_ID_MINOR_AR7161:
+			soc = ATH79_SOC_AR7161;
+			break;
+		}
+		break;

This could easily be a lookup-table instead of such big switch statement.

This has already been explained in v4, i have tried to use lookup-table, but the code is not more beautiful than now, the bit filed of id is not regular.

The shift bits of minor and revision is different for same chips, same chips
should ignore the minor bits, the lookup table must store these shift information and which was ignored in common, so the table will become more complex if this code want to be compatible with many other SOCs.

If people want to add other QCA's SoC, need spend a great deal of time to debug this code.

Quoted 26 lines

Quoted 4 lines

arch/mips/mach-ath79/cpu.c new file +4 -0

+	case REV_ID_MAJOR_AR7240:
+		soc = ATH79_SOC_AR7240;
+		rev = id & AR71XX_REV_ID_REVISION_MASK;
+		break;

[...]

Quoted 19 lines

(quoted diff) +0 -0

b/arch/mips/mach-ath79/include/mach/ar71xx_regs.h new file mode 100644 index 0000000..5e80eaf

arch/mips/mach-ath79/include/mach/ar71xx_regs.h new file +13 -0

@@ -0,0 +1,1187 @@
+/*
+ * Atheros AR71XX/AR724X/AR913X SoC register definitions
+ *
+ * Copyright (C) 2015-2016 Wills Wang <[email protected]>
+ * Copyright (C) 2010-2011 Jaiganesh Narayanan <[email protected]>
+ * Copyright (C) 2008-2010 Gabor Juhos <[email protected]>
+ * Copyright (C) 2008 Imre Kaloz <[email protected]>
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#ifndef __ASM_MACH_AR71XX_REGS_H
+#define __ASM_MACH_AR71XX_REGS_H

Quoted 8 lines

arch/mips/mach-ath79/include/mach/ar71xx_regs.h line 19

Quoted 6 lines

arch/mips/mach-ath79/include/mach/ar71xx_regs.h new file +6 -0

+
+#ifndef __ASSEMBLY__
+#include <linux/bitops.h>
+#else
+#ifndef BIT
+#define BIT(nr)                 (1 << (nr))

Linux defines the macro as (1ul << (nr))

This header is also used by assembler, the assembler don't recognize label 1ul.

Quoted 4 lines

Quoted 2 lines

arch/mips/mach-ath79/include/mach/ar71xx_regs.h new file +2 -0

+#endif
+#endif

[...]

Quoted 31 lines · Wills Wang

Quoted 30 lines · Marek Vasut

On Saturday, January 16, 2016 at 07:13:47 PM, Wills Wang wrote:

Commit message is missing.

Quoted 12 lines

Signed-off-by Wills Wang <[email protected]>

---

Changes in v7:
- Use setbits_32
- Fix include path for SoC specific headers

Changes in v6:
- Move ar933x as separate patch
- Add get_bootstrap in reset.c
- Use map_physmem instead of KSEG1ADDR
- Add arch_cpu_init for detect SOC type for early

[...]

arch/mips/mach-ath79/Kconfig line 5

Quoted 11 lines

arch/mips/mach-ath79/Kconfig new file +5 -0

new file mode 100644
index 0000000..df84876
@@ -0,0 +1,10 @@
+menu "QCA/Athroes 7xxx/9xxx platforms"
+	depends on ARCH_ATH79
+
+config SYS_VENDOR
+	default "ath79"

Vendor should be atheros I believe.

Quoted 2 lines

Now atheros was merged into qualcomm, ap121 and ap143, one belongs to atheros and the other to qualcomm.

So write qualcomm/atheros ? What's the problem ?

Quoted 46 lines

Quoted 46 lines

Quoted 35 lines

arch/mips/mach-ath79/Kconfig new file +4 -0

+config SYS_SOC
+	default "ath79"
+
+endmenu

(quoted diff) +0 -0

b/arch/mips/mach-ath79/Makefile new file mode 100644 index 0000000..6203cf0

arch/mips/mach-ath79/Makefile new file +7 -0

@@ -0,0 +1,7 @@
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y += reset.o
+obj-y += cpu.o
+obj-y += dram.o

arch/mips/mach-ath79/cpu.c new file +12 -0

new file mode 100644
index 0000000..d8910a0
@@ -0,0 +1,203 @@
+/*
+ * Copyright (C) 2015-2016 Wills Wang <[email protected]>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/addrspace.h>
+#include <asm/types.h>
+#include <mach/ath79.h>
+#include <mach/ar71xx_regs.h>

arch/mips/mach-ath79/cpu.c line 22

Quoted 10 lines

arch/mips/mach-ath79/cpu.c new file +10 -0

+
+struct ath79_soc_desc {
+	enum ath79_soc_type soc;
+	const char *chip;
+};
+
+static struct ath79_soc_desc desc[] = {
+	{ATH79_SOC_AR7130,      "7130"},
+	{ATH79_SOC_AR7141,      "7141"},
+	{ATH79_SOC_AR7161,      "7161"},

Just curious, were 7161 chips ever tested ?

Quoted 3 lines

These id rules are verified by kernel and openwrt project, Of course, we can also remove support for these chips that faded out the market.

That's not answering my question, I am asking if the code was tested on those chips at all or not.

Quoted 54 lines

Quoted 42 lines

Quoted 42 lines

arch/mips/mach-ath79/cpu.c new file +42 -0

+	{ATH79_SOC_AR7240,      "7240"},
+	{ATH79_SOC_AR7242,      "7242"},
+	{ATH79_SOC_AR9130,      "9130"},
+	{ATH79_SOC_AR9132,      "9132"},
+	{ATH79_SOC_AR9330,      "9330"},
+	{ATH79_SOC_AR9331,      "9331"},
+	{ATH79_SOC_AR9341,      "9341"},
+	{ATH79_SOC_AR9342,      "9342"},
+	{ATH79_SOC_AR9344,      "9344"},
+	{ATH79_SOC_QCA9533,     "9533"},
+	{ATH79_SOC_QCA9556,     "9556"},
+	{ATH79_SOC_QCA9558,     "9558"},
+	{ATH79_SOC_TP9343,      "9343"},
+	{ATH79_SOC_QCA9561,     "9561"},
+};
+
+int arch_cpu_init(void)
+{
+	void __iomem *base;
+	enum ath79_soc_type soc = ATH79_SOC_UNKNOWN;
+	u32 id, major, minor;
+	u32 rev = 0;
+	u32 ver = 1;
+
+	base = map_physmem(AR71XX_RESET_BASE, AR71XX_RESET_SIZE,
+			   MAP_NOCACHE);
+
+	id = readl(base + AR71XX_RESET_REG_REV_ID);
+	major = id & REV_ID_MAJOR_MASK;
+
+	switch (major) {
+	case REV_ID_MAJOR_AR71XX:
+		minor = id & AR71XX_REV_ID_MINOR_MASK;
+		rev = id >> AR71XX_REV_ID_REVISION_SHIFT;
+		rev &= AR71XX_REV_ID_REVISION_MASK;
+		switch (minor) {
+		case AR71XX_REV_ID_MINOR_AR7130:
+			soc = ATH79_SOC_AR7130;
+			break;
+
+		case AR71XX_REV_ID_MINOR_AR7141:
+			soc = ATH79_SOC_AR7141;

Quoted 8 lines

arch/mips/mach-ath79/cpu.c line 71

Quoted 7 lines

arch/mips/mach-ath79/cpu.c new file +7 -0

+			break;
+
+		case AR71XX_REV_ID_MINOR_AR7161:
+			soc = ATH79_SOC_AR7161;
+			break;
+		}
+		break;

This could easily be a lookup-table instead of such big switch statement.

This has already been explained in v4, i have tried to use lookup-table, but the code is not more beautiful than now, the bit filed of id is not regular.

Quoted 5 lines

The shift bits of minor and revision is different for same chips, same chips
should ignore the minor bits, the lookup table must store these shift information and which was ignored in common, so the table will become more complex if this code want to be compatible with many other SOCs.

I don't see a problem with storing offset and mask in the table.

Quoted 2 lines

If people want to add other QCA's SoC, need spend a great deal of time to debug this code.

Why? They'd just add the necessary entry into the table.

Quoted 32 lines

Quoted 24 lines

Quoted 4 lines

arch/mips/mach-ath79/cpu.c new file +4 -0

+	case REV_ID_MAJOR_AR7240:
+		soc = ATH79_SOC_AR7240;
+		rev = id & AR71XX_REV_ID_REVISION_MASK;
+		break;

[...]

Quoted 18 lines

(quoted diff) +0 -0

b/arch/mips/mach-ath79/include/mach/ar71xx_regs.h new file mode 100644 index 0000000..5e80eaf

arch/mips/mach-ath79/include/mach/ar71xx_regs.h new file +12 -0

@@ -0,0 +1,1187 @@
+/*
+ * Atheros AR71XX/AR724X/AR913X SoC register definitions
+ *
+ * Copyright (C) 2015-2016 Wills Wang <[email protected]>
+ * Copyright (C) 2010-2011 Jaiganesh Narayanan <[email protected]>
+ * Copyright (C) 2008-2010 Gabor Juhos <[email protected]>
+ * Copyright (C) 2008 Imre Kaloz <[email protected]>
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#ifndef __ASM_MACH_AR71XX_REGS_H

Quoted 8 lines

arch/mips/mach-ath79/include/mach/ar71xx_regs.h line 19

Quoted 7 lines

arch/mips/mach-ath79/include/mach/ar71xx_regs.h new file +7 -0

+#define __ASM_MACH_AR71XX_REGS_H
+
+#ifndef __ASSEMBLY__
+#include <linux/bitops.h>
+#else
+#ifndef BIT
+#define BIT(nr)                 (1 << (nr))

Linux defines the macro as (1ul << (nr))

Quoted 2 lines

This header is also used by assembler, the assembler don't recognize label 1ul.

In that case, this should be fixed in bitops.h and brought up in the kernel mailing list. Otherwise, we will develop unnecessary boilerplate code soon.

Quoted 3 lines

Quoted 3 lines

Quoted 2 lines

arch/mips/mach-ath79/include/mach/ar71xx_regs.h new file +2 -0

+#endif
+#endif

[...]

Quoted 35 lines · Marek Vasut

Quoted 34 lines · Wills Wang

Quoted 32 lines · Marek Vasut

On Saturday, January 16, 2016 at 07:13:47 PM, Wills Wang wrote:

Commit message is missing.

Quoted 12 lines

Signed-off-by Wills Wang <[email protected]>

---

Changes in v7:
- Use setbits_32
- Fix include path for SoC specific headers

Changes in v6:
- Move ar933x as separate patch
- Add get_bootstrap in reset.c
- Use map_physmem instead of KSEG1ADDR
- Add arch_cpu_init for detect SOC type for early

[...]

arch/mips/mach-ath79/Kconfig line 5

Quoted 11 lines

(quoted diff) +0 -0

b/arch/mips/mach-ath79/Kconfig new file mode 100644 index 0000000..df84876

arch/mips/mach-ath79/Kconfig new file +5 -0

@@ -0,0 +1,10 @@
+menu "QCA/Athroes 7xxx/9xxx platforms"
+	depends on ARCH_ATH79
+
+config SYS_VENDOR
+	default "ath79"

Vendor should be atheros I believe.

Quoted 4 lines

Quoted 2 lines

Now atheros was merged into qualcomm, ap121 and ap143, one belongs to atheros and the other to qualcomm.

So write qualcomm/atheros ? What's the problem ?

SYS_VENDOR is used to specify the folder

name under board, i will change it into atheros-qualcomm or qca.

Quoted 48 lines

Quoted 48 lines

Quoted 47 lines

Quoted 35 lines

arch/mips/mach-ath79/Kconfig new file +4 -0

+config SYS_SOC
+	default "ath79"
+
+endmenu

(quoted diff) +0 -0

b/arch/mips/mach-ath79/Makefile new file mode 100644 index 0000000..6203cf0

arch/mips/mach-ath79/Makefile new file +7 -0

@@ -0,0 +1,7 @@
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y += reset.o
+obj-y += cpu.o
+obj-y += dram.o

arch/mips/mach-ath79/cpu.c new file +12 -0

new file mode 100644
index 0000000..d8910a0
@@ -0,0 +1,203 @@
+/*
+ * Copyright (C) 2015-2016 Wills Wang <[email protected]>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/addrspace.h>
+#include <asm/types.h>
+#include <mach/ath79.h>
+#include <mach/ar71xx_regs.h>

arch/mips/mach-ath79/cpu.c line 22

Quoted 10 lines

arch/mips/mach-ath79/cpu.c new file +10 -0

+
+struct ath79_soc_desc {
+	enum ath79_soc_type soc;
+	const char *chip;
+};
+
+static struct ath79_soc_desc desc[] = {
+	{ATH79_SOC_AR7130,      "7130"},
+	{ATH79_SOC_AR7141,      "7141"},
+	{ATH79_SOC_AR7161,      "7161"},

Just curious, were 7161 chips ever tested ?

Quoted 6 lines

Quoted 3 lines

These id rules are verified by kernel and openwrt project, Of course, we can also remove support for these chips that faded out the market.

That's not answering my question, I am asking if the code was tested on those chips at all or not.

Not test.

Quoted 65 lines

Quoted 57 lines

Quoted 44 lines

Quoted 44 lines

arch/mips/mach-ath79/cpu.c new file +44 -0

+	{ATH79_SOC_AR7240,      "7240"},
+	{ATH79_SOC_AR7242,      "7242"},
+	{ATH79_SOC_AR9130,      "9130"},
+	{ATH79_SOC_AR9132,      "9132"},
+	{ATH79_SOC_AR9330,      "9330"},
+	{ATH79_SOC_AR9331,      "9331"},
+	{ATH79_SOC_AR9341,      "9341"},
+	{ATH79_SOC_AR9342,      "9342"},
+	{ATH79_SOC_AR9344,      "9344"},
+	{ATH79_SOC_QCA9533,     "9533"},
+	{ATH79_SOC_QCA9556,     "9556"},
+	{ATH79_SOC_QCA9558,     "9558"},
+	{ATH79_SOC_TP9343,      "9343"},
+	{ATH79_SOC_QCA9561,     "9561"},
+};
+
+int arch_cpu_init(void)
+{
+	void __iomem *base;
+	enum ath79_soc_type soc = ATH79_SOC_UNKNOWN;
+	u32 id, major, minor;
+	u32 rev = 0;
+	u32 ver = 1;
+
+	base = map_physmem(AR71XX_RESET_BASE, AR71XX_RESET_SIZE,
+			   MAP_NOCACHE);
+
+	id = readl(base + AR71XX_RESET_REG_REV_ID);
+	major = id & REV_ID_MAJOR_MASK;
+
+	switch (major) {
+	case REV_ID_MAJOR_AR71XX:
+		minor = id & AR71XX_REV_ID_MINOR_MASK;
+		rev = id >> AR71XX_REV_ID_REVISION_SHIFT;
+		rev &= AR71XX_REV_ID_REVISION_MASK;
+		switch (minor) {
+		case AR71XX_REV_ID_MINOR_AR7130:
+			soc = ATH79_SOC_AR7130;
+			break;
+
+		case AR71XX_REV_ID_MINOR_AR7141:
+			soc = ATH79_SOC_AR7141;
+			break;
+

Quoted 8 lines

arch/mips/mach-ath79/cpu.c line 71

Quoted 5 lines

arch/mips/mach-ath79/cpu.c new file +5 -0

+		case AR71XX_REV_ID_MINOR_AR7161:
+			soc = ATH79_SOC_AR7161;
+			break;
+		}
+		break;

This could easily be a lookup-table instead of such big switch statement.

This has already been explained in v4, i have tried to use lookup-table, but the code is not more beautiful than now, the bit filed of id is not regular.

Quoted 5 lines

The shift bits of minor and revision is different for same chips, same chips
should ignore the minor bits, the lookup table must store these shift information and which was ignored in common, so the table will become more complex if this code want to be compatible with many other SOCs.

I don't see a problem with storing offset and mask in the table.

Quoted 4 lines

Quoted 2 lines

If people want to add other QCA's SoC, need spend a great deal of time to debug this code.

Why? They'd just add the necessary entry into the table.

The bit filed of id register is not regular, they need modify this lookup table sometimes.

Quoted 47 lines

Quoted 36 lines

Quoted 27 lines

Quoted 4 lines

arch/mips/mach-ath79/cpu.c new file +4 -0

+	case REV_ID_MAJOR_AR7240:
+		soc = ATH79_SOC_AR7240;
+		rev = id & AR71XX_REV_ID_REVISION_MASK;
+		break;

[...]

Quoted 20 lines

(quoted diff) +0 -0

b/arch/mips/mach-ath79/include/mach/ar71xx_regs.h new file mode 100644 index 0000000..5e80eaf

arch/mips/mach-ath79/include/mach/ar71xx_regs.h new file +5 -0

@@ -0,0 +1,1187 @@
+/*
+ * Atheros AR71XX/AR724X/AR913X SoC register definitions
+ *
+ * Copyright (C) 2015-2016 Wills Wang <[email protected]>
+ * Copyright (C) 2010-2011 Jaiganesh Narayanan

<[email protected]> + * Copyright (C) 2008-2010 Gabor Juhos <[email protected]>
+ * Copyright (C) 2008 Imre Kaloz <[email protected]>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */

arch/mips/mach-ath79/include/mach/ar71xx_regs.h new file +3 -0

+
+#ifndef __ASM_MACH_AR71XX_REGS_H
+#define __ASM_MACH_AR71XX_REGS_H

Quoted 8 lines

arch/mips/mach-ath79/include/mach/ar71xx_regs.h line 19

Quoted 6 lines

arch/mips/mach-ath79/include/mach/ar71xx_regs.h new file +6 -0

+
+#ifndef __ASSEMBLY__
+#include <linux/bitops.h>
+#else
+#ifndef BIT
+#define BIT(nr)                 (1 << (nr))

Linux defines the macro as (1ul << (nr))

Quoted 2 lines

This header is also used by assembler, the assembler don't recognize label 1ul.

In that case, this should be fixed in bitops.h and brought up in the kernel mailing list. Otherwise, we will develop unnecessary boilerplate code soon.

Quoted 4 lines

Quoted 4 lines

Quoted 2 lines

arch/mips/mach-ath79/include/mach/ar71xx_regs.h new file +2 -0

+#endif
+#endif

[...]

Quoted 33 lines · Wills Wang

Quoted 32 lines · Marek Vasut

Quoted 31 lines · Wills Wang

Quoted 30 lines · Marek Vasut

On Saturday, January 16, 2016 at 07:13:47 PM, Wills Wang wrote:

Commit message is missing.

Quoted 12 lines

Signed-off-by Wills Wang <[email protected]>

---

Changes in v7:
- Use setbits_32
- Fix include path for SoC specific headers

Changes in v6:
- Move ar933x as separate patch
- Add get_bootstrap in reset.c
- Use map_physmem instead of KSEG1ADDR
- Add arch_cpu_init for detect SOC type for early

[...]

arch/mips/mach-ath79/Kconfig line 5

Quoted 11 lines

(quoted diff) +0 -0

b/arch/mips/mach-ath79/Kconfig new file mode 100644 index 0000000..df84876

arch/mips/mach-ath79/Kconfig new file +5 -0

@@ -0,0 +1,10 @@
+menu "QCA/Athroes 7xxx/9xxx platforms"
+	depends on ARCH_ATH79
+
+config SYS_VENDOR
+	default "ath79"

Vendor should be atheros I believe.

Quoted 4 lines

Quoted 3 lines

Quoted 2 lines

Now atheros was merged into qualcomm, ap121 and ap143, one belongs to atheros and the other to qualcomm.

So write qualcomm/atheros ? What's the problem ?

SYS_VENDOR is used to specify the folder

directory, this is not windows.

Quoted 1 line

name under board, i will change it into atheros-qualcomm or qca.

qca then.

Quoted 46 lines

Quoted 46 lines

Quoted 46 lines

Quoted 46 lines

Quoted 35 lines

arch/mips/mach-ath79/Kconfig new file +4 -0

+config SYS_SOC
+	default "ath79"
+
+endmenu

(quoted diff) +0 -0

b/arch/mips/mach-ath79/Makefile new file mode 100644 index 0000000..6203cf0

arch/mips/mach-ath79/Makefile new file +7 -0

@@ -0,0 +1,7 @@
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y += reset.o
+obj-y += cpu.o
+obj-y += dram.o

arch/mips/mach-ath79/cpu.c new file +12 -0

new file mode 100644
index 0000000..d8910a0
@@ -0,0 +1,203 @@
+/*
+ * Copyright (C) 2015-2016 Wills Wang <[email protected]>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/addrspace.h>
+#include <asm/types.h>
+#include <mach/ath79.h>
+#include <mach/ar71xx_regs.h>

arch/mips/mach-ath79/cpu.c line 22

Quoted 10 lines

arch/mips/mach-ath79/cpu.c new file +10 -0

+
+struct ath79_soc_desc {
+	enum ath79_soc_type soc;
+	const char *chip;
+};
+
+static struct ath79_soc_desc desc[] = {
+	{ATH79_SOC_AR7130,      "7130"},
+	{ATH79_SOC_AR7141,      "7141"},
+	{ATH79_SOC_AR7161,      "7161"},

Just curious, were 7161 chips ever tested ?

Quoted 6 lines

Quoted 5 lines

Quoted 3 lines

These id rules are verified by kernel and openwrt project, Of course, we can also remove support for these chips that faded out the market.

That's not answering my question, I am asking if the code was tested on those chips at all or not.

Not test.

OK, which SoCs were tested ?

Quoted 60 lines

Quoted 60 lines

Quoted 60 lines

Quoted 43 lines

Quoted 43 lines

arch/mips/mach-ath79/cpu.c new file +43 -0

+	{ATH79_SOC_AR7240,      "7240"},
+	{ATH79_SOC_AR7242,      "7242"},
+	{ATH79_SOC_AR9130,      "9130"},
+	{ATH79_SOC_AR9132,      "9132"},
+	{ATH79_SOC_AR9330,      "9330"},
+	{ATH79_SOC_AR9331,      "9331"},
+	{ATH79_SOC_AR9341,      "9341"},
+	{ATH79_SOC_AR9342,      "9342"},
+	{ATH79_SOC_AR9344,      "9344"},
+	{ATH79_SOC_QCA9533,     "9533"},
+	{ATH79_SOC_QCA9556,     "9556"},
+	{ATH79_SOC_QCA9558,     "9558"},
+	{ATH79_SOC_TP9343,      "9343"},
+	{ATH79_SOC_QCA9561,     "9561"},
+};
+
+int arch_cpu_init(void)
+{
+	void __iomem *base;
+	enum ath79_soc_type soc = ATH79_SOC_UNKNOWN;
+	u32 id, major, minor;
+	u32 rev = 0;
+	u32 ver = 1;
+
+	base = map_physmem(AR71XX_RESET_BASE, AR71XX_RESET_SIZE,
+			   MAP_NOCACHE);
+
+	id = readl(base + AR71XX_RESET_REG_REV_ID);
+	major = id & REV_ID_MAJOR_MASK;
+
+	switch (major) {
+	case REV_ID_MAJOR_AR71XX:
+		minor = id & AR71XX_REV_ID_MINOR_MASK;
+		rev = id >> AR71XX_REV_ID_REVISION_SHIFT;
+		rev &= AR71XX_REV_ID_REVISION_MASK;
+		switch (minor) {
+		case AR71XX_REV_ID_MINOR_AR7130:
+			soc = ATH79_SOC_AR7130;
+			break;
+
+		case AR71XX_REV_ID_MINOR_AR7141:
+			soc = ATH79_SOC_AR7141;
+			break;

Quoted 8 lines

arch/mips/mach-ath79/cpu.c line 71

Quoted 6 lines

arch/mips/mach-ath79/cpu.c new file +6 -0

+
+		case AR71XX_REV_ID_MINOR_AR7161:
+			soc = ATH79_SOC_AR7161;
+			break;
+		}
+		break;

This could easily be a lookup-table instead of such big switch statement.

This has already been explained in v4, i have tried to use lookup-table, but the code is not more beautiful than now, the bit filed of id is not regular.

The shift bits of minor and revision is different for same chips, same chips
should ignore the minor bits, the lookup table must store these shift information and which was ignored in common, so the table will become more complex if this code want to be compatible with many other SOCs.

Quoted 7 lines

Quoted 5 lines

I don't see a problem with storing offset and mask in the table.

Quoted 2 lines

If people want to add other QCA's SoC, need spend a great deal of time to debug this code.

Why? They'd just add the necessary entry into the table.

The bit filed of id register is not regular, they need modify this lookup table sometimes.

Major seems pretty regular to me, minor might be different.

Quoted 42 lines

Quoted 42 lines

Quoted 33 lines

Quoted 25 lines

Quoted 4 lines

arch/mips/mach-ath79/cpu.c new file +4 -0

+	case REV_ID_MAJOR_AR7240:
+		soc = ATH79_SOC_AR7240;
+		rev = id & AR71XX_REV_ID_REVISION_MASK;
+		break;

[...]

Quoted 19 lines

(quoted diff) +0 -0

b/arch/mips/mach-ath79/include/mach/ar71xx_regs.h new file mode 100644 index 0000000..5e80eaf

arch/mips/mach-ath79/include/mach/ar71xx_regs.h new file +5 -0

@@ -0,0 +1,1187 @@
+/*
+ * Atheros AR71XX/AR724X/AR913X SoC register definitions
+ *
+ * Copyright (C) 2015-2016 Wills Wang <[email protected]>
+ * Copyright (C) 2010-2011 Jaiganesh Narayanan

<[email protected]> + * Copyright (C) 2008-2010 Gabor Juhos <[email protected]>
+ * Copyright (C) 2008 Imre Kaloz <[email protected]>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */

arch/mips/mach-ath79/include/mach/ar71xx_regs.h new file +2 -0

+
+#ifndef __ASM_MACH_AR71XX_REGS_H

Quoted 8 lines

arch/mips/mach-ath79/include/mach/ar71xx_regs.h line 19

Quoted 7 lines

arch/mips/mach-ath79/include/mach/ar71xx_regs.h new file +7 -0

+#define __ASM_MACH_AR71XX_REGS_H
+
+#ifndef __ASSEMBLY__
+#include <linux/bitops.h>
+#else
+#ifndef BIT
+#define BIT(nr)                 (1 << (nr))

Linux defines the macro as (1ul << (nr))

Quoted 2 lines

This header is also used by assembler, the assembler don't recognize label 1ul.

In that case, this should be fixed in bitops.h and brought up in the kernel mailing list. Otherwise, we will develop unnecessary boilerplate code soon.

Quoted 3 lines

Quoted 3 lines

Quoted 2 lines

arch/mips/mach-ath79/include/mach/ar71xx_regs.h new file +2 -0

+#endif
+#endif

[...]

Signed-off-by Wills Wang <[email protected]>

---

This patch enable work for ar933x SOC.

Signed-off-by Wills Wang <[email protected]>

---

arch/mips/mach-ath79/ar933x/ddr.c new file +30 -0

+void ddr_init(void)
+{
+	void __iomem *regs;
+	u32 val;
+
+	regs = map_physmem(AR71XX_DDR_CTRL_BASE, AR71XX_DDR_CTRL_SIZE,
+			   MAP_NOCACHE);
+
+	writel(DDR_CONF_REG_VAL, regs + AR71XX_DDR_REG_CONFIG);
+	writel(DDR_CONF2_REG_VAL, regs + AR71XX_DDR_REG_CONFIG2);
+
+	val = get_bootstrap();
+	if (val & AR933X_BOOTSTRAP_DDR2) {
+		/* AHB maximum timeout */
+		writel(0xfffff, regs + AR933X_DDR_REG_TIMEOUT_MAX);
+
+		/* Enable DDR2 */
+		writel(DDR2_CONF_VAL, regs + AR933X_DDR_REG_DDR2_CONFIG);
+
+		/* Precharge All */
+		writel(DDR_CTRL_PRECHARGE, regs + AR71XX_DDR_REG_CONTROL);
+
+		/* Disable High Temperature Self-Refresh, Full Array */
+		writel(0x00, regs + AR933X_DDR_REG_EMR2);
+		/* Extended Mode Register 2 Set (EMR2S) */
+		writel(DDR_CTRL_UPD_EMR2S, regs + AR71XX_DDR_REG_CONTROL);
+
+		writel(0x00, regs + AR933X_DDR_REG_EMR3);
+		/* Extended Mode Register 3 Set (EMR3S) */
+		writel(DDR_CTRL_UPD_EMR3S, regs + AR71XX_DDR_REG_CONTROL);

arch/mips/mach-ath79/ar933x/ddr.c new file +9 -0

+		writel(DDR2_MODE_VAL, regs + AR71XX_DDR_REG_MODE);
+		/* Mode Register Set (MRS) */
+		writel(DDR_CTRL_UPD_MRS, regs + AR71XX_DDR_REG_CONTROL);
+
+		/* Enable OCD defaults, Enable DLL,
+		 * Reduced Drive Strength */
+		writel(DDR2_EXT_MODE_OCD_VAL, regs + AR71XX_DDR_REG_EMR);
+		/* Extended Mode Register Set (EMRS) */
+		writel(DDR_CTRL_UPD_EMRS, regs + AR71XX_DDR_REG_CONTROL);

arch/mips/mach-ath79/ar933x/ddr.c new file +78 -0

+	addr = (void *)CKSEG0ADDR(0x2000);
+	for (i = 0; i < 256; i++) {
+		val = 0;
+		for (j = 0; j < 8; j++) {
+			if (i & (1 << j)) {
+				if (j % 2)
+					val |= 0xffff0000;
+				else
+					val |= 0x0000ffff;
+			}
+
+			if (j % 2) {
+				*addr++ = val;
+				val = 0;
+			}
+		}
+	}
+
+	err = 0;
+	done = 0;
+	dir = 1;
+	tap = readl(regs + AR71XX_DDR_REG_TAP_CTRL0);
+	val = tap;
+	while (!done) {
+		err = 0;
+		writel(val, regs + AR71XX_DDR_REG_TAP_CTRL0);
+		writel(val, regs + AR71XX_DDR_REG_TAP_CTRL1);
+		for (i = 0; i < 2; i++) {
+			addr_k1 = (void *)CKSEG1ADDR(0x2000);
+			addr_k0 = (void *)CKSEG0ADDR(0x2000);
+			addr = (void *)CKSEG0ADDR(0x3000);
+
+			while (addr_k0 < addr) {
+				if (*addr_k1++ != *addr_k0++) {
+					err = 1;
+					break;
+				}
+			}
+
+			if (err)
+				break;
+		}
+
+		if (err) {
+			if (dir) {
+				dir = 0;
+				val--;
+				upper = val;
+				val = tap;
+			} else {
+				val++;
+				lower = val;
+				done = 1;
+			}
+		} else {
+			if (dir) {
+				if (val < 0x20) {
+					val++;
+				} else {
+					dir = 0;
+					upper = val;
+					val = tap;
+				}
+			} else {
+				if (!val) {
+					lower = val;
+					done = 1;
+				} else {
+					val--;
+				}
+			}
+		}
+	}
+	val = (upper + lower) / 2;
+	writel(val, regs + AR71XX_DDR_REG_TAP_CTRL0);
+	val++;
+	writel(val, regs + AR71XX_DDR_REG_TAP_CTRL1);
+}

Quoted 1 line · Wills Wang

This patch enable work for ar933x SOC.

And it adds DDR code and clock code ... which is missing from the commit message.

Quoted 2 lines

Signed-off-by Wills Wang <[email protected]>

---

[...]

Quoted 34 lines

arch/mips/mach-ath79/ar933x/ddr.c new file +34 -0

+void ddr_init(void)
+{
+	void __iomem *regs;
+	u32 val;
+
+	regs = map_physmem(AR71XX_DDR_CTRL_BASE, AR71XX_DDR_CTRL_SIZE,
+			   MAP_NOCACHE);
+
+	writel(DDR_CONF_REG_VAL, regs + AR71XX_DDR_REG_CONFIG);
+	writel(DDR_CONF2_REG_VAL, regs + AR71XX_DDR_REG_CONFIG2);
+
+	val = get_bootstrap();
+	if (val & AR933X_BOOTSTRAP_DDR2) {
+		/* AHB maximum timeout */
+		writel(0xfffff, regs + AR933X_DDR_REG_TIMEOUT_MAX);
+
+		/* Enable DDR2 */
+		writel(DDR2_CONF_VAL, regs + AR933X_DDR_REG_DDR2_CONFIG);
+
+		/* Precharge All */
+		writel(DDR_CTRL_PRECHARGE, regs + AR71XX_DDR_REG_CONTROL);
+
+		/* Disable High Temperature Self-Refresh, Full Array */
+		writel(0x00, regs + AR933X_DDR_REG_EMR2);
+		/* Extended Mode Register 2 Set (EMR2S) */
+		writel(DDR_CTRL_UPD_EMR2S, regs + AR71XX_DDR_REG_CONTROL);
+
+		writel(0x00, regs + AR933X_DDR_REG_EMR3);
+		/* Extended Mode Register 3 Set (EMR3S) */
+		writel(DDR_CTRL_UPD_EMR3S, regs + AR71XX_DDR_REG_CONTROL);
+
+		/* Enable DLL,  Full strength, ODT Disabled */
+		writel(0x00, regs + AR71XX_DDR_REG_EMR);
+		/* Extended Mode Register Set (EMRS) */

arch/mips/mach-ath79/ar933x/ddr.c line 144

Quoted 6 lines

arch/mips/mach-ath79/ar933x/ddr.c new file +6 -0

+		writel(DDR_CTRL_UPD_EMRS, regs + AR71XX_DDR_REG_CONTROL);
+
+		/* Reset DLL */
+		writel(DDR2_MODE_DLL_VAL, regs + AR71XX_DDR_REG_MODE);
+		/* Mode Register Set (MRS) */
+		writel(DDR_CTRL_UPD_MRS, regs + AR71XX_DDR_REG_CONTROL);

Make sure that there is at least a newline before comment, to improve the readability of the code.

arch/mips/mach-ath79/ar933x/ddr.c line 154

Quoted 9 lines

arch/mips/mach-ath79/ar933x/ddr.c new file +9 -0

+		/* Precharge All */
+		writel(DDR_CTRL_PRECHARGE, regs + AR71XX_DDR_REG_CONTROL);
+
+		/* Auto Refresh */
+		writel(DDR_CTRL_AUTO_REFRESH, regs + AR71XX_DDR_REG_CONTROL);
+		writel(DDR_CTRL_AUTO_REFRESH, regs + AR71XX_DDR_REG_CONTROL);
+
+		/* Write recovery (WR) 6 clock, CAS Latency 3,
+		 * Burst Length 8 */

Fix the multiline comments please.

Quoted 9 lines

arch/mips/mach-ath79/ar933x/ddr.c new file +9 -0

+		writel(DDR2_MODE_VAL, regs + AR71XX_DDR_REG_MODE);
+		/* Mode Register Set (MRS) */
+		writel(DDR_CTRL_UPD_MRS, regs + AR71XX_DDR_REG_CONTROL);
+
+		/* Enable OCD defaults, Enable DLL,
+		 * Reduced Drive Strength */
+		writel(DDR2_EXT_MODE_OCD_VAL, regs + AR71XX_DDR_REG_EMR);
+		/* Extended Mode Register Set (EMRS) */
+		writel(DDR_CTRL_UPD_EMRS, regs + AR71XX_DDR_REG_CONTROL);

[...]

arch/mips/mach-ath79/ar933x/ddr.c line 237

Quoted 9 lines

arch/mips/mach-ath79/ar933x/ddr.c new file +9 -0

+void ddr_tap_tuning(void)
+{
+	void __iomem *regs;
+	u32 *addr_k0, *addr_k1, *addr;
+	u32 val, tap, upper, lower;
+	int i, j, dir, err, done;
+
+	regs = map_physmem(AR71XX_DDR_CTRL_BASE, AR71XX_DDR_CTRL_SIZE,
+			   MAP_NOCACHE);

Explanation of this code would be great. To an external reviewer, this is entirely inobvious.

Quoted 78 lines

arch/mips/mach-ath79/ar933x/ddr.c new file +78 -0

+	addr = (void *)CKSEG0ADDR(0x2000);
+	for (i = 0; i < 256; i++) {
+		val = 0;
+		for (j = 0; j < 8; j++) {
+			if (i & (1 << j)) {
+				if (j % 2)
+					val |= 0xffff0000;
+				else
+					val |= 0x0000ffff;
+			}
+
+			if (j % 2) {
+				*addr++ = val;
+				val = 0;
+			}
+		}
+	}
+
+	err = 0;
+	done = 0;
+	dir = 1;
+	tap = readl(regs + AR71XX_DDR_REG_TAP_CTRL0);
+	val = tap;
+	while (!done) {
+		err = 0;
+		writel(val, regs + AR71XX_DDR_REG_TAP_CTRL0);
+		writel(val, regs + AR71XX_DDR_REG_TAP_CTRL1);
+		for (i = 0; i < 2; i++) {
+			addr_k1 = (void *)CKSEG1ADDR(0x2000);
+			addr_k0 = (void *)CKSEG0ADDR(0x2000);
+			addr = (void *)CKSEG0ADDR(0x3000);
+
+			while (addr_k0 < addr) {
+				if (*addr_k1++ != *addr_k0++) {
+					err = 1;
+					break;
+				}
+			}
+
+			if (err)
+				break;
+		}
+
+		if (err) {
+			if (dir) {
+				dir = 0;
+				val--;
+				upper = val;
+				val = tap;
+			} else {
+				val++;
+				lower = val;
+				done = 1;
+			}
+		} else {
+			if (dir) {
+				if (val < 0x20) {
+					val++;
+				} else {
+					dir = 0;
+					upper = val;
+					val = tap;
+				}
+			} else {
+				if (!val) {
+					lower = val;
+					done = 1;
+				} else {
+					val--;
+				}
+			}
+		}
+	}
+	val = (upper + lower) / 2;
+	writel(val, regs + AR71XX_DDR_REG_TAP_CTRL0);
+	val++;
+	writel(val, regs + AR71XX_DDR_REG_TAP_CTRL1);
+}

[...]

Quoted 5 lines · Marek Vasut

Quoted 1 line · Wills Wang

This patch enable work for ar933x SOC.

And it adds DDR code and clock code ... which is missing from the commit message.

These code was split in v5, the commit message before v5 was placed in patch 1/7.

This patch enable work for qca953x SOC.

Signed-off-by Wills Wang <[email protected]>

---

Changes in v7:
- Use CKSEGxADDR instead of KSEGxADDR for qca953x

Changes in v6: None
Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2: None

arch/mips/mach-ath79/qca953x/clk.c new file +6 -0

+	regs = map_physmem(AR71XX_PLL_BASE, AR71XX_PLL_SIZE,
+			   MAP_NOCACHE);
+
+	xtal = qca953x_get_xtal();
+	ctrl = readl(regs + QCA953X_PLL_CLK_CTRL_REG);
+	val = readl(regs + QCA953X_PLL_CPU_CONFIG_REG);

arch/mips/mach-ath79/qca953x/ddr.c new file +28 -0

+	regs = map_physmem(AR71XX_DDR_CTRL_BASE, AR71XX_DDR_CTRL_SIZE,
+			   MAP_NOCACHE);
+	val = get_bootstrap();
+	if (val & QCA953X_BOOTSTRAP_DDR1) {
+		writel(DDR_CTL_CONFIG_VAL, regs + QCA953X_DDR_REG_CTL_CONF);
+		udelay(10);
+
+		/* For 16-bit DDR */
+		writel(0xffff, regs + AR71XX_DDR_REG_RD_CYCLE);
+		udelay(100);
+
+		/* Burst size */
+		writel(DDR_BURST_VAL, regs + QCA953X_DDR_REG_BURST);
+		udelay(100);
+		writel(DDR_BURST2_VAL, regs + QCA953X_DDR_REG_BURST2);
+		udelay(100);
+
+		/* AHB maximum timeout */
+		writel(0xfffff, regs + QCA953X_DDR_REG_TIMEOUT_MAX);
+		udelay(100);
+
+		/* DRAM timing */
+		writel(DDR1_CONF_REG_VAL, regs + AR71XX_DDR_REG_CONFIG);
+		udelay(100);
+		writel(DDR1_CONF2_REG_VAL, regs + AR71XX_DDR_REG_CONFIG2);
+		udelay(100);
+		writel(DDR1_CONF3_REG_VAL, regs + QCA953X_DDR_REG_CONFIG3);
+		udelay(100);

Quoted 13 lines · Wills Wang

This patch enable work for qca953x SOC.

Signed-off-by Wills Wang <[email protected]>

---

Changes in v7:
- Use CKSEGxADDR instead of KSEGxADDR for qca953x

Changes in v6: None
Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2: None

[...]

arch/mips/mach-ath79/qca953x/clk.c line 35

Quoted 9 lines

arch/mips/mach-ath79/qca953x/clk.c new file +9 -0

+int get_serial_clock(void)
+{
+	return qca953x_get_xtal();
+}
+
+int get_clocks(void)
+{
+	void __iomem *regs;
+	u32 val, ctrl, xtal, pll, div;

This looks like a copy of the same code in patch 2/7 .

Quoted 6 lines

arch/mips/mach-ath79/qca953x/clk.c new file +6 -0

+	regs = map_physmem(AR71XX_PLL_BASE, AR71XX_PLL_SIZE,
+			   MAP_NOCACHE);
+
+	xtal = qca953x_get_xtal();
+	ctrl = readl(regs + QCA953X_PLL_CLK_CTRL_REG);
+	val = readl(regs + QCA953X_PLL_CPU_CONFIG_REG);

[...]

arch/mips/mach-ath79/qca953x/ddr.c line 224

Quoted 4 lines

arch/mips/mach-ath79/qca953x/ddr.c new file +4 -0

+void ddr_init(void)
+{
+	void __iomem *regs;
+	u32 val;

This looks like a copy of the same code in patch 2/7 .

Quoted 28 lines

arch/mips/mach-ath79/qca953x/ddr.c new file +28 -0

+	regs = map_physmem(AR71XX_DDR_CTRL_BASE, AR71XX_DDR_CTRL_SIZE,
+			   MAP_NOCACHE);
+	val = get_bootstrap();
+	if (val & QCA953X_BOOTSTRAP_DDR1) {
+		writel(DDR_CTL_CONFIG_VAL, regs + QCA953X_DDR_REG_CTL_CONF);
+		udelay(10);
+
+		/* For 16-bit DDR */
+		writel(0xffff, regs + AR71XX_DDR_REG_RD_CYCLE);
+		udelay(100);
+
+		/* Burst size */
+		writel(DDR_BURST_VAL, regs + QCA953X_DDR_REG_BURST);
+		udelay(100);
+		writel(DDR_BURST2_VAL, regs + QCA953X_DDR_REG_BURST2);
+		udelay(100);
+
+		/* AHB maximum timeout */
+		writel(0xfffff, regs + QCA953X_DDR_REG_TIMEOUT_MAX);
+		udelay(100);
+
+		/* DRAM timing */
+		writel(DDR1_CONF_REG_VAL, regs + AR71XX_DDR_REG_CONFIG);
+		udelay(100);
+		writel(DDR1_CONF2_REG_VAL, regs + AR71XX_DDR_REG_CONFIG2);
+		udelay(100);
+		writel(DDR1_CONF3_REG_VAL, regs + QCA953X_DDR_REG_CONFIG3);
+		udelay(100);

[...]

Quoted 17 lines · Marek Vasut

Quoted 13 lines · Wills Wang

This patch enable work for qca953x SOC.

Signed-off-by Wills Wang <[email protected]>

---

Changes in v7:
- Use CKSEGxADDR instead of KSEGxADDR for qca953x

Changes in v6: None
Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2: None

[...]

Quoted 11 lines

arch/mips/mach-ath79/qca953x/clk.c line 35

Quoted 9 lines

arch/mips/mach-ath79/qca953x/clk.c new file +9 -0

+int get_serial_clock(void)
+{
+	return qca953x_get_xtal();
+}
+
+int get_clocks(void)
+{
+	void __iomem *regs;
+	u32 val, ctrl, xtal, pll, div;

This looks like a copy of the same code in patch 2/7 .

There are different in detail.

Quoted 9 lines

Quoted 6 lines

arch/mips/mach-ath79/qca953x/clk.c new file +6 -0

+	regs = map_physmem(AR71XX_PLL_BASE, AR71XX_PLL_SIZE,
+			   MAP_NOCACHE);
+
+	xtal = qca953x_get_xtal();
+	ctrl = readl(regs + QCA953X_PLL_CLK_CTRL_REG);
+	val = readl(regs + QCA953X_PLL_CPU_CONFIG_REG);

[...]

Quoted 6 lines

arch/mips/mach-ath79/qca953x/ddr.c line 224

Quoted 4 lines

arch/mips/mach-ath79/qca953x/ddr.c new file +4 -0

+void ddr_init(void)
+{
+	void __iomem *regs;
+	u32 val;

This looks like a copy of the same code in patch 2/7 .

There are different in detail, the bit fields of register are not identical copies of one another.

there is no way to extract a common code.

Quoted 30 lines

Quoted 28 lines

arch/mips/mach-ath79/qca953x/ddr.c new file +28 -0

+	regs = map_physmem(AR71XX_DDR_CTRL_BASE, AR71XX_DDR_CTRL_SIZE,
+			   MAP_NOCACHE);
+	val = get_bootstrap();
+	if (val & QCA953X_BOOTSTRAP_DDR1) {
+		writel(DDR_CTL_CONFIG_VAL, regs + QCA953X_DDR_REG_CTL_CONF);
+		udelay(10);
+
+		/* For 16-bit DDR */
+		writel(0xffff, regs + AR71XX_DDR_REG_RD_CYCLE);
+		udelay(100);
+
+		/* Burst size */
+		writel(DDR_BURST_VAL, regs + QCA953X_DDR_REG_BURST);
+		udelay(100);
+		writel(DDR_BURST2_VAL, regs + QCA953X_DDR_REG_BURST2);
+		udelay(100);
+
+		/* AHB maximum timeout */
+		writel(0xfffff, regs + QCA953X_DDR_REG_TIMEOUT_MAX);
+		udelay(100);
+
+		/* DRAM timing */
+		writel(DDR1_CONF_REG_VAL, regs + AR71XX_DDR_REG_CONFIG);
+		udelay(100);
+		writel(DDR1_CONF2_REG_VAL, regs + AR71XX_DDR_REG_CONFIG2);
+		udelay(100);
+		writel(DDR1_CONF3_REG_VAL, regs + QCA953X_DDR_REG_CONFIG3);
+		udelay(100);

[...]

Reviewed-by Thomas Chou <[email protected]>

Signed-off-by Wills Wang <[email protected]>

---

Changes in v7:
- remove map_physmem for debug port

Changes in v6:
- Remove wait loop in putc and getc
- Use map_physmem instead of KSEG1ADDR

Changes in v5:
- remove ar933x_serial_platdata
- Import document "qca,ar9330-uart.txt" from kernel
- Add support for debug UART

Changes in v4:
- Auto calculate baudrate for serial driver
- Move pinctrl code in serial driver into arch/mips/mach-ath79
- Use get_serial_clock to serial clock source

Changes in v3:
- Convert serial driver to driver model

Changes in v2:
- Move serial driver code into drivers/serial

 .../serial/qca,ar9330-uart.txt                     |  24 ++
 drivers/serial/Kconfig                             |  17 ++
 drivers/serial/Makefile                            |   1 +
 drivers/serial/serial_ar933x.c                     | 254
+++++++++++++++++++++
 4 files changed, 296 insertions(+)
 create mode 100644 doc/device-tree-bindings/serial/qca,ar9330

(quoted diff) +0 -1

-uart.txt
 create mode 100644 drivers/serial/serial_ar933x.c

doc/device-tree-bindings/serial/qca,ar9330-uart.txt new file +24 -0

new file mode 100644
index 0000000..ec576a1
@@ -0,0 +1,24 @@
+* Qualcomm Atheros AR9330 High-Speed UART
+
+Required properties:
+
+- compatible: Must be "qca,ar9330-uart"
+
+- reg: Specifies the physical base address of the controller and
+  the length of the memory mapped region.
+
+Additional requirements:
+
+  Each UART port must have an alias correctly numbered in "aliases"
+  node.
+
+Example:
+
+	aliases {
+		serial0 = &uart0;
+	};
+
+	uart0: uart at 18020000 {
+		compatible = "qca,ar9330-uart";
+		reg = <0x18020000 0x14>;
+	};

drivers/serial/Kconfig +0 -0

index 1fc287e..f147379 100644
@@ -69,6 +69,14 @@ config DEBUG_UART_ALTERA_UART
 	  You will need to provide parameters to make this work. The

driver will
be available until the real driver model serial is
running.

drivers/serial/Kconfig +2 -0

+	help
+	  Select this to enable a debug UART using the ar933x uart

driver.

drivers/serial/Kconfig +2 -0

+	  You will need to provide parameters to make this work. The
+	  driver will be available until the real driver model

serial is

drivers/serial/Kconfig +2 -0

+	  running.
+
 config DEBUG_UART_NS16550
 	bool "ns16550"
 	help

@@ -186,6 +194,15 @@ config ALTERA_UART
 	  Select this to enable an UART for Altera devices. Please

find
details on the "Embedded Peripherals IP User Guide" of
Altera.

drivers/serial/Kconfig +3 -0

+	help
+	  Select this to enable UART support for QCA/Atheros ar933x
+	  devices. This driver uses driver model and requires a

device

drivers/serial/Kconfig +3 -0

+	  tree binding to operate, please refer to the document at
+	  doc/device-tree-bindings/serial/qca,ar9330-uart.txt.
+
 config SYS_NS16550
 	bool "NS16550 UART or compatible"
 	help

drivers/serial/Makefile +1 -0

index dd87147..b7b82ae 100644
@@ -17,6 +17,7 @@ endif
 
 obj-$(CONFIG_ALTERA_UART) += altera_uart.o
 obj-$(CONFIG_ALTERA_JTAG_UART) += altera_jtag_uart.o
+obj-$(CONFIG_AR933X_UART) += serial_ar933x.o
 obj-$(CONFIG_ARM_DCC) += arm_dcc.o
 obj-$(CONFIG_ATMEL_USART) += atmel_usart.o
 obj-$(CONFIG_EFI_APP) += serial_efi.o

drivers/serial/serial_ar933x.c new file +39 -0

new file mode 100644
index 0000000..ccba2f5
@@ -0,0 +1,254 @@
+/*
+ * Copyright (C) 2015-2016 Wills Wang <[email protected]>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <div64.h>
+#include <errno.h>
+#include <serial.h>
+#include <asm/io.h>
+#include <asm/addrspace.h>
+#include <asm/types.h>
+#include <mach/ar71xx_regs.h>
+
+#define AR933X_UART_DATA_REG            0x00
+#define AR933X_UART_CS_REG              0x04
+#define AR933X_UART_CLK_REG             0x08
+
+#define AR933X_UART_DATA_TX_RX_MASK     0xff
+#define AR933X_UART_DATA_RX_CSR         BIT(8)
+#define AR933X_UART_DATA_TX_CSR         BIT(9)
+#define AR933X_UART_CS_IF_MODE_S        2
+#define AR933X_UART_CS_IF_MODE_M        0x3
+#define AR933X_UART_CS_IF_MODE_DTE      1
+#define AR933X_UART_CS_IF_MODE_DCE      2
+#define AR933X_UART_CS_TX_RDY_ORIDE     BIT(7)
+#define AR933X_UART_CS_RX_RDY_ORIDE     BIT(8)
+#define AR933X_UART_CLK_STEP_M          0xffff
+#define AR933X_UART_CLK_SCALE_M         0xfff
+#define AR933X_UART_CLK_SCALE_S         16
+#define AR933X_UART_CLK_STEP_S          0
+
+struct ar933x_serial_priv {
+	void __iomem *regs;
+};
+
+static inline u32 ar933x_serial_read(struct udevice *dev, u32

offset)

drivers/serial/serial_ar933x.c new file +42 -0

+{
+	struct ar933x_serial_priv *priv = dev_get_priv(dev);
+
+	return readl(priv->regs + offset);
+}
+
+static inline void ar933x_serial_write(struct udevice *dev,
+				       u32 val, u32 offset)
+{
+	struct ar933x_serial_priv *priv = dev_get_priv(dev);
+
+	writel(val, priv->regs + offset);
+}
+
+/*
+ * baudrate = (clk / (scale + 1)) * (step * (1 / 2^17))
+ */
+static u32 ar933x_serial_get_baud(u32 clk, u32 scale, u32 step)
+{
+	u64 t;
+	u32 div;
+
+	div = (2 << 16) * (scale + 1);
+	t = clk;
+	t *= step;
+	t += (div / 2);
+	do_div(t, div);
+
+	return t;
+}
+
+static void ar933x_serial_get_scale_step(u32 clk, u32 baud,
+					 u32 *scale, u32 *step)
+{
+	u32 tscale, baudrate;
+	long min_diff;
+
+	*scale = 0;
+	*step = 0;
+
+	min_diff = baud;
+	for (tscale = 0; tscale < AR933X_UART_CLK_SCALE_M; tscale++)

{

drivers/serial/serial_ar933x.c new file +11 -0

+		u64 tstep;
+		int diff;
+
+		tstep = baud * (tscale + 1);
+		tstep *= (2 << 16);
+		do_div(tstep, clk);
+
+		if (tstep > AR933X_UART_CLK_STEP_M)
+			break;
+
+		baudrate = ar933x_serial_get_baud(clk, tscale,

tstep);

drivers/serial/serial_ar933x.c new file +87 -0

+		diff = abs(baudrate - baud);
+		if (diff < min_diff) {
+			min_diff = diff;
+			*scale = tscale;
+			*step = tstep;
+		}
+	}
+}
+
+static int ar933x_serial_setbrg(struct udevice *dev, int baudrate)
+{
+	u32 val, scale, step;
+
+	val = get_serial_clock();
+	ar933x_serial_get_scale_step(val, baudrate, &scale, &step);
+
+	val  = (scale & AR933X_UART_CLK_SCALE_M)
+			<< AR933X_UART_CLK_SCALE_S;
+	val |= (step & AR933X_UART_CLK_STEP_M)
+			<< AR933X_UART_CLK_STEP_S;
+	ar933x_serial_write(dev, val, AR933X_UART_CLK_REG);
+
+	return 0;
+}
+
+static int ar933x_serial_putc(struct udevice *dev, const char c)
+{
+	u32 data;
+
+	data = ar933x_serial_read(dev, AR933X_UART_DATA_REG);
+	if (!(data & AR933X_UART_DATA_TX_CSR))
+		return -EAGAIN;
+
+	data  = (u32)c | AR933X_UART_DATA_TX_CSR;
+	ar933x_serial_write(dev, data, AR933X_UART_DATA_REG);
+
+	return 0;
+}
+
+static int ar933x_serial_getc(struct udevice *dev)
+{
+	u32 data;
+
+	data = ar933x_serial_read(dev, AR933X_UART_DATA_REG);
+	if (!(data & AR933X_UART_DATA_RX_CSR))
+		return -EAGAIN;
+
+	ar933x_serial_write(dev, AR933X_UART_DATA_RX_CSR,
+			    AR933X_UART_DATA_REG);
+	return data & AR933X_UART_DATA_TX_RX_MASK;
+}
+
+static int ar933x_serial_pending(struct udevice *dev, bool input)
+{
+	u32 data;
+
+	data = ar933x_serial_read(dev, AR933X_UART_DATA_REG);
+	if (input)
+		return (data & AR933X_UART_DATA_RX_CSR) ? 1 : 0;
+	else
+		return (data & AR933X_UART_DATA_TX_CSR) ? 0 : 1;
+}
+
+static int ar933x_serial_probe(struct udevice *dev)
+{
+	struct ar933x_serial_priv *priv = dev_get_priv(dev);
+	u32 val;
+	fdt_addr_t addr;
+
+	addr = dev_get_addr(dev);
+	if (addr == FDT_ADDR_T_NONE)
+		return -EINVAL;
+
+	priv->regs = map_physmem(addr,
+				 AR933X_UART_SIZE,
+				 MAP_NOCACHE);
+
+	/*
+	 * UART controller configuration:
+	 * - no DMA
+	 * - no interrupt
+	 * - DCE mode
+	 * - no flow control
+	 * - set RX ready oride
+	 * - set TX ready oride
+	 */
+	val = (AR933X_UART_CS_IF_MODE_DCE <<

AR933X_UART_CS_IF_MODE_S) |

drivers/serial/serial_ar933x.c new file +1 -0

+	      AR933X_UART_CS_TX_RDY_ORIDE |

AR933X_UART_CS_RX_RDY_ORIDE;

drivers/serial/serial_ar933x.c new file +45 -0

+	ar933x_serial_write(dev, val, AR933X_UART_CS_REG);
+	return 0;
+}
+
+static const struct dm_serial_ops ar933x_serial_ops = {
+	.putc = ar933x_serial_putc,
+	.pending = ar933x_serial_pending,
+	.getc = ar933x_serial_getc,
+	.setbrg = ar933x_serial_setbrg,
+};
+
+static const struct udevice_id ar933x_serial_ids[] = {
+	{ .compatible = "qca,ar9330-uart" },
+	{ }
+};
+
+U_BOOT_DRIVER(serial_ar933x) = {
+	.name   = "serial_ar933x",
+	.id = UCLASS_SERIAL,
+	.of_match = ar933x_serial_ids,
+	.priv_auto_alloc_size = sizeof(struct ar933x_serial_priv),
+	.probe = ar933x_serial_probe,
+	.ops    = &ar933x_serial_ops,
+	.flags = DM_FLAG_PRE_RELOC,
+};
+
+#ifdef CONFIG_DEBUG_UART_AR933X
+
+#include <debug_uart.h>
+
+static inline void _debug_uart_init(void)
+{
+	void __iomem *regs = (void *)CONFIG_DEBUG_UART_BASE;
+	u32 val, scale, step;
+
+	/*
+	 * UART controller configuration:
+	 * - no DMA
+	 * - no interrupt
+	 * - DCE mode
+	 * - no flow control
+	 * - set RX ready oride
+	 * - set TX ready oride
+	 */
+	val = (AR933X_UART_CS_IF_MODE_DCE <<

AR933X_UART_CS_IF_MODE_S) |

drivers/serial/serial_ar933x.c new file +1 -0

+	      AR933X_UART_CS_TX_RDY_ORIDE |

AR933X_UART_CS_RX_RDY_ORIDE;

drivers/serial/serial_ar933x.c new file +4 -0

+	writel(val, regs + AR933X_UART_CS_REG);
+
+	ar933x_serial_get_scale_step(CONFIG_DEBUG_UART_CLOCK,
+				     CONFIG_BAUDRATE, &scale,

&step);

drivers/serial/serial_ar933x.c new file +24 -0

+
+	val  = (scale & AR933X_UART_CLK_SCALE_M)
+			<< AR933X_UART_CLK_SCALE_S;
+	val |= (step & AR933X_UART_CLK_STEP_M)
+			<< AR933X_UART_CLK_STEP_S;
+	writel(val, regs + AR933X_UART_CLK_REG);
+}
+
+static inline void _debug_uart_putc(int c)
+{
+	void __iomem *regs = (void *)CONFIG_DEBUG_UART_BASE;
+	u32 data;
+
+	do {
+		data = readl(regs + AR933X_UART_DATA_REG);
+	} while (!(data & AR933X_UART_DATA_TX_CSR));
+
+	data  = (u32)c | AR933X_UART_DATA_TX_CSR;
+	writel(data, regs + AR933X_UART_DATA_REG);
+}
+
+DEBUG_UART_FUNCS
+
+#endif

Reviewed-by Thomas Chou <[email protected]>

Signed-off-by Wills Wang <[email protected]>

---

Changes in v7:
- remove map_physmem for debug port

Changes in v6:
- Remove wait loop in putc and getc
- Use map_physmem instead of KSEG1ADDR

Changes in v5:
- remove ar933x_serial_platdata
- Import document "qca,ar9330-uart.txt" from kernel
- Add support for debug UART

Changes in v4:
- Auto calculate baudrate for serial driver
- Move pinctrl code in serial driver into arch/mips/mach-ath79
- Use get_serial_clock to serial clock source

Changes in v3:
- Convert serial driver to driver model

Changes in v2:
- Move serial driver code into drivers/serial

 .../serial/qca,ar9330-uart.txt                     |  24 ++
 drivers/serial/Kconfig                             |  17 ++
 drivers/serial/Makefile                            |   1 +
 drivers/serial/serial_ar933x.c                     | 254 +++++++++++++++++++++
 4 files changed, 296 insertions(+)
 create mode 100644 doc/device-tree-bindings/serial/qca,ar9330-uart.txt
 create mode 100644 drivers/serial/serial_ar933x.c

Reviewed-by Thomas Chou <[email protected]>

Signed-off-by Wills Wang <[email protected]>

---

Changes in v7:
- Define spi_cs_activate/spi_cs_deactivate
- Rename MHZ to ATH79_SPI_MHZ
- Use clrsetbits_32

Changes in v6:
- Add rrw_delay in ath79_spi_priv for more accurate timing
- Remove ath79_spi_delay
- Calculate delay in ath79_spi_set_speed

Changes in v5:
- remove ar933x_spi_platdata
- Import document "spi-ath79.txt" from kernel
- Add delay for bitbang operation

Changes in v4:
- Use get_bus_freq instead of hardcode in SPI driver

Changes in v3:
- Convert spi driver to driver model

Changes in v2:
- Add a compatible spi driver

 doc/device-tree-bindings/spi/spi-ath79.txt |  19 +++
 drivers/spi/Kconfig                        |   8 +
 drivers/spi/Makefile                       |   1 +
 drivers/spi/ath79_spi.c                    | 237
+++++++++++++++++++++++++++++
 4 files changed, 265 insertions(+)
 create mode 100644 doc/device-tree-bindings/spi/spi-ath79.txt
 create mode 100644 drivers/spi/ath79_spi.c

doc/device renamed from doc/device-tree-bindings/spi/spi-ath79.txt +0 -1

-tree-bindings/spi/spi-ath79.txt

new file mode 100644
index 0000000..3fd9d67

doc/device-tree-bindings/spi/spi-ath79.txt new file +4 -0

@@ -0,0 +1,19 @@
+Binding for Qualcomm Atheros AR7xxx/AR9xxx SPI controller
+
+Required properties:
+- compatible: has to be "qca,<soc-type>-spi", "qca,ar7100-spi" as

fallback.

+- reg: Base address and size of the controllers memory area
+- #address-cells: <1>, as required by generic SPI binding.
+- #size-cells: <0>, also as required by generic SPI binding.

doc/device-tree-bindings/spi/spi-ath79.txt new file +12 -0

+
+Child nodes as per the generic SPI binding.
+
+Example:
+
+	spi at 1f000000 {
+		compatible = "qca,ar9132-spi", "qca,ar7100-spi";
+		reg = <0x1f000000 0x10>;
+
+		#address-cells = <1>;
+		#size-cells = <0>;
+	};

drivers/spi/Kconfig +0 -0

index 2cdb110..0ab2741 100644
@@ -23,6 +23,14 @@ config ALTERA_SPI
 	  IP core. Please find details on the "Embedded Peripherals

IP

drivers/spi/Kconfig +2 -0

+	help
+	  Enable the Atheros ar7xxx/ar9xxx SoC SPI driver, it was

used

drivers/spi/Kconfig +1 -0

+	  to access SPI NOR flash and other SPI peripherals. This

driver

drivers/spi/Kconfig +1 -0

+	  uses driver model and requires a device tree binding to

operate.

drivers/spi/Kconfig +2 -1

+	  please refer to doc/device-tree-bindings/spi/spi
-ath79.txt.
+
 config CADENCE_QSPI
 	bool "Cadence QSPI driver"
 	help

drivers/spi/Makefile +1 -0

index 3eca745..7fb2926 100644
@@ -17,6 +17,7 @@ endif
 
 obj-$(CONFIG_ALTERA_SPI) += altera_spi.o
 obj-$(CONFIG_ARMADA100_SPI) += armada100_spi.o
+obj-$(CONFIG_ATH79_SPI) += ath79_spi.o
 obj-$(CONFIG_ATMEL_DATAFLASH_SPI) += atmel_dataflash_spi.o
 obj-$(CONFIG_ATMEL_SPI) += atmel_spi.o
 obj-$(CONFIG_BFIN_SPI) += bfin_spi.o

drivers/spi/ath79_spi.c new file +28 -0

new file mode 100644
index 0000000..568548f
@@ -0,0 +1,237 @@
+/*
+ * Copyright (C) 2015-2016 Wills Wang <[email protected]>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <spi.h>
+#include <dm.h>
+#include <div64.h>
+#include <errno.h>
+#include <asm/io.h>
+#include <asm/addrspace.h>
+#include <asm/types.h>
+#include <mach/ar71xx_regs.h>
+
+/* CLOCK_DIVIDER = 3 (SPI clock = 200 / 8 ~ 25 MHz) */
+#define ATH79_SPI_CLK_DIV(x)           (((x) >> 1) - 1)
+#define ATH79_SPI_RRW_DELAY_FACTOR     12000
+#define ATH79_SPI_MHZ                  (1000 * 1000)
+
+struct ath79_spi_priv {
+	void __iomem *regs;
+	u32 rrw_delay;
+};
+
+static inline u32 ath79_spi_read(struct udevice *bus, u32 offset)
+{

drivers/spi/ath79_spi.c new file +3 -0

+
+	ath79_spi_write(bus, AR71XX_SPI_FS_GPIO, AR71XX_SPI_REG_FS);
+	ath79_spi_write(bus, AR71XX_SPI_IOC_CS_ALL,

AR71XX_SPI_REG_IOC);

drivers/spi/ath79_spi.c new file +7 -0

+}
+
+static void spi_cs_deactivate(struct udevice *dev)
+{
+	struct udevice *bus = dev->parent;
+
+	ath79_spi_write(bus, AR71XX_SPI_IOC_CS_ALL,

AR71XX_SPI_REG_IOC);

drivers/spi/ath79_spi.c new file +19 -0

+	ath79_spi_write(bus, 0, AR71XX_SPI_REG_FS);
+}
+
+static int ath79_spi_claim_bus(struct udevice *dev)
+{
+	return 0;
+}
+
+static int ath79_spi_release_bus(struct udevice *dev)
+{
+	return 0;
+}
+
+static int ath79_spi_xfer(struct udevice *dev, unsigned int bitlen,
+		const void *dout, void *din, unsigned long flags)
+{
+	struct udevice *bus = dev->parent;
+	struct ath79_spi_priv *priv = dev_get_priv(bus);
+	struct dm_spi_slave_platdata *slave =

dev_get_parent_platdata(dev);

drivers/spi/ath79_spi.c new file +29 -1

+	u8 *rx = din;
+	const u8 *tx = dout;
+	u8 curbyte, curbitlen, restbits;
+	u32 bytes = bitlen / 8;
+	u32 out, in;
+	u64 tick;
+
+	if (flags & SPI_XFER_BEGIN)
+		spi_cs_activate(dev);
+
+	restbits = (bitlen % 8);
+	if (restbits)
+		bytes++;
+
+	out = AR71XX_SPI_IOC_CS_ALL & ~(AR71XX_SPI_IOC_CS(slave
->cs));
+	while (bytes > 0) {
+		bytes--;
+		curbyte = 0;
+		if (tx)
+			curbyte = *tx++;
+
+		if (restbits && !bytes) {
+			curbitlen = restbits;
+			curbyte <<= 8 - restbits;
+		} else {
+			curbitlen = 8;
+		}
+
+		for (curbyte <<= (8 - curbitlen); curbitlen;

curbitlen--) {

drivers/spi/ath79_spi.c new file +6 -0

+			if (curbyte & 0x80)
+				out |= AR71XX_SPI_IOC_DO;
+			else
+				out &= ~(AR71XX_SPI_IOC_DO);
+
+			ath79_spi_write(bus, out,

AR71XX_SPI_REG_IOC);

drivers/spi/ath79_spi.c new file +9 -1

+
+			/* delay for low level */
+			if (priv->rrw_delay) {
+				tick = get_ticks() + priv
->rrw_delay;
+				while (get_ticks() < tick)
+					/*NOP*/;
+			}
+
+			ath79_spi_write(bus, out |

AR71XX_SPI_IOC_CLK,

drivers/spi/ath79_spi.c new file +14 -1

+					AR71XX_SPI_REG_IOC);
+
+			/* delay for high level */
+			if (priv->rrw_delay) {
+				tick = get_ticks() + priv
->rrw_delay;
+				while (get_ticks() < tick)
+					/*NOP*/;
+			}
+
+			curbyte <<= 1;
+		}
+
+		if (!bytes)
+			ath79_spi_write(bus, out,

AR71XX_SPI_REG_IOC);

drivers/spi/ath79_spi.c new file +45 -0

+
+		in = ath79_spi_read(bus, AR71XX_SPI_REG_RDS);
+		if (rx) {
+			if (restbits && !bytes)
+				*rx++ = (in << (8 - restbits));
+			else
+				*rx++ = in;
+		}
+	}
+
+	if (flags & SPI_XFER_END)
+		spi_cs_deactivate(dev);
+
+	return 0;
+}
+
+
+static int ath79_spi_set_speed(struct udevice *bus, uint speed)
+{
+	struct ath79_spi_priv *priv = dev_get_priv(bus);
+	u32 val, div = 0;
+	u64 time;
+
+	if (speed)
+		div = get_bus_freq(0) / speed;
+
+	if (div > 63)
+		div = 63;
+
+	if (div < 5)
+		div = 5;
+
+	/* calculate delay */
+	time = get_tbclk();
+	do_div(time, speed / 2);
+	val = get_bus_freq(0) / ATH79_SPI_MHZ;
+	val = ATH79_SPI_RRW_DELAY_FACTOR / val;
+	if (time > val)
+		priv->rrw_delay = time - val + 1;
+	else
+		priv->rrw_delay = 0;
+
+	ath79_spi_write(bus, AR71XX_SPI_FS_GPIO, AR71XX_SPI_REG_FS);
+	clrsetbits_32(priv->regs + AR71XX_SPI_REG_CTRL,
+		      AR71XX_SPI_CTRL_DIV_MASK,

ATH79_SPI_CLK_DIV(div));

drivers/spi/ath79_spi.c new file +25 -0

+	ath79_spi_write(bus, 0, AR71XX_SPI_REG_FS);
+	return 0;
+}
+
+static int ath79_spi_set_mode(struct udevice *bus, uint mode)
+{
+	return 0;
+}
+
+static int ath79_spi_probe(struct udevice *bus)
+{
+	struct ath79_spi_priv *priv = dev_get_priv(bus);
+	fdt_addr_t addr;
+
+	addr = dev_get_addr(bus);
+	if (addr == FDT_ADDR_T_NONE)
+		return -EINVAL;
+
+	priv->regs = map_physmem(addr,
+				 AR71XX_SPI_SIZE,
+				 MAP_NOCACHE);
+
+	/* Init SPI Hardware, disable remap, set clock */
+	ath79_spi_write(bus, AR71XX_SPI_FS_GPIO, AR71XX_SPI_REG_FS);
+	ath79_spi_write(bus, AR71XX_SPI_CTRL_RD |

ATH79_SPI_CLK_DIV(8),

drivers/spi/ath79_spi.c new file +38 -0

+			AR71XX_SPI_REG_CTRL);
+	ath79_spi_write(bus, 0, AR71XX_SPI_REG_FS);
+
+	return 0;
+}
+
+static int ath79_cs_info(struct udevice *bus, uint cs,
+			   struct spi_cs_info *info)
+{
+	/* Always allow activity on CS 0/1/2 */
+	if (cs >= 3)
+		return -ENODEV;
+
+	return 0;
+}
+
+static const struct dm_spi_ops ath79_spi_ops = {
+	.claim_bus  = ath79_spi_claim_bus,
+	.release_bus    = ath79_spi_release_bus,
+	.xfer       = ath79_spi_xfer,
+	.set_speed  = ath79_spi_set_speed,
+	.set_mode   = ath79_spi_set_mode,
+	.cs_info    = ath79_cs_info,
+};
+
+static const struct udevice_id ath79_spi_ids[] = {
+	{ .compatible = "qca,ar7100-spi" },
+	{}
+};
+
+U_BOOT_DRIVER(ath79_spi) = {
+	.name   = "ath79_spi",
+	.id = UCLASS_SPI,
+	.of_match = ath79_spi_ids,
+	.ops    = &ath79_spi_ops,
+	.priv_auto_alloc_size = sizeof(struct ath79_spi_priv),
+	.probe  = ath79_spi_probe,
+};

Am Sonntag, den 17.01.2016, 02:13 +0800 schrieb Wills Wang:

Quoted 3 lines

Reviewed-by Thomas Chou <[email protected]>

Signed-off-by Wills Wang <[email protected]>

Reviewed-by Daniel Schwierzeck <[email protected]>

nits below

Quoted 71 lines

---

Changes in v7:
- Define spi_cs_activate/spi_cs_deactivate
- Rename MHZ to ATH79_SPI_MHZ
- Use clrsetbits_32

Changes in v6:
- Add rrw_delay in ath79_spi_priv for more accurate timing
- Remove ath79_spi_delay
- Calculate delay in ath79_spi_set_speed

Changes in v5:
- remove ar933x_spi_platdata
- Import document "spi-ath79.txt" from kernel
- Add delay for bitbang operation

Changes in v4:
- Use get_bus_freq instead of hardcode in SPI driver

Changes in v3:
- Convert spi driver to driver model

Changes in v2:
- Add a compatible spi driver

  doc/device-tree-bindings/spi/spi-ath79.txt |  19 +++
  drivers/spi/Kconfig                        |   8 +
  drivers/spi/Makefile                       |   1 +
  drivers/spi/ath79_spi.c                    | 237
+++++++++++++++++++++++++++++
  4 files changed, 265 insertions(+)

create mode 100644 doc/device-tree-bindings/spi/spi-ath79.txt create mode 100644 drivers/spi/ath79_spi.c

doc/device renamed from doc/device-tree-bindings/spi/spi-ath79.txt +0 -1

-tree-bindings/spi/spi-ath79.txt

new file mode 100644
index 0000000..3fd9d67

doc/device-tree-bindings/spi/spi-ath79.txt new file +4 -0

@@ -0,0 +1,19 @@
+Binding for Qualcomm Atheros AR7xxx/AR9xxx SPI controller
+
+Required properties:
+- compatible: has to be "qca,<soc-type>-spi", "qca,ar7100-spi" as

fallback.

+- reg: Base address and size of the controllers memory area
+- #address-cells: <1>, as required by generic SPI binding.
+- #size-cells: <0>, also as required by generic SPI binding.

doc/device-tree-bindings/spi/spi-ath79.txt new file +12 -0

+
+Child nodes as per the generic SPI binding.
+
+Example:
+
+	spi at 1f000000 {
+		compatible = "qca,ar9132-spi", "qca,ar7100-spi";
+		reg = <0x1f000000 0x10>;
+
+		#address-cells = <1>;
+		#size-cells = <0>;
+	};

drivers/spi/Kconfig +0 -0

index 2cdb110..0ab2741 100644
@@ -23,6 +23,14 @@ config ALTERA_SPI
  	  IP core. Please find details on the "Embedded Peripherals

IP
User Guide" of Altera.

drivers/spi/Kconfig config ALTERA_SPI · line 27

Quoted 2 lines

drivers/spi/Kconfig +2 -0

+config ATH79_SPI
+	bool "Atheros SPI driver"

you should add

depends on ARCH_ATH79

Quoted 63 lines

drivers/spi/Kconfig +2 -0

+	help
+	  Enable the Atheros ar7xxx/ar9xxx SoC SPI driver, it was

used

drivers/spi/Kconfig +1 -0

+	  to access SPI NOR flash and other SPI peripherals. This

driver

drivers/spi/Kconfig +1 -0

+	  uses driver model and requires a device tree binding to

operate.

drivers/spi/Kconfig +2 -1

+	  please refer to doc/device-tree-bindings/spi/spi
-ath79.txt.
+
  config CADENCE_QSPI
  	bool "Cadence QSPI driver"
  	help

drivers/spi/Makefile +1 -0

index 3eca745..7fb2926 100644
@@ -17,6 +17,7 @@ endif
 
  obj-$(CONFIG_ALTERA_SPI) += altera_spi.o
  obj-$(CONFIG_ARMADA100_SPI) += armada100_spi.o
+obj-$(CONFIG_ATH79_SPI) += ath79_spi.o
  obj-$(CONFIG_ATMEL_DATAFLASH_SPI) += atmel_dataflash_spi.o
  obj-$(CONFIG_ATMEL_SPI) += atmel_spi.o
  obj-$(CONFIG_BFIN_SPI) += bfin_spi.o

drivers/spi/ath79_spi.c new file +32 -0

new file mode 100644
index 0000000..568548f
@@ -0,0 +1,237 @@
+/*
+ * Copyright (C) 2015-2016 Wills Wang <[email protected]>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <spi.h>
+#include <dm.h>
+#include <div64.h>
+#include <errno.h>
+#include <asm/io.h>
+#include <asm/addrspace.h>
+#include <asm/types.h>
+#include <mach/ar71xx_regs.h>
+
+/* CLOCK_DIVIDER = 3 (SPI clock = 200 / 8 ~ 25 MHz) */
+#define ATH79_SPI_CLK_DIV(x)           (((x) >> 1) - 1)
+#define ATH79_SPI_RRW_DELAY_FACTOR     12000
+#define ATH79_SPI_MHZ                  (1000 * 1000)
+
+struct ath79_spi_priv {
+	void __iomem *regs;
+	u32 rrw_delay;
+};
+
+static inline u32 ath79_spi_read(struct udevice *bus, u32 offset)
+{
+	struct ath79_spi_priv *priv = dev_get_priv(bus);
+	return readl(priv->regs + offset);
+}
+

drivers/spi/ath79_spi.c line 38

Quoted 6 lines

drivers/spi/ath79_spi.c new file +6 -0

+static inline void ath79_spi_write(struct udevice *bus,
+					u32 val, u32 offset)
+{
+	struct ath79_spi_priv *priv = dev_get_priv(bus);
+	writel(val, priv->regs + offset);
+}

actually you could use the I/O accessors directly, there is no need for wrapper functions. The same is true for your serial driver.

of

drivers/spi/ath79_spi.c line 42

Quoted 4 lines

drivers/spi/ath79_spi.c new file +4 -0

+
+static void spi_cs_activate(struct udevice *dev)
+{
+	struct udevice *bus = dev->parent;

for a consistent use of the DM API, you should use dev_get_parent(dev)

Quoted 207 lines

drivers/spi/ath79_spi.c new file +3 -0

+
+	ath79_spi_write(bus, AR71XX_SPI_FS_GPIO, AR71XX_SPI_REG_FS);
+	ath79_spi_write(bus, AR71XX_SPI_IOC_CS_ALL,

AR71XX_SPI_REG_IOC);

drivers/spi/ath79_spi.c new file +7 -0

+}
+
+static void spi_cs_deactivate(struct udevice *dev)
+{
+	struct udevice *bus = dev->parent;
+
+	ath79_spi_write(bus, AR71XX_SPI_IOC_CS_ALL,

AR71XX_SPI_REG_IOC);

drivers/spi/ath79_spi.c new file +19 -0

+	ath79_spi_write(bus, 0, AR71XX_SPI_REG_FS);
+}
+
+static int ath79_spi_claim_bus(struct udevice *dev)
+{
+	return 0;
+}
+
+static int ath79_spi_release_bus(struct udevice *dev)
+{
+	return 0;
+}
+
+static int ath79_spi_xfer(struct udevice *dev, unsigned int bitlen,
+		const void *dout, void *din, unsigned long flags)
+{
+	struct udevice *bus = dev->parent;
+	struct ath79_spi_priv *priv = dev_get_priv(bus);
+	struct dm_spi_slave_platdata *slave =

dev_get_parent_platdata(dev);

drivers/spi/ath79_spi.c new file +29 -1

+	u8 *rx = din;
+	const u8 *tx = dout;
+	u8 curbyte, curbitlen, restbits;
+	u32 bytes = bitlen / 8;
+	u32 out, in;
+	u64 tick;
+
+	if (flags & SPI_XFER_BEGIN)
+		spi_cs_activate(dev);
+
+	restbits = (bitlen % 8);
+	if (restbits)
+		bytes++;
+
+	out = AR71XX_SPI_IOC_CS_ALL & ~(AR71XX_SPI_IOC_CS(slave
->cs));
+	while (bytes > 0) {
+		bytes--;
+		curbyte = 0;
+		if (tx)
+			curbyte = *tx++;
+
+		if (restbits && !bytes) {
+			curbitlen = restbits;
+			curbyte <<= 8 - restbits;
+		} else {
+			curbitlen = 8;
+		}
+
+		for (curbyte <<= (8 - curbitlen); curbitlen;

curbitlen--) {

drivers/spi/ath79_spi.c new file +6 -0

+			if (curbyte & 0x80)
+				out |= AR71XX_SPI_IOC_DO;
+			else
+				out &= ~(AR71XX_SPI_IOC_DO);
+
+			ath79_spi_write(bus, out,

AR71XX_SPI_REG_IOC);

drivers/spi/ath79_spi.c new file +9 -1

+
+			/* delay for low level */
+			if (priv->rrw_delay) {
+				tick = get_ticks() + priv
->rrw_delay;
+				while (get_ticks() < tick)
+					/*NOP*/;
+			}
+
+			ath79_spi_write(bus, out |

AR71XX_SPI_IOC_CLK,

drivers/spi/ath79_spi.c new file +14 -1

+					AR71XX_SPI_REG_IOC);
+
+			/* delay for high level */
+			if (priv->rrw_delay) {
+				tick = get_ticks() + priv
->rrw_delay;
+				while (get_ticks() < tick)
+					/*NOP*/;
+			}
+
+			curbyte <<= 1;
+		}
+
+		if (!bytes)
+			ath79_spi_write(bus, out,

AR71XX_SPI_REG_IOC);

drivers/spi/ath79_spi.c new file +45 -0

+
+		in = ath79_spi_read(bus, AR71XX_SPI_REG_RDS);
+		if (rx) {
+			if (restbits && !bytes)
+				*rx++ = (in << (8 - restbits));
+			else
+				*rx++ = in;
+		}
+	}
+
+	if (flags & SPI_XFER_END)
+		spi_cs_deactivate(dev);
+
+	return 0;
+}
+
+
+static int ath79_spi_set_speed(struct udevice *bus, uint speed)
+{
+	struct ath79_spi_priv *priv = dev_get_priv(bus);
+	u32 val, div = 0;
+	u64 time;
+
+	if (speed)
+		div = get_bus_freq(0) / speed;
+
+	if (div > 63)
+		div = 63;
+
+	if (div < 5)
+		div = 5;
+
+	/* calculate delay */
+	time = get_tbclk();
+	do_div(time, speed / 2);
+	val = get_bus_freq(0) / ATH79_SPI_MHZ;
+	val = ATH79_SPI_RRW_DELAY_FACTOR / val;
+	if (time > val)
+		priv->rrw_delay = time - val + 1;
+	else
+		priv->rrw_delay = 0;
+
+	ath79_spi_write(bus, AR71XX_SPI_FS_GPIO, AR71XX_SPI_REG_FS);
+	clrsetbits_32(priv->regs + AR71XX_SPI_REG_CTRL,
+		      AR71XX_SPI_CTRL_DIV_MASK,

ATH79_SPI_CLK_DIV(div));

drivers/spi/ath79_spi.c new file +25 -0

+	ath79_spi_write(bus, 0, AR71XX_SPI_REG_FS);
+	return 0;
+}
+
+static int ath79_spi_set_mode(struct udevice *bus, uint mode)
+{
+	return 0;
+}
+
+static int ath79_spi_probe(struct udevice *bus)
+{
+	struct ath79_spi_priv *priv = dev_get_priv(bus);
+	fdt_addr_t addr;
+
+	addr = dev_get_addr(bus);
+	if (addr == FDT_ADDR_T_NONE)
+		return -EINVAL;
+
+	priv->regs = map_physmem(addr,
+				 AR71XX_SPI_SIZE,
+				 MAP_NOCACHE);
+
+	/* Init SPI Hardware, disable remap, set clock */
+	ath79_spi_write(bus, AR71XX_SPI_FS_GPIO, AR71XX_SPI_REG_FS);
+	ath79_spi_write(bus, AR71XX_SPI_CTRL_RD |

ATH79_SPI_CLK_DIV(8),

drivers/spi/ath79_spi.c new file +38 -0

+			AR71XX_SPI_REG_CTRL);
+	ath79_spi_write(bus, 0, AR71XX_SPI_REG_FS);
+
+	return 0;
+}
+
+static int ath79_cs_info(struct udevice *bus, uint cs,
+			   struct spi_cs_info *info)
+{
+	/* Always allow activity on CS 0/1/2 */
+	if (cs >= 3)
+		return -ENODEV;
+
+	return 0;
+}
+
+static const struct dm_spi_ops ath79_spi_ops = {
+	.claim_bus  = ath79_spi_claim_bus,
+	.release_bus    = ath79_spi_release_bus,
+	.xfer       = ath79_spi_xfer,
+	.set_speed  = ath79_spi_set_speed,
+	.set_mode   = ath79_spi_set_mode,
+	.cs_info    = ath79_cs_info,
+};
+
+static const struct udevice_id ath79_spi_ids[] = {
+	{ .compatible = "qca,ar7100-spi" },
+	{}
+};
+
+U_BOOT_DRIVER(ath79_spi) = {
+	.name   = "ath79_spi",
+	.id = UCLASS_SPI,
+	.of_match = ath79_spi_ids,
+	.ops    = &ath79_spi_ops,
+	.priv_auto_alloc_size = sizeof(struct ath79_spi_priv),
+	.probe  = ath79_spi_probe,
+};