arm64: cpufeature: Fix sign of feature bits
Suzuki K Poulose
reviewercover arm64: cpufeature: Fix sign of feature bits
ARM ARM is getting updated with the guidelines on how to treat the feature values for their sign. This series fixes the handling of sign based on the new update. Also make the capabilities aware of the sign of the feature to use the appropriate helper for extracting the values.
See Patch2 for more details on the rules.
Suzuki K. Poulose (4):
arm64: cpufeature: Correct feature register tables
arm64: cpufeature: Fix the sign of feature bits
arm64: capabilities: Handle sign of the feature bit
arm64: Rename cpuid_feature field extract routines
arch/arm64/include/asm/cpufeature.h | 29 +++++++---- arch/arm64/include/asm/kvm_mmu.h | 2 +- arch/arm64/kernel/cpufeature.c | 96 ++++++++++++++++++++--------------- arch/arm64/kernel/debug-monitors.c | 2 +- arch/arm64/kvm/sys_regs.c | 2 +- arch/arm64/mm/context.c | 2 +- 6 files changed, 78 insertions(+), 55 deletions(-)
Signature · 1 line
1.7.9.5
Suzuki K Poulose
reviewerPATCH 1/4 arm64: cpufeature: Correct feature register tables
Correct the feature bit entries for :
ID_DFR0
ID_MMFR0
to fix the default safe value for some of the bits.
Signed-off-by Suzuki K. Poulose <[email protected]>
--- arch/arm64/kernel/cpufeature.c | 18 +++++++++++++++--- 1 file changed, 15 insertions(+), 3 deletions(-)
arch/arm64/kernel/cpufeature.c +15 -3
@@ -141,12 +141,12 @@ static struct arm64_ftr_bits ftr_ctr[] = { };static struct arm64_ftr_bits ftr_id_mmfr0[] = { -ARM64_FTR_BITS (FTR_STRICT ,FTR_EXACT ,28 ,4 ,0 ),/* InnerShr */ +ARM64_FTR_BITS (FTR_STRICT ,FTR_EXACT ,28 ,4 ,0xf ),/* InnerShr */ ARM64_FTR_BITS (FTR_STRICT ,FTR_EXACT ,24 ,4 ,0 ),/* FCSE */ ARM64_FTR_BITS (FTR_NONSTRICT ,FTR_LOWER_SAFE ,20 ,4 ,0 ),/* AuxReg */ ARM64_FTR_BITS (FTR_STRICT ,FTR_EXACT ,16 ,4 ,0 ),/* TCM */ ARM64_FTR_BITS (FTR_STRICT ,FTR_EXACT ,12 ,4 ,0 ),/* ShareLvl */ -ARM64_FTR_BITS (FTR_STRICT ,FTR_EXACT ,8 ,4 ,0 ),/* OuterShr */ +ARM64_FTR_BITS (FTR_STRICT ,FTR_EXACT ,8 ,4 ,0xf ),/* OuterShr */ ARM64_FTR_BITS (FTR_STRICT ,FTR_EXACT ,4 ,4 ,0 ),/* PMSA */ ARM64_FTR_BITS (FTR_STRICT ,FTR_EXACT ,0 ,4 ,0 ),/* VMSA */ ARM64_FTR_END ,
@@ -205,6 +205,18 @@ static struct arm64_ftr_bits ftr_id_pfr0[] = { ARM64_FTR_END, }; +static struct arm64_ftr_bits ftr_id_dfr0[] = { +ARM64_FTR_BITS (FTR_STRICT ,FTR_LOWER_SAFE ,28 ,4 ,0 ), +ARM64_FTR_BITS (FTR_STRICT ,FTR_LOWER_SAFE ,24 ,4 ,0xf ),/* PerfMon */ +ARM64_FTR_BITS (FTR_STRICT ,FTR_LOWER_SAFE ,20 ,4 ,0 ), +ARM64_FTR_BITS (FTR_STRICT ,FTR_LOWER_SAFE ,16 ,4 ,0 ), +ARM64_FTR_BITS (FTR_STRICT ,FTR_LOWER_SAFE ,12 ,4 ,0 ), +ARM64_FTR_BITS (FTR_STRICT ,FTR_LOWER_SAFE ,8 ,4 ,0 ), +ARM64_FTR_BITS (FTR_STRICT ,FTR_LOWER_SAFE ,4 ,4 ,0 ), +ARM64_FTR_BITS (FTR_STRICT ,FTR_LOWER_SAFE ,0 ,4 ,0 ), +ARM64_FTR_END , +}; +/* * Common ftr bits for a 32bit register with all hidden, strict * attributes, with 4bit feature fields and a default safe value of
@@ -250,7 +262,7 @@ static struct arm64_ftr_reg arm64_ftr_regs[] = {/* Op1 = 0, CRn = 0, CRm = 1 */ ARM64_FTR_REG (SYS_ID_PFR0_EL1 , ftr_id_pfr0),ARM64_FTR_REG (SYS_ID_PFR1_EL1 , ftr_generic_32bits), -ARM64_FTR_REG (SYS_ID_DFR0_EL1 , ftr_generic_32bits), +ARM64_FTR_REG (SYS_ID_DFR0_EL1 , ftr_id_dfr0),ARM64_FTR_REG (SYS_ID_MMFR0_EL1 , ftr_id_mmfr0),ARM64_FTR_REG (SYS_ID_MMFR1_EL1 , ftr_generic_32bits), ARM64_FTR_REG(SYS_ID_MMFR2_EL1, ftr_generic_32bits),
Signature · 1 line
1.7.9.5
Suzuki K Poulose
reviewerPATCH 2/4 arm64: cpufeature: Fix the sign of feature bits
In reply to Suzuki K PouloseThere is a confusion on whether the values of a feature are signed or not in ARM. This is not clearly mentioned in the ARM ARM either. We have dealt most of the bits as signed so far, and marked the rest as unsigned explicitly. This fixed in ARM ARM and will be rolled out soon.
Here is the criteria in a nutshell:
1) The fields, which are either signed or unsigned, use increasing numerical values to indicate an increase in functionality. Thus, if a value of 0x1 indicates the presence of some instructions, then the 0x2 value will indicate the presence of those instructions plus some additional instructions or functionality.
2) For ID field values where the value 0x0 defines that a feature is not present, the number is an unsigned value.
3) For some features where the feature was made optional or removed after the start of the definition of the architecture, the value 0x0 is used to indicate the presence of a feature, and 0xF indicates the absence of the feature. In these cases, the fields are, in effect, holding signed values.
So with these rules applied, we have only the following fields which are signed and the rest are unsigned.
a) ID_AA64PFR0_EL1: {FP, ASIMD}
b) ID_AA64MMFR0_EL1: {TGran4K, TGran64K}
c) ID_AA64DFR0_EL1: PMUVer (0xf - PMUv3 not implemented)
d) ID_DFR0_EL1: PerfMon
e) ID_MMFR0_EL1: {InnerShr, OuterShr}
Signed-off-by Suzuki K. Poulose <[email protected]>
--- arch/arm64/kernel/cpufeature.c | 50 ++++++++++++++++++++-------------------- 1 file changed, 25 insertions(+), 25 deletions(-)
arch/arm64/kernel/cpufeature.c +25 -25
@@ -55,14 +55,14 @@ DECLARE_BITMAP(cpu_hwcaps, ARM64_NCAPS); .safe_val = SAFE_VAL, \ } -/* Define a feature with signed values */ +/* Define a feature with unsigned values */ #define ARM64_FTR_BITS (STRICT ,TYPE ,SHIFT ,WIDTH ,SAFE_VAL ) \ - __ARM64_FTR_BITS(FTR_SIGNED, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) - -/* Define a feature with unsigned value */ -#define U_ARM64_FTR_BITS (STRICT ,TYPE ,SHIFT ,WIDTH ,SAFE_VAL ) \ __ARM64_FTR_BITS(FTR_UNSIGNED, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) +/* Define a feature with a signed value */ +#define S_ARM64_FTR_BITS (STRICT ,TYPE ,SHIFT ,WIDTH ,SAFE_VAL ) \ + __ARM64_FTR_BITS(FTR_SIGNED, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) +#define ARM64_FTR_END \ { \ .width = 0, \
@@ -85,8 +85,8 @@ static struct arm64_ftr_bits ftr_id_aa64pfr0[] = {ARM64_FTR_BITS (FTR_STRICT ,FTR_EXACT ,32 ,32 ,0 ),ARM64_FTR_BITS (FTR_STRICT ,FTR_EXACT ,28 ,4 ,0 ),ARM64_FTR_BITS (FTR_STRICT ,FTR_EXACT ,ID_AA64PFR0_GIC_SHIFT ,4 ,0 ), -ARM64_FTR_BITS (FTR_STRICT ,FTR_LOWER_SAFE ,ID_AA64PFR0_ASIMD_SHIFT ,4 ,ID_AA64PFR0_ASIMD_NI ), -ARM64_FTR_BITS (FTR_STRICT ,FTR_LOWER_SAFE ,ID_AA64PFR0_FP_SHIFT ,4 ,ID_AA64PFR0_FP_NI ), +S_ARM64_FTR_BITS (FTR_STRICT ,FTR_LOWER_SAFE ,ID_AA64PFR0_ASIMD_SHIFT ,4 ,ID_AA64PFR0_ASIMD_NI ), +S_ARM64_FTR_BITS (FTR_STRICT ,FTR_LOWER_SAFE ,ID_AA64PFR0_FP_SHIFT ,4 ,ID_AA64PFR0_FP_NI ),/* Linux doesn't care about the EL3 */ ARM64_FTR_BITS (FTR_NONSTRICT ,FTR_EXACT ,ID_AA64PFR0_EL3_SHIFT ,4 ,0 ), ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64PFR0_EL2_SHIFT, 4, 0),
@@ -97,8 +97,8 @@ static struct arm64_ftr_bits ftr_id_aa64pfr0[] = {static struct arm64_ftr_bits ftr_id_aa64mmfr0[] = {ARM64_FTR_BITS (FTR_STRICT ,FTR_EXACT ,32 ,32 ,0 ), -ARM64_FTR_BITS (FTR_STRICT ,FTR_EXACT ,ID_AA64MMFR0_TGRAN4_SHIFT ,4 ,ID_AA64MMFR0_TGRAN4_NI ), -ARM64_FTR_BITS (FTR_STRICT ,FTR_EXACT ,ID_AA64MMFR0_TGRAN64_SHIFT ,4 ,ID_AA64MMFR0_TGRAN64_NI ), +S_ARM64_FTR_BITS (FTR_STRICT ,FTR_EXACT ,ID_AA64MMFR0_TGRAN4_SHIFT ,4 ,ID_AA64MMFR0_TGRAN4_NI ), +S_ARM64_FTR_BITS (FTR_STRICT ,FTR_EXACT ,ID_AA64MMFR0_TGRAN64_SHIFT ,4 ,ID_AA64MMFR0_TGRAN64_NI ),ARM64_FTR_BITS (FTR_STRICT ,FTR_EXACT ,ID_AA64MMFR0_TGRAN16_SHIFT ,4 ,ID_AA64MMFR0_TGRAN16_NI ),ARM64_FTR_BITS (FTR_STRICT ,FTR_EXACT ,ID_AA64MMFR0_BIGENDEL0_SHIFT ,4 ,0 ),/* Linux shouldn't care about secure memory */
@@ -109,7 +109,7 @@ static struct arm64_ftr_bits ftr_id_aa64mmfr0[] = {* Differing PARange is fine as long as all peripherals and memory are mapped * within the minimum PARange of all CPUs */ -U_ARM64_FTR_BITS (FTR_NONSTRICT ,FTR_LOWER_SAFE ,ID_AA64MMFR0_PARANGE_SHIFT ,4 ,0 ), +ARM64_FTR_BITS (FTR_NONSTRICT ,FTR_LOWER_SAFE ,ID_AA64MMFR0_PARANGE_SHIFT ,4 ,0 ), ARM64_FTR_END, };
@@ -125,28 +125,28 @@ static struct arm64_ftr_bits ftr_id_aa64mmfr1[] = { };static struct arm64_ftr_bits ftr_ctr[] = { -U_ARM64_FTR_BITS (FTR_STRICT ,FTR_EXACT ,31 ,1 ,1 ),/* RAO */ +ARM64_FTR_BITS (FTR_STRICT ,FTR_EXACT ,31 ,1 ,1 ),/* RAO */ ARM64_FTR_BITS (FTR_STRICT ,FTR_EXACT ,28 ,3 ,0 ), -U_ARM64_FTR_BITS (FTR_STRICT ,FTR_HIGHER_SAFE ,24 ,4 ,0 ),/* CWG */ -U_ARM64_FTR_BITS (FTR_STRICT ,FTR_LOWER_SAFE ,20 ,4 ,0 ),/* ERG */ -U_ARM64_FTR_BITS (FTR_STRICT ,FTR_LOWER_SAFE ,16 ,4 ,1 ),/* DminLine */ +ARM64_FTR_BITS (FTR_STRICT ,FTR_HIGHER_SAFE ,24 ,4 ,0 ),/* CWG */ +ARM64_FTR_BITS (FTR_STRICT ,FTR_LOWER_SAFE ,20 ,4 ,0 ),/* ERG */ +ARM64_FTR_BITS (FTR_STRICT ,FTR_LOWER_SAFE ,16 ,4 ,1 ),/* DminLine */ /* * Linux can handle differing I-cache policies. Userspace JITs will * make use of *minLine */ -U_ARM64_FTR_BITS (FTR_NONSTRICT ,FTR_EXACT ,14 ,2 ,0 ),/* L1Ip */ +ARM64_FTR_BITS (FTR_NONSTRICT ,FTR_EXACT ,14 ,2 ,0 ),/* L1Ip */ ARM64_FTR_BITS (FTR_STRICT ,FTR_EXACT ,4 ,10 ,0 ),/* RAZ */ -U_ARM64_FTR_BITS (FTR_STRICT ,FTR_LOWER_SAFE ,0 ,4 ,0 ),/* IminLine */ +ARM64_FTR_BITS (FTR_STRICT ,FTR_LOWER_SAFE ,0 ,4 ,0 ),/* IminLine */ ARM64_FTR_END , };static struct arm64_ftr_bits ftr_id_mmfr0[] = { -ARM64_FTR_BITS (FTR_STRICT ,FTR_EXACT ,28 ,4 ,0xf ),/* InnerShr */ +S_ARM64_FTR_BITS (FTR_STRICT ,FTR_EXACT ,28 ,4 ,0xf ),/* InnerShr */ ARM64_FTR_BITS (FTR_STRICT ,FTR_EXACT ,24 ,4 ,0 ),/* FCSE */ ARM64_FTR_BITS (FTR_NONSTRICT ,FTR_LOWER_SAFE ,20 ,4 ,0 ),/* AuxReg */ ARM64_FTR_BITS (FTR_STRICT ,FTR_EXACT ,16 ,4 ,0 ),/* TCM */ ARM64_FTR_BITS (FTR_STRICT ,FTR_EXACT ,12 ,4 ,0 ),/* ShareLvl */ -ARM64_FTR_BITS (FTR_STRICT ,FTR_EXACT ,8 ,4 ,0xf ),/* OuterShr */ +S_ARM64_FTR_BITS (FTR_STRICT ,FTR_EXACT ,8 ,4 ,0xf ),/* OuterShr */ ARM64_FTR_BITS (FTR_STRICT ,FTR_EXACT ,4 ,4 ,0 ),/* PMSA */ ARM64_FTR_BITS (FTR_STRICT ,FTR_EXACT ,0 ,4 ,0 ),/* VMSA */ ARM64_FTR_END ,
@@ -154,12 +154,12 @@ static struct arm64_ftr_bits ftr_id_mmfr0[] = {static struct arm64_ftr_bits ftr_id_aa64dfr0[] = {ARM64_FTR_BITS (FTR_STRICT ,FTR_EXACT ,32 ,32 ,0 ), -U_ARM64_FTR_BITS (FTR_STRICT ,FTR_LOWER_SAFE ,ID_AA64DFR0_CTX_CMPS_SHIFT ,4 ,0 ), -U_ARM64_FTR_BITS (FTR_STRICT ,FTR_LOWER_SAFE ,ID_AA64DFR0_WRPS_SHIFT ,4 ,0 ), -U_ARM64_FTR_BITS (FTR_STRICT ,FTR_LOWER_SAFE ,ID_AA64DFR0_BRPS_SHIFT ,4 ,0 ), -U_ARM64_FTR_BITS (FTR_STRICT ,FTR_EXACT ,ID_AA64DFR0_PMUVER_SHIFT ,4 ,0 ), -U_ARM64_FTR_BITS (FTR_STRICT ,FTR_EXACT ,ID_AA64DFR0_TRACEVER_SHIFT ,4 ,0 ), -U_ARM64_FTR_BITS (FTR_STRICT ,FTR_EXACT ,ID_AA64DFR0_DEBUGVER_SHIFT ,4 ,0x6 ), +ARM64_FTR_BITS (FTR_STRICT ,FTR_LOWER_SAFE ,ID_AA64DFR0_CTX_CMPS_SHIFT ,4 ,0 ), +ARM64_FTR_BITS (FTR_STRICT ,FTR_LOWER_SAFE ,ID_AA64DFR0_WRPS_SHIFT ,4 ,0 ), +ARM64_FTR_BITS (FTR_STRICT ,FTR_LOWER_SAFE ,ID_AA64DFR0_BRPS_SHIFT ,4 ,0 ), +S_ARM64_FTR_BITS (FTR_STRICT ,FTR_EXACT ,ID_AA64DFR0_PMUVER_SHIFT ,4 ,0 ), +ARM64_FTR_BITS (FTR_STRICT ,FTR_EXACT ,ID_AA64DFR0_TRACEVER_SHIFT ,4 ,0 ), +ARM64_FTR_BITS (FTR_STRICT ,FTR_EXACT ,ID_AA64DFR0_DEBUGVER_SHIFT ,4 ,0x6 ),ARM64_FTR_END , };
@@ -207,7 +207,7 @@ static struct arm64_ftr_bits ftr_id_pfr0[] = {static struct arm64_ftr_bits ftr_id_dfr0[] = {ARM64_FTR_BITS (FTR_STRICT ,FTR_LOWER_SAFE ,28 ,4 ,0 ), -ARM64_FTR_BITS (FTR_STRICT ,FTR_LOWER_SAFE ,24 ,4 ,0xf ),/* PerfMon */ +S_ARM64_FTR_BITS (FTR_STRICT ,FTR_LOWER_SAFE ,24 ,4 ,0xf ),/* PerfMon */ ARM64_FTR_BITS (FTR_STRICT ,FTR_LOWER_SAFE ,20 ,4 ,0 ),ARM64_FTR_BITS (FTR_STRICT ,FTR_LOWER_SAFE ,16 ,4 ,0 ),ARM64_FTR_BITS (FTR_STRICT ,FTR_LOWER_SAFE ,12 ,4 ,0 ),
Signature · 1 line
1.7.9.5
Suzuki K Poulose
reviewerPATCH 3/4 arm64: capabilities: Handle sign of the feature bit
In reply to Suzuki K PouloseUse the appropriate accessor for the feature bit by keeping track of the sign of the feature
Signed-off-by Suzuki K. Poulose <[email protected]>
--- arch/arm64/include/asm/cpufeature.h | 7 ++++--- arch/arm64/kernel/cpufeature.c | 32 ++++++++++++++++++-------------- 2 files changed, 22 insertions(+), 17 deletions(-)
arch/arm64/include/asm/cpufeature.h +4 -3
@@ -85,9 +85,10 @@ struct arm64_cpu_capabilities {struct {/* Feature register checking */ u32 sys_reg; -int field_pos; -int min_field_value; -int hwcap_type; +u8 field_pos; +u8 min_field_value; +u8 hwcap_type; +bool sign;unsigned long hwcap; }; };
arch/arm64/kernel/cpufeature.c +18 -14
@@ -641,6 +641,7 @@ static const struct arm64_cpu_capabilities arm64_features[] = { .matches = has_useable_gicv3_cpuif, .sys_reg = SYS_ID_AA64PFR0_EL1, .field_pos = ID_AA64PFR0_GIC_SHIFT, + .sign = FTR_UNSIGNED, .min_field_value = 1, },#ifdef CONFIG_ARM64_PAN
@@ -650,6 +651,7 @@ static const struct arm64_cpu_capabilities arm64_features[] = { .matches = has_cpuid_feature, .sys_reg = SYS_ID_AA64MMFR1_EL1, .field_pos = ID_AA64MMFR1_PAN_SHIFT, + .sign = FTR_UNSIGNED, .min_field_value = 1, .enable = cpu_enable_pan, },
@@ -661,38 +663,40 @@ static const struct arm64_cpu_capabilities arm64_features[] = { .matches = has_cpuid_feature, .sys_reg = SYS_ID_AA64ISAR0_EL1, .field_pos = ID_AA64ISAR0_ATOMICS_SHIFT, + .sign = FTR_UNSIGNED, .min_field_value = 2, },#endif /* CONFIG_AS_LSE && CONFIG_ARM64_LSE_ATOMICS */ {}, }; -#define HWCAP_CAP (reg, field, min_value, type, cap) \ +#define HWCAP_CAP (reg, field, s, min_value, type, cap) \ { \ .desc = #cap, \ .matches = has_cpuid_feature, \ .sys_reg = reg, \ .field_pos = field, \ + .sign = s, \ .min_field_value = min_value, \ .hwcap_type = type, \ .hwcap = cap, \ }static const struct arm64_cpu_capabilities arm64_hwcaps[] = { -HWCAP_CAP (SYS_ID_AA64ISAR0_EL1 ,ID_AA64ISAR0_AES_SHIFT ,2 ,CAP_HWCAP ,HWCAP_PMULL ), -HWCAP_CAP (SYS_ID_AA64ISAR0_EL1 ,ID_AA64ISAR0_AES_SHIFT ,1 ,CAP_HWCAP ,HWCAP_AES ), -HWCAP_CAP (SYS_ID_AA64ISAR0_EL1 ,ID_AA64ISAR0_SHA1_SHIFT ,1 ,CAP_HWCAP ,HWCAP_SHA1 ), -HWCAP_CAP (SYS_ID_AA64ISAR0_EL1 ,ID_AA64ISAR0_SHA2_SHIFT ,1 ,CAP_HWCAP ,HWCAP_SHA2 ), -HWCAP_CAP (SYS_ID_AA64ISAR0_EL1 ,ID_AA64ISAR0_CRC32_SHIFT ,1 ,CAP_HWCAP ,HWCAP_CRC32 ), -HWCAP_CAP (SYS_ID_AA64ISAR0_EL1 ,ID_AA64ISAR0_ATOMICS_SHIFT ,2 ,CAP_HWCAP ,HWCAP_ATOMICS ), -HWCAP_CAP (SYS_ID_AA64PFR0_EL1 ,ID_AA64PFR0_FP_SHIFT ,0 ,CAP_HWCAP ,HWCAP_FP ), -HWCAP_CAP (SYS_ID_AA64PFR0_EL1 ,ID_AA64PFR0_ASIMD_SHIFT ,0 ,CAP_HWCAP ,HWCAP_ASIMD ), +HWCAP_CAP (SYS_ID_AA64ISAR0_EL1 ,ID_AA64ISAR0_AES_SHIFT ,FTR_UNSIGNED ,2 ,CAP_HWCAP ,HWCAP_PMULL ), +HWCAP_CAP (SYS_ID_AA64ISAR0_EL1 ,ID_AA64ISAR0_AES_SHIFT ,FTR_UNSIGNED ,1 ,CAP_HWCAP ,HWCAP_AES ), +HWCAP_CAP (SYS_ID_AA64ISAR0_EL1 ,ID_AA64ISAR0_SHA1_SHIFT ,FTR_UNSIGNED ,1 ,CAP_HWCAP ,HWCAP_SHA1 ), +HWCAP_CAP (SYS_ID_AA64ISAR0_EL1 ,ID_AA64ISAR0_SHA2_SHIFT ,FTR_UNSIGNED ,1 ,CAP_HWCAP ,HWCAP_SHA2 ), +HWCAP_CAP (SYS_ID_AA64ISAR0_EL1 ,ID_AA64ISAR0_CRC32_SHIFT ,FTR_UNSIGNED ,1 ,CAP_HWCAP ,HWCAP_CRC32 ), +HWCAP_CAP (SYS_ID_AA64ISAR0_EL1 ,ID_AA64ISAR0_ATOMICS_SHIFT ,FTR_UNSIGNED ,2 ,CAP_HWCAP ,HWCAP_ATOMICS ), +HWCAP_CAP (SYS_ID_AA64PFR0_EL1 ,ID_AA64PFR0_FP_SHIFT ,FTR_SIGNED ,0 ,CAP_HWCAP ,HWCAP_FP ), +HWCAP_CAP (SYS_ID_AA64PFR0_EL1 ,ID_AA64PFR0_ASIMD_SHIFT ,FTR_SIGNED ,0 ,CAP_HWCAP ,HWCAP_ASIMD ), #ifdef CONFIG_COMPAT -HWCAP_CAP (SYS_ID_ISAR5_EL1 ,ID_ISAR5_AES_SHIFT ,2 ,CAP_COMPAT_HWCAP2 ,COMPAT_HWCAP2_PMULL ), -HWCAP_CAP (SYS_ID_ISAR5_EL1 ,ID_ISAR5_AES_SHIFT ,1 ,CAP_COMPAT_HWCAP2 ,COMPAT_HWCAP2_AES ), -HWCAP_CAP (SYS_ID_ISAR5_EL1 ,ID_ISAR5_SHA1_SHIFT ,1 ,CAP_COMPAT_HWCAP2 ,COMPAT_HWCAP2_SHA1 ), -HWCAP_CAP (SYS_ID_ISAR5_EL1 ,ID_ISAR5_SHA2_SHIFT ,1 ,CAP_COMPAT_HWCAP2 ,COMPAT_HWCAP2_SHA2 ), -HWCAP_CAP (SYS_ID_ISAR5_EL1 ,ID_ISAR5_CRC32_SHIFT ,1 ,CAP_COMPAT_HWCAP2 ,COMPAT_HWCAP2_CRC32 ), +HWCAP_CAP (SYS_ID_ISAR5_EL1 ,ID_ISAR5_AES_SHIFT ,FTR_UNSIGNED ,2 ,CAP_COMPAT_HWCAP2 ,COMPAT_HWCAP2_PMULL ), +HWCAP_CAP (SYS_ID_ISAR5_EL1 ,ID_ISAR5_AES_SHIFT ,FTR_UNSIGNED ,1 ,CAP_COMPAT_HWCAP2 ,COMPAT_HWCAP2_AES ), +HWCAP_CAP (SYS_ID_ISAR5_EL1 ,ID_ISAR5_SHA1_SHIFT ,FTR_UNSIGNED ,1 ,CAP_COMPAT_HWCAP2 ,COMPAT_HWCAP2_SHA1 ), +HWCAP_CAP (SYS_ID_ISAR5_EL1 ,ID_ISAR5_SHA2_SHIFT ,FTR_UNSIGNED ,1 ,CAP_COMPAT_HWCAP2 ,COMPAT_HWCAP2_SHA2 ), +HWCAP_CAP (SYS_ID_ISAR5_EL1 ,ID_ISAR5_CRC32_SHIFT ,FTR_UNSIGNED ,1 ,CAP_COMPAT_HWCAP2 ,COMPAT_HWCAP2_CRC32 ), #endif {}, };
Signature · 1 line
1.7.9.5
Suzuki K Poulose
reviewerPATCH 4/4 arm64: Rename cpuid_feature field extract routines
In reply to Suzuki K PouloseNow that we have a clear understanding of the sign of a feature, rename the routines to reflect the sign, so that it is not misused. The cpuid_feature_extract_field() now accepts a 'sign' parameter.
Signed-off-by Suzuki K. Poulose <[email protected]>
--- arch/arm64/include/asm/cpufeature.h | 22 ++++++++++++++-------- arch/arm64/include/asm/kvm_mmu.h | 2 +- arch/arm64/kernel/cpufeature.c | 2 +- arch/arm64/kernel/debug-monitors.c | 2 +- arch/arm64/kvm/sys_regs.c | 2 +- arch/arm64/mm/context.c | 2 +- 6 files changed, 19 insertions(+), 13 deletions(-)
arch/arm64/include/asm/cpufeature.h +14 -8
@@ -118,15 +118,15 @@ static inline void cpus_set_cap(unsigned int num) } static inline int __attribute_const__ -cpuid_feature_extract_field_width (u64 features,int field,int width) +cpuid_feature_extract_signed_field_width (u64 features,int field,int width) {return (s64)(features << (64 - width - field)) >> (64 - width); } static inline int __attribute_const__ -cpuid_feature_extract_field (u64 features,int field) +cpuid_feature_extract_signed_field (u64 features,int field) { -return cpuid_feature_extract_field_width (features, field,4 ); +return cpuid_feature_extract_signed_field_width (features, field,4 ); }static inline unsigned int __attribute_const__
@@ -146,17 +146,23 @@ static inline u64 arm64_ftr_mask(struct arm64_ftr_bits *ftrp)return (u64 )GENMASK (ftrp->shift + ftrp->width -1 , ftrp->shift); } +static inline int __attribute_const__ +cpuid_feature_extract_field (u64 features,int field,bool sign) +{ +return (sign) ? +cpuid_feature_extract_signed_field (features, field) : +cpuid_feature_extract_unsigned_field (features, field); +} +static inline s64 arm64_ftr_value (struct arm64_ftr_bits *ftrp,u64 val) { -return ftrp->sign ? -cpuid_feature_extract_field_width (val, ftrp->shift, ftrp->width) : -cpuid_feature_extract_unsigned_field_width (val, ftrp->shift, ftrp->width); +return (s64 )cpuid_feature_extract_field (val, ftrp->shift, ftrp->sign); }static inline bool id_aa64mmfr0_mixed_endian_el0 (u64 mmfr0) { -return cpuid_feature_extract_field (mmfr0,ID_AA64MMFR0_BIGENDEL_SHIFT ) ==0x1 || -cpuid_feature_extract_field (mmfr0,ID_AA64MMFR0_BIGENDEL0_SHIFT ) ==0x1 ; +return cpuid_feature_extract_unsigned_field (mmfr0,ID_AA64MMFR0_BIGENDEL_SHIFT ) ==0x1 || +cpuid_feature_extract_unsigned_field (mmfr0,ID_AA64MMFR0_BIGENDEL0_SHIFT ) ==0x1 ; }void __init setup_cpu_features (void );
arch/arm64/include/asm/kvm_mmu.h +1 -1
@@ -307,7 +307,7 @@ static inline unsigned int kvm_get_vmid_bits(void) {int reg =read_system_reg (SYS_ID_AA64MMFR1_EL1 ); -return (cpuid_feature_extract_field (reg,ID_AA64MMFR1_VMIDBITS_SHIFT ) ==2 ) ?16 :8 ; +return (cpuid_feature_extract_unsigned_field (reg,ID_AA64MMFR1_VMIDBITS_SHIFT ) ==2 ) ?16 :8 ; }#endif /* __ASSEMBLY__ */
arch/arm64/kernel/cpufeature.c +1 -1
@@ -605,7 +605,7 @@ u64 read_system_reg(u32 id)static bool feature_matches (u64 reg,const struct arm64_cpu_capabilities *entry) { -int val =cpuid_feature_extract_field (reg, entry->field_pos); +int val =cpuid_feature_extract_field (reg, entry->field_pos, entry->sign);return val >= entry->min_field_value; }
arch/arm64/kernel/debug-monitors.c +1 -1
@@ -34,7 +34,7 @@/* Determine debug architecture. */ u8 debug_monitors_arch (void ) { -return cpuid_feature_extract_field (read_system_reg (SYS_ID_AA64DFR0_EL1 ), +return cpuid_feature_extract_unsigned_field (read_system_reg (SYS_ID_AA64DFR0_EL1 ),ID_AA64DFR0_DEBUGVER_SHIFT ); }
arch/arm64/kvm/sys_regs.c +1 -1
@@ -688,7 +688,7 @@ static bool trap_dbgidr(struct kvm_vcpu *vcpu, }else {u64 dfr =read_system_reg (SYS_ID_AA64DFR0_EL1 );u64 pfr =read_system_reg (SYS_ID_AA64PFR0_EL1 ); -u32 el3 = !!cpuid_feature_extract_field (pfr,ID_AA64PFR0_EL3_SHIFT ); +u32 el3 = !!cpuid_feature_extract_unsigned_field (pfr,ID_AA64PFR0_EL3_SHIFT ); p->regval = ((((dfr >> ID_AA64DFR0_WRPS_SHIFT) & 0xf) << 28) | (((dfr >> ID_AA64DFR0_BRPS_SHIFT) & 0xf) << 24) |
arch/arm64/mm/context.c +1 -1
@@ -45,7 +45,7 @@ static cpumask_t tlb_flush_pending;static u32 get_cpu_asid_bits (void ) {u32 asid; -int fld =cpuid_feature_extract_field (read_cpuid (ID_AA64MMFR0_EL1 ), +int fld =cpuid_feature_extract_unsigned_field (read_cpuid (ID_AA64MMFR0_EL1 ),ID_AA64MMFR0_ASID_SHIFT );switch (fld) {
Signature · 1 line
1.7.9.5
Catalin Marinas
maintainerPATCH 4/4 arm64: Rename cpuid_feature field extract routines
Quoted 5 lines · Suzuki K. Poulose
Now that we have a clear understanding of the sign of a feature, rename the routines to reflect the sign, so that it is not misused. The
cpuid_feature_extract_field()now accepts a 'sign' parameter.Signed-off-by Suzuki K. Poulose <[email protected]>
[...]
arch/arm64/include/asm/kvm_mmu.h static inline unsigned int kvm_get_vmid_bits(void) · line 311
Quoted 11 lines
arch/arm64/include/asm/kvm_mmu.h +1
-1@@ -307,7 +307,7 @@ static inline unsigned int kvm_get_vmid_bits(void) {int reg =read_system_reg (SYS_ID_AA64MMFR1_EL1 ); -return (cpuid_feature_extract_field (reg,ID_AA64MMFR1_VMIDBITS_SHIFT ) ==2 ) ?16 :8 ; +return (cpuid_feature_extract_unsigned_field (reg,ID_AA64MMFR1_VMIDBITS_SHIFT ) ==2 ) ?16 :8 ; }
Since this is touch a KVM file, it would be good to have an ack from Marc or Christoffer.
Thanks.
Signature · 1 line
Catalin
PATCH 4/4 arm64: Rename cpuid_feature field extract routines
Quoted 15 lines · Catalin Marinas
Quoted 5 lines · Suzuki K. Poulose
Now that we have a clear understanding of the sign of a feature, rename the routines to reflect the sign, so that it is not misused. The
cpuid_feature_extract_field()now accepts a 'sign' parameter.Signed-off-by Suzuki K. Poulose <[email protected]>[...]
Quoted 8 lines
arch/arm64/include/asm/kvm_mmu.h +0
-0@@ -307,7 +307,7 @@ static inline unsigned int kvm_get_vmid_bits(void) {int reg =read_system_reg (SYS_ID_AA64MMFR1_EL1 );
Quoted 6 lines
arch/arm64/include/asm/kvm_mmu.h static inline unsigned int kvm_get_vmid_bits(void) · line 311
Quoted 3 lines
arch/arm64/include/asm/kvm_mmu.h +1
-1-return (cpuid_feature_extract_field (reg,ID_AA64MMFR1_VMIDBITS_SHIFT ) ==2 ) ?16 :8 ; +return (cpuid_feature_extract_unsigned_field (reg,ID_AA64MMFR1_VMIDBITS_SHIFT ) ==2 ) ?16 :8 ; }Since this is touch a KVM file, it would be good to have an ack from Marc or Christoffer.
Works for me.
Acked-by Marc Zyngier <[email protected]>
M.
Signature · 1 line
Jazz is not dead. It just smells funny...
Suzuki K. Poulose
reviewercover arm64: cpufeature: Fix sign of feature bits
In reply to Suzuki K PouloseQuoted 6 lines · Suzuki K Poulose
ARM ARM is getting updated with the guidelines on how to treat the feature values for their sign. This series fixes the handling of sign based on the new update. Also make the capabilities aware of the sign of the feature to use the appropriate helper for extracting the values.
See Patch2 for more details on the rules.
This series applies on top of the "Early CPU feature verification" :
http://lists.infradead.org/pipermail/linux-arm-kernel/2016-January/401727.html
I can send a version based on 4.5-rc1 if this can be picked up for 4.5
Thanks
Suzuki
cover arm64: cpufeature: Fix sign of feature bits
In reply to Suzuki K PouloseQuoted 4 lines · Suzuki K Poulose
ARM ARM is getting updated with the guidelines on how to treat the feature values for their sign. This series fixes the handling of sign based on the new update. Also make the capabilities aware of the sign of the feature to use the appropriate helper for extracting the values.
For the series:
Acked-by Will Deacon <[email protected]>
Will