spi: bcm2835aux: auxiliary spi improvements

From: Stephan Olbrich <[email protected]>

The bitmasks for txempty and idle interrupts were interchanged.

Signed-off-by Stephan Olbrich <[email protected]>

---
  drivers/spi/spi-bcm2835aux.c | 4 ++--
  1 file changed, 2 insertions(+), 2 deletions(-)

drivers/spi/spi-bcm2835aux.c +0 -0

index 7de6f84..ecc73c0 100644

drivers/spi/spi-bcm2835aux.c +2 -0

+#define BCM2835_AUX_SPI_CNTL1_TXEMPTY	0x00000080
+#define BCM2835_AUX_SPI_CNTL1_IDLE	0x00000040
  #define BCM2835_AUX_SPI_CNTL1_MSBF_IN	0x00000002
  #define BCM2835_AUX_SPI_CNTL1_KEEP_IN	0x00000001
 

Hi Stephan,

Am 09.02.2016 um 19:10 schrieb stephanolbrich at gmx.de:

Quoted 15 lines

From: Stephan Olbrich <[email protected]>

The bitmasks for txempty and idle interrupts were interchanged.

Signed-off-by Stephan Olbrich <[email protected]>

---

  drivers/spi/spi-bcm2835aux.c | 4 ++--
  1 file changed, 2 insertions(+), 2 deletions(-)

drivers/spi/spi-bcm2835aux.c +0 -0

index 7de6f84..ecc73c0 100644

drivers/spi/spi-bcm2835aux.c line 78

Quoted 6 lines

drivers/spi/spi-bcm2835aux.c +0 -2

@@ -73,8 +73,8 @@
 
  /* Bitfields in CNTL1 */
  #define BCM2835_AUX_SPI_CNTL1_CSHIGH	0x00000700
 
-#define BCM2835_AUX_SPI_CNTL1_IDLE	0x00000080
-#define BCM2835_AUX_SPI_CNTL1_TXEMPTY	0x00000040

according to a comment in this file these values are from brcm_usrlib/dag/vmcsx/vcinclude/bcm2708_chip/aux_io.h.

So you want to say that at least these 2 are wrong and you took the values from BCM2835-ARM-Peripherals.pdf [1]?

I think it's worth to mention it.

[1] -
https://www.raspberrypi.org/wp-content/uploads/2012/02/BCM2835-ARM-Periphera
ls.pdf

Quoted 5 lines

drivers/spi/spi-bcm2835aux.c +2 -0

+#define BCM2835_AUX_SPI_CNTL1_TXEMPTY	0x00000080
+#define BCM2835_AUX_SPI_CNTL1_IDLE	0x00000040
 
  #define BCM2835_AUX_SPI_CNTL1_MSBF_IN	0x00000002

  #define BCM2835_AUX_SPI_CNTL1_KEEP_IN	0x00000001

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From: Stephan Olbrich <[email protected]>

The bitmasks for txempty and idle interrupts were interchanged.

Signed-off-by Stephan Olbrich <[email protected]>

---
 drivers/spi/spi-bcm2835aux.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

drivers/spi/spi-bcm2835aux.c +0 -0

index 7de6f84..ecc73c0 100644

From fe0e2304f560f81c1673711ac3f9a8c7c3cbb8be Mon Sep 17 00:00:00 2001

From: Stephan Olbrich <[email protected]>

The tx empty irq can be disabled when all data was copied. This prevents unnecessary interrupts while the last bytes are sent.

Signed-off-by Stephan Olbrich <[email protected]>

---
 drivers/spi/spi-bcm2835aux.c | 6 ++++++
 1 file changed, 6 insertions(+)

drivers/spi/spi-bcm2835aux.c +6 -0

index ecc73c0..d2f0067 100644
@@ -212,6 +212,12 @@ static irqreturn_t bcm2835aux_spi_interrupt(int irq, void *dev_id)
 		ret = IRQ_HANDLED;
 	}
 
+	if (!bs->tx_len) {
+		/* disable tx fifo empty interrupt */
+		bcm2835aux_wr(bs, BCM2835_AUX_SPI_CNTL1, bs->cntl[1] |
+			BCM2835_AUX_SPI_CNTL1_IDLE);
+	}
+
 	/* and if rx_len is 0 then wake up completion and disable spi */
 	if (!bs->rx_len) {
 		bcm2835aux_spi_reset_hw(bs);

Signature · 1 line

2.5.0

From f29ab1845f3e2684ba1c6de6c3bd5198e4b1459c Mon Sep 17 00:00:00 2001

From: Stephan Olbrich <[email protected]>

When using reverse polarity for clock (spi-cpol) on a device the clock line gets altered after chip-select has been asserted resulting in an additional clock beat, which confuses hardware.

To avoid this situation this patch moves the setup of polarity (spi-cpol and spi-cpha) outside of the chip-select into prepare_message, which is run prior to asserting chip-select.

Signed-off-by Stephan Olbrich <[email protected]>

---
 drivers/spi/spi-bcm2835aux.c | 54 +++++++++++++++++++++++++++++++-------------
 1 file changed, 38 insertions(+), 16 deletions(-)

drivers/spi/spi-bcm2835aux.c +2 -5

index d2f0067..b90aa34 100644
@@ -218,9 +218,9 @@ static irqreturn_t bcm2835aux_spi_interrupt(int irq, void *dev_id)
 			BCM2835_AUX_SPI_CNTL1_IDLE);
 	}
 
-	/* and if rx_len is 0 then wake up completion and disable spi */
+	/* and if rx_len is 0 then disable interrupts and wake up completion */
 	if (!bs->rx_len) {
-		bcm2835aux_spi_reset_hw(bs);
+		bcm2835aux_wr(bs, BCM2835_AUX_SPI_CNTL1, bs->cntl[1]);
 		complete(&master->xfer_completion);
 	}
 

@@ -313,9 +313,6 @@ static int bcm2835aux_spi_transfer_one_poll(struct spi_master *master,
 		}
 	}
 
-	/* Transfer complete - reset SPI HW */
-	bcm2835aux_spi_reset_hw(bs);
-
 	/* and return without waiting for completion */
 	return 0;
 }

This patch surprised me. I would have thought that the solution was to just write the updated CNTL bits for CPOL and wait a moment whenever it changes. The CS only gets asserted later on when we get some data in the TX FIFO, so I think you're just reducing the chance of losing the race to get our inverted clock noticed by the device before the CS gets asserted.

Quoted 6 lines · Eric Anholt

This patch surprised me. I would have thought that the solution was to just write the updated CNTL bits for CPOL and wait a moment whenever it changes. The CS only gets asserted later on when we get some data in the TX FIFO, so I think you're just reducing the chance of losing the race to get our inverted clock noticed by the device before the CS gets asserted.

We support (and generally want to use since hardware chip selects are often very limited in what they do) chip select on GPIO.

Oops, this makes more sense now. Subject even mentioned gpio, and a GPIO CS must be getting set around the transfer_one call. I'll be ready to send an r-b for a v2 with the speed update bug fixed (unless transfer speeds are guaranteed to be constant between a prepare and unprepare).

Quoted 4 lines

Oops, this makes more sense now. Subject even mentioned gpio, and a GPIO CS must be getting set around the transfer_one call. I'll be ready to send an r-b for a v2 with the speed update bug fixed (unless transfer speeds are guaranteed to be constant between a prepare and unprepare).

No guarantee that they'll not change, especially in a situation where we have two devices on different speeds on a bus working at the same time.

Am Wednesday 10 February 2016, 19:02:04 schrieb Mark Brown:

Quoted 6 lines · Eric Anholt

Quoted 4 lines

Oops, this makes more sense now. Subject even mentioned gpio, and a GPIO CS must be getting set around the transfer_one call. I'll be ready to send an r-b for a v2 with the speed update bug fixed (unless transfer speeds are guaranteed to be constant between a prepare and unprepare).

Quoted 2 lines

No guarantee that they'll not change, especially in a situation where we have two devices on different speeds on a bus working at the same time.

Are you saying, that between a prepare and unprepare there could be transfers for another device? Then all the clock setting couldn't be done in prepare either.
Apart from that, if two transfers in the same message are not guarantied to have the same speed, this still needs to be fixed. I'll roll a v2.

Am Wednesday 10 February 2016, 19:02:04 schrieb Mark Brown:

Quoted 2 lines

No guarantee that they'll not change, especially in a situation where we have two devices on different speeds on a bus working at the same time.

Are you saying, that between a prepare and unprepare there could be transfers for another device? Then all the clock setting couldn't be done in prepare either.
Apart from that, if two transfers in the same message are not guarantied to have the same speed, this still needs to be fixed. I'll roll a v2.

drivers/spi/spi-bcm2835aux.c +1 -7

 	spi_used_hz = clk_hz / (2 * (speed + 1));
 
-	/* handle all the modes */
-	if (spi->mode & SPI_CPOL)
-		bs->cntl[0] |= BCM2835_AUX_SPI_CNTL0_CPOL;
-	if (spi->mode & SPI_CPHA)
-		bs->cntl[0] |= BCM2835_AUX_SPI_CNTL0_CPHA_OUT |
-			       BCM2835_AUX_SPI_CNTL0_CPHA_IN;
-
 	/* set transmit buffers and length */
 	bs->tx_buf = tfr->tx_buf;
 	bs->rx_buf = tfr->rx_buf;
 

@@ -388,6 +374,40 @@ static int bcm2835aux_spi_transfer_one(struct spi_master *master,
 	return bcm2835aux_spi_transfer_one_irq(master, spi, tfr);
 }
 
+

From: Stephan Olbrich <[email protected]>

The auxiliary spi supports only CPHA=0 modes as the first bit is always output to the pin before the first clock cycle. In CPHA=1 modes the first clock edge outputs the second bit hence the slave can never read the first bit.

From: Stephan Olbrich <[email protected]>

The auxiliary spi supports only CPHA=0 modes as the first bit is always output to the pin before the first clock cycle. In CPHA=1 modes the first clock edge outputs the second bit hence the slave can never read the first bit.

Also the CPHA registers switch between clocking data in/out on rising/falling edge hence depend on the CPOL setting.

Signed-off-by Stephan Olbrich <[email protected]>

---
 drivers/spi/spi-bcm2835aux.c | 10 +++++-----
 1 file changed, 5 insertions(+), 5 deletions(-)

drivers/spi/spi-bcm2835aux.c +1 -1

index b90aa34..169f521 100644
@@ -386,12 +386,12 @@ static int bcm2835aux_spi_prepare_message(struct spi_master *master,
 	bs->cntl[1] = BCM2835_AUX_SPI_CNTL1_MSBF_IN;
 
 	/* handle all the modes */
-	if (spi->mode & SPI_CPOL)
+	if (spi->mode & SPI_CPOL) {
 		bs->cntl[0] |= BCM2835_AUX_SPI_CNTL0_CPOL;

Quoted 40 lines · stephanolbrich at gmx.de

From: Stephan Olbrich <[email protected]>

The auxiliary spi supports only CPHA=0 modes as the first bit is always output to the pin before the first clock cycle. In CPHA=1 modes the first clock edge outputs the second bit hence the slave can never read the first bit.

Also the CPHA registers switch between clocking data in/out on rising/falling edge hence depend on the CPOL setting.

Signed-off-by Stephan Olbrich <[email protected]>

---

 drivers/spi/spi-bcm2835aux.c | 10 +++++-----
 1 file changed, 5 insertions(+), 5 deletions(-)

drivers/spi/spi-bcm2835aux.c +0 -0

index b90aa34..169f521 100644
@@ -386,12 +386,12 @@ static int bcm2835aux_spi_prepare_message(struct

spi_master *master,>

drivers/spi/spi-bcm2835aux.c +5 -5

 	bs->cntl[1] = BCM2835_AUX_SPI_CNTL1_MSBF_IN;
 
 	/* handle all the modes */
 
-	if (spi->mode & SPI_CPOL)
+	if (spi->mode & SPI_CPOL) {
 
 		bs->cntl[0] |= BCM2835_AUX_SPI_CNTL0_CPOL;
 
-	if (spi->mode & SPI_CPHA)
-		bs->cntl[0] |= BCM2835_AUX_SPI_CNTL0_CPHA_OUT |
-			       BCM2835_AUX_SPI_CNTL0_CPHA_IN;
-
+		bs->cntl[0] |= BCM2835_AUX_SPI_CNTL0_CPHA_OUT;
+	} else {
+		bs->cntl[0] |= BCM2835_AUX_SPI_CNTL0_CPHA_IN;
+	}

drivers/spi/spi-bcm2835aux.c static int bcm2835aux_spi_prepare_message(struct spi_master *master, · line 396

Quoted 2 lines

drivers/spi/spi-bcm2835aux.c +0 -0

 	bcm2835aux_wr(bs, BCM2835_AUX_SPI_CNTL1, bs->cntl[1]);
 	bcm2835aux_wr(bs, BCM2835_AUX_SPI_CNTL0, bs->cntl[0]);

(Note for other readers: A better name for CNTL0_CPHA_* would be CNTL0_*_RISING).

I think you're right about not actually supporting CPHA. I don't see wany way to keep bit 1 out lasting through the first full clock cycle. I think Stefan's right that we should drop CPHA from MODE_BITS (actually, MODE_BITS would be nicer if we just merged it into its one user, I think).

Am Tuesday 09 February 2016, 16:13:06 schrieb Eric Anholt:

Quoted 41 lines

Quoted 40 lines · stephanolbrich at gmx.de

From: Stephan Olbrich <[email protected]>

The auxiliary spi supports only CPHA=0 modes as the first bit is always output to the pin before the first clock cycle. In CPHA=1 modes the first clock edge outputs the second bit hence the slave can never read the first bit.

Also the CPHA registers switch between clocking data in/out on rising/falling edge hence depend on the CPOL setting.

Signed-off-by Stephan Olbrich <[email protected]>

---

 drivers/spi/spi-bcm2835aux.c | 10 +++++-----
 1 file changed, 5 insertions(+), 5 deletions(-)

drivers/spi/spi-bcm2835aux.c +0 -0

index b90aa34..169f521 100644
@@ -386,12 +386,12 @@ static int bcm2835aux_spi_prepare_message(struct

spi_master *master,>

drivers/spi/spi-bcm2835aux.c +5 -5

 	bs->cntl[1] = BCM2835_AUX_SPI_CNTL1_MSBF_IN;
 
 	/* handle all the modes */
 
-	if (spi->mode & SPI_CPOL)
+	if (spi->mode & SPI_CPOL) {
 
 		bs->cntl[0] |= BCM2835_AUX_SPI_CNTL0_CPOL;
 
-	if (spi->mode & SPI_CPHA)
-		bs->cntl[0] |= BCM2835_AUX_SPI_CNTL0_CPHA_OUT |
-			       BCM2835_AUX_SPI_CNTL0_CPHA_IN;
-
+		bs->cntl[0] |= BCM2835_AUX_SPI_CNTL0_CPHA_OUT;
+	} else {
+		bs->cntl[0] |= BCM2835_AUX_SPI_CNTL0_CPHA_IN;
+	}

Quoted 5 lines

drivers/spi/spi-bcm2835aux.c static int bcm2835aux_spi_prepare_message(struct spi_master *master, · line 396

Quoted 2 lines

drivers/spi/spi-bcm2835aux.c +0 -0

 	bcm2835aux_wr(bs, BCM2835_AUX_SPI_CNTL1, bs->cntl[1]);
 	bcm2835aux_wr(bs, BCM2835_AUX_SPI_CNTL0, bs->cntl[0]);

(Note for other readers: A better name for CNTL0_CPHA_* would be CNTL0_*_RISING).

Should I rename them?

Quoted 26 lines · stephanolbrich at gmx.de

From: Stephan Olbrich <[email protected]>

The auxiliary spi supports only CPHA=0 modes as the first bit is always output to the pin before the first clock cycle. In CPHA=1 modes the first clock edge outputs the second bit hence the slave can never read the first bit.

Also the CPHA registers switch between clocking data in/out on rising/falling edge hence depend on the CPOL setting.

Signed-off-by Stephan Olbrich <[email protected]>

---
drivers/spi/spi-bcm2835aux.c | 10 +++++-----

1 file changed, 5 insertions(+), 5 deletions(-)

drivers/spi/spi-bcm2835aux.c +1 -1

index b90aa34..169f521 100644
@@ -386,12 +386,12 @@ static int bcm2835aux_spi_prepare_message(struct spi_master *master,
 	bs->cntl[1] = BCM2835_AUX_SPI_CNTL1_MSBF_IN;
 
 	/* handle all the modes */
-	if (spi->mode & SPI_CPOL)
+	if (spi->mode & SPI_CPOL) {
 		bs->cntl[0] |= BCM2835_AUX_SPI_CNTL0_CPOL;

drivers/spi/spi-bcm2835aux.c static int bcm2835aux_spi_prepare_message(struct spi_master *master, · line 396

Quoted 10 lines

drivers/spi/spi-bcm2835aux.c +4 -4

-	if (spi->mode & SPI_CPHA)
-		bs->cntl[0] |= BCM2835_AUX_SPI_CNTL0_CPHA_OUT |
-			       BCM2835_AUX_SPI_CNTL0_CPHA_IN;
-
+		bs->cntl[0] |= BCM2835_AUX_SPI_CNTL0_CPHA_OUT;
+	} else {
+		bs->cntl[0] |= BCM2835_AUX_SPI_CNTL0_CPHA_IN;
+	}
 	bcm2835aux_wr(bs, BCM2835_AUX_SPI_CNTL1, bs->cntl[1]);
 	bcm2835aux_wr(bs, BCM2835_AUX_SPI_CNTL0, bs->cntl[0]);

(Note for other readers: A better name for CNTL0_CPHA_* would be CNTL0_*_RISING).

I think you're right about not actually supporting CPHA. I don't see wany way to keep bit 1 out lasting through the first full clock cycle. I think Stefan's right that we should drop CPHA from MODE_BITS (actually, MODE_BITS would be nicer if we just merged it into its one user, I think).

However, this hunk appears to be correct and would fix the timing of our data going out in the CPOL=0 case and of sampling IN data for CPOL=1.

Quoted 48 lines · Eric Anholt

Quoted 39 lines · stephanolbrich at gmx.de

From: Stephan Olbrich <[email protected]>

The auxiliary spi supports only CPHA=0 modes as the first bit is always output to the pin before the first clock cycle. In CPHA=1 modes the first clock edge outputs the second bit hence the slave can never read the first bit.

Also the CPHA registers switch between clocking data in/out on rising/falling edge hence depend on the CPOL setting.

Signed-off-by Stephan Olbrich <[email protected]>

---
drivers/spi/spi-bcm2835aux.c | 10 +++++-----

1 file changed, 5 insertions(+), 5 deletions(-)

drivers/spi/spi-bcm2835aux.c +0 -0

index b90aa34..169f521 100644
@@ -386,12 +386,12 @@ static int bcm2835aux_spi_prepare_message(struct

spi_master *master,>>

	bs->cntl[1] = BCM2835_AUX_SPI_CNTL1_MSBF_IN;
	
	/* handle all the modes */

drivers/spi/spi-bcm2835aux.c +1 -1

-	if (spi->mode & SPI_CPOL)
+	if (spi->mode & SPI_CPOL) {

		bs->cntl[0] |= BCM2835_AUX_SPI_CNTL0_CPOL;

drivers/spi/spi-bcm2835aux.c +4 -4

-	if (spi->mode & SPI_CPHA)
-		bs->cntl[0] |= BCM2835_AUX_SPI_CNTL0_CPHA_OUT |
-			       BCM2835_AUX_SPI_CNTL0_CPHA_IN;
-
+		bs->cntl[0] |= BCM2835_AUX_SPI_CNTL0_CPHA_OUT;
+	} else {
+		bs->cntl[0] |= BCM2835_AUX_SPI_CNTL0_CPHA_IN;
+	}

Quoted 2 lines

	bcm2835aux_wr(bs, BCM2835_AUX_SPI_CNTL1, bs->cntl[1]);
	bcm2835aux_wr(bs, BCM2835_AUX_SPI_CNTL0, bs->cntl[0]);

(Note for other readers: A better name for CNTL0_CPHA_* would be CNTL0_*_RISING).

Quoted 8 lines

I think you're right about not actually supporting CPHA. I don't see wany way to keep bit 1 out lasting through the first full clock cycle. I think Stefan's right that we should drop CPHA from MODE_BITS (actually, MODE_BITS would be nicer if we just merged it into its one user, I think).

However, this hunk appears to be correct and would fix the timing of our data going out in the CPOL=0 case and of sampling IN data for CPOL=1.

Are you sure that CPHA is not working?

I have used the following to test all combinations:
for C in "" "-C"; do
for O in "" "-O"; do
for H in "" "-H"; do

    spidev_test -vD /dev/*.1 $H $O -p "\x00\x82\x00" -s 1000000;

done
done
done

I have tested with the 4.5-rc3 kernel without any of your patches.

And looked at the logic-analyzer: I see distinct waveform pattern for clk and data for all events!

Martin,

Am Thursday 11 February 2016, 16:25:43 schrieb Martin Sperl:

Quoted 68 lines

Quoted 48 lines · Eric Anholt

Quoted 39 lines · stephanolbrich at gmx.de

From: Stephan Olbrich <[email protected]>

The auxiliary spi supports only CPHA=0 modes as the first bit is always output to the pin before the first clock cycle. In CPHA=1 modes the first clock edge outputs the second bit hence the slave can never read the first bit.

Also the CPHA registers switch between clocking data in/out on rising/falling edge hence depend on the CPOL setting.

Signed-off-by Stephan Olbrich <[email protected]>

---
drivers/spi/spi-bcm2835aux.c | 10 +++++-----

1 file changed, 5 insertions(+), 5 deletions(-)

drivers/spi/spi-bcm2835aux.c +0 -0

index b90aa34..169f521 100644
@@ -386,12 +386,12 @@ static int bcm2835aux_spi_prepare_message(struct

spi_master *master,>>

	bs->cntl[1] = BCM2835_AUX_SPI_CNTL1_MSBF_IN;
	
	/* handle all the modes */

drivers/spi/spi-bcm2835aux.c +1 -1

-	if (spi->mode & SPI_CPOL)
+	if (spi->mode & SPI_CPOL) {

		bs->cntl[0] |= BCM2835_AUX_SPI_CNTL0_CPOL;

drivers/spi/spi-bcm2835aux.c +4 -4

-	if (spi->mode & SPI_CPHA)
-		bs->cntl[0] |= BCM2835_AUX_SPI_CNTL0_CPHA_OUT |
-			       BCM2835_AUX_SPI_CNTL0_CPHA_IN;
-
+		bs->cntl[0] |= BCM2835_AUX_SPI_CNTL0_CPHA_OUT;
+	} else {
+		bs->cntl[0] |= BCM2835_AUX_SPI_CNTL0_CPHA_IN;
+	}

Quoted 2 lines

	bcm2835aux_wr(bs, BCM2835_AUX_SPI_CNTL1, bs->cntl[1]);
	bcm2835aux_wr(bs, BCM2835_AUX_SPI_CNTL0, bs->cntl[0]);

(Note for other readers: A better name for CNTL0_CPHA_* would be CNTL0_*_RISING).

Quoted 8 lines

I think you're right about not actually supporting CPHA. I don't see wany way to keep bit 1 out lasting through the first full clock cycle. I think Stefan's right that we should drop CPHA from MODE_BITS (actually, MODE_BITS would be nicer if we just merged it into its one user, I think).

However, this hunk appears to be correct and would fix the timing of our data going out in the CPOL=0 case and of sampling IN data for CPOL=1.

Are you sure that CPHA is not working?

I have used the following to test all combinations:
for C in "" "-C"; do
for O in "" "-O"; do
for H in "" "-H"; do
spidev_test -vD /dev/*.1 $H $O -p "\x00\x82\x00" -s 1000000;
done
done
done

Quoted 4 lines

I have tested with the 4.5-rc3 kernel without any of your patches.

And looked at the logic-analyzer: I see distinct waveform pattern for clk and data for all events!

The problem I see, is not that there is no waveform but that it has the wrong timing.
I'll make an example:
Data is 0xAA,0xFF, CPOL=1, CPHA=1
What happens is this:
CS goes active and MOSI goes high (first bit in 1)
After a short time, SCLK goes from low to high and MOSI goes to low (second bit is 0)
Then SCLK goes low (sampling data)
Then SCLK goes high and MOSI goes high (third bit is 1)
and so on.
At the end with the last rising edge of SCLK MOSI goes to low and stays there while SCLK goes to low and then CS to inactive.

So the slave has no chance to get the first bit but gets an additional 0 at the end.
It may not be easy visible with 0x00,0x82,0x00 as data, so could you repeat your test with 0xAA,0xFF if you see the same as I do or not?

Quoted 6 lines

At the end with the last rising edge of SCLK MOSI goes to low and stays there while SCLK goes to low and then CS to inactive.

So the slave has no chance to get the first bit but gets an additional 0 at the end.

Quoted 2 lines

It may not be easy visible with 0x00,0x82,0x00 as data, so could you repeat your test with 0xAA,0xFF if you see the same as I do or not?

I did retest also with 0x81,0x00,0x81 and saw my expected behavior - but maybe me understanding of those modes is wrong.

I will send you the images for the pattern I have generated with 0x81, 0x00, 0x81 as a personal email.