arm64: Initial support for Marvell Armada 7K/8K

This commit adds the base Device Tree files for the Armada 7K and 8K SoCs, as well as the Armada 8040 DB board.

The Armada 7020, 7040 (7K family) and 8020, 8040 (8K family) are composed of:

- An AP806 block that contains the CPU core and a few basic peripherals. The AP806 is available in dual core configurations (used in 7020 and 8020) and quad core configurations (used in 8020 and 8040).

- One or two CP110 blocks that contain all the high-speed interfaces (SATA, PCIe, Ethernet, etc.). The 7K family chips have one CP110, and the 8K family chips have two CP110, giving them twice the number of HW interfaces.

In order to represent this from a Device Tree point of view, this commit creates the following hierarchy:

* armada-ap806.dtsi - definitions common to dual/quad ap806
* armada-ap806-dual.dtsi - description of the two CPUs
* armada-7020.dtsi - description of the 7020 SoC
* armada-8020.dtsi - description of the 8020 SoC
* armada-ap806-quad.dtsi - description of the four CPUs
* armada-7040.dtsi - description of the 7040 SoC
* armada-7040-db.dts - description of the 7040 board
* armada-8040.dtsi - description of the 8040 SoC

The CP110 blocks are not described yet, and will be part of future patch series.

Signed-off-by Thomas Petazzoni <[email protected]>

---
 .../bindings/arm/marvell/armada-7k-8k.txt          |  24 +++
 arch/arm64/boot/dts/marvell/Makefile               |   1 +
 arch/arm64/boot/dts/marvell/armada-7020.dtsi       |  54 +++++
 arch/arm64/boot/dts/marvell/armada-7040-db.dts     |  92 ++++++++
 arch/arm64/boot/dts/marvell/armada-7040.dtsi       |  54 +++++
 arch/arm64/boot/dts/marvell/armada-8020.dtsi       |  54 +++++
 arch/arm64/boot/dts/marvell/armada-8040.dtsi       |  54 +++++
 arch/arm64/boot/dts/marvell/armada-ap806-dual.dtsi |  71 +++++++
 arch/arm64/boot/dts/marvell/armada-ap806-quad.dtsi |  84 ++++++++
 arch/arm64/boot/dts/marvell/armada-ap806.dtsi      | 235 +++++++++++++++++++++
 10 files changed, 723 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/arm/marvell/armada-7k-8k.txt

 create mode 100644 arch/arm64/boot/dts/marvell/armada-7020.dtsi
 create mode 100644 arch/arm64/boot/dts/marvell/armada-7040-db.dts
 create mode 100644 arch/arm64/boot/dts/marvell/armada-7040.dtsi
 create mode 100644 arch/arm64/boot/dts/marvell/armada-8020.dtsi
 create mode 100644 arch/arm64/boot/dts/marvell/armada-8040.dtsi
 create mode 100644 arch/arm64/boot/dts/marvell/armada-ap806-dual.dtsi
 create mode 100644 arch/arm64/boot/dts/marvell/armada-ap806-quad.dtsi
 create mode 100644 arch/arm64/boot/dts/marvell/armada-ap806.dtsi

arch/arm64/boot/dts/marvell/armada-ap806.dtsi new file +76 -0

new file mode 100644
index 0000000..3303db2
@@ -0,0 +1,235 @@
+/*
+ * Copyright (C) 2016 Marvell Technology Group Ltd.
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPLv2 or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This library is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This library is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/*
+ * Device Tree file for Marvell Armada AP806.
+ */
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+/dts-v1/;
+
+/ {
+	model = "Marvell Armada AP806";
+	compatible = "marvell,armada-ap806";
+	#address-cells = <2>;
+	#size-cells = <2>;
+
+	psci {
+		compatible = "arm,psci-0.2";
+		method = "smc";
+	};
+
+
+	ap806 {
+		#address-cells = <2>;
+		#size-cells = <2>;
+		compatible = "simple-bus";
+		interrupt-parent = <&gic>;
+		ranges;
+
+		config-space {
+			#address-cells = <1>;
+			#size-cells = <1>;
+			compatible = "simple-bus";
+			ranges = <0x0 0x0 0xf0000000 0x1000000>;
+
+			gic: interrupt-controller at 210000 {

arch/arm64/boot/dts/marvell/armada-ap806.dtsi new file +22 -0

+				      <0x240000 0x2000>,
+				      <0x260000 0x2000>;
+
+				gic_v2m0: v2m at 280000 {
+					compatible = "arm,gic-v2m-frame";
+					msi-controller;
+					reg = <0x280000 0x1000>;
+					arm,msi-base-spi = <160>;
+					arm,msi-num-spis = <32>;
+				};
+				gic_v2m1: v2m at 290000 {
+					compatible = "arm,gic-v2m-frame";
+					msi-controller;
+					reg = <0x290000 0x1000>;
+					arm,msi-base-spi = <192>;
+					arm,msi-num-spis = <32>;
+				};
+				gic_v2m2: v2m at 2a0000 {
+					compatible = "arm,gic-v2m-frame";
+					msi-controller;
+					reg = <0x2a0000 0x1000>;
+					arm,msi-base-spi = <224>;

arch/arm64/boot/dts/marvell/armada-ap806.dtsi line 86

Quoted 3 lines

arch/arm64/boot/dts/marvell/armada-ap806.dtsi new file +3 -0

+				interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
+				reg = <0x210000 0x1000>,
+				      <0x220000 0x1000>,

Assuming we do have a GIC400 here (which is extremely likely), the GICC block should be at least 8kB to reflect the fact that this is a GICv2.

Marc,

Thanks for the review!

Quoted 6 lines · Marc Zyngier

arch/arm64/boot/dts/marvell/armada-ap806.dtsi line 86

Quoted 3 lines

arch/arm64/boot/dts/marvell/armada-ap806.dtsi new file +3 -0

+				interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
+				reg = <0x210000 0x1000>,
+				      <0x220000 0x1000>,

Assuming we do have a GIC400 here (which is extremely likely), the GICC block should be at least 8kB to reflect the fact that this is a GICv2.

According to the datasheet I have, the GICD, GICC, GICV and GICH blocks are all 0x10000 in size. Not sure the entire 0x10000 is actually used, but th memory map is pretty clear.

Quoted 3 lines

According to the datasheet I have, the GICD, GICC, GICV and GICH blocks are all 0x10000 in size. Not sure the entire 0x10000 is actually used, but th memory map is pretty clear.

No, that's just a way to make sure that you can give the GICV block to a guest while using 64k pages.

Talking about GICV: are you sure it is 0x10000 and not 0x20000? SBSA recommends to have the first 4kB GICV page aliased over 64kB, and the second 4kB page over the second 64kB block. That is to ensure that a hypervisor can trap access to GICV_DIR register independently of the rest of the virtual CPU interface.

But hey, almost everybody got it wrong so far, so I wouldn't be surprised if that was broken on this platform as well...

This commit adds the base Device Tree files for the Armada 7K and 8K SoCs, as well as the Armada 8040 DB board.

The Armada 7020, 7040 (7K family) and 8020, 8040 (8K family) are composed of:

- An AP806 block that contains the CPU core and a few basic peripherals. The AP806 is available in dual core configurations (used in 7020 and 8020) and quad core configurations (used in 8020 and 8040).

- One or two CP110 blocks that contain all the high-speed interfaces (SATA, PCIe, Ethernet, etc.). The 7K family chips have one CP110, and the 8K family chips have two CP110, giving them twice the number of HW interfaces.

arch/arm64/boot/dts/marvell/armada-ap806-quad.dtsi new file +84 -0

new file mode 100644
index 0000000..baa7d9a
@@ -0,0 +1,84 @@
+/*
+ * Copyright (C) 2016 Marvell Technology Group Ltd.
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPLv2 or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This library is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This library is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/*
+ * Device Tree file for Marvell Armada AP806.
+ */
+
+#include "armada-ap806.dtsi"
+
+/ {
+	model = "Marvell Armada AP806 Quad";
+	compatible = "marvell,armada-ap806-quad", "marvell,armada-ap806";
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu at 000 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a72", "arm,armv8";
+			reg = <0x000>;
+			enable-method = "psci";
+		};
+		cpu at 001 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a72", "arm,armv8";
+			reg = <0x001>;
+			enable-method = "psci";
+		};
+		cpu at 100 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a72", "arm,armv8";
+			reg = <0x100>;
+			enable-method = "psci";
+		};
+		cpu at 101 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a72", "arm,armv8";
+			reg = <0x101>;
+			enable-method = "psci";
+		};
+	};
+
+};
+

arch/arm64/boot/dts/marvell/armada-ap806.dtsi new file +48 -0

new file mode 100644
index 0000000..3303db2
@@ -0,0 +1,235 @@
+/*
+ * Copyright (C) 2016 Marvell Technology Group Ltd.
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPLv2 or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This library is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This library is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/*
+ * Device Tree file for Marvell Armada AP806.
+ */
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+

arch/arm64/boot/dts/marvell/armada-ap806.dtsi new file +10 -0

+		method = "smc";
+	};
+
+
+	ap806 {
+		#address-cells = <2>;
+		#size-cells = <2>;
+		compatible = "simple-bus";
+		interrupt-parent = <&gic>;
+		ranges;

arch/arm64/boot/dts/marvell/armada-ap806.dtsi line 58

Quoted 8 lines

arch/arm64/boot/dts/marvell/armada-ap806.dtsi new file +8 -0

+/ {
+	model = "Marvell Armada AP806";
+	compatible = "marvell,armada-ap806";
+	#address-cells = <2>;
+	#size-cells = <2>;
+
+	psci {
+		compatible = "arm,psci-0.2";

I guess the firmware is also psci-1.0 compatible.

Quoted 10 lines

arch/arm64/boot/dts/marvell/armada-ap806.dtsi new file +10 -0

+	ap806 {
+		#address-cells = <2>;
+		#size-cells = <2>;
+		compatible = "simple-bus";
+		interrupt-parent = <&gic>;
+		ranges;
+
+		config-space {
+			#address-cells = <1>;
+			#size-cells = <1>;

arch/arm64/boot/dts/marvell/armada-ap806.dtsi line 78

Quoted 6 lines

arch/arm64/boot/dts/marvell/armada-ap806.dtsi new file +6 -0

+			compatible = "simple-bus";
+			ranges = <0x0 0x0 0xf0000000 0x1000000>;
+
+			gic: interrupt-controller at 210000 {
+				compatible = "arm,cortex-a15-gic",
+					     "arm,cortex-a9-gic";

I guess the GIC is neither the one in cortex-a15 or cortex-a9.

Hello,

Quoted 10 lines · Jisheng Zhang

arch/arm64/boot/dts/marvell/armada-ap806.dtsi line 58

Quoted 8 lines

arch/arm64/boot/dts/marvell/armada-ap806.dtsi new file +8 -0

+/ {
+	model = "Marvell Armada AP806";
+	compatible = "marvell,armada-ap806";
+	#address-cells = <2>;
+	#size-cells = <2>;
+
+	psci {
+		compatible = "arm,psci-0.2";  

I guess the firmware is also psci-1.0 compatible.

At boot time, the kernel queries the PSCI firmware, and it says:

[    0.000000] psci: probing for conduit method from DT.
[    0.000000] psci: PSCIv0.2 detected in firmware.
[    0.000000] psci: Using standard PSCI v0.2 function IDs

So I think psci-0.2 is correct here. Should this change for the production revision of the chip, we'll send an update to the Device Tree accordingly.

Quoted 11 lines

Quoted 11 lines

arch/arm64/boot/dts/marvell/armada-ap806.dtsi new file +10 -0

+	ap806 {
+		#address-cells = <2>;
+		#size-cells = <2>;
+		compatible = "simple-bus";
+		interrupt-parent = <&gic>;
+		ranges;
+
+		config-space {
+			#address-cells = <1>;
+			#size-cells = <1>;

Quoted 8 lines

arch/arm64/boot/dts/marvell/armada-ap806.dtsi line 78

Quoted 6 lines

arch/arm64/boot/dts/marvell/armada-ap806.dtsi new file +6 -0

+			compatible = "simple-bus";
+			ranges = <0x0 0x0 0xf0000000 0x1000000>;
+
+			gic: interrupt-controller at 210000 {
+				compatible = "arm,cortex-a15-gic",
+					     "arm,cortex-a9-gic";  

I guess the GIC is neither the one in cortex-a15 or cortex-a9.

What makes you think this?

The GIC is a GIC400, which is GICv2 compliant, and arm-cortex-a15-gic /

arm-cortex-a9-gic are valid compatible strings to identify a GICv2 compliant interrupt controller.

See:

arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi: compatible = "arm,gic-400", "arm,cortex-a15-gic";
arch/arm64/boot/dts/amd/amd-seattle-soc.dtsi: compatible = "arm,gic-400", "arm,cortex-a15-gic";
arch/arm64/boot/dts/apm/apm-shadowcat.dtsi: compatible = "arm,cortex-a15-gic";
arch/arm64/boot/dts/apm/apm-storm.dtsi: compatible = "arm,cortex-a15-gic";
arch/arm64/boot/dts/arm/foundation-v8.dts: compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic";
arch/arm64/boot/dts/arm/juno-base.dtsi: compatible = "arm,gic-400", "arm,cortex-a15-gic";
arch/arm64/boot/dts/arm/rtsm_ve-aemv8a.dts: compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic";
arch/arm64/boot/dts/marvell/armada-ap806.dtsi: compatible = "arm,cortex-a15-gic",
arch/arm64/boot/dts/nvidia/tegra132.dtsi: compatible = "arm,cortex-a15-gic";
arch/arm64/boot/dts/xilinx/zynqmp.dtsi: compatible = "arm,gic-400", "arm,cortex-a15-gic";

Or do you have a more specific reason to think that this compatible string is wrong?

Best regards,

Thomas

Quoted 5 lines

Quoted 1 line

I guess the GIC is neither the one in cortex-a15 or cortex-a9.

What makes you think this?

The GIC is a GIC400, which is GICv2 compliant, and arm-cortex-a15-gic /

That's my point, why not "gic-400" explicitly?

Hello,

This series adds initial support for the new Armada 7K and 8K Marvell 64 bits processors. Details about those processors based on the Cortex-A72 can be found at:

http://www.marvell.com/embedded-processors/armada-70xx/
http://www.marvell.com/embedded-processors/armada-80xx/

One characteristic of those processors is that internally they are built from several components:

- One "AP", which contains the processor itself and a few core IP blocks. The AP in 7K and 8K is called AP806, and is available on two variants: dual Cortex-A72 and quad Cortex-A72.

- Or or two "CP", which contains most of the I/Os (SATA, PCIe, etc.). The CP in 7K and 8K is called CP110. One CP110 is available in the 7K family, while two CP110 are available in the 8K family, doubling the number of I/O interfaces.

The support added in this series only brings minimal support for the AP side (and not yet all IP blocks, obviously). Support for the CP part will come in the future.

Since the series touches similar files as the Armada 3700 series from Gregory Clement, it is based on it.

The new code looks ok, but I think I need to resubmit my cleanup of the Documentation/arm/Marvell/README fiel that I submitted a while ago, which now conflicts with the changes you did in patch 3.

If you don't mind, can you add my patch to your series to resolve the conflict? I'll resend in a minute.

Arnd,

Quoted 4 lines · Arnd Bergmann

The new code looks ok, but I think I need to resubmit my cleanup of the Documentation/arm/Marvell/README fiel that I submitted a while ago, which now conflicts with the changes you did in patch 3.

Quoted 2 lines

If you don't mind, can you add my patch to your series to resolve the conflict? I'll resend in a minute.

Before my series, Gregory's series is already doing some changes to the Marvell README file, though it is possible that they don't conflict with your changes. Anyway, we'll take care of merging your file, I'll sync with Gregory on this.