exynos: video: Convert exynos LCD driver to use driver model

similarity index 100%
rename from drivers/video/exynos_dp.c
rename to drivers/video/exynos/exynos_dp.c

similarity index 100%
rename from drivers/video/exynos_dp_lowlevel.c
rename to drivers/video/exynos/exynos_dp_lowlevel.c

similarity index 100%
rename from drivers/video/exynos_dp_lowlevel.h
rename to drivers/video/exynos/exynos_dp_lowlevel.h

similarity index 100%
rename from drivers/video/exynos_fb.c
rename to drivers/video/exynos/exynos_fb.c

similarity index 100%
rename from drivers/video/exynos_fb.h
rename to drivers/video/exynos/exynos_fb.h

similarity index 100%
rename from drivers/video/exynos_fimd.c
rename to drivers/video/exynos/exynos_fimd.c

similarity index 100%
rename from drivers/video/exynos_mipi_dsi.c
rename to drivers/video/exynos/exynos_mipi_dsi.c

similarity index 100%
rename from drivers/video/exynos_mipi_dsi_common.c
rename to drivers/video/exynos/exynos_mipi_dsi_common.c

similarity index 100%
rename from drivers/video/exynos_mipi_dsi_common.h
rename to drivers/video/exynos/exynos_mipi_dsi_common.h

similarity index 100%
rename from drivers/video/exynos_mipi_dsi_lowlevel.c
rename to drivers/video/exynos/exynos_mipi_dsi_lowlevel.c

similarity index 100%
rename from drivers/video/exynos_mipi_dsi_lowlevel.h
rename to drivers/video/exynos/exynos_mipi_dsi_lowlevel.h

similarity index 100%
rename from drivers/video/exynos_pwm_bl.c
rename to drivers/video/exynos/exynos_pwm_bl.c

index 8494817..1bd49ee 100644
@@ -9,8 +9,8 @@
 #include <common.h>
 #include <asm/arch/mipi_dsim.h>
 
-#include "exynos_mipi_dsi_lowlevel.h"
-#include "exynos_mipi_dsi_common.h"
+#include "exynos/exynos_mipi_dsi_lowlevel.h"
+#include "exynos/exynos_mipi_dsi_common.h"
 
 static void s6e8ax0_panel_cond(struct mipi_dsim_device *dsim_dev)
 {

index 14a1692..abcfcf3 100644
@@ -288,9 +288,7 @@ static inline unsigned int __attribute__((no_instrument_function)) \
 SAMSUNG_BASE(adc, ADC_BASE)
 SAMSUNG_BASE(clock, CLOCK_BASE)
 SAMSUNG_BASE(ace_sfr, ACE_SFR_BASE)
-SAMSUNG_BASE(dp, DP_BASE)
 SAMSUNG_BASE(sysreg, SYSREG_BASE)
-SAMSUNG_BASE(fimd, FIMD_BASE)
 SAMSUNG_BASE(i2c, I2C_BASE)
 SAMSUNG_BASE(i2s, I2S_BASE)
 SAMSUNG_BASE(mipi_dsim, MIPI_DSIM_BASE)

index acb5bc8..e417cf8 100644
@@ -22,7 +22,6 @@ struct exynos_dp *dp_regs;
 
 void exynos_dp_set_base_addr(void)
 {
-#if CONFIG_IS_ENABLED(OF_CONTROL)
 	unsigned int node = fdtdec_next_compatible(gd->fdt_blob,
 					0, COMPAT_SAMSUNG_EXYNOS5_DP);
 	if (node <= 0)

@@ -32,9 +31,6 @@ void exynos_dp_set_base_addr(void)
 								node, "reg");
 	if (dp_regs == NULL)
 		debug("Can't get the DP base address\n");
-#else
-	dp_regs = (struct exynos_dp *)samsung_get_base_dp();
-#endif
 }
 
 static void exynos_dp_enable_video_input(unsigned int enable)

index 69edc3a..39e3ade 100644
@@ -28,7 +28,6 @@ DECLARE_GLOBAL_DATA_PTR;
 
 static unsigned int panel_width, panel_height;
 
-#if CONFIG_IS_ENABLED(OF_CONTROL)
 vidinfo_t panel_info  = {
 	/*
 	 * Insert a value here so that we don't end up in the BSS

@@ -36,7 +35,6 @@ vidinfo_t panel_info  = {
 	 */
 	.vl_col = -1,
 };
-#endif
 
 ushort *configuration_get_cmap(void)
 {

@@ -126,7 +124,6 @@ static void lcd_panel_on(vidinfo_t *vid)
 
 	exynos_backlight_on(1);
 
-#if CONFIG_IS_ENABLED(OF_CONTROL)
 	node = fdtdec_next_compatible(gd->fdt_blob, 0,
 						COMPAT_SAMSUNG_EXYNOS_FIMD);
 	if (node <= 0) {

@@ -141,7 +138,6 @@ static void lcd_panel_on(vidinfo_t *vid)
 				   &bl_en_gpio,
 				   GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE);
 
-#endif
 	exynos_cfg_ldo();
 
 	exynos_enable_ldo(1);

@@ -150,7 +146,6 @@ static void lcd_panel_on(vidinfo_t *vid)
 		exynos_mipi_dsi_init();
 }
 
-#if CONFIG_IS_ENABLED(OF_CONTROL)
 int exynos_lcd_early_init(const void *blob)
 {
 	unsigned int node;

@@ -288,22 +283,16 @@ int exynos_lcd_early_init(const void *blob)
 
 	return 0;
 }
-#endif
 
 void lcd_ctrl_init(void *lcdbase)
 {
 	set_system_display_ctrl();
 	set_lcd_clk();
 
-#if CONFIG_IS_ENABLED(OF_CONTROL)
 #ifdef CONFIG_EXYNOS_MIPI_DSIM
 	exynos_init_dsim_platform_data(&panel_info);
 #endif
 	exynos_lcd_misc_init(&panel_info);
-#else
-	/* initialize parameters which is specific to panel. */
-	init_panel_info(&panel_info);
-#endif
 
 	panel_width = panel_info.vl_width;
 	panel_height = panel_info.vl_height;

index ac001a8..019d88f 100644
@@ -251,7 +251,6 @@ void exynos_fimd_window_off(unsigned int win_id)
 	writel(cfg, &fimd_ctrl->winshmap);
 }
 
-#if CONFIG_IS_ENABLED(OF_CONTROL)
 /*
 * The reset value for FIMD SYSMMU register MMU_CTRL is 3
 * on Exynos5420 and newer versions.

@@ -289,13 +288,11 @@ void exynos_fimd_disable_sysmmu(void)
 		writel(0x0, sysmmufimd);
 	}
 }
-#endif
 
 void exynos_fimd_lcd_init(vidinfo_t *vid)
 {
 	unsigned int cfg = 0, rgb_mode;
 	unsigned int offset;
-#if CONFIG_IS_ENABLED(OF_CONTROL)
 	unsigned int node;
 
 	node = fdtdec_next_compatible(gd->fdt_blob,

@@ -311,10 +308,6 @@ void exynos_fimd_lcd_init(vidinfo_t *vid)
 	if (fdtdec_get_bool(gd->fdt_blob, node, "samsung,disable-sysmmu"))
 		exynos_fimd_disable_sysmmu();
 
-#else
-	fimd_ctrl = (struct exynos_fb *)samsung_get_base_fimd();
-#endif
-
 	offset = exynos_fimd_get_base_offset();
 
 	/* store panel info to global variable */

index b597acc..5001e16 100644
@@ -28,11 +28,9 @@
 DECLARE_GLOBAL_DATA_PTR;
 
 static struct exynos_platform_mipi_dsim *dsim_pd;
-#if CONFIG_IS_ENABLED(OF_CONTROL)
 static struct mipi_dsim_config dsim_config_dt;
 static struct exynos_platform_mipi_dsim dsim_platform_data_dt;
 static struct mipi_dsim_lcd_device mipi_lcd_device_dt;
-#endif
 
 struct mipi_dsim_ddi {
 	int				bus_id;

@@ -249,7 +247,6 @@ void exynos_set_dsim_platform_data(struct exynos_platform_mipi_dsim *pd)
 	dsim_pd = pd;
 }
 
-#if CONFIG_IS_ENABLED(OF_CONTROL)
 int exynos_dsim_config_parse_dt(const void *blob)
 {
 	int node;

@@ -334,4 +331,3 @@ void exynos_init_dsim_platform_data(vidinfo_t *vid)
 
 	dsim_pd = &dsim_platform_data_dt;
 }
-#endif

index 3969a6a..e1769f0 100644
@@ -77,6 +77,4 @@ typedef struct vidinfo {
 	unsigned int dual_lcd_enabled;
 } vidinfo_t;
 
-void init_panel_info(vidinfo_t *vid);
-
 #endif

index c9e8e06..a77b5c8 100644
@@ -369,7 +369,8 @@ int exynos_mipi_dsi_register_lcd_device(struct mipi_dsim_lcd_device
 						*lcd_dev);
 
 void exynos_set_dsim_platform_data(struct exynos_platform_mipi_dsim *pd);
-void exynos_init_dsim_platform_data(vidinfo_t *vid);
+struct vidinfo;
+void exynos_init_dsim_platform_data(struct vidinfo *vid);
 
 /* panel driver init based on mipi dsi interface */
 void s6e8ax0_init(void);

index 39e3ade..90d2038 100644
@@ -28,7 +28,7 @@ DECLARE_GLOBAL_DATA_PTR;
 
 static unsigned int panel_width, panel_height;
 
-vidinfo_t panel_info  = {
+struct vidinfo panel_info  = {
 	/*
 	 * Insert a value here so that we don't end up in the BSS
 	 * Reference: drivers/video/tegra.c

@@ -45,7 +45,7 @@ ushort *configuration_get_cmap(void)
 #endif
 }
 
-static void exynos_lcd_init_mem(void *lcdbase, vidinfo_t *vid)
+static void exynos_lcd_init_mem(void *lcdbase, struct vidinfo *vid)
 {
 	unsigned long palette_size;
 	unsigned int fb_size;

@@ -58,7 +58,7 @@ static void exynos_lcd_init_mem(void *lcdbase, vidinfo_t *vid)
 			(unsigned long)fb_size, palette_size);
 }
 
-static void exynos_lcd_init(vidinfo_t *vid)
+static void exynos_lcd_init(struct vidinfo *vid)
 {
 	exynos_fimd_lcd_init(vid);
 

@@ -94,12 +94,12 @@ __weak void exynos_backlight_reset(void)
 {
 }
 
-__weak int exynos_lcd_misc_init(vidinfo_t *vid)
+__weak int exynos_lcd_misc_init(struct vidinfo *vid)
 {
 	return 0;
 }
 
-static void lcd_panel_on(vidinfo_t *vid)
+static void lcd_panel_on(struct vidinfo *vid)
 {
 	struct gpio_desc pwm_out_gpio;
 	struct gpio_desc bl_en_gpio;

index 019d88f..e6fb5d1 100644
@@ -22,7 +22,7 @@
 DECLARE_GLOBAL_DATA_PTR;
 
 static unsigned long *lcd_base_addr;
-static vidinfo_t *pvid;
+static struct vidinfo *pvid;
 static struct exynos_fb *fimd_ctrl;
 
 void exynos_fimd_lcd_init_mem(u_long screen_base, u_long fb_size,

@@ -123,7 +123,7 @@ static void exynos_fimd_set_buffer_address(unsigned int win_id)
 			EXYNOS_BUFFER_OFFSET(win_id));
 }
 
-static void exynos_fimd_set_clock(vidinfo_t *pvid)
+static void exynos_fimd_set_clock(struct vidinfo *pvid)
 {
 	unsigned int cfg = 0, div = 0, remainder, remainder_div;
 	unsigned long pixel_clock;

@@ -289,7 +289,7 @@ void exynos_fimd_disable_sysmmu(void)
 	}
 }
 
-void exynos_fimd_lcd_init(vidinfo_t *vid)
+void exynos_fimd_lcd_init(struct vidinfo *vid)
 {
 	unsigned int cfg = 0, rgb_mode;
 	unsigned int offset;

index 925d515..85c5e0d 100644
@@ -465,7 +465,7 @@ int exynos_mipi_dsi_enable_frame_done_int(struct mipi_dsim_device *dsim,
 }
 
 static void convert_to_fb_videomode(struct fb_videomode *mode1,
-				vidinfo_t *mode2)
+				    struct vidinfo *mode2)
 {
 	mode1->xres = mode2->vl_width;
 	mode1->yres = mode2->vl_height;

@@ -482,10 +482,10 @@ int exynos_mipi_dsi_set_display_mode(struct mipi_dsim_device *dsim,
 {
 	struct exynos_platform_mipi_dsim *dsim_pd;
 	struct fb_videomode lcd_video;
-	vidinfo_t *vid;
+	struct vidinfo *vid;
 
 	dsim_pd = (struct exynos_platform_mipi_dsim *)dsim->pd;
-	vid = (vidinfo_t *)dsim_pd->lcd_panel_info;
+	vid = (struct vidinfo *)dsim_pd->lcd_panel_info;
 
 	convert_to_fb_videomode(&lcd_video, vid);
 

index 90d2038..a3acdcc 100644
@@ -45,22 +45,9 @@ ushort *configuration_get_cmap(void)
 #endif
 }
 
-static void exynos_lcd_init_mem(void *lcdbase, struct vidinfo *vid)
+static void exynos_lcd_init(struct vidinfo *vid, ulong lcd_base)
 {
-	unsigned long palette_size;
-	unsigned int fb_size;
-
-	fb_size = vid->vl_row * vid->vl_col * (NBITS(vid->vl_bpix) >> 3);
-
-	palette_size = NBITS(vid->vl_bpix) == 8 ? 256 : 16;
-
-	exynos_fimd_lcd_init_mem((unsigned long)lcdbase,
-			(unsigned long)fb_size, palette_size);
-}
-
-static void exynos_lcd_init(struct vidinfo *vid)
-{
-	exynos_fimd_lcd_init(vid);
+	exynos_fimd_lcd_init(vid, lcd_base);
 
 	/* Enable flushing after LCD writes if requested */
 	lcd_set_flush_dcache(1);

@@ -297,9 +284,7 @@ void lcd_ctrl_init(void *lcdbase)
 	panel_width = panel_info.vl_width;
 	panel_height = panel_info.vl_height;
 
-	exynos_lcd_init_mem(lcdbase, &panel_info);
-
-	exynos_lcd_init(&panel_info);
+	exynos_lcd_init(&panel_info, (ulong)lcdbase);
 }
 
 void lcd_enable(void)

index 2c2f94b..833be6a 100644
@@ -35,7 +35,7 @@ enum exynos_cpu_auto_cmd_rate {
 
 void exynos_fimd_lcd_init_mem(unsigned long screen_base, unsigned long fb_size,
 	unsigned long palette_size);
-void exynos_fimd_lcd_init(vidinfo_t *vid);
+void exynos_fimd_lcd_init(struct vidinfo *vid, ulong lcd_base_address);
 unsigned long exynos_fimd_calc_fbsize(void);
 
 #endif

index e6fb5d1..a1de9ac 100644
@@ -21,16 +21,9 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-static unsigned long *lcd_base_addr;
 static struct vidinfo *pvid;
 static struct exynos_fb *fimd_ctrl;
 
-void exynos_fimd_lcd_init_mem(u_long screen_base, u_long fb_size,
-		u_long palette_size)
-{
-	lcd_base_addr = (unsigned long *)screen_base;
-}
-
 static void exynos_fimd_set_dualrgb(unsigned int enabled)
 {
 	unsigned int cfg = 0;

@@ -47,7 +40,8 @@ static void exynos_fimd_set_dualrgb(unsigned int enabled)
 	writel(cfg, &fimd_ctrl->dualrgb);
 }
 
-static void exynos_fimd_set_dp_clkcon(unsigned int enabled)
+static void exynos_fimd_set_dp_clkcon(struct vidinfo *pvid,
+				      unsigned int enabled)
 {
 	unsigned int cfg = 0;
 

@@ -57,7 +51,7 @@ static void exynos_fimd_set_dp_clkcon(unsigned int enabled)
 	writel(cfg, &fimd_ctrl->dp_mie_clkcon);
 }
 
-static void exynos_fimd_set_par(unsigned int win_id)
+static void exynos_fimd_set_par(struct vidinfo *pvid, unsigned int win_id)
 {
 	unsigned int cfg = 0;
 

@@ -109,11 +103,13 @@ static void exynos_fimd_set_par(unsigned int win_id)
 			EXYNOS_VIDOSD(win_id));
 }
 
-static void exynos_fimd_set_buffer_address(unsigned int win_id)
+static void exynos_fimd_set_buffer_address(struct vidinfo *pvid,
+					   unsigned int win_id,
+					   ulong lcd_base_addr)
 {
 	unsigned long start_addr, end_addr;
 
-	start_addr = (unsigned long)lcd_base_addr;
+	start_addr = lcd_base_addr;
 	end_addr = start_addr + ((pvid->vl_col * (NBITS(pvid->vl_bpix) / 8)) *
 				pvid->vl_row);
 

@@ -289,7 +285,7 @@ void exynos_fimd_disable_sysmmu(void)
 	}
 }
 
-void exynos_fimd_lcd_init(struct vidinfo *vid)
+void exynos_fimd_lcd_init(struct vidinfo *vid, ulong lcd_base_address)
 {
 	unsigned int cfg = 0, rgb_mode;
 	unsigned int offset;

@@ -367,10 +363,10 @@ void exynos_fimd_lcd_init(struct vidinfo *vid)
 	writel(cfg, &fimd_ctrl->vidcon0);
 
 	/* set par */
-	exynos_fimd_set_par(pvid->win_id);
+	exynos_fimd_set_par(pvid, pvid->win_id);
 
 	/* set memory address */
-	exynos_fimd_set_buffer_address(pvid->win_id);
+	exynos_fimd_set_buffer_address(pvid, pvid->win_id, lcd_base_address);
 
 	/* set buffer size */
 	cfg = EXYNOS_VIDADDR_PAGEWIDTH(pvid->vl_col * NBITS(pvid->vl_bpix) / 8) |

@@ -393,7 +389,7 @@ void exynos_fimd_lcd_init(struct vidinfo *vid)
 	/* window on */
 	exynos_fimd_window_on(pvid->win_id);
 
-	exynos_fimd_set_dp_clkcon(pvid->dp_enabled);
+	exynos_fimd_set_dp_clkcon(pvid, pvid->dp_enabled);
 }
 
 unsigned long exynos_fimd_calc_fbsize(void)

index 833be6a..f59cce0 100644
@@ -36,6 +36,6 @@ enum exynos_cpu_auto_cmd_rate {
 void exynos_fimd_lcd_init_mem(unsigned long screen_base, unsigned long fb_size,
 	unsigned long palette_size);
 void exynos_fimd_lcd_init(struct vidinfo *vid, ulong lcd_base_address);
-unsigned long exynos_fimd_calc_fbsize(void);
+unsigned long exynos_fimd_calc_fbsize(struct vidinfo *pvid);
 
 #endif

160 lines not on this page · raw message

index e1769f0..1f6c6c7 100644
@@ -75,6 +75,7 @@ typedef struct vidinfo {
 	unsigned int sclk_div;
 
 	unsigned int dual_lcd_enabled;
+	struct exynos_fb *fimd_ctrl;
 } vidinfo_t;
 
 #endif

index a3acdcc..abc6091 100644
@@ -26,8 +26,6 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-static unsigned int panel_width, panel_height;
-
 struct vidinfo panel_info  = {
 	/*
 	 * Insert a value here so that we don't end up in the BSS

@@ -281,16 +279,14 @@ void lcd_ctrl_init(void *lcdbase)
 #endif
 	exynos_lcd_misc_init(&panel_info);
 
-	panel_width = panel_info.vl_width;
-	panel_height = panel_info.vl_height;
-
 	exynos_lcd_init(&panel_info, (ulong)lcdbase);
 }
 
 void lcd_enable(void)
 {
 	if (panel_info.logo_on) {
-		memset((void *) gd->fb_base, 0, panel_width * panel_height *
+		memset((void *)gd->fb_base, 0,
+		       panel_info.vl_width * panel_info.vl_height *
 				(NBITS(panel_info.vl_bpix) >> 3));
 	}
 

index 0d5d090..9945c4b 100644
@@ -38,20 +38,20 @@ static void exynos_dp_disp_info(struct edp_disp_info *disp_info)
 	return;
 }
 
-static int exynos_dp_init_dp(void)
+static int exynos_dp_init_dp(struct exynos_dp *dp_regs)
 {
 	int ret;
-	exynos_dp_reset();
+	exynos_dp_reset(dp_regs);
 
 	/* SW defined function Normal operation */
-	exynos_dp_enable_sw_func(DP_ENABLE);
+	exynos_dp_enable_sw_func(dp_regs, DP_ENABLE);
 
-	ret = exynos_dp_init_analog_func();
+	ret = exynos_dp_init_analog_func(dp_regs);
 	if (ret != EXYNOS_DP_SUCCESS)
 		return ret;
 
-	exynos_dp_init_hpd();
-	exynos_dp_init_aux();
+	exynos_dp_init_hpd(dp_regs);
+	exynos_dp_init_aux(dp_regs);
 
 	return ret;
 }

@@ -67,7 +67,7 @@ static unsigned char exynos_dp_calc_edid_check_sum(unsigned char *edid_data)
 	return sum;
 }
 
-static unsigned int exynos_dp_read_edid(void)
+static unsigned int exynos_dp_read_edid(struct exynos_dp *dp_regs)
 {
 	unsigned char edid[EDID_BLOCK_LENGTH * 2];
 	unsigned int extend_block = 0;

@@ -82,14 +82,15 @@ static unsigned int exynos_dp_read_edid(void)
 	 */
 
 	/* Read Extension Flag, Number of 128-byte EDID extension blocks */
-	exynos_dp_read_byte_from_i2c(I2C_EDID_DEVICE_ADDR, EDID_EXTENSION_FLAG,
-			&extend_block);
+	exynos_dp_read_byte_from_i2c(dp_regs, I2C_EDID_DEVICE_ADDR,
+				     EDID_EXTENSION_FLAG, &extend_block);
 
 	if (extend_block > 0) {
 		printf("DP EDID data includes a single extension!\n");
 
 		/* Read EDID data */
-		retval = exynos_dp_read_bytes_from_i2c(I2C_EDID_DEVICE_ADDR,
+		retval = exynos_dp_read_bytes_from_i2c(dp_regs,
+						I2C_EDID_DEVICE_ADDR,
 						EDID_HEADER_PATTERN,
 						EDID_BLOCK_LENGTH,
 						&edid[EDID_HEADER_PATTERN]);

@@ -104,7 +105,8 @@ static unsigned int exynos_dp_read_edid(void)
 		}
 
 		/* Read additional EDID data */
-		retval = exynos_dp_read_bytes_from_i2c(I2C_EDID_DEVICE_ADDR,
+		retval = exynos_dp_read_bytes_from_i2c(dp_regs,
+				I2C_EDID_DEVICE_ADDR,
 				EDID_BLOCK_LENGTH,
 				EDID_BLOCK_LENGTH,
 				&edid[EDID_BLOCK_LENGTH]);

@@ -118,19 +120,22 @@ static unsigned int exynos_dp_read_edid(void)
 			return -1;
 		}
 
-		exynos_dp_read_byte_from_dpcd(DPCD_TEST_REQUEST,
-					&test_vector);
+		exynos_dp_read_byte_from_dpcd(dp_regs, DPCD_TEST_REQUEST,
+					      &test_vector);
 		if (test_vector & DPCD_TEST_EDID_READ) {
-			exynos_dp_write_byte_to_dpcd(DPCD_TEST_EDID_CHECKSUM,
+			exynos_dp_write_byte_to_dpcd(dp_regs,
+				DPCD_TEST_EDID_CHECKSUM,
 				edid[EDID_BLOCK_LENGTH + EDID_CHECKSUM]);
-			exynos_dp_write_byte_to_dpcd(DPCD_TEST_RESPONSE,
+			exynos_dp_write_byte_to_dpcd(dp_regs,
+				DPCD_TEST_RESPONSE,
 				DPCD_TEST_EDID_CHECKSUM_WRITE);
 		}
 	} else {
 		debug("DP EDID data does not include any extensions.\n");
 
 		/* Read EDID data */
-		retval = exynos_dp_read_bytes_from_i2c(I2C_EDID_DEVICE_ADDR,
+		retval = exynos_dp_read_bytes_from_i2c(dp_regs,
+				I2C_EDID_DEVICE_ADDR,
 				EDID_HEADER_PATTERN,
 				EDID_BLOCK_LENGTH,
 				&edid[EDID_HEADER_PATTERN]);

@@ -145,12 +150,13 @@ static unsigned int exynos_dp_read_edid(void)
 			return -1;
 		}
 
-		exynos_dp_read_byte_from_dpcd(DPCD_TEST_REQUEST,
+		exynos_dp_read_byte_from_dpcd(dp_regs, DPCD_TEST_REQUEST,
 			&test_vector);
 		if (test_vector & DPCD_TEST_EDID_READ) {
-			exynos_dp_write_byte_to_dpcd(DPCD_TEST_EDID_CHECKSUM,
-				edid[EDID_CHECKSUM]);
-			exynos_dp_write_byte_to_dpcd(DPCD_TEST_RESPONSE,
+			exynos_dp_write_byte_to_dpcd(dp_regs,
+				DPCD_TEST_EDID_CHECKSUM, edid[EDID_CHECKSUM]);
+			exynos_dp_write_byte_to_dpcd(dp_regs,
+				DPCD_TEST_RESPONSE,
 				DPCD_TEST_EDID_CHECKSUM_WRITE);
 		}
 	}

@@ -160,7 +166,8 @@ static unsigned int exynos_dp_read_edid(void)
 	return 0;
 }
 
-static unsigned int exynos_dp_handle_edid(struct edp_device_info *edp_info)
+static unsigned int exynos_dp_handle_edid(struct exynos_dp *dp_regs,
+					  struct edp_device_info *edp_info)
 {
 	unsigned char buf[12];
 	unsigned int ret;

@@ -178,8 +185,8 @@ static unsigned int exynos_dp_handle_edid(struct edp_device_info *edp_info)
 	retry_cnt = 5;
 	while (retry_cnt) {
 		/* Read DPCD 0x0000-0x000b */
-		ret = exynos_dp_read_bytes_from_dpcd(DPCD_DPCD_REV, 12,
-				buf);
+		ret = exynos_dp_read_bytes_from_dpcd(dp_regs, DPCD_DPCD_REV, 12,
+						     buf);
 		if (ret != EXYNOS_DP_SUCCESS) {
 			if (retry_cnt == 0) {
 				printf("DP read_byte_from_dpcd() failed\n");

@@ -227,7 +234,7 @@ static unsigned int exynos_dp_handle_edid(struct edp_device_info *edp_info)
 		return -EINVAL;
 	}
 
-	ret = exynos_dp_read_edid();
+	ret = exynos_dp_read_edid(dp_regs);
 	if (ret != EXYNOS_DP_SUCCESS) {
 		printf("DP exynos_dp_read_edid() failed\n");
 		return -EINVAL;

@@ -236,19 +243,20 @@ static unsigned int exynos_dp_handle_edid(struct edp_device_info *edp_info)
 	return ret;
 }
 
-static void exynos_dp_init_training(void)
+static void exynos_dp_init_training(struct exynos_dp *dp_regs)
 {
 	/*
 	 * MACRO_RST must be applied after the PLL_LOCK to avoid
 	 * the DP inter pair skew issue for at least 10 us
 	 */
-	exynos_dp_reset_macro();
+	exynos_dp_reset_macro(dp_regs);
 
 	/* All DP analog module power up */
-	exynos_dp_set_analog_power_down(POWER_ALL, 0);
+	exynos_dp_set_analog_power_down(dp_regs, POWER_ALL, 0);
 }
 
-static unsigned int exynos_dp_link_start(struct edp_device_info *edp_info)
+static unsigned int exynos_dp_link_start(struct exynos_dp *dp_regs,
+					 struct edp_device_info *edp_info)
 {
 	unsigned char buf[5];
 	unsigned int ret = 0;

@@ -263,33 +271,32 @@ static unsigned int exynos_dp_link_start(struct edp_device_info *edp_info)
 	edp_info->lt_info.cr_loop[3] = 0;
 
 		/* Set sink to D0 (Sink Not Ready) mode. */
-		ret = exynos_dp_write_byte_to_dpcd(DPCD_SINK_POWER_STATE,
-				DPCD_SET_POWER_STATE_D0);
+	ret = exynos_dp_write_byte_to_dpcd(dp_regs, DPCD_SINK_POWER_STATE,
+					   DPCD_SET_POWER_STATE_D0);
 	if (ret != EXYNOS_DP_SUCCESS) {
 		printf("DP write_dpcd_byte failed\n");
 		return ret;
 	}
 
 	/* Set link rate and count as you want to establish */
-	exynos_dp_set_link_bandwidth(edp_info->lane_bw);
-	exynos_dp_set_lane_count(edp_info->lane_cnt);
+	exynos_dp_set_link_bandwidth(dp_regs, edp_info->lane_bw);
+	exynos_dp_set_lane_count(dp_regs, edp_info->lane_cnt);
 
 	/* Setup RX configuration */
 	buf[0] = edp_info->lane_bw;
 	buf[1] = edp_info->lane_cnt;
 
-	ret = exynos_dp_write_bytes_to_dpcd(DPCD_LINK_BW_SET, 2,
-			buf);
+	ret = exynos_dp_write_bytes_to_dpcd(dp_regs, DPCD_LINK_BW_SET, 2, buf);
 	if (ret != EXYNOS_DP_SUCCESS) {
 		printf("DP write_dpcd_byte failed\n");
 		return ret;
 	}
 
-	exynos_dp_set_lane_pre_emphasis(PRE_EMPHASIS_LEVEL_0,
+	exynos_dp_set_lane_pre_emphasis(dp_regs, PRE_EMPHASIS_LEVEL_0,
 			edp_info->lane_cnt);
 
 	/* Set training pattern 1 */
-	exynos_dp_set_training_pattern(TRAINING_PTN1);
+	exynos_dp_set_training_pattern(dp_regs, TRAINING_PTN1);
 
 	/* Set RX training pattern */
 	buf[0] = DPCD_SCRAMBLING_DISABLED | DPCD_TRAINING_PATTERN_1;

@@ -303,8 +310,8 @@ static unsigned int exynos_dp_link_start(struct edp_device_info *edp_info)
 	buf[4] = DPCD_PRE_EMPHASIS_SET_PATTERN_2_LEVEL_0 |
 		DPCD_VOLTAGE_SWING_SET_PATTERN_1_LEVEL_0;
 
-	ret = exynos_dp_write_bytes_to_dpcd(DPCD_TRAINING_PATTERN_SET,
-			5, buf);
+	ret = exynos_dp_write_bytes_to_dpcd(dp_regs, DPCD_TRAINING_PATTERN_SET,
+					    5, buf);
 	if (ret != EXYNOS_DP_SUCCESS) {
 		printf("DP write_dpcd_byte failed\n");
 		return ret;

@@ -313,14 +320,14 @@ static unsigned int exynos_dp_link_start(struct edp_device_info *edp_info)
 	return ret;
 }
 
-static unsigned int exynos_dp_training_pattern_dis(void)
+static unsigned int exynos_dp_training_pattern_dis(struct exynos_dp *dp_regs)
 {
 	unsigned int ret = EXYNOS_DP_SUCCESS;
 
-	exynos_dp_set_training_pattern(DP_NONE);
+	exynos_dp_set_training_pattern(dp_regs, DP_NONE);
 
-	ret = exynos_dp_write_byte_to_dpcd(DPCD_TRAINING_PATTERN_SET,
-			DPCD_TRAINING_PATTERN_DISABLED);
+	ret = exynos_dp_write_byte_to_dpcd(dp_regs, DPCD_TRAINING_PATTERN_SET,
+					   DPCD_TRAINING_PATTERN_DISABLED);
 	if (ret != EXYNOS_DP_SUCCESS) {
 		printf("DP request_link_training_req failed\n");
 		return -EAGAIN;

@@ -329,13 +336,14 @@ static unsigned int exynos_dp_training_pattern_dis(void)
 	return ret;
 }
 
-static unsigned int exynos_dp_enable_rx_to_enhanced_mode(unsigned char enable)
+static unsigned int exynos_dp_enable_rx_to_enhanced_mode(
+		struct exynos_dp *dp_regs, unsigned char enable)
 {
 	unsigned char data;
 	unsigned int ret = EXYNOS_DP_SUCCESS;
 
-	ret = exynos_dp_read_byte_from_dpcd(DPCD_LANE_COUNT_SET,
-			&data);
+	ret = exynos_dp_read_byte_from_dpcd(dp_regs, DPCD_LANE_COUNT_SET,
+					    &data);
 	if (ret != EXYNOS_DP_SUCCESS) {
 		printf("DP read_from_dpcd failed\n");
 		return -EAGAIN;

@@ -346,8 +354,7 @@ static unsigned int exynos_dp_enable_rx_to_enhanced_mode(unsigned char enable)
 	else
 		data = DPCD_LN_COUNT_SET(data);
 
-	ret = exynos_dp_write_byte_to_dpcd(DPCD_LANE_COUNT_SET,
-			data);
+	ret = exynos_dp_write_byte_to_dpcd(dp_regs, DPCD_LANE_COUNT_SET, data);
 	if (ret != EXYNOS_DP_SUCCESS) {
 			printf("DP write_to_dpcd failed\n");
 			return -EAGAIN;

@@ -357,23 +364,25 @@ static unsigned int exynos_dp_enable_rx_to_enhanced_mode(unsigned char enable)
 	return ret;
 }
 
-static unsigned int exynos_dp_set_enhanced_mode(unsigned char enhance_mode)
+static unsigned int exynos_dp_set_enhanced_mode(struct exynos_dp *dp_regs,
+						unsigned char enhance_mode)
 {
 	unsigned int ret = EXYNOS_DP_SUCCESS;
 
-	ret = exynos_dp_enable_rx_to_enhanced_mode(enhance_mode);
+	ret = exynos_dp_enable_rx_to_enhanced_mode(dp_regs, enhance_mode);
 	if (ret != EXYNOS_DP_SUCCESS) {
 		printf("DP rx_enhance_mode failed\n");
 		return -EAGAIN;
 	}
 
-	exynos_dp_enable_enhanced_mode(enhance_mode);
+	exynos_dp_enable_enhanced_mode(dp_regs, enhance_mode);
 
 	return ret;
 }
 
-static int exynos_dp_read_dpcd_lane_stat(struct edp_device_info *edp_info,
-		unsigned char *status)
+static int exynos_dp_read_dpcd_lane_stat(struct exynos_dp *dp_regs,
+					 struct edp_device_info *edp_info,
+					 unsigned char *status)
 {
 	unsigned int ret, i;
 	unsigned char buf[2];

@@ -385,7 +394,8 @@ static int exynos_dp_read_dpcd_lane_stat(struct edp_device_info *edp_info,
 	shift_val[2] = 0;
 	shift_val[3] = 4;
 
-	ret = exynos_dp_read_bytes_from_dpcd(DPCD_LANE0_1_STATUS, 2, buf);
+	ret = exynos_dp_read_bytes_from_dpcd(dp_regs, DPCD_LANE0_1_STATUS, 2,
+					     buf);
 	if (ret != EXYNOS_DP_SUCCESS) {
 		printf("DP read lane status failed\n");
 		return ret;

@@ -404,8 +414,8 @@ static int exynos_dp_read_dpcd_lane_stat(struct edp_device_info *edp_info,
 	return ret;
 }
 
-static unsigned int exynos_dp_read_dpcd_adj_req(unsigned char lane_num,
-		unsigned char *sw, unsigned char *em)
+static unsigned int exynos_dp_read_dpcd_adj_req(struct exynos_dp *dp_regs,
+		unsigned char lane_num, unsigned char *sw, unsigned char *em)
 {
 	unsigned int ret = EXYNOS_DP_SUCCESS;
 	unsigned char buf;

@@ -415,7 +425,7 @@ static unsigned int exynos_dp_read_dpcd_adj_req(unsigned char lane_num,
 	/* lane_num value is used as array index, so this range 0 ~ 3 */
 	dpcd_addr = DPCD_ADJUST_REQUEST_LANE0_1 + (lane_num / 2);
 
-	ret = exynos_dp_read_byte_from_dpcd(dpcd_addr, &buf);
+	ret = exynos_dp_read_byte_from_dpcd(dp_regs, dpcd_addr, &buf);
 	if (ret != EXYNOS_DP_SUCCESS) {
 		printf("DP read adjust request failed\n");
 		return -EAGAIN;

@@ -427,17 +437,18 @@ static unsigned int exynos_dp_read_dpcd_adj_req(unsigned char lane_num,
 	return ret;
 }
 
-static int exynos_dp_equalizer_err_link(struct edp_device_info *edp_info)
+static int exynos_dp_equalizer_err_link(struct exynos_dp *dp_regs,
+					struct edp_device_info *edp_info)
 {
 	int ret;
 
-	ret = exynos_dp_training_pattern_dis();
+	ret = exynos_dp_training_pattern_dis(dp_regs);
 	if (ret != EXYNOS_DP_SUCCESS) {
 		printf("DP training_pattern_disable() failed\n");
 		edp_info->lt_info.lt_status = DP_LT_FAIL;
 	}
 
-	ret = exynos_dp_set_enhanced_mode(edp_info->dpcd_efc);
+	ret = exynos_dp_set_enhanced_mode(dp_regs, edp_info->dpcd_efc);
 	if (ret != EXYNOS_DP_SUCCESS) {
 		printf("DP set_enhanced_mode() failed\n");
 		edp_info->lt_info.lt_status = DP_LT_FAIL;

@@ -446,7 +457,8 @@ static int exynos_dp_equalizer_err_link(struct edp_device_info *edp_info)
 	return ret;
 }
 
-static int exynos_dp_reduce_link_rate(struct edp_device_info *edp_info)
+static int exynos_dp_reduce_link_rate(struct exynos_dp *dp_regs,
+				      struct edp_device_info *edp_info)
 {
 	int ret;
 

@@ -456,11 +468,11 @@ static int exynos_dp_reduce_link_rate(struct edp_device_info *edp_info)
 		edp_info->lt_info.lt_status = DP_LT_START;
 		ret = EXYNOS_DP_SUCCESS;
 	} else {
-		ret = exynos_dp_training_pattern_dis();
+		ret = exynos_dp_training_pattern_dis(dp_regs);
 		if (ret != EXYNOS_DP_SUCCESS)
 			printf("DP training_patter_disable() failed\n");
 
-		ret = exynos_dp_set_enhanced_mode(edp_info->dpcd_efc);
+		ret = exynos_dp_set_enhanced_mode(dp_regs, edp_info->dpcd_efc);
 		if (ret != EXYNOS_DP_SUCCESS)
 			printf("DP set_enhanced_mode() failed\n");
 

@@ -470,8 +482,8 @@ static int exynos_dp_reduce_link_rate(struct edp_device_info *edp_info)
 	return ret;
 }
 
-static unsigned int exynos_dp_process_clock_recovery(struct edp_device_info
-							*edp_info)
+static unsigned int exynos_dp_process_clock_recovery(struct exynos_dp *dp_regs,
+					struct edp_device_info *edp_info)
 {
 	unsigned int ret = EXYNOS_DP_SUCCESS;
 	unsigned char lane_stat;

@@ -484,7 +496,7 @@ static unsigned int exynos_dp_process_clock_recovery(struct edp_device_info
 	debug("DP: %s was called\n", __func__);
 	mdelay(1);
 
-	ret = exynos_dp_read_dpcd_lane_stat(edp_info, &lane_stat);
+	ret = exynos_dp_read_dpcd_lane_stat(dp_regs, edp_info, &lane_stat);
 	if (ret != EXYNOS_DP_SUCCESS) {
 			printf("DP read lane status failed\n");
 			edp_info->lt_info.lt_status = DP_LT_FAIL;

@@ -493,11 +505,11 @@ static unsigned int exynos_dp_process_clock_recovery(struct edp_device_info
 
 	if (lane_stat & DP_LANE_STAT_CR_DONE) {
 		debug("DP clock Recovery training succeed\n");
-		exynos_dp_set_training_pattern(TRAINING_PTN2);
+		exynos_dp_set_training_pattern(dp_regs, TRAINING_PTN2);
 
 		for (i = 0; i < edp_info->lane_cnt; i++) {
-			ret = exynos_dp_read_dpcd_adj_req(i, &adj_req_sw,
-					&adj_req_em);
+			ret = exynos_dp_read_dpcd_adj_req(dp_regs, i,
+						&adj_req_sw, &adj_req_em);
 			if (ret != EXYNOS_DP_SUCCESS) {
 				edp_info->lt_info.lt_status = DP_LT_FAIL;
 				return ret;

@@ -511,7 +523,8 @@ static unsigned int exynos_dp_process_clock_recovery(struct edp_device_info
 				lt_ctl_val[i] |= MAX_DRIVE_CURRENT_REACH_3 |
 					MAX_PRE_EMPHASIS_REACH_3;
 			}
-			exynos_dp_set_lanex_pre_emphasis(lt_ctl_val[i], i);
+			exynos_dp_set_lanex_pre_emphasis(dp_regs,
+							 lt_ctl_val[i], i);
 		}
 
 		buf[0] =  DPCD_SCRAMBLING_DISABLED | DPCD_TRAINING_PATTERN_2;

@@ -520,7 +533,7 @@ static unsigned int exynos_dp_process_clock_recovery(struct edp_device_info
 		buf[3] = lt_ctl_val[2];
 		buf[4] = lt_ctl_val[3];
 
-		ret = exynos_dp_write_bytes_to_dpcd(
+		ret = exynos_dp_write_bytes_to_dpcd(dp_regs,
 				DPCD_TRAINING_PATTERN_SET, 5, buf);
 		if (ret != EXYNOS_DP_SUCCESS) {
 			printf("DP write training pattern1 failed\n");

@@ -530,8 +543,9 @@ static unsigned int exynos_dp_process_clock_recovery(struct edp_device_info
 			edp_info->lt_info.lt_status = DP_LT_ET;
 	} else {
 		for (i = 0; i < edp_info->lane_cnt; i++) {
-			lt_ctl_val[i] = exynos_dp_get_lanex_pre_emphasis(i);
-				ret = exynos_dp_read_dpcd_adj_req(i,
+			lt_ctl_val[i] = exynos_dp_get_lanex_pre_emphasis(
+						dp_regs, i);
+				ret = exynos_dp_read_dpcd_adj_req(dp_regs, i,
 						&adj_req_sw, &adj_req_em);
 			if (ret != EXYNOS_DP_SUCCESS) {
 				printf("DP read adj req failed\n");

@@ -541,7 +555,8 @@ static unsigned int exynos_dp_process_clock_recovery(struct edp_device_info
 
 			if ((adj_req_sw == VOLTAGE_LEVEL_3) ||
 					(adj_req_em == PRE_EMPHASIS_LEVEL_3))
-				ret = exynos_dp_reduce_link_rate(edp_info);
+				ret = exynos_dp_reduce_link_rate(dp_regs,
+								 edp_info);
 
 			if ((DRIVE_CURRENT_SET_0_GET(lt_ctl_val[i]) ==
 						adj_req_sw) &&

@@ -550,7 +565,7 @@ static unsigned int exynos_dp_process_clock_recovery(struct edp_device_info
 				edp_info->lt_info.cr_loop[i]++;
 				if (edp_info->lt_info.cr_loop[i] == MAX_CR_LOOP)
 					ret = exynos_dp_reduce_link_rate(
-							edp_info);
+							dp_regs, edp_info);
 			}
 
 			lt_ctl_val[i] = 0;

@@ -561,10 +576,11 @@ static unsigned int exynos_dp_process_clock_recovery(struct edp_device_info
 				lt_ctl_val[i] |= MAX_DRIVE_CURRENT_REACH_3 |
 					MAX_PRE_EMPHASIS_REACH_3;
 			}
-			exynos_dp_set_lanex_pre_emphasis(lt_ctl_val[i], i);
+			exynos_dp_set_lanex_pre_emphasis(dp_regs,
+							 lt_ctl_val[i], i);
 		}
 
-		ret = exynos_dp_write_bytes_to_dpcd(
+		ret = exynos_dp_write_bytes_to_dpcd(dp_regs,
 				DPCD_TRAINING_LANE0_SET, 4, lt_ctl_val);
 		if (ret != EXYNOS_DP_SUCCESS) {
 			printf("DP write training pattern2 failed\n");

@@ -576,8 +592,8 @@ static unsigned int exynos_dp_process_clock_recovery(struct edp_device_info
 	return ret;
 }
 
-static unsigned int exynos_dp_process_equalizer_training(struct edp_device_info
-		*edp_info)
+static unsigned int exynos_dp_process_equalizer_training(
+		struct exynos_dp *dp_regs, struct edp_device_info *edp_info)
 {
 	unsigned int ret = EXYNOS_DP_SUCCESS;
 	unsigned char lane_stat, adj_req_sw, adj_req_em, i;

@@ -589,7 +605,7 @@ static unsigned int exynos_dp_process_equalizer_training(struct edp_device_info
 
 	mdelay(1);
 
-	ret = exynos_dp_read_dpcd_lane_stat(edp_info, &lane_stat);
+	ret = exynos_dp_read_dpcd_lane_stat(dp_regs, edp_info, &lane_stat);
 	if (ret != EXYNOS_DP_SUCCESS) {
 		printf("DP read lane status failed\n");
 		edp_info->lt_info.lt_status = DP_LT_FAIL;

@@ -599,8 +615,9 @@ static unsigned int exynos_dp_process_equalizer_training(struct edp_device_info
 	debug("DP lane stat : %x\n", lane_stat);
 
 	if (lane_stat & DP_LANE_STAT_CR_DONE) {
-		ret = exynos_dp_read_byte_from_dpcd(DPCD_LN_ALIGN_UPDATED,
-				&sink_stat);
+		ret = exynos_dp_read_byte_from_dpcd(dp_regs,
+						    DPCD_LN_ALIGN_UPDATED,
+						    &sink_stat);
 		if (ret != EXYNOS_DP_SUCCESS) {
 			edp_info->lt_info.lt_status = DP_LT_FAIL;
 

@@ -610,7 +627,7 @@ static unsigned int exynos_dp_process_equalizer_training(struct edp_device_info
 		interlane_aligned = (sink_stat & DPCD_INTERLANE_ALIGN_DONE);
 
 		for (i = 0; i < edp_info->lane_cnt; i++) {
-			ret = exynos_dp_read_dpcd_adj_req(i,
+			ret = exynos_dp_read_dpcd_adj_req(dp_regs, i,
 					&adj_req_sw, &adj_req_em);
 			if (ret != EXYNOS_DP_SUCCESS) {
 				printf("DP read adj req 1 failed\n");

@@ -634,15 +651,15 @@ static unsigned int exynos_dp_process_equalizer_training(struct edp_device_info
 			&& (interlane_aligned == DPCD_INTERLANE_ALIGN_DONE)) {
 			debug("DP Equalizer training succeed\n");
 
-			f_bw = exynos_dp_get_link_bandwidth();
-			f_lane_cnt = exynos_dp_get_lane_count();
+			f_bw = exynos_dp_get_link_bandwidth(dp_regs);
+			f_lane_cnt = exynos_dp_get_lane_count(dp_regs);
 
 			debug("DP final BandWidth : %x\n", f_bw);
 			debug("DP final Lane Count : %x\n", f_lane_cnt);
 
 			edp_info->lt_info.lt_status = DP_LT_FINISHED;
 
-			exynos_dp_equalizer_err_link(edp_info);
+			exynos_dp_equalizer_err_link(dp_regs, edp_info);
 
 		} else {
 			edp_info->lt_info.ep_loop++;

@@ -650,46 +667,49 @@ static unsigned int exynos_dp_process_equalizer_training(struct edp_device_info
 			if (edp_info->lt_info.ep_loop > MAX_EQ_LOOP) {
 				if (edp_info->lane_bw == DP_LANE_BW_2_70) {
 					ret = exynos_dp_reduce_link_rate(
-							edp_info);
+							dp_regs, edp_info);
 				} else {
 					edp_info->lt_info.lt_status =
 								DP_LT_FAIL;
-					exynos_dp_equalizer_err_link(edp_info);
+					exynos_dp_equalizer_err_link(dp_regs,
+								     edp_info);
 				}
 			} else {
 				for (i = 0; i < edp_info->lane_cnt; i++)
 					exynos_dp_set_lanex_pre_emphasis(
-							lt_ctl_val[i], i);
+						dp_regs, lt_ctl_val[i], i);
 
-				ret = exynos_dp_write_bytes_to_dpcd(
-					DPCD_TRAINING_LANE0_SET,
-					4, lt_ctl_val);
+				ret = exynos_dp_write_bytes_to_dpcd(dp_regs,
+						DPCD_TRAINING_LANE0_SET,
+						4, lt_ctl_val);
 				if (ret != EXYNOS_DP_SUCCESS) {
 					printf("DP set lt pattern failed\n");
 					edp_info->lt_info.lt_status =
 								DP_LT_FAIL;
-					exynos_dp_equalizer_err_link(edp_info);
+					exynos_dp_equalizer_err_link(dp_regs,
+								     edp_info);
 				}
 			}
 		}
 	} else if (edp_info->lane_bw == DP_LANE_BW_2_70) {
-		ret = exynos_dp_reduce_link_rate(edp_info);
+		ret = exynos_dp_reduce_link_rate(dp_regs, edp_info);
 	} else {
 		edp_info->lt_info.lt_status = DP_LT_FAIL;
-		exynos_dp_equalizer_err_link(edp_info);
+		exynos_dp_equalizer_err_link(dp_regs, edp_info);
 	}
 
 	return ret;
 }
 
-static unsigned int exynos_dp_sw_link_training(struct edp_device_info *edp_info)
+static unsigned int exynos_dp_sw_link_training(struct exynos_dp *dp_regs,
+					       struct edp_device_info *edp_info)
 {
 	unsigned int ret = 0;
 	int training_finished;
 
 	/* Turn off unnecessary lane */
 	if (edp_info->lane_cnt == 1)
-		exynos_dp_set_analog_power_down(CH1_BLOCK, 1);
+		exynos_dp_set_analog_power_down(dp_regs, CH1_BLOCK, 1);
 
 	training_finished = 0;
 

@@ -699,21 +719,23 @@ static unsigned int exynos_dp_sw_link_training(struct edp_device_info *edp_info)
 	while (!training_finished) {
 		switch (edp_info->lt_info.lt_status) {
 		case DP_LT_START:
-			ret = exynos_dp_link_start(edp_info);
+			ret = exynos_dp_link_start(dp_regs, edp_info);
 			if (ret != EXYNOS_DP_SUCCESS) {
 				printf("DP LT:link start failed\n");
 				return ret;
 			}
 			break;
 		case DP_LT_CR:
-			ret = exynos_dp_process_clock_recovery(edp_info);
+			ret = exynos_dp_process_clock_recovery(dp_regs,
+							       edp_info);
 			if (ret != EXYNOS_DP_SUCCESS) {
 				printf("DP LT:clock recovery failed\n");
 				return ret;
 			}
 			break;
 		case DP_LT_ET:
-			ret = exynos_dp_process_equalizer_training(edp_info);
+			ret = exynos_dp_process_equalizer_training(dp_regs,
+								   edp_info);
 			if (ret != EXYNOS_DP_SUCCESS) {
 				printf("DP LT:equalizer training failed\n");
 				return ret;

@@ -730,40 +752,43 @@ static unsigned int exynos_dp_sw_link_training(struct edp_device_info *edp_info)
 	return ret;
 }
 
-static unsigned int exynos_dp_set_link_train(struct edp_device_info *edp_info)
+static unsigned int exynos_dp_set_link_train(struct exynos_dp *dp_regs,
+					     struct edp_device_info *edp_info)
 {
 	unsigned int ret;
 
-	exynos_dp_init_training();
+	exynos_dp_init_training(dp_regs);
 
-	ret = exynos_dp_sw_link_training(edp_info);
+	ret = exynos_dp_sw_link_training(dp_regs, edp_info);
 	if (ret != EXYNOS_DP_SUCCESS)
 		printf("DP dp_sw_link_training() failed\n");
 
 	return ret;
 }
 
-static void exynos_dp_enable_scramble(unsigned int enable)
+static void exynos_dp_enable_scramble(struct exynos_dp *dp_regs,
+				      unsigned int enable)
 {
 	unsigned char data;
 
 	if (enable) {
-		exynos_dp_enable_scrambling(DP_ENABLE);
+		exynos_dp_enable_scrambling(dp_regs, DP_ENABLE);
 
-		exynos_dp_read_byte_from_dpcd(DPCD_TRAINING_PATTERN_SET,
-				&data);
-		exynos_dp_write_byte_to_dpcd(DPCD_TRAINING_PATTERN_SET,
+		exynos_dp_read_byte_from_dpcd(dp_regs,
+					      DPCD_TRAINING_PATTERN_SET, &data);
+		exynos_dp_write_byte_to_dpcd(dp_regs, DPCD_TRAINING_PATTERN_SET,
 			(u8)(data & ~DPCD_SCRAMBLING_DISABLED));
 	} else {
-		exynos_dp_enable_scrambling(DP_DISABLE);
-		exynos_dp_read_byte_from_dpcd(DPCD_TRAINING_PATTERN_SET,
-				&data);
-		exynos_dp_write_byte_to_dpcd(DPCD_TRAINING_PATTERN_SET,
+		exynos_dp_enable_scrambling(dp_regs, DP_DISABLE);
+		exynos_dp_read_byte_from_dpcd(dp_regs,
+					      DPCD_TRAINING_PATTERN_SET, &data);
+		exynos_dp_write_byte_to_dpcd(dp_regs, DPCD_TRAINING_PATTERN_SET,
 			(u8)(data | DPCD_SCRAMBLING_DISABLED));
 	}
 }
 
-static unsigned int exynos_dp_config_video(struct edp_device_info *edp_info)
+static unsigned int exynos_dp_config_video(struct exynos_dp *dp_regs,
+					   struct edp_device_info *edp_info)
 {
 	unsigned int ret = 0;
 	unsigned int retry_cnt;

@@ -775,17 +800,18 @@ static unsigned int exynos_dp_config_video(struct edp_device_info *edp_info)
 		return -ENODEV;
 	} else {
 		/* debug slave */
-		exynos_dp_config_video_slave_mode(&edp_info->video_info);
+		exynos_dp_config_video_slave_mode(dp_regs,
+						  &edp_info->video_info);
 	}
 
-	exynos_dp_set_video_color_format(&edp_info->video_info);
+	exynos_dp_set_video_color_format(dp_regs, &edp_info->video_info);
 
 	if (edp_info->video_info.bist_mode) {
-		if (exynos_dp_config_video_bist(edp_info) != 0)
+		if (exynos_dp_config_video_bist(dp_regs, edp_info) != 0)
 			return -1;
 	}
 
-	ret = exynos_dp_get_pll_lock_status();
+	ret = exynos_dp_get_pll_lock_status(dp_regs);
 	if (ret != PLL_LOCKED) {
 		printf("DP PLL is not locked yet\n");
 		return -EIO;

@@ -794,7 +820,7 @@ static unsigned int exynos_dp_config_video(struct edp_device_info *edp_info)
 	if (edp_info->video_info.master_mode == 0) {
 		retry_cnt = 10;
 		while (retry_cnt) {
-			ret = exynos_dp_is_slave_video_stream_clock_on();
+			ret = exynos_dp_is_slave_video_stream_clock_on(dp_regs);
 			if (ret != EXYNOS_DP_SUCCESS) {
 				if (retry_cnt == 0) {
 					printf("DP stream_clock_on failed\n");

@@ -808,32 +834,34 @@ static unsigned int exynos_dp_config_video(struct edp_device_info *edp_info)
 	}
 
 	/* Set to use the register calculated M/N video */
-	exynos_dp_set_video_cr_mn(CALCULATED_M, 0, 0);
+	exynos_dp_set_video_cr_mn(dp_regs, CALCULATED_M, 0, 0);
 
 	/* For video bist, Video timing must be generated by register */
-	exynos_dp_set_video_timing_mode(VIDEO_TIMING_FROM_CAPTURE);
+	exynos_dp_set_video_timing_mode(dp_regs, VIDEO_TIMING_FROM_CAPTURE);
 
 	/* Enable video bist */
 	if (edp_info->video_info.bist_pattern != COLOR_RAMP &&
 		edp_info->video_info.bist_pattern != BALCK_WHITE_V_LINES &&
 		edp_info->video_info.bist_pattern != COLOR_SQUARE)
-		exynos_dp_enable_video_bist(edp_info->video_info.bist_mode);
+		exynos_dp_enable_video_bist(dp_regs,
+					    edp_info->video_info.bist_mode);
 	else
-		exynos_dp_enable_video_bist(DP_DISABLE);
+		exynos_dp_enable_video_bist(dp_regs, DP_DISABLE);
 
 	/* Disable video mute */
-	exynos_dp_enable_video_mute(DP_DISABLE);
+	exynos_dp_enable_video_mute(dp_regs, DP_DISABLE);
 
 	/* Configure video Master or Slave mode */
-	exynos_dp_enable_video_master(edp_info->video_info.master_mode);
+	exynos_dp_enable_video_master(dp_regs,
+				      edp_info->video_info.master_mode);
 
 	/* Enable video */
-	exynos_dp_start_video();
+	exynos_dp_start_video(dp_regs);
 
 	if (edp_info->video_info.master_mode == 0) {
 		retry_cnt = 100;
 		while (retry_cnt) {
-			ret = exynos_dp_is_video_stream_on();
+			ret = exynos_dp_is_video_stream_on(dp_regs);
 			if (ret != EXYNOS_DP_SUCCESS) {
 				if (retry_cnt == 0) {
 					printf("DP Timeout of video stream\n");

@@ -907,6 +935,8 @@ unsigned int exynos_init_dp(void)
 {
 	unsigned int ret;
 	struct edp_device_info *edp_info;
+	struct exynos_dp *dp_regs;
+	int node;
 
 	edp_info = kzalloc(sizeof(struct edp_device_info), GFP_KERNEL);
 	if (!edp_info) {

@@ -917,39 +947,47 @@ unsigned int exynos_init_dp(void)
 	if (exynos_dp_parse_dt(gd->fdt_blob, edp_info))
 		debug("unable to parse DP DT node\n");
 
-	exynos_dp_set_base_addr();
+	node = fdtdec_next_compatible(gd->fdt_blob, 0,
+				      COMPAT_SAMSUNG_EXYNOS5_DP);
+	if (node <= 0)
+		debug("exynos_dp: Can't get device node for dp\n");
+
+	dp_regs = (struct exynos_dp *)fdtdec_get_addr(gd->fdt_blob, node,
+						      "reg");
+	if (dp_regs == NULL)
+		debug("Can't get the DP base address\n");
 
 	exynos_dp_disp_info(&edp_info->disp_info);
 
 	exynos_set_dp_phy(1);
 
-	ret = exynos_dp_init_dp();
+	ret = exynos_dp_init_dp(dp_regs);
 	if (ret != EXYNOS_DP_SUCCESS) {
 		printf("DP exynos_dp_init_dp() failed\n");
 		return ret;
 	}
 
-	ret = exynos_dp_handle_edid(edp_info);
+	ret = exynos_dp_handle_edid(dp_regs, edp_info);
 	if (ret != EXYNOS_DP_SUCCESS) {
 		printf("EDP handle_edid fail\n");
 		return ret;
 	}
 
-	ret = exynos_dp_set_link_train(edp_info);
+	ret = exynos_dp_set_link_train(dp_regs, edp_info);
 	if (ret != EXYNOS_DP_SUCCESS) {
 		printf("DP link training fail\n");
 		return ret;
 	}
 
-	exynos_dp_enable_scramble(DP_ENABLE);
-	exynos_dp_enable_rx_to_enhanced_mode(DP_ENABLE);
-	exynos_dp_enable_enhanced_mode(DP_ENABLE);
+	exynos_dp_enable_scramble(dp_regs, DP_ENABLE);
+	exynos_dp_enable_rx_to_enhanced_mode(dp_regs, DP_ENABLE);
+	exynos_dp_enable_enhanced_mode(dp_regs, DP_ENABLE);
 
-	exynos_dp_set_link_bandwidth(edp_info->lane_bw);
-	exynos_dp_set_lane_count(edp_info->lane_cnt);
+	exynos_dp_set_link_bandwidth(dp_regs, edp_info->lane_bw);
+	exynos_dp_set_lane_count(dp_regs, edp_info->lane_cnt);
 
-	exynos_dp_init_video();
-	ret = exynos_dp_config_video(edp_info);
+	exynos_dp_init_video(dp_regs);
+	ret = exynos_dp_config_video(dp_regs, edp_info);
 	if (ret != EXYNOS_DP_SUCCESS) {
 		printf("Exynos DP init failed\n");
 		return ret;

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index 5001e16..fd96382 100644
@@ -28,7 +28,6 @@
 DECLARE_GLOBAL_DATA_PTR;
 
 static struct exynos_platform_mipi_dsim *dsim_pd;
-static struct mipi_dsim_config dsim_config_dt;
 static struct exynos_platform_mipi_dsim dsim_platform_data_dt;
 static struct mipi_dsim_lcd_device mipi_lcd_device_dt;
 

@@ -247,7 +246,7 @@ void exynos_set_dsim_platform_data(struct exynos_platform_mipi_dsim *pd)
 	dsim_pd = pd;
 }
 
-int exynos_dsim_config_parse_dt(const void *blob)
+int exynos_dsim_config_parse_dt(const void *blob, struct mipi_dsim_config *dt)
 {
 	int node;
 

@@ -257,47 +256,47 @@ int exynos_dsim_config_parse_dt(const void *blob)
 		return -ENODEV;
 	}
 
-	dsim_config_dt.e_interface = fdtdec_get_int(blob, node,
+	dt->e_interface = fdtdec_get_int(blob, node,
 				"samsung,dsim-config-e-interface", 0);
 
-	dsim_config_dt.e_virtual_ch = fdtdec_get_int(blob, node,
+	dt->e_virtual_ch = fdtdec_get_int(blob, node,
 				"samsung,dsim-config-e-virtual-ch", 0);
 
-	dsim_config_dt.e_pixel_format = fdtdec_get_int(blob, node,
+	dt->e_pixel_format = fdtdec_get_int(blob, node,
 				"samsung,dsim-config-e-pixel-format", 0);
 
-	dsim_config_dt.e_burst_mode = fdtdec_get_int(blob, node,
+	dt->e_burst_mode = fdtdec_get_int(blob, node,
 				"samsung,dsim-config-e-burst-mode", 0);
 
-	dsim_config_dt.e_no_data_lane = fdtdec_get_int(blob, node,
+	dt->e_no_data_lane = fdtdec_get_int(blob, node,
 				"samsung,dsim-config-e-no-data-lane", 0);
 
-	dsim_config_dt.e_byte_clk = fdtdec_get_int(blob, node,
+	dt->e_byte_clk = fdtdec_get_int(blob, node,
 				"samsung,dsim-config-e-byte-clk", 0);
 
-	dsim_config_dt.hfp = fdtdec_get_int(blob, node,
+	dt->hfp = fdtdec_get_int(blob, node,
 				"samsung,dsim-config-hfp", 0);
 
-	dsim_config_dt.p = fdtdec_get_int(blob, node,
+	dt->p = fdtdec_get_int(blob, node,
 					  "samsung,dsim-config-p", 0);
-	dsim_config_dt.m = fdtdec_get_int(blob, node,
+	dt->m = fdtdec_get_int(blob, node,
 					  "samsung,dsim-config-m", 0);
-	dsim_config_dt.s = fdtdec_get_int(blob, node,
+	dt->s = fdtdec_get_int(blob, node,
 					  "samsung,dsim-config-s", 0);
 
-	dsim_config_dt.pll_stable_time = fdtdec_get_int(blob, node,
+	dt->pll_stable_time = fdtdec_get_int(blob, node,
 				"samsung,dsim-config-pll-stable-time", 0);
 
-	dsim_config_dt.esc_clk = fdtdec_get_int(blob, node,
+	dt->esc_clk = fdtdec_get_int(blob, node,
 				"samsung,dsim-config-esc-clk", 0);
 
-	dsim_config_dt.stop_holding_cnt = fdtdec_get_int(blob, node,
+	dt->stop_holding_cnt = fdtdec_get_int(blob, node,
 				"samsung,dsim-config-stop-holding-cnt", 0);
 
-	dsim_config_dt.bta_timeout = fdtdec_get_int(blob, node,
+	dt->bta_timeout = fdtdec_get_int(blob, node,
 				"samsung,dsim-config-bta-timeout", 0);
 
-	dsim_config_dt.rx_timeout = fdtdec_get_int(blob, node,
+	dt->rx_timeout = fdtdec_get_int(blob, node,
 				"samsung,dsim-config-rx-timeout", 0);
 
 	mipi_lcd_device_dt.name = fdtdec_get_config_string(blob,

@@ -317,7 +316,9 @@ int exynos_dsim_config_parse_dt(const void *blob)
 
 void exynos_init_dsim_platform_data(vidinfo_t *vid)
 {
-	if (exynos_dsim_config_parse_dt(gd->fdt_blob))
+	struct mipi_dsim_config dsim_config_dt;
+
+	if (exynos_dsim_config_parse_dt(gd->fdt_blob, &dsim_config_dt))
 		debug("Can't get proper dsim config.\n");
 
 	strcpy(dsim_platform_data_dt.lcd_panel_name, mipi_lcd_device_dt.name);

index a77b5c8..df68186 100644
@@ -347,9 +347,10 @@ struct mipi_dsim_lcd_driver {
 };
 
 #ifdef CONFIG_EXYNOS_MIPI_DSIM
-int exynos_mipi_dsi_init(void);
+int exynos_mipi_dsi_init(struct exynos_platform_mipi_dsim *dsim_pd);
 #else
-static inline int exynos_mipi_dsi_init(void)
+static inline int exynos_mipi_dsi_init(
+			struct exynos_platform_mipi_dsim *dsim_pd)
 {
 	return 0;
 }

index abc6091..22b9723 100644
@@ -128,7 +128,7 @@ static void lcd_panel_on(struct vidinfo *vid)
 	exynos_enable_ldo(1);
 
 	if (vid->mipi_enabled)
-		exynos_mipi_dsi_init();
+		exynos_mipi_dsi_init(panel_info.dsim_platform_data_dt);
 }
 
 int exynos_lcd_early_init(const void *blob)

index fd96382..b39858a 100644
@@ -27,8 +27,6 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-static struct exynos_platform_mipi_dsim *dsim_pd;
-static struct exynos_platform_mipi_dsim dsim_platform_data_dt;
 static struct mipi_dsim_lcd_device mipi_lcd_device_dt;
 
 struct mipi_dsim_ddi {

@@ -175,7 +173,7 @@ static struct mipi_dsim_master_ops master_ops = {
 	.clear_dsim_frame_done		= exynos_mipi_dsi_clear_frame_done,
 };
 
-int exynos_mipi_dsi_init(void)
+int exynos_mipi_dsi_init(struct exynos_platform_mipi_dsim *dsim_pd)
 {
 	struct mipi_dsim_device *dsim;
 	struct mipi_dsim_config *dsim_config;

@@ -236,16 +234,6 @@ int exynos_mipi_dsi_init(void)
 	return 0;
 }
 
-void exynos_set_dsim_platform_data(struct exynos_platform_mipi_dsim *pd)
-{
-	if (pd == NULL) {
-		debug("pd is NULL\n");
-		return;
-	}
-
-	dsim_pd = pd;
-}
-
 int exynos_dsim_config_parse_dt(const void *blob, struct mipi_dsim_config *dt)
 {
 	int node;

@@ -316,7 +304,8 @@ int exynos_dsim_config_parse_dt(const void *blob, struct mipi_dsim_config *dt)
 
 void exynos_init_dsim_platform_data(vidinfo_t *vid)
 {
-	struct mipi_dsim_config dsim_config_dt;
+	static struct mipi_dsim_config dsim_config_dt;
+	static struct exynos_platform_mipi_dsim dsim_platform_data_dt;
 
 	if (exynos_dsim_config_parse_dt(gd->fdt_blob, &dsim_config_dt))
 		debug("Can't get proper dsim config.\n");

@@ -330,5 +319,5 @@ void exynos_init_dsim_platform_data(vidinfo_t *vid)
 	mipi_lcd_device_dt.platform_data = (void *)&dsim_platform_data_dt;
 	exynos_mipi_dsi_register_lcd_device(&mipi_lcd_device_dt);
 
-	dsim_pd = &dsim_platform_data_dt;
+	vid->dsim_platform_data_dt = &dsim_platform_data_dt;
 }

index 1f6c6c7..0aa0fc7 100644
@@ -76,6 +76,7 @@ typedef struct vidinfo {
 
 	unsigned int dual_lcd_enabled;
 	struct exynos_fb *fimd_ctrl;
+	struct exynos_platform_mipi_dsim *dsim_platform_data_dt;
 } vidinfo_t;
 
 #endif

index df68186..43b5c01 100644
@@ -320,7 +320,7 @@ struct mipi_dsim_lcd_device {
 	int			reverse_panel;
 
 	struct mipi_dsim_device *master;
-	void			*platform_data;
+	struct exynos_platform_mipi_dsim *platform_data;
 };
 
 /*

index b39858a..a5d9b59 100644
@@ -27,8 +27,6 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-static struct mipi_dsim_lcd_device mipi_lcd_device_dt;
-
 struct mipi_dsim_ddi {
 	int				bus_id;
 	struct list_head		list;

@@ -234,7 +232,8 @@ int exynos_mipi_dsi_init(struct exynos_platform_mipi_dsim *dsim_pd)
 	return 0;
 }
 
-int exynos_dsim_config_parse_dt(const void *blob, struct mipi_dsim_config *dt)
+int exynos_dsim_config_parse_dt(const void *blob, struct mipi_dsim_config *dt,
+				struct mipi_dsim_lcd_device *lcd_dt)
 {
 	int node;
 

@@ -287,16 +286,16 @@ int exynos_dsim_config_parse_dt(const void *blob, struct mipi_dsim_config *dt)
 	dt->rx_timeout = fdtdec_get_int(blob, node,
 				"samsung,dsim-config-rx-timeout", 0);
 
-	mipi_lcd_device_dt.name = fdtdec_get_config_string(blob,
+	lcd_dt->name = fdtdec_get_config_string(blob,
 				"samsung,dsim-device-name");
 
-	mipi_lcd_device_dt.id = fdtdec_get_int(blob, node,
+	lcd_dt->id = fdtdec_get_int(blob, node,
 				"samsung,dsim-device-id", 0);
 
-	mipi_lcd_device_dt.bus_id = fdtdec_get_int(blob, node,
+	lcd_dt->bus_id = fdtdec_get_int(blob, node,
 				"samsung,dsim-device-bus_id", 0);
 
-	mipi_lcd_device_dt.reverse_panel = fdtdec_get_int(blob, node,
+	lcd_dt->reverse_panel = fdtdec_get_int(blob, node,
 				"samsung,dsim-device-reverse-panel", 0);
 
 	return 0;

@@ -306,8 +305,10 @@ void exynos_init_dsim_platform_data(vidinfo_t *vid)
 {
 	static struct mipi_dsim_config dsim_config_dt;
 	static struct exynos_platform_mipi_dsim dsim_platform_data_dt;
+	static struct mipi_dsim_lcd_device mipi_lcd_device_dt;
 
-	if (exynos_dsim_config_parse_dt(gd->fdt_blob, &dsim_config_dt))
+	if (exynos_dsim_config_parse_dt(gd->fdt_blob, &dsim_config_dt,
+					&mipi_lcd_device_dt))
 		debug("Can't get proper dsim config.\n");
 
 	strcpy(dsim_platform_data_dt.lcd_panel_name, mipi_lcd_device_dt.name);

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index 949abb1..b63036c 100644
@@ -12,6 +12,9 @@
 #include <asm/io.h>
 #include <asm/arch/pwm.h>
 #include <asm/arch/clk.h>
+
+/* Use the old PWM interface for now */
+#undef CONFIG_DM_PWM
 #include <pwm.h>
 
 DECLARE_GLOBAL_DATA_PTR;

120 lines not on this page · raw message

index c434bc7..0d5bd21 100644
@@ -23,6 +23,11 @@ struct video_uc_platdata {
 	ulong base;
 };
 
+enum video_polarity {
+	VIDEO_ACTIVE_HIGH,	/* Pins are active high */
+	VIDEO_ACTIVE_LOW,	/* Pins are active low */
+};
+
 /*
  * Bits per pixel selector. Each value n is such that the bits-per-pixel is
  * 2 ^ n

index 6490fb5..55dccff 100644
@@ -10,6 +10,8 @@
 
 #define HD_RESOLUTION	0
 
+#ifdef CONFIG_LCD
 void get_tizen_logo_info(vidinfo_t *vid);
+#endif
 
 #endif	/* _LIBTIZEN_H_ */

index 814ed18..d207f77 100644
@@ -12,6 +12,7 @@
 #include "tizen_logo_16bpp.h"
 #include "tizen_logo_16bpp_gzip.h"
 
+#ifdef CONFIG_LCD
 void get_tizen_logo_info(vidinfo_t *vid)
 {
 	switch (vid->vl_bpix) {

@@ -31,3 +32,4 @@ void get_tizen_logo_info(vidinfo_t *vid)
 		break;
 	}
 }
+#endif

index da0d4db..77d0a4e 100644
@@ -147,6 +147,7 @@ static int key_pressed(int key)
 	return value;
 }
 
+#ifdef CONFIG_LCD
 static int check_keys(void)
 {
 	int keys = 0;

@@ -235,9 +236,11 @@ static void display_board_info(void)
 
 	lcd_printf("\tDisplay BPP: %u\n", 1 << vid->vl_bpix);
 }
+#endif
 
 static int mode_leave_menu(int mode)
 {
+#ifdef CONFIG_LCD
 	char *exit_option;
 	char *exit_reset = "reset";
 	char *exit_back = "back";

@@ -301,8 +304,12 @@ static int mode_leave_menu(int mode)
 
 	lcd_clear();
 	return leave;
+#else
+	return 0;
+#endif
 }
 
+#ifdef CONFIG_LCD
 static void display_download_menu(int mode)
 {
 	char *selection[BOOT_MODE_EXIT + 1];

@@ -320,9 +327,11 @@ static void display_download_menu(int mode)
 		lcd_printf("\t%s  %s - %s\n\n", selection[i],
 			   mode_name[i][0], mode_info[i]);
 }
+#endif
 
 static void download_menu(void)
 {
+#ifdef CONFIG_LCD
 	int mode = 0;
 	int last_mode = 0;
 	int run;

@@ -393,6 +402,7 @@ static void download_menu(void)
 	}
 
 	lcd_clear();
+#endif
 }
 
 void check_boot_mode(void)

index 54d01ec..66a54d4 100644
@@ -596,6 +596,7 @@ int mipi_power(void)
 	return 0;
 }
 
+#ifdef CONFIG_LCD
 void exynos_lcd_misc_init(vidinfo_t *vid)
 {
 #ifdef CONFIG_TIZEN

@@ -606,3 +607,4 @@ void exynos_lcd_misc_init(vidinfo_t *vid)
 	setenv("lcdinfo", "lcd=s6e8ax0");
 #endif
 }
+#endif

index 426ae14..81e35b6 100644
@@ -367,6 +367,7 @@ int exynos_init(void)
 	return 0;
 }
 
+#ifdef CONFIG_LCD
 void exynos_lcd_misc_init(vidinfo_t *vid)
 {
 #ifdef CONFIG_TIZEN

@@ -379,3 +380,4 @@ void exynos_lcd_misc_init(vidinfo_t *vid)
 
 	setenv("lcdinfo", "lcd=ld9040");
 }
+#endif

index 7bb62ca..8e63407 100644
@@ -222,9 +222,6 @@ int universal_spi_read(void);
 /*
  * LCD Settings
  */
-#define CONFIG_EXYNOS_FB
-#define CONFIG_LCD
-#define CONFIG_CMD_BMP
 #define CONFIG_BMP_16BPP
 #define CONFIG_LD9040
 #define CONFIG_VIDEO_BMP_GZIP

index f66bb12..92a0833 100644
@@ -13,6 +13,9 @@
 #include <configs/exynos5-dt-common.h>
 #include <configs/exynos5-common.h>
 
+#undef CONFIG_LCD
+#undef CONFIG_EXYNOS_FB
+#undef CONFIG_EXYNOS_DP
 #undef CONFIG_KEYBOARD
 
 #define CONFIG_BOARD_COMMON

index 9cf886c..5fe21d9 100644
@@ -13,6 +13,10 @@
 #include <configs/exynos5-dt-common.h>
 #include <configs/exynos5-common.h>
 
+#undef CONFIG_LCD
+#undef CONFIG_EXYNOS_FB
+#undef CONFIG_EXYNOS_DP
+
 #undef CONFIG_KEYBOARD
 
 #define CONFIG_BOARD_COMMON

index 5fb991b..0423033 100644
@@ -247,12 +247,8 @@
 #define CONFIG_SYS_WHITE_ON_BLACK
 
 /* LCD */
-#define CONFIG_EXYNOS_FB
-#define CONFIG_LCD
-#define CONFIG_CMD_BMP
 #define CONFIG_BMP_16BPP
 #define CONFIG_FB_ADDR		0x52504000
-#define CONFIG_S6E8AX0
 #define CONFIG_EXYNOS_MIPI_DSIM
 #define CONFIG_VIDEO_BMP_GZIP
 #define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE  ((500 * 160 * 4) + 54)

index f12a952..24fbc1a 100644
@@ -226,12 +226,8 @@ int get_soft_i2c_sda_pin(void);
 #define CONFIG_SYS_WHITE_ON_BLACK
 
 /* LCD */
-#define CONFIG_EXYNOS_FB
-#define CONFIG_LCD
-#define CONFIG_CMD_BMP
 #define CONFIG_BMP_16BPP
 #define CONFIG_FB_ADDR		0x52504000
-#define CONFIG_S6E8AX0
 #define CONFIG_EXYNOS_MIPI_DSIM
 #define CONFIG_VIDEO_BMP_GZIP
 #define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE ((500 * 160 * 4) + 54)

new file mode 100644
index 0000000..997312e
@@ -0,0 +1,22 @@
+/*
+ * Copyright (C) 2014 Google, Inc
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Device Tree binding constants clocks for the Maxim 77802 PMIC.
+ */
+
+#ifndef _DT_BINDINGS_CLOCK_MAXIM_MAX77802_CLOCK_H
+#define _DT_BINDINGS_CLOCK_MAXIM_MAX77802_CLOCK_H
+
+/* Fixed rate clocks. */
+
+#define MAX77802_CLK_32K_AP		0
+#define MAX77802_CLK_32K_CP		1
+
+/* Total number of clocks. */
+#define MAX77802_CLKS_NUM		(MAX77802_CLK_32K_CP + 1)
+
+#endif /* _DT_BINDINGS_CLOCK_MAXIM_MAX77802_CLOCK_H */

new file mode 100644
index 0000000..cf28631
@@ -0,0 +1,18 @@
+/*
+ * Copyright (C) 2014 Google, Inc
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Device Tree binding constants for the Maxim 77802 PMIC regulators
+ */
+
+#ifndef _DT_BINDINGS_REGULATOR_MAXIM_MAX77802_H
+#define _DT_BINDINGS_REGULATOR_MAXIM_MAX77802_H
+
+/* Regulator operating modes */
+#define MAX77802_OPMODE_LP	1
+#define MAX77802_OPMODE_NORMAL	3
+
+#endif /* _DT_BINDINGS_REGULATOR_MAXIM_MAX77802_H */

index 12eb79c..fec2df9 100644
@@ -506,6 +506,9 @@ static int exynos5_pinmux_config(int peripheral, int flags)
 		 */
 		gpio_set_pull(EXYNOS5_GPIO_X07, S5P_GPIO_PULL_NONE);
 		break;
+	case PERIPH_ID_PWM0:
+		gpio_cfg_pin(EXYNOS5_GPIO_B20, S5P_GPIO_FUNC(2));
+		break;
 	default:
 		debug("%s: invalid peripheral %d", __func__, peripheral);
 		return -1;

@@ -548,6 +551,9 @@ static int exynos5420_pinmux_config(int peripheral, int flags)
 	case PERIPH_ID_I2C10:
 		exynos5420_i2c_config(peripheral);
 		break;
+	case PERIPH_ID_PWM0:
+		gpio_cfg_pin(EXYNOS5420_GPIO_B20, S5P_GPIO_FUNC(2));
+		break;
 	default:
 		debug("%s: invalid peripheral %d", __func__, peripheral);
 		return -1;

index 3f97b31..88f70d9 100644
@@ -1717,7 +1717,7 @@ void set_usbdrd_phy_ctrl(unsigned int enable);
 #define POWER_USB_DRD_PHY_CTRL_EN		(1 << 0)
 #define POWER_USB_DRD_PHY_CTRL_DISABLE		(0 << 0)
 
-void set_dp_phy_ctrl(unsigned int enable);
+void exynos_dp_phy_ctrl(unsigned int enable);
 
 #define EXYNOS_DP_PHY_ENABLE		(1 << 0)
 

index cd2d661..c923460 100644
@@ -147,7 +147,7 @@ static void exynos5_dp_phy_control(unsigned int enable)
 	writel(cfg, &power->dptx_phy_control);
 }
 
-void set_dp_phy_ctrl(unsigned int enable)
+void exynos_dp_phy_ctrl(unsigned int enable)
 {
 	if (cpu_is_exynos5())
 		exynos5_dp_phy_control(enable);

index 4d9e151..0dcea71 100644
@@ -235,11 +235,6 @@ void exynos_cfg_lcd_gpio(void)
 	gpio_set_value(EXYNOS5_GPIO_B20, 1);
 }
 
-void exynos_set_dp_phy(unsigned int onoff)
-{
-	set_dp_phy_ctrl(onoff);
-}
-
 static int board_dp_set_backlight(int percent)
 {
 	struct udevice *dev;

index 9945c4b..88926b9 100644
@@ -15,6 +15,7 @@
 #include <asm/arch/cpu.h>
 #include <asm/arch/dp_info.h>
 #include <asm/arch/dp.h>
+#include <asm/arch/power.h>
 #include <fdtdec.h>
 #include <libfdt.h>
 

@@ -22,12 +23,6 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-void __exynos_set_dp_phy(unsigned int onoff)
-{
-}
-void exynos_set_dp_phy(unsigned int onoff)
-	__attribute__((weak, alias("__exynos_set_dp_phy")));
-
 static void exynos_dp_disp_info(struct edp_disp_info *disp_info)
 {
 	disp_info->h_total = disp_info->h_res + disp_info->h_sync_width +

@@ -959,7 +954,7 @@ unsigned int exynos_init_dp(void)
 
 	exynos_dp_disp_info(&edp_info->disp_info);
 
-	exynos_set_dp_phy(1);
+	exynos_dp_phy_ctrl(1);
 
 	ret = exynos_dp_init_dp(dp_regs);
 	if (ret != EXYNOS_DP_SUCCESS) {

index 17e8f56..8ce33d6 100644
@@ -61,7 +61,7 @@ struct edp_video_info {
 	unsigned int color_depth;
 };
 
-struct edp_device_info {
+struct exynos_dp_priv {
 	struct edp_disp_info disp_info;
 	struct edp_link_train_info lt_info;
 	struct edp_video_info video_info;

@@ -185,7 +185,7 @@ enum {
 
 
 struct exynos_dp_platform_data {
-	struct edp_device_info *edp_dev_info;
+	struct exynos_dp_priv *edp_dev_info;
 };
 
 #ifdef CONFIG_EXYNOS_DP

index 88926b9..0d4ceef 100644
@@ -162,7 +162,7 @@ static unsigned int exynos_dp_read_edid(struct exynos_dp *dp_regs)
 }
 
 static unsigned int exynos_dp_handle_edid(struct exynos_dp *dp_regs,
-					  struct edp_device_info *edp_info)
+					  struct exynos_dp_priv *edp_info)
 {
 	unsigned char buf[12];
 	unsigned int ret;

@@ -251,7 +251,7 @@ static void exynos_dp_init_training(struct exynos_dp *dp_regs)
 }
 
 static unsigned int exynos_dp_link_start(struct exynos_dp *dp_regs,
-					 struct edp_device_info *edp_info)
+					 struct exynos_dp_priv *edp_info)
 {
 	unsigned char buf[5];
 	unsigned int ret = 0;

@@ -376,7 +376,7 @@ static unsigned int exynos_dp_set_enhanced_mode(struct exynos_dp *dp_regs,
 }
 
 static int exynos_dp_read_dpcd_lane_stat(struct exynos_dp *dp_regs,
-					 struct edp_device_info *edp_info,
+					 struct exynos_dp_priv *edp_info,
 					 unsigned char *status)
 {
 	unsigned int ret, i;

@@ -433,7 +433,7 @@ static unsigned int exynos_dp_read_dpcd_adj_req(struct exynos_dp *dp_regs,
 }
 
 static int exynos_dp_equalizer_err_link(struct exynos_dp *dp_regs,
-					struct edp_device_info *edp_info)
+					struct exynos_dp_priv *edp_info)
 {
 	int ret;
 

@@ -453,7 +453,7 @@ static int exynos_dp_equalizer_err_link(struct exynos_dp *dp_regs,
 }
 
 static int exynos_dp_reduce_link_rate(struct exynos_dp *dp_regs,
-				      struct edp_device_info *edp_info)
+				      struct exynos_dp_priv *edp_info)
 {
 	int ret;
 

@@ -478,7 +478,7 @@ static int exynos_dp_reduce_link_rate(struct exynos_dp *dp_regs,
 }
 
 static unsigned int exynos_dp_process_clock_recovery(struct exynos_dp *dp_regs,
-					struct edp_device_info *edp_info)
+					struct exynos_dp_priv *edp_info)
 {
 	unsigned int ret = EXYNOS_DP_SUCCESS;
 	unsigned char lane_stat;

@@ -588,7 +588,7 @@ static unsigned int exynos_dp_process_clock_recovery(struct exynos_dp *dp_regs,
 }
 
 static unsigned int exynos_dp_process_equalizer_training(
-		struct exynos_dp *dp_regs, struct edp_device_info *edp_info)
+		struct exynos_dp *dp_regs, struct exynos_dp_priv *edp_info)
 {
 	unsigned int ret = EXYNOS_DP_SUCCESS;
 	unsigned char lane_stat, adj_req_sw, adj_req_em, i;

@@ -697,7 +697,7 @@ static unsigned int exynos_dp_process_equalizer_training(
 }
 
 static unsigned int exynos_dp_sw_link_training(struct exynos_dp *dp_regs,
-					       struct edp_device_info *edp_info)
+					       struct exynos_dp_priv *edp_info)
 {
 	unsigned int ret = 0;
 	int training_finished;

@@ -748,7 +748,7 @@ static unsigned int exynos_dp_sw_link_training(struct exynos_dp *dp_regs,
 }
 
 static unsigned int exynos_dp_set_link_train(struct exynos_dp *dp_regs,
-					     struct edp_device_info *edp_info)
+					     struct exynos_dp_priv *edp_info)
 {
 	unsigned int ret;
 

@@ -783,7 +783,7 @@ static void exynos_dp_enable_scramble(struct exynos_dp *dp_regs,
 }
 
 static unsigned int exynos_dp_config_video(struct exynos_dp *dp_regs,
-					   struct edp_device_info *edp_info)
+					   struct exynos_dp_priv *edp_info)
 {
 	unsigned int ret = 0;
 	unsigned int retry_cnt;

@@ -872,7 +872,7 @@ static unsigned int exynos_dp_config_video(struct exynos_dp *dp_regs,
 	return ret;
 }
 
-int exynos_dp_parse_dt(const void *blob, struct edp_device_info *edp_info)
+int exynos_dp_parse_dt(const void *blob, struct exynos_dp_priv *edp_info)
 {
 	unsigned int node = fdtdec_next_compatible(blob, 0,
 						COMPAT_SAMSUNG_EXYNOS5_DP);

@@ -929,11 +929,11 @@ int exynos_dp_parse_dt(const void *blob, struct edp_device_info *edp_info)
 unsigned int exynos_init_dp(void)
 {
 	unsigned int ret;
-	struct edp_device_info *edp_info;
+	struct exynos_dp_priv *edp_info;
 	struct exynos_dp *dp_regs;
 	int node;
 
-	edp_info = kzalloc(sizeof(struct edp_device_info), GFP_KERNEL);
+	edp_info = kzalloc(sizeof(struct exynos_dp_priv), GFP_KERNEL);
 	if (!edp_info) {
 		debug("failed to allocate edp device object.\n");
 		return -EFAULT;

index 153c1c6..00a79ea 100644
@@ -1066,7 +1066,7 @@ void exynos_dp_set_video_color_format(struct exynos_dp *dp_regs,
 }
 
 int exynos_dp_config_video_bist(struct exynos_dp *dp_regs,
-				struct edp_device_info *edp_info)
+				struct exynos_dp_priv *edp_info)
 {
 	unsigned int reg;
 	unsigned int bist_type = 0;

index 85459b5..0a7657e 100644
@@ -74,7 +74,7 @@ void exynos_dp_config_video_slave_mode(struct exynos_dp *dp_regs,
 void exynos_dp_set_video_color_format(struct exynos_dp *dp_regs,
 				      struct edp_video_info *video_info);
 int exynos_dp_config_video_bist(struct exynos_dp *dp_regs,
-				struct edp_device_info *edp_info);
+				struct exynos_dp_priv *edp_info);
 unsigned int exynos_dp_is_slave_video_stream_clock_on(
 					struct exynos_dp *dp_regs);
 void exynos_dp_set_video_cr_mn(struct exynos_dp *dp_regs, unsigned int type,

index 0d4ceef..d7bccc3 100644
@@ -33,20 +33,20 @@ static void exynos_dp_disp_info(struct edp_disp_info *disp_info)
 	return;
 }
 
-static int exynos_dp_init_dp(struct exynos_dp *dp_regs)
+static int exynos_dp_init_dp(struct exynos_dp *regs)
 {
 	int ret;
-	exynos_dp_reset(dp_regs);
+	exynos_dp_reset(regs);
 
 	/* SW defined function Normal operation */
-	exynos_dp_enable_sw_func(dp_regs, DP_ENABLE);
+	exynos_dp_enable_sw_func(regs, DP_ENABLE);
 
-	ret = exynos_dp_init_analog_func(dp_regs);
+	ret = exynos_dp_init_analog_func(regs);
 	if (ret != EXYNOS_DP_SUCCESS)
 		return ret;
 
-	exynos_dp_init_hpd(dp_regs);
-	exynos_dp_init_aux(dp_regs);
+	exynos_dp_init_hpd(regs);
+	exynos_dp_init_aux(regs);
 
 	return ret;
 }

@@ -62,7 +62,7 @@ static unsigned char exynos_dp_calc_edid_check_sum(unsigned char *edid_data)
 	return sum;
 }
 
-static unsigned int exynos_dp_read_edid(struct exynos_dp *dp_regs)
+static unsigned int exynos_dp_read_edid(struct exynos_dp *regs)
 {
 	unsigned char edid[EDID_BLOCK_LENGTH * 2];
 	unsigned int extend_block = 0;

@@ -77,14 +77,14 @@ static unsigned int exynos_dp_read_edid(struct exynos_dp *dp_regs)
 	 */
 
 	/* Read Extension Flag, Number of 128-byte EDID extension blocks */
-	exynos_dp_read_byte_from_i2c(dp_regs, I2C_EDID_DEVICE_ADDR,
+	exynos_dp_read_byte_from_i2c(regs, I2C_EDID_DEVICE_ADDR,
 				     EDID_EXTENSION_FLAG, &extend_block);
 
 	if (extend_block > 0) {
 		printf("DP EDID data includes a single extension!\n");
 
 		/* Read EDID data */
-		retval = exynos_dp_read_bytes_from_i2c(dp_regs,
+		retval = exynos_dp_read_bytes_from_i2c(regs,
 						I2C_EDID_DEVICE_ADDR,
 						EDID_HEADER_PATTERN,
 						EDID_BLOCK_LENGTH,

@@ -100,7 +100,7 @@ static unsigned int exynos_dp_read_edid(struct exynos_dp *dp_regs)
 		}
 
 		/* Read additional EDID data */
-		retval = exynos_dp_read_bytes_from_i2c(dp_regs,
+		retval = exynos_dp_read_bytes_from_i2c(regs,
 				I2C_EDID_DEVICE_ADDR,
 				EDID_BLOCK_LENGTH,
 				EDID_BLOCK_LENGTH,

@@ -115,13 +115,13 @@ static unsigned int exynos_dp_read_edid(struct exynos_dp *dp_regs)
 			return -1;
 		}
 
-		exynos_dp_read_byte_from_dpcd(dp_regs, DPCD_TEST_REQUEST,
+		exynos_dp_read_byte_from_dpcd(regs, DPCD_TEST_REQUEST,
 					      &test_vector);
 		if (test_vector & DPCD_TEST_EDID_READ) {
-			exynos_dp_write_byte_to_dpcd(dp_regs,
+			exynos_dp_write_byte_to_dpcd(regs,
 				DPCD_TEST_EDID_CHECKSUM,
 				edid[EDID_BLOCK_LENGTH + EDID_CHECKSUM]);
-			exynos_dp_write_byte_to_dpcd(dp_regs,
+			exynos_dp_write_byte_to_dpcd(regs,
 				DPCD_TEST_RESPONSE,
 				DPCD_TEST_EDID_CHECKSUM_WRITE);
 		}

@@ -129,7 +129,7 @@ static unsigned int exynos_dp_read_edid(struct exynos_dp *dp_regs)
 		debug("DP EDID data does not include any extensions.\n");
 
 		/* Read EDID data */
-		retval = exynos_dp_read_bytes_from_i2c(dp_regs,
+		retval = exynos_dp_read_bytes_from_i2c(regs,
 				I2C_EDID_DEVICE_ADDR,
 				EDID_HEADER_PATTERN,
 				EDID_BLOCK_LENGTH,

@@ -145,12 +145,12 @@ static unsigned int exynos_dp_read_edid(struct exynos_dp *dp_regs)
 			return -1;
 		}
 
-		exynos_dp_read_byte_from_dpcd(dp_regs, DPCD_TEST_REQUEST,
+		exynos_dp_read_byte_from_dpcd(regs, DPCD_TEST_REQUEST,
 			&test_vector);
 		if (test_vector & DPCD_TEST_EDID_READ) {
-			exynos_dp_write_byte_to_dpcd(dp_regs,
+			exynos_dp_write_byte_to_dpcd(regs,
 				DPCD_TEST_EDID_CHECKSUM, edid[EDID_CHECKSUM]);
-			exynos_dp_write_byte_to_dpcd(dp_regs,
+			exynos_dp_write_byte_to_dpcd(regs,
 				DPCD_TEST_RESPONSE,
 				DPCD_TEST_EDID_CHECKSUM_WRITE);
 		}

@@ -161,8 +161,8 @@ static unsigned int exynos_dp_read_edid(struct exynos_dp *dp_regs)
 	return 0;
 }
 
-static unsigned int exynos_dp_handle_edid(struct exynos_dp *dp_regs,
-					  struct exynos_dp_priv *edp_info)
+static unsigned int exynos_dp_handle_edid(struct exynos_dp *regs,
+					  struct exynos_dp_priv *priv)
 {
 	unsigned char buf[12];
 	unsigned int ret;

@@ -180,7 +180,7 @@ static unsigned int exynos_dp_handle_edid(struct exynos_dp *dp_regs,
 	retry_cnt = 5;
 	while (retry_cnt) {
 		/* Read DPCD 0x0000-0x000b */
-		ret = exynos_dp_read_bytes_from_dpcd(dp_regs, DPCD_DPCD_REV, 12,
+		ret = exynos_dp_read_bytes_from_dpcd(regs, DPCD_DPCD_REV, 12,
 						     buf);
 		if (ret != EXYNOS_DP_SUCCESS) {
 			if (retry_cnt == 0) {

@@ -195,7 +195,7 @@ static unsigned int exynos_dp_handle_edid(struct exynos_dp *dp_regs,
 	/* */
 	temp = buf[DPCD_DPCD_REV];
 	if (temp == DP_DPCD_REV_10 || temp == DP_DPCD_REV_11)
-		edp_info->dpcd_rev = temp;
+		priv->dpcd_rev = temp;
 	else {
 		printf("DP Wrong DPCD Rev : %x\n", temp);
 		return -ENODEV;

@@ -203,33 +203,33 @@ static unsigned int exynos_dp_handle_edid(struct exynos_dp *dp_regs,
 
 	temp = buf[DPCD_MAX_LINK_RATE];
 	if (temp == DP_LANE_BW_1_62 || temp == DP_LANE_BW_2_70)
-		edp_info->lane_bw = temp;
+		priv->lane_bw = temp;
 	else {
 		printf("DP Wrong MAX LINK RATE : %x\n", temp);
 		return -EINVAL;
 	}
 
 	/* Refer VESA Display Port Standard Ver1.1a Page 120 */
-	if (edp_info->dpcd_rev == DP_DPCD_REV_11) {
+	if (priv->dpcd_rev == DP_DPCD_REV_11) {
 		temp = buf[DPCD_MAX_LANE_COUNT] & 0x1f;
 		if (buf[DPCD_MAX_LANE_COUNT] & 0x80)
-			edp_info->dpcd_efc = 1;
+			priv->dpcd_efc = 1;
 		else
-			edp_info->dpcd_efc = 0;
+			priv->dpcd_efc = 0;
 	} else {
 		temp = buf[DPCD_MAX_LANE_COUNT];
-		edp_info->dpcd_efc = 0;
+		priv->dpcd_efc = 0;
 	}
 
 	if (temp == DP_LANE_CNT_1 || temp == DP_LANE_CNT_2 ||
 			temp == DP_LANE_CNT_4) {
-		edp_info->lane_cnt = temp;
+		priv->lane_cnt = temp;
 	} else {
 		printf("DP Wrong MAX LANE COUNT : %x\n", temp);
 		return -EINVAL;
 	}
 
-	ret = exynos_dp_read_edid(dp_regs);
+	ret = exynos_dp_read_edid(regs);
 	if (ret != EXYNOS_DP_SUCCESS) {
 		printf("DP exynos_dp_read_edid() failed\n");
 		return -EINVAL;

@@ -238,35 +238,35 @@ static unsigned int exynos_dp_handle_edid(struct exynos_dp *dp_regs,
 	return ret;
 }
 
-static void exynos_dp_init_training(struct exynos_dp *dp_regs)
+static void exynos_dp_init_training(struct exynos_dp *regs)
 {
 	/*
 	 * MACRO_RST must be applied after the PLL_LOCK to avoid
 	 * the DP inter pair skew issue for at least 10 us
 	 */
-	exynos_dp_reset_macro(dp_regs);
+	exynos_dp_reset_macro(regs);
 
 	/* All DP analog module power up */
-	exynos_dp_set_analog_power_down(dp_regs, POWER_ALL, 0);
+	exynos_dp_set_analog_power_down(regs, POWER_ALL, 0);
 }
 
-static unsigned int exynos_dp_link_start(struct exynos_dp *dp_regs,
-					 struct exynos_dp_priv *edp_info)
+static unsigned int exynos_dp_link_start(struct exynos_dp *regs,
+					 struct exynos_dp_priv *priv)
 {
 	unsigned char buf[5];
 	unsigned int ret = 0;
 
 	debug("DP: %s was called\n", __func__);
 
-	edp_info->lt_info.lt_status = DP_LT_CR;
-	edp_info->lt_info.ep_loop = 0;
-	edp_info->lt_info.cr_loop[0] = 0;
-	edp_info->lt_info.cr_loop[1] = 0;
-	edp_info->lt_info.cr_loop[2] = 0;
-	edp_info->lt_info.cr_loop[3] = 0;
+	priv->lt_info.lt_status = DP_LT_CR;
+	priv->lt_info.ep_loop = 0;
+	priv->lt_info.cr_loop[0] = 0;
+	priv->lt_info.cr_loop[1] = 0;
+	priv->lt_info.cr_loop[2] = 0;
+	priv->lt_info.cr_loop[3] = 0;
 
 		/* Set sink to D0 (Sink Not Ready) mode. */
-	ret = exynos_dp_write_byte_to_dpcd(dp_regs, DPCD_SINK_POWER_STATE,
+	ret = exynos_dp_write_byte_to_dpcd(regs, DPCD_SINK_POWER_STATE,
 					   DPCD_SET_POWER_STATE_D0);
 	if (ret != EXYNOS_DP_SUCCESS) {
 		printf("DP write_dpcd_byte failed\n");

@@ -274,24 +274,24 @@ static unsigned int exynos_dp_link_start(struct exynos_dp *dp_regs,
 	}
 
 	/* Set link rate and count as you want to establish */
-	exynos_dp_set_link_bandwidth(dp_regs, edp_info->lane_bw);
-	exynos_dp_set_lane_count(dp_regs, edp_info->lane_cnt);
+	exynos_dp_set_link_bandwidth(regs, priv->lane_bw);
+	exynos_dp_set_lane_count(regs, priv->lane_cnt);
 
 	/* Setup RX configuration */
-	buf[0] = edp_info->lane_bw;
-	buf[1] = edp_info->lane_cnt;
+	buf[0] = priv->lane_bw;
+	buf[1] = priv->lane_cnt;
 
-	ret = exynos_dp_write_bytes_to_dpcd(dp_regs, DPCD_LINK_BW_SET, 2, buf);
+	ret = exynos_dp_write_bytes_to_dpcd(regs, DPCD_LINK_BW_SET, 2, buf);
 	if (ret != EXYNOS_DP_SUCCESS) {
 		printf("DP write_dpcd_byte failed\n");
 		return ret;
 	}
 
-	exynos_dp_set_lane_pre_emphasis(dp_regs, PRE_EMPHASIS_LEVEL_0,
-			edp_info->lane_cnt);
+	exynos_dp_set_lane_pre_emphasis(regs, PRE_EMPHASIS_LEVEL_0,
+			priv->lane_cnt);
 
 	/* Set training pattern 1 */
-	exynos_dp_set_training_pattern(dp_regs, TRAINING_PTN1);
+	exynos_dp_set_training_pattern(regs, TRAINING_PTN1);
 
 	/* Set RX training pattern */
 	buf[0] = DPCD_SCRAMBLING_DISABLED | DPCD_TRAINING_PATTERN_1;

@@ -305,7 +305,7 @@ static unsigned int exynos_dp_link_start(struct exynos_dp *dp_regs,
 	buf[4] = DPCD_PRE_EMPHASIS_SET_PATTERN_2_LEVEL_0 |
 		DPCD_VOLTAGE_SWING_SET_PATTERN_1_LEVEL_0;
 
-	ret = exynos_dp_write_bytes_to_dpcd(dp_regs, DPCD_TRAINING_PATTERN_SET,
+	ret = exynos_dp_write_bytes_to_dpcd(regs, DPCD_TRAINING_PATTERN_SET,
 					    5, buf);
 	if (ret != EXYNOS_DP_SUCCESS) {
 		printf("DP write_dpcd_byte failed\n");

@@ -315,13 +315,13 @@ static unsigned int exynos_dp_link_start(struct exynos_dp *dp_regs,
 	return ret;
 }
 
-static unsigned int exynos_dp_training_pattern_dis(struct exynos_dp *dp_regs)
+static unsigned int exynos_dp_training_pattern_dis(struct exynos_dp *regs)
 {
 	unsigned int ret = EXYNOS_DP_SUCCESS;
 
-	exynos_dp_set_training_pattern(dp_regs, DP_NONE);
+	exynos_dp_set_training_pattern(regs, DP_NONE);
 
-	ret = exynos_dp_write_byte_to_dpcd(dp_regs, DPCD_TRAINING_PATTERN_SET,
+	ret = exynos_dp_write_byte_to_dpcd(regs, DPCD_TRAINING_PATTERN_SET,
 					   DPCD_TRAINING_PATTERN_DISABLED);
 	if (ret != EXYNOS_DP_SUCCESS) {
 		printf("DP request_link_training_req failed\n");

@@ -332,12 +332,12 @@ static unsigned int exynos_dp_training_pattern_dis(struct exynos_dp *dp_regs)
 }
 
 static unsigned int exynos_dp_enable_rx_to_enhanced_mode(
-		struct exynos_dp *dp_regs, unsigned char enable)
+		struct exynos_dp *regs, unsigned char enable)
 {
 	unsigned char data;
 	unsigned int ret = EXYNOS_DP_SUCCESS;
 
-	ret = exynos_dp_read_byte_from_dpcd(dp_regs, DPCD_LANE_COUNT_SET,
+	ret = exynos_dp_read_byte_from_dpcd(regs, DPCD_LANE_COUNT_SET,
 					    &data);
 	if (ret != EXYNOS_DP_SUCCESS) {
 		printf("DP read_from_dpcd failed\n");

@@ -349,7 +349,7 @@ static unsigned int exynos_dp_enable_rx_to_enhanced_mode(
 	else
 		data = DPCD_LN_COUNT_SET(data);
 
-	ret = exynos_dp_write_byte_to_dpcd(dp_regs, DPCD_LANE_COUNT_SET, data);
+	ret = exynos_dp_write_byte_to_dpcd(regs, DPCD_LANE_COUNT_SET, data);
 	if (ret != EXYNOS_DP_SUCCESS) {
 			printf("DP write_to_dpcd failed\n");
 			return -EAGAIN;

@@ -359,24 +359,24 @@ static unsigned int exynos_dp_enable_rx_to_enhanced_mode(
 	return ret;
 }
 
-static unsigned int exynos_dp_set_enhanced_mode(struct exynos_dp *dp_regs,
+static unsigned int exynos_dp_set_enhanced_mode(struct exynos_dp *regs,
 						unsigned char enhance_mode)
 {
 	unsigned int ret = EXYNOS_DP_SUCCESS;
 
-	ret = exynos_dp_enable_rx_to_enhanced_mode(dp_regs, enhance_mode);
+	ret = exynos_dp_enable_rx_to_enhanced_mode(regs, enhance_mode);
 	if (ret != EXYNOS_DP_SUCCESS) {
 		printf("DP rx_enhance_mode failed\n");
 		return -EAGAIN;
 	}
 
-	exynos_dp_enable_enhanced_mode(dp_regs, enhance_mode);
+	exynos_dp_enable_enhanced_mode(regs, enhance_mode);
 
 	return ret;
 }
 
-static int exynos_dp_read_dpcd_lane_stat(struct exynos_dp *dp_regs,
-					 struct exynos_dp_priv *edp_info,
+static int exynos_dp_read_dpcd_lane_stat(struct exynos_dp *regs,
+					 struct exynos_dp_priv *priv,
 					 unsigned char *status)
 {
 	unsigned int ret, i;

@@ -389,14 +389,14 @@ static int exynos_dp_read_dpcd_lane_stat(struct exynos_dp *dp_regs,
 	shift_val[2] = 0;
 	shift_val[3] = 4;
 
-	ret = exynos_dp_read_bytes_from_dpcd(dp_regs, DPCD_LANE0_1_STATUS, 2,
+	ret = exynos_dp_read_bytes_from_dpcd(regs, DPCD_LANE0_1_STATUS, 2,
 					     buf);
 	if (ret != EXYNOS_DP_SUCCESS) {
 		printf("DP read lane status failed\n");
 		return ret;
 	}
 
-	for (i = 0; i < edp_info->lane_cnt; i++) {
+	for (i = 0; i < priv->lane_cnt; i++) {
 		lane_stat[i] = (buf[(i / 2)] >> shift_val[i]) & 0x0f;
 		if (lane_stat[0] != lane_stat[i]) {
 			printf("Wrong lane status\n");

@@ -409,7 +409,7 @@ static int exynos_dp_read_dpcd_lane_stat(struct exynos_dp *dp_regs,
 	return ret;
 }
 
-static unsigned int exynos_dp_read_dpcd_adj_req(struct exynos_dp *dp_regs,
+static unsigned int exynos_dp_read_dpcd_adj_req(struct exynos_dp *regs,
 		unsigned char lane_num, unsigned char *sw, unsigned char *em)
 {
 	unsigned int ret = EXYNOS_DP_SUCCESS;

@@ -420,7 +420,7 @@ static unsigned int exynos_dp_read_dpcd_adj_req(struct exynos_dp *dp_regs,
 	/* lane_num value is used as array index, so this range 0 ~ 3 */
 	dpcd_addr = DPCD_ADJUST_REQUEST_LANE0_1 + (lane_num / 2);
 
-	ret = exynos_dp_read_byte_from_dpcd(dp_regs, dpcd_addr, &buf);
+	ret = exynos_dp_read_byte_from_dpcd(regs, dpcd_addr, &buf);
 	if (ret != EXYNOS_DP_SUCCESS) {
 		printf("DP read adjust request failed\n");
 		return -EAGAIN;

@@ -432,53 +432,53 @@ static unsigned int exynos_dp_read_dpcd_adj_req(struct exynos_dp *dp_regs,
 	return ret;
 }
 
-static int exynos_dp_equalizer_err_link(struct exynos_dp *dp_regs,
-					struct exynos_dp_priv *edp_info)
+static int exynos_dp_equalizer_err_link(struct exynos_dp *regs,
+					struct exynos_dp_priv *priv)
 {
 	int ret;
 
-	ret = exynos_dp_training_pattern_dis(dp_regs);
+	ret = exynos_dp_training_pattern_dis(regs);
 	if (ret != EXYNOS_DP_SUCCESS) {
 		printf("DP training_pattern_disable() failed\n");
-		edp_info->lt_info.lt_status = DP_LT_FAIL;
+		priv->lt_info.lt_status = DP_LT_FAIL;
 	}
 
-	ret = exynos_dp_set_enhanced_mode(dp_regs, edp_info->dpcd_efc);
+	ret = exynos_dp_set_enhanced_mode(regs, priv->dpcd_efc);
 	if (ret != EXYNOS_DP_SUCCESS) {
 		printf("DP set_enhanced_mode() failed\n");
-		edp_info->lt_info.lt_status = DP_LT_FAIL;
+		priv->lt_info.lt_status = DP_LT_FAIL;
 	}
 
 	return ret;
 }
 
-static int exynos_dp_reduce_link_rate(struct exynos_dp *dp_regs,
-				      struct exynos_dp_priv *edp_info)
+static int exynos_dp_reduce_link_rate(struct exynos_dp *regs,
+				      struct exynos_dp_priv *priv)
 {
 	int ret;
 
-	if (edp_info->lane_bw == DP_LANE_BW_2_70) {
-		edp_info->lane_bw = DP_LANE_BW_1_62;
+	if (priv->lane_bw == DP_LANE_BW_2_70) {
+		priv->lane_bw = DP_LANE_BW_1_62;
 		printf("DP Change lane bw to 1.62Gbps\n");
-		edp_info->lt_info.lt_status = DP_LT_START;
+		priv->lt_info.lt_status = DP_LT_START;
 		ret = EXYNOS_DP_SUCCESS;
 	} else {
-		ret = exynos_dp_training_pattern_dis(dp_regs);
+		ret = exynos_dp_training_pattern_dis(regs);
 		if (ret != EXYNOS_DP_SUCCESS)
 			printf("DP training_patter_disable() failed\n");
 
-		ret = exynos_dp_set_enhanced_mode(dp_regs, edp_info->dpcd_efc);
+		ret = exynos_dp_set_enhanced_mode(regs, priv->dpcd_efc);
 		if (ret != EXYNOS_DP_SUCCESS)
 			printf("DP set_enhanced_mode() failed\n");
 
-		edp_info->lt_info.lt_status = DP_LT_FAIL;
+		priv->lt_info.lt_status = DP_LT_FAIL;
 	}
 
 	return ret;
 }
 
-static unsigned int exynos_dp_process_clock_recovery(struct exynos_dp *dp_regs,
-					struct exynos_dp_priv *edp_info)
+static unsigned int exynos_dp_process_clock_recovery(struct exynos_dp *regs,
+					struct exynos_dp_priv *priv)
 {
 	unsigned int ret = EXYNOS_DP_SUCCESS;
 	unsigned char lane_stat;

@@ -491,22 +491,22 @@ static unsigned int exynos_dp_process_clock_recovery(struct exynos_dp *dp_regs,
 	debug("DP: %s was called\n", __func__);
 	mdelay(1);
 
-	ret = exynos_dp_read_dpcd_lane_stat(dp_regs, edp_info, &lane_stat);
+	ret = exynos_dp_read_dpcd_lane_stat(regs, priv, &lane_stat);
 	if (ret != EXYNOS_DP_SUCCESS) {
 			printf("DP read lane status failed\n");
-			edp_info->lt_info.lt_status = DP_LT_FAIL;
+			priv->lt_info.lt_status = DP_LT_FAIL;
 			return ret;
 	}
 
 	if (lane_stat & DP_LANE_STAT_CR_DONE) {
 		debug("DP clock Recovery training succeed\n");
-		exynos_dp_set_training_pattern(dp_regs, TRAINING_PTN2);
+		exynos_dp_set_training_pattern(regs, TRAINING_PTN2);
 
-		for (i = 0; i < edp_info->lane_cnt; i++) {
-			ret = exynos_dp_read_dpcd_adj_req(dp_regs, i,
+		for (i = 0; i < priv->lane_cnt; i++) {
+			ret = exynos_dp_read_dpcd_adj_req(regs, i,
 						&adj_req_sw, &adj_req_em);
 			if (ret != EXYNOS_DP_SUCCESS) {
-				edp_info->lt_info.lt_status = DP_LT_FAIL;
+				priv->lt_info.lt_status = DP_LT_FAIL;
 				return ret;
 			}
 

@@ -518,7 +518,7 @@ static unsigned int exynos_dp_process_clock_recovery(struct exynos_dp *dp_regs,
 				lt_ctl_val[i] |= MAX_DRIVE_CURRENT_REACH_3 |
 					MAX_PRE_EMPHASIS_REACH_3;
 			}
-			exynos_dp_set_lanex_pre_emphasis(dp_regs,
+			exynos_dp_set_lanex_pre_emphasis(regs,
 							 lt_ctl_val[i], i);
 		}
 

@@ -528,39 +528,39 @@ static unsigned int exynos_dp_process_clock_recovery(struct exynos_dp *dp_regs,
 		buf[3] = lt_ctl_val[2];
 		buf[4] = lt_ctl_val[3];
 
-		ret = exynos_dp_write_bytes_to_dpcd(dp_regs,
+		ret = exynos_dp_write_bytes_to_dpcd(regs,
 				DPCD_TRAINING_PATTERN_SET, 5, buf);
 		if (ret != EXYNOS_DP_SUCCESS) {
 			printf("DP write training pattern1 failed\n");
-			edp_info->lt_info.lt_status = DP_LT_FAIL;
+			priv->lt_info.lt_status = DP_LT_FAIL;
 			return ret;
 		} else
-			edp_info->lt_info.lt_status = DP_LT_ET;
+			priv->lt_info.lt_status = DP_LT_ET;
 	} else {
-		for (i = 0; i < edp_info->lane_cnt; i++) {
+		for (i = 0; i < priv->lane_cnt; i++) {
 			lt_ctl_val[i] = exynos_dp_get_lanex_pre_emphasis(
-						dp_regs, i);
-				ret = exynos_dp_read_dpcd_adj_req(dp_regs, i,
+						regs, i);
+				ret = exynos_dp_read_dpcd_adj_req(regs, i,
 						&adj_req_sw, &adj_req_em);
 			if (ret != EXYNOS_DP_SUCCESS) {
 				printf("DP read adj req failed\n");
-				edp_info->lt_info.lt_status = DP_LT_FAIL;
+				priv->lt_info.lt_status = DP_LT_FAIL;
 				return ret;
 			}
 
 			if ((adj_req_sw == VOLTAGE_LEVEL_3) ||
 					(adj_req_em == PRE_EMPHASIS_LEVEL_3))
-				ret = exynos_dp_reduce_link_rate(dp_regs,
-								 edp_info);
+				ret = exynos_dp_reduce_link_rate(regs,
+								 priv);
 
 			if ((DRIVE_CURRENT_SET_0_GET(lt_ctl_val[i]) ==
 						adj_req_sw) &&
 				(PRE_EMPHASIS_SET_0_GET(lt_ctl_val[i]) ==
 						adj_req_em)) {
-				edp_info->lt_info.cr_loop[i]++;
-				if (edp_info->lt_info.cr_loop[i] == MAX_CR_LOOP)
+				priv->lt_info.cr_loop[i]++;
+				if (priv->lt_info.cr_loop[i] == MAX_CR_LOOP)
 					ret = exynos_dp_reduce_link_rate(
-							dp_regs, edp_info);
+							regs, priv);
 			}
 
 			lt_ctl_val[i] = 0;

@@ -571,15 +571,15 @@ static unsigned int exynos_dp_process_clock_recovery(struct exynos_dp *dp_regs,
 				lt_ctl_val[i] |= MAX_DRIVE_CURRENT_REACH_3 |
 					MAX_PRE_EMPHASIS_REACH_3;
 			}
-			exynos_dp_set_lanex_pre_emphasis(dp_regs,
+			exynos_dp_set_lanex_pre_emphasis(regs,
 							 lt_ctl_val[i], i);
 		}
 
-		ret = exynos_dp_write_bytes_to_dpcd(dp_regs,
+		ret = exynos_dp_write_bytes_to_dpcd(regs,
 				DPCD_TRAINING_LANE0_SET, 4, lt_ctl_val);
 		if (ret != EXYNOS_DP_SUCCESS) {
 			printf("DP write training pattern2 failed\n");
-			edp_info->lt_info.lt_status = DP_LT_FAIL;
+			priv->lt_info.lt_status = DP_LT_FAIL;
 			return ret;
 		}
 	}

@@ -588,7 +588,7 @@ static unsigned int exynos_dp_process_clock_recovery(struct exynos_dp *dp_regs,
 }
 
 static unsigned int exynos_dp_process_equalizer_training(
-		struct exynos_dp *dp_regs, struct exynos_dp_priv *edp_info)
+		struct exynos_dp *regs, struct exynos_dp_priv *priv)
 {
 	unsigned int ret = EXYNOS_DP_SUCCESS;
 	unsigned char lane_stat, adj_req_sw, adj_req_em, i;

@@ -600,33 +600,33 @@ static unsigned int exynos_dp_process_equalizer_training(
 
 	mdelay(1);
 
-	ret = exynos_dp_read_dpcd_lane_stat(dp_regs, edp_info, &lane_stat);
+	ret = exynos_dp_read_dpcd_lane_stat(regs, priv, &lane_stat);
 	if (ret != EXYNOS_DP_SUCCESS) {
 		printf("DP read lane status failed\n");
-		edp_info->lt_info.lt_status = DP_LT_FAIL;
+		priv->lt_info.lt_status = DP_LT_FAIL;
 		return ret;
 	}
 
 	debug("DP lane stat : %x\n", lane_stat);
 
 	if (lane_stat & DP_LANE_STAT_CR_DONE) {
-		ret = exynos_dp_read_byte_from_dpcd(dp_regs,
+		ret = exynos_dp_read_byte_from_dpcd(regs,
 						    DPCD_LN_ALIGN_UPDATED,
 						    &sink_stat);
 		if (ret != EXYNOS_DP_SUCCESS) {
-			edp_info->lt_info.lt_status = DP_LT_FAIL;
+			priv->lt_info.lt_status = DP_LT_FAIL;
 
 			return ret;
 		}
 
 		interlane_aligned = (sink_stat & DPCD_INTERLANE_ALIGN_DONE);
 
-		for (i = 0; i < edp_info->lane_cnt; i++) {
-			ret = exynos_dp_read_dpcd_adj_req(dp_regs, i,
+		for (i = 0; i < priv->lane_cnt; i++) {
+			ret = exynos_dp_read_dpcd_adj_req(regs, i,
 					&adj_req_sw, &adj_req_em);
 			if (ret != EXYNOS_DP_SUCCESS) {
 				printf("DP read adj req 1 failed\n");
-				edp_info->lt_info.lt_status = DP_LT_FAIL;
+				priv->lt_info.lt_status = DP_LT_FAIL;
 
 				return ret;
 			}

@@ -646,91 +646,91 @@ static unsigned int exynos_dp_process_equalizer_training(
 			&& (interlane_aligned == DPCD_INTERLANE_ALIGN_DONE)) {
 			debug("DP Equalizer training succeed\n");
 
-			f_bw = exynos_dp_get_link_bandwidth(dp_regs);
-			f_lane_cnt = exynos_dp_get_lane_count(dp_regs);
+			f_bw = exynos_dp_get_link_bandwidth(regs);
+			f_lane_cnt = exynos_dp_get_lane_count(regs);
 
 			debug("DP final BandWidth : %x\n", f_bw);
 			debug("DP final Lane Count : %x\n", f_lane_cnt);
 
-			edp_info->lt_info.lt_status = DP_LT_FINISHED;
+			priv->lt_info.lt_status = DP_LT_FINISHED;
 
-			exynos_dp_equalizer_err_link(dp_regs, edp_info);
+			exynos_dp_equalizer_err_link(regs, priv);
 
 		} else {
-			edp_info->lt_info.ep_loop++;
+			priv->lt_info.ep_loop++;
 
-			if (edp_info->lt_info.ep_loop > MAX_EQ_LOOP) {
-				if (edp_info->lane_bw == DP_LANE_BW_2_70) {
+			if (priv->lt_info.ep_loop > MAX_EQ_LOOP) {
+				if (priv->lane_bw == DP_LANE_BW_2_70) {
 					ret = exynos_dp_reduce_link_rate(
-							dp_regs, edp_info);
+							regs, priv);
 				} else {
-					edp_info->lt_info.lt_status =
+					priv->lt_info.lt_status =
 								DP_LT_FAIL;
-					exynos_dp_equalizer_err_link(dp_regs,
-								     edp_info);
+					exynos_dp_equalizer_err_link(regs,
+								     priv);
 				}
 			} else {
-				for (i = 0; i < edp_info->lane_cnt; i++)
+				for (i = 0; i < priv->lane_cnt; i++)
 					exynos_dp_set_lanex_pre_emphasis(
-						dp_regs, lt_ctl_val[i], i);
+						regs, lt_ctl_val[i], i);
 
-				ret = exynos_dp_write_bytes_to_dpcd(dp_regs,
+				ret = exynos_dp_write_bytes_to_dpcd(regs,
 						DPCD_TRAINING_LANE0_SET,
 						4, lt_ctl_val);
 				if (ret != EXYNOS_DP_SUCCESS) {
 					printf("DP set lt pattern failed\n");
-					edp_info->lt_info.lt_status =
+					priv->lt_info.lt_status =
 								DP_LT_FAIL;
-					exynos_dp_equalizer_err_link(dp_regs,
-								     edp_info);
+					exynos_dp_equalizer_err_link(regs,
+								     priv);
 				}
 			}
 		}
-	} else if (edp_info->lane_bw == DP_LANE_BW_2_70) {
-		ret = exynos_dp_reduce_link_rate(dp_regs, edp_info);
+	} else if (priv->lane_bw == DP_LANE_BW_2_70) {
+		ret = exynos_dp_reduce_link_rate(regs, priv);
 	} else {
-		edp_info->lt_info.lt_status = DP_LT_FAIL;
-		exynos_dp_equalizer_err_link(dp_regs, edp_info);
+		priv->lt_info.lt_status = DP_LT_FAIL;
+		exynos_dp_equalizer_err_link(regs, priv);
 	}
 
 	return ret;
 }
 
-static unsigned int exynos_dp_sw_link_training(struct exynos_dp *dp_regs,
-					       struct exynos_dp_priv *edp_info)
+static unsigned int exynos_dp_sw_link_training(struct exynos_dp *regs,
+					       struct exynos_dp_priv *priv)
 {
 	unsigned int ret = 0;
 	int training_finished;
 
 	/* Turn off unnecessary lane */
-	if (edp_info->lane_cnt == 1)
-		exynos_dp_set_analog_power_down(dp_regs, CH1_BLOCK, 1);
+	if (priv->lane_cnt == 1)
+		exynos_dp_set_analog_power_down(regs, CH1_BLOCK, 1);
 
 	training_finished = 0;
 
-	edp_info->lt_info.lt_status = DP_LT_START;
+	priv->lt_info.lt_status = DP_LT_START;
 
 	/* Process here */
 	while (!training_finished) {
-		switch (edp_info->lt_info.lt_status) {
+		switch (priv->lt_info.lt_status) {
 		case DP_LT_START:
-			ret = exynos_dp_link_start(dp_regs, edp_info);
+			ret = exynos_dp_link_start(regs, priv);
 			if (ret != EXYNOS_DP_SUCCESS) {
 				printf("DP LT:link start failed\n");
 				return ret;
 			}
 			break;
 		case DP_LT_CR:
-			ret = exynos_dp_process_clock_recovery(dp_regs,
-							       edp_info);
+			ret = exynos_dp_process_clock_recovery(regs,
+							       priv);
 			if (ret != EXYNOS_DP_SUCCESS) {
 				printf("DP LT:clock recovery failed\n");
 				return ret;
 			}
 			break;
 		case DP_LT_ET:
-			ret = exynos_dp_process_equalizer_training(dp_regs,
-								   edp_info);
+			ret = exynos_dp_process_equalizer_training(regs,
+								   priv);
 			if (ret != EXYNOS_DP_SUCCESS) {
 				printf("DP LT:equalizer training failed\n");
 				return ret;