x86: Add support for samus

Commit 1057e6c broke use of the timer with driver model. If the timer is used before relocation, then it becomes broken after relocation. This prevents some x86 boards from booting. Fix it.

Fixes 1057e6c (timer: Set up the real timer after driver model is available)

Signed-off-by Simon Glass <[email protected]>

---

 common/board_r.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

common/board_r.c +2 -0

index 52a9b26..0f068bf 100644
@@ -318,11 +318,13 @@ static int initr_dm(void)
        /* Save the pre-reloc driver model and start a new one */
        gd->dm_root_f = gd->dm_root;
        gd->dm_root = NULL;
+#ifdef CONFIG_TIMER
+       gd->timer = NULL;

Hi Simon,

Quoted 3 lines · Simon Glass

Commit 1057e6c broke use of the timer with driver model. If the timer is used before relocation, then it becomes broken after relocation. This prevents some x86 boards from booting. Fix it.

Isn't the broken due to gd not initialized to zero?

Quoted 25 lines

Fixes 1057e6c (timer: Set up the real timer after driver model is available)

Signed-off-by Simon Glass <[email protected]>

---

 common/board_r.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

common/board_r.c +3 -0

index 52a9b26..0f068bf 100644
@@ -318,11 +318,13 @@ static int initr_dm(void)
        /* Save the pre-reloc driver model and start a new one */
        gd->dm_root_f = gd->dm_root;
        gd->dm_root = NULL;
+#ifdef CONFIG_TIMER
+       gd->timer = NULL;
+#endif
        ret = dm_init_and_scan(false);
        if (ret)
                return ret;
 #ifdef CONFIG_TIMER_EARLY

common/board_r.c static int initr_dm(void)

Quoted 5 lines

common/board_r.c +0 -2

-       gd->timer = NULL;
        ret = dm_timer_init();
        if (ret)
                return ret;
--

Regards,
Bin

This is missing, with causes lldiv() to fail on boards with use the private libgcc. Add the missing routine.

Code is available for using the CLZ instruction but it is not enabled at present.

If the device cannot be probed, syscon_get_by_driver_data() will still return a useful value in its devp parameter. Ensure that it returns NULL instead.

Signed-off-by Simon Glass <[email protected]>

---

 drivers/core/syscon-uclass.c | 1 +
 1 file changed, 1 insertion(+)

drivers/core/syscon-uclass.c +0 -0

index a0666d0..e03f46a 100644

Hi Simon,

Quoted 3 lines · Simon Glass

If the device cannot be probed, syscon_get_by_driver_data() will still return a useful value in its devp parameter. Ensure that it returns NULL instead.

Shouldn't this be the caller's bug, that caller must check the return value?

Quoted 16 lines

Signed-off-by Simon Glass <[email protected]>

---

 drivers/core/syscon-uclass.c | 1 +
 1 file changed, 1 insertion(+)

drivers/core/syscon-uclass.c +0 -0

index a0666d0..e03f46a 100644
@@ -38,6 +38,7 @@ int syscon_get_by_driver_data(ulong driver_data, struct udevice **devp)
        struct uclass *uc;
        int ret;
 

drivers/core/syscon-uclass.c int syscon_get_by_driver_data(ulong driver_data, struct udevice **devp)

Quoted 5 lines

drivers/core/syscon-uclass.c +1 -1

+       *devp = NULL;
        ret = uclass_get(UCLASS_SYSCON, &uc);
        if (ret)
                return ret;
--

Regards,
Bin

At present simple-panel requires regulator support and will not build without it. But some panels do not have a power supply, or at least not one that can be controlled. Update the implementation to cope with this.

Signed-off-by Simon Glass <[email protected]>

Hi Simon,

On Sun, 6 Mar 2016 19:27:48 -0700
Simon Glass sjg at chromium.org wrote:

Quoted 5 lines

At present simple-panel requires regulator support and will not build without it. But some panels do not have a power supply, or at least not one that can be controlled. Update the implementation to cope with this.

Signed-off-by Simon Glass <[email protected]>

Acked-by Anatolij Gustschin <[email protected]>

Some CPUs use microcode and each core can have a different version of microcode loaded. Also some CPUs support the concept of an integer ID used for identification purposes. Add support for these in the CPU uclass.

Signed-off-by Simon Glass <[email protected]>

---

 cmd/cpu.c     | 7 +++++++
 include/cpu.h | 5 +++++
 2 files changed, 12 insertions(+)

Quoted 7 lines · Simon Glass

Some CPUs use microcode and each core can have a different version of microcode loaded. Also some CPUs support the concept of an integer ID used for identification purposes. Add support for these in the CPU uclass.

Signed-off-by Simon Glass <[email protected]>

---

Quoted 4 lines

 cmd/cpu.c     | 7 +++++++
 include/cpu.h | 5 +++++
 2 files changed, 12 insertions(+)

Reviewed-by Bin Meng <[email protected]>

We can use GPIOs as binary digits for reading 'strapping' values. Each GPIO is assigned a single bit and can be set high or low on the circuit board. We already have a legacy function for reading these values. Add one that supports driver model.

Signed-off-by Simon Glass <[email protected]>

---

 drivers/gpio/gpio-uclass.c | 18 ++++++++++++++++++
 include/asm-generic/gpio.h | 12 ++++++++++++
 2 files changed, 30 insertions(+)

Quoted 8 lines · Simon Glass

We can use GPIOs as binary digits for reading 'strapping' values. Each GPIO is assigned a single bit and can be set high or low on the circuit board. We already have a legacy function for reading these values. Add one that supports driver model.

Signed-off-by Simon Glass <[email protected]>

---

Quoted 4 lines

 drivers/gpio/gpio-uclass.c | 18 ++++++++++++++++++
 include/asm-generic/gpio.h | 12 ++++++++++++
 2 files changed, 30 insertions(+)

Reviewed-by Bin Meng <[email protected]>

Some functions do not change the struct gpio_desc parameter. Update these to use const so this is clear.

Signed-off-by Simon Glass <[email protected]>

---

 drivers/gpio/gpio-uclass.c | 10 +++++-----
 include/asm-generic/gpio.h | 10 +++++-----
 2 files changed, 10 insertions(+), 10 deletions(-)

Quoted 6 lines · Simon Glass

Some functions do not change the struct gpio_desc parameter. Update these to use const so this is clear.

Signed-off-by Simon Glass <[email protected]>

---

Quoted 4 lines

 drivers/gpio/gpio-uclass.c | 10 +++++-----
 include/asm-generic/gpio.h | 10 +++++-----
 2 files changed, 10 insertions(+), 10 deletions(-)

Reviewed-by Bin Meng <[email protected]>

It is common to read a config register value, clear and set some bits, then write back the updated value. Add functions to do this in one step, for convenience.

Signed-off-by Simon Glass <[email protected]>

---

 drivers/pci/pci-uclass.c | 57 ++++++++++++++++++++++++++++++++++++++++++++++++
 include/pci.h            | 23 +++++++++++++++++++
 2 files changed, 80 insertions(+)

Quoted 7 lines · Simon Glass

It is common to read a config register value, clear and set some bits, then write back the updated value. Add functions to do this in one step, for convenience.

Signed-off-by Simon Glass <[email protected]>

---

Quoted 4 lines

 drivers/pci/pci-uclass.c | 57 ++++++++++++++++++++++++++++++++++++++++++++++++
 include/pci.h            | 23 +++++++++++++++++++
 2 files changed, 80 insertions(+)

Reviewed-by Bin Meng <[email protected]>

Two comments are missing a parameter and there is an extra blank line. Also two of the region access macros are misnamed. Correct these problems.

Signed-off-by Simon Glass <[email protected]>

---

 drivers/pci/pci-uclass.c | 1 -
 include/pci.h            | 6 ++++--
 2 files changed, 4 insertions(+), 3 deletions(-)

Quoted 6 lines · Simon Glass

Two comments are missing a parameter and there is an extra blank line. Also two of the region access macros are misnamed. Correct these problems.

Signed-off-by Simon Glass <[email protected]>

---

Quoted 4 lines

 drivers/pci/pci-uclass.c | 1 -
 include/pci.h            | 6 ++++--
 2 files changed, 4 insertions(+), 3 deletions(-)

Reviewed-by Bin Meng <[email protected]>

Add one more step into the init sequence. This fixes the keyboard on samus, which otherwise does not work.

Signed-off-by Simon Glass <[email protected]>

---

 drivers/input/i8042.c | 6 ++++++
 1 file changed, 6 insertions(+)

drivers/input/i8042.c +0 -0

index 661d7fd..12f8934 100644

Output the pointer returned by each call to malloc(). This can be useful when debugging memory problems.

Signed-off-by Simon Glass <[email protected]>

---

 common/malloc_simple.c | 7 +++++--
 1 file changed, 5 insertions(+), 2 deletions(-)

Quoted 3 lines · Simon Glass

Output the pointer returned by each call to malloc(). This can be useful when debugging memory problems.

Quoted 6 lines

Signed-off-by Simon Glass <[email protected]>

---

 common/malloc_simple.c | 7 +++++--
 1 file changed, 5 insertions(+), 2 deletions(-)

Reviewed-by Bin Meng <[email protected]>

At present on x86 machines with use cache-as-RAM, the memory goes away just before board_init_r() is called. This means that serial drivers are no-longer unavailable, until initr_dm() it called, etc.

Any attempt to use printf() within this period will cause a hang.

To fix this, mark the serial devices as 'unavailable' when it is no-longer available. Bring it back when serial_initialize() is called. This means that the debug UART will be used instead for this period.

Signed-off-by Simon Glass <[email protected]>

---

 common/board_f.c               | 7 +++++++
 drivers/serial/serial-uclass.c | 1 +
 2 files changed, 8 insertions(+)

common/board_f.c +0 -0

index 622093a..109025a 100644

Hi Simon,

Quoted 24 lines · Simon Glass

At present on x86 machines with use cache-as-RAM, the memory goes away just before board_init_r() is called. This means that serial drivers are no-longer unavailable, until initr_dm() it called, etc.

Any attempt to use printf() within this period will cause a hang.

To fix this, mark the serial devices as 'unavailable' when it is no-longer available. Bring it back when serial_initialize() is called. This means that the debug UART will be used instead for this period.

Signed-off-by Simon Glass <[email protected]>

---

 common/board_f.c               | 7 +++++++
 drivers/serial/serial-uclass.c | 1 +
 2 files changed, 8 insertions(+)

common/board_f.c +0 -0

index 622093a..109025a 100644
@@ -1096,6 +1096,13 @@ void board_init_f_r(void)
                hang();
 

common/board_f.c void board_init_f_r(void) · line 1104

Quoted 7 lines

common/board_f.c +6 -0

        /*
+        * The pre-relocation drivers may be using memory that has now gone
+        * away. Mark serial as unavailable - this will fall back to the debug
+        * UART if available.
+        */
+       gd->flags &= ~GD_FLG_SERIAL_READY;
+

What about other architectures (non-X86 and non-ARC)?

Quoted 10 lines

common/board_f.c +1 -0

+       /*
         * U-Boot has been copied into SDRAM, the BSS has been cleared etc.
         * Transfer execution from Flash to RAM by calculating the address
         * of the in-RAM copy of board_init_r() and calling it

drivers/serial/serial-uclass.c +0 -0

index 1c447ff..6562be0 100644

drivers/serial/serial-uclass.c int serial_init(void) · line 119

Quoted 4 lines

drivers/serial/serial-uclass.c +1 -0

@@ -116,6 +116,7 @@ int serial_init(void)
 void serial_initialize(void)
 {
        serial_find_console_or_panic();
+       gd->flags |= GD_FLG_SERIAL_READY;

I think we can simply replace this to:

void serial_initialize(void)

{
    serial_init();
}

This does not need to be modified at run-time, so make it const.

Signed-off-by Simon Glass <[email protected]>

---

 arch/x86/cpu/cpu.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

Quoted 8 lines · Simon Glass

This does not need to be modified at run-time, so make it const.

Signed-off-by Simon Glass <[email protected]>

---

 arch/x86/cpu/cpu.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

Reviewed-by Bin Meng <[email protected]>

These two identifiers can be useful for drivers which need to adjust their behaviour depending on the CPU family or stepping (revision).

Signed-off-by Simon Glass <[email protected]>

---

 arch/x86/cpu/cpu.c         | 10 ++++++++++
 arch/x86/include/asm/cpu.h | 14 ++++++++++++++
 2 files changed, 24 insertions(+)

arch/x86/cpu/cpu.c +0 -0

index 8800e09..e2aad19 100644

arch/x86/cpu/cpu.c +2 -0

+}
+
 int x86_cpu_init_f(void)
 {
        const u32 em_rst = ~X86_CR0_EM;

arch/x86/include/asm/cpu.h +6 -0

index 18b0345..987dc65 100644
@@ -260,4 +260,18 @@ void cpu_call32(ulong code_seg32, ulong target, ulong table);
  */
 int cpu_jump_to_64bit(ulong setup_base, ulong target);
 
+/**
+ * cpu_get_family_model() - Get the family and model for the CPU
+ *
+ * @return the CPU ID masked with 0x0fff0ff0
+ */
+u32 cpu_get_family_model(void);

Hi Simon,

Quoted 18 lines · Simon Glass

These two identifiers can be useful for drivers which need to adjust their behaviour depending on the CPU family or stepping (revision).

Signed-off-by Simon Glass <[email protected]>

---

 arch/x86/cpu/cpu.c         | 10 ++++++++++
 arch/x86/include/asm/cpu.h | 14 ++++++++++++++
 2 files changed, 24 insertions(+)

arch/x86/cpu/cpu.c +0 -0

index 8800e09..e2aad19 100644
@@ -333,6 +333,16 @@ static inline void get_fms(struct cpuinfo_x86 *c, uint32_t tfms)
                c->x86_model += ((tfms >> 16) & 0xF) << 4;
 }
 

arch/x86/cpu/cpu.c static inline void get_fms(struct cpuinfo_x86 *c, uint32_t tfms) · line 338

Quoted 3 lines

arch/x86/cpu/cpu.c +3 -0

+u32 cpu_get_family_model(void)
+{
+       return gd->arch.x86_device & 0x0fff0ff0;

The decrypted family and model are stored in gd->arch.x86 and gd->arch.x86_model. Returning raw data would still need the caller to parse it. Why not just return these directly?

arch/x86/cpu/cpu.c static inline void get_fms(struct cpuinfo_x86 *c, uint32_t tfms) · line 343

Quoted 6 lines

arch/x86/cpu/cpu.c +5 -0

+}
+
+u32 cpu_get_stepping(void)
+{
+       return gd->arch.x86_device & 0xf;

This is gd->arch.x86_mask.

Quoted 20 lines

arch/x86/cpu/cpu.c +2 -0

+}
+
 int x86_cpu_init_f(void)
 {
        const u32 em_rst = ~X86_CR0_EM;

arch/x86/include/asm/cpu.h +6 -0

index 18b0345..987dc65 100644
@@ -260,4 +260,18 @@ void cpu_call32(ulong code_seg32, ulong target, ulong table);
  */
 int cpu_jump_to_64bit(ulong setup_base, ulong target);
 
+/**
+ * cpu_get_family_model() - Get the family and model for the CPU
+ *
+ * @return the CPU ID masked with 0x0fff0ff0
+ */
+u32 cpu_get_family_model(void);

arch/x86/include/asm/cpu.h void cpu_call32(ulong code_seg32, ulong target, ulong table);

Quoted 10 lines

arch/x86/include/asm/cpu.h +8 -1

+
+/**
+ * cpu_get_stepping() - Get the stepping value for the CPU
+ *
+ * @return the CPU ID masked with 0xf
+ */
+u32 cpu_get_stepping(void);
+
 #endif
--

Regards,
Bin

Hi Bin,

Quoted 21 lines · Bin Meng

Hi Simon,

Quoted 18 lines · Simon Glass

These two identifiers can be useful for drivers which need to adjust their behaviour depending on the CPU family or stepping (revision).

Signed-off-by Simon Glass <[email protected]>

---

 arch/x86/cpu/cpu.c         | 10 ++++++++++
 arch/x86/include/asm/cpu.h | 14 ++++++++++++++
 2 files changed, 24 insertions(+)

arch/x86/cpu/cpu.c +0 -0

index 8800e09..e2aad19 100644
@@ -333,6 +333,16 @@ static inline void get_fms(struct cpuinfo_x86 *c, uint32_t tfms)
                c->x86_model += ((tfms >> 16) & 0xF) << 4;
 }
 

Quoted 7 lines

arch/x86/cpu/cpu.c static inline void get_fms(struct cpuinfo_x86 *c, uint32_t tfms) · line 338

Quoted 3 lines

arch/x86/cpu/cpu.c +3 -0

+u32 cpu_get_family_model(void)
+{
+       return gd->arch.x86_device & 0x0fff0ff0;

The decrypted family and model are stored in gd->arch.x86 and gd->arch.x86_model. Returning raw data would still need the caller to parse it. Why not just return these directly?

I want to compare them in one shot to BROADWELL_FAMILY_ULT, etc.

What exactly are you suggesting?

Quoted 8 lines

arch/x86/cpu/cpu.c static inline void get_fms(struct cpuinfo_x86 *c, uint32_t tfms) · line 343

Quoted 6 lines

arch/x86/cpu/cpu.c +5 -0

+}
+
+u32 cpu_get_stepping(void)
+{
+       return gd->arch.x86_device & 0xf;

This is gd->arch.x86_mask.

OK. That's a funny name for stepping.

This cache-as-RAM (CAR) code is common to several Intel chips. Create a new intel_common directory and move it in there.

Signed-off-by Simon Glass <[email protected]>

---

 arch/x86/cpu/Makefile                          | 1 +
 arch/x86/cpu/intel_common/Makefile             | 7 +++++++
 arch/x86/cpu/{ivybridge => intel_common}/car.S | 0
 arch/x86/cpu/ivybridge/Makefile                | 1 -
 4 files changed, 8 insertions(+), 1 deletion(-)
 create mode 100644 arch/x86/cpu/intel_common/Makefile
 rename arch/x86/cpu/{ivybridge => intel_common}/car.S (100%)

This code is used on several Intel CPUs. Move it into a common location.

Signed-off-by Simon Glass <[email protected]>

---

 arch/x86/cpu/intel_common/Makefile                         | 3 +++
 arch/x86/cpu/intel_common/car.S                            | 2 +-
 arch/x86/cpu/{ivybridge => intel_common}/microcode_intel.c | 4 +++-

 arch/x86/cpu/ivybridge/Makefile                            | 1 -
 arch/x86/cpu/ivybridge/cpu.c                               | 2 +-
 arch/x86/include/asm/{arch-ivybridge => }/microcode.h      | 0
 6 files changed, 8 insertions(+), 4 deletions(-)
 rename arch/x86/cpu/{ivybridge => intel_common}/microcode_intel.c (98%)
 rename arch/x86/include/asm/{arch-ivybridge => }/microcode.h (100%)

arch/x86/cpu/intel_common/Makefile +3 -0

index 5dd9573..bc7c3ff 100644
@@ -5,3 +5,6 @@
 #
 
 obj-$(CONFIG_HAVE_MRC) += car.o
+ifndef CONFIG_TARGET_EFI
+obj-y += microcode_intel.o
+endif

arch/x86/cpu/intel_common/car.S +1 -1

index 1defabf..81ac976 100644
@@ -12,12 +12,12 @@
  */
 
 #include <common.h>
+#include <asm/microcode.h>
 #include <asm/msr-index.h>
 #include <asm/mtrr.h>
 #include <asm/post.h>
 #include <asm/processor.h>
 #include <asm/processor-flags.h>
-#include <asm/arch/microcode.h>
 
 #define MTRR_PHYS_BASE_MSR(reg) (0x200 + 2 * (reg))
 #define MTRR_PHYS_MASK_MSR(reg) (0x200 + 2 * (reg) + 1)

arch/x86/cpu/intel_common/microcode_intel.c renamed from arch/x86/cpu/ivybridge/microcode_intel.c +3 -1

similarity index 98%
rename from arch/x86/cpu/ivybridge/microcode_intel.c
rename to arch/x86/cpu/intel_common/microcode_intel.c
index 2440a97..3054fab 100644
@@ -12,10 +12,12 @@
 #include <fdtdec.h>
 #include <libfdt.h>
 #include <asm/cpu.h>
+#include <asm/microcode.h>
 #include <asm/msr.h>
 #include <asm/msr-index.h>
 #include <asm/processor.h>
-#include <asm/arch/microcode.h>
+
+DECLARE_GLOBAL_DATA_PTR;
 
 /**
  * struct microcode_update - standard microcode header from Intel

arch/x86/cpu/ivybridge/Makefile +0 -1

index b117f0d..78006f1 100644
@@ -13,7 +13,6 @@ obj-y += gma.o
 obj-y += lpc.o
 obj-y += me_status.o
 obj-y += model_206ax.o
-obj-y += microcode_intel.o
 obj-y += northbridge.o
 obj-y += report_platform.o
 obj-y += sata.o

arch/x86/cpu/ivybridge/cpu.c +1 -1

index 948833c..c54e800 100644
@@ -19,13 +19,13 @@
 #include <asm/cpu.h>
 #include <asm/io.h>
 #include <asm/lapic.h>
+#include <asm/microcode.h>
 #include <asm/msr.h>
 #include <asm/mtrr.h>
 #include <asm/pci.h>
 #include <asm/post.h>
 #include <asm/processor.h>
 #include <asm/arch/model_206ax.h>
-#include <asm/arch/microcode.h>
 #include <asm/arch/pch.h>
 #include <asm/arch/sandybridge.h>
 

arch/x86/include/asm/microcode.h renamed from arch/x86/include/asm/arch-ivybridge/microcode.h +0 -0

similarity index 100%
rename from arch/x86/include/asm/arch-ivybridge/microcode.h
rename to arch/x86/include/asm/microcode.h

There are several blocks of registers that are accessed from all over the code on Intel CPUs. These don't currently have their own driver and it is not clear whether having a driver makes sense.

An example is the Memory Controller Hub (MCH). We map it to a known location on some Intel chips (mostly those without FSP - Firmware Support Package).

Add a new header file for these registers, and move MCH into it.

Signed-off-by Simon Glass <[email protected]>

---

 arch/x86/cpu/ivybridge/cpu.c                      |  1 +
 arch/x86/cpu/ivybridge/gma.c                      |  1 +
 arch/x86/cpu/ivybridge/northbridge.c              |  5 +++--
 arch/x86/cpu/ivybridge/sdram.c                    |  3 ++-
 arch/x86/include/asm/arch-ivybridge/sandybridge.h |  3 ---
 arch/x86/include/asm/intel_regs.h                 | 15 +++++++++++++++
 6 files changed, 22 insertions(+), 6 deletions(-)
 create mode 100644 arch/x86/include/asm/intel_regs.h

arch/x86/cpu/ivybridge/cpu.c +1 -0

index c54e800..f847a2f 100644
@@ -17,6 +17,7 @@
 #include <fdtdec.h>
 #include <pch.h>
 #include <asm/cpu.h>
+#include <asm/intel_regs.h>
 #include <asm/io.h>
 #include <asm/lapic.h>
 #include <asm/microcode.h>

arch/x86/cpu/ivybridge/gma.c +1 -0

index 3b6291e..87e06e7 100644
@@ -12,6 +12,7 @@
 #include <errno.h>
 #include <fdtdec.h>
 #include <pci_rom.h>
+#include <asm/intel_regs.h>
 #include <asm/io.h>
 #include <asm/mtrr.h>
 #include <asm/pci.h>

arch/x86/cpu/ivybridge/northbridge.c +3 -2

index a066607..f7e0bc3 100644
@@ -12,6 +12,7 @@
 #include <asm/msr.h>
 #include <asm/acpi.h>
 #include <asm/cpu.h>
+#include <asm/intel_regs.h>
 #include <asm/io.h>
 #include <asm/pci.h>
 #include <asm/processor.h>

@@ -167,8 +168,8 @@ static void sandybridge_setup_northbridge_bars(struct udevice *dev)
        debug("Setting up static registers\n");
        dm_pci_write_config32(dev, EPBAR, DEFAULT_EPBAR | 1);
        dm_pci_write_config32(dev, EPBAR + 4, (0LL + DEFAULT_EPBAR) >> 32);
-       dm_pci_write_config32(dev, MCHBAR, DEFAULT_MCHBAR | 1);
-       dm_pci_write_config32(dev, MCHBAR + 4, (0LL + DEFAULT_MCHBAR) >> 32);
+       dm_pci_write_config32(dev, MCHBAR, MCH_BASE_ADDRESS | 1);
+       dm_pci_write_config32(dev, MCHBAR + 4, (0LL + MCH_BASE_ADDRESS) >> 32);
        /* 64MB - busses 0-63 */
        dm_pci_write_config32(dev, PCIEXBAR, DEFAULT_PCIEXBAR | 5);
        dm_pci_write_config32(dev, PCIEXBAR + 4,

arch/x86/cpu/ivybridge/sdram.c +2 -1

index e23c422..6f45071 100644
@@ -23,6 +23,7 @@
 #include <asm/processor.h>
 #include <asm/gpio.h>
 #include <asm/global_data.h>
+#include <asm/intel_regs.h>
 #include <asm/mrccache.h>
 #include <asm/mtrr.h>
 #include <asm/pci.h>

@@ -682,7 +683,7 @@ int dram_init(void)
 {
        struct pei_data pei_data __aligned(8) = {
                .pei_version = PEI_VERSION,
-               .mchbar = DEFAULT_MCHBAR,
+               .mchbar = MCH_BASE_ADDRESS,
                .dmibar = DEFAULT_DMIBAR,
                .epbar = DEFAULT_EPBAR,
                .pciexbar = CONFIG_PCIE_ECAM_BASE,

arch/x86/include/asm/arch-ivybridge/sandybridge.h +0 -3

index d137d67..59b05cc 100644
@@ -38,7 +38,6 @@
 #define IED_SIZE       0x400000
 
 /* Northbridge BARs */
-#define DEFAULT_MCHBAR         0xfed10000      /* 16 KB */
 #define DEFAULT_DMIBAR         0xfed18000      /* 4 KB */
 #define DEFAULT_EPBAR          0xfed19000      /* 4 KB */
 #define DEFAULT_RCBABASE       0xfed1c000

@@ -97,8 +96,6 @@
 /*
  * MCHBAR
  */
-#define MCHBAR_REG(reg)                (DEFAULT_MCHBAR + (reg))
-
 #define SSKPD          0x5d14  /* 16bit (scratchpad) */
 #define BIOS_RESET_CPL 0x5da8  /* 8bit */
 

arch/x86/include/asm/intel_regs.h new file +0 -0

new file mode 100644
index 0000000..61e0ec2

This is similar to MCH in that it is used in various drivers. Add it to the common header.

Signed-off-by Simon Glass <[email protected]>

---

 arch/x86/cpu/ivybridge/bd82x6x.c          | 1 +
 arch/x86/cpu/ivybridge/lpc.c              | 6 ++++--
 arch/x86/include/asm/arch-ivybridge/pch.h | 5 -----
 arch/x86/include/asm/intel_regs.h         | 4 ++++
 4 files changed, 9 insertions(+), 7 deletions(-)

Some of the LPC code is common to several Intel LPC devices. Move it into a common location.

Signed-off-by Simon Glass <[email protected]>

---

 arch/x86/cpu/intel_common/Makefile        |   1 +
 arch/x86/cpu/intel_common/lpc_common.c    | 102 ++++++++++++++++++++++++++++++
 arch/x86/cpu/ivybridge/bd82x6x.c          |  16 +----
 arch/x86/cpu/ivybridge/lpc.c              |  73 ++-------------------
 arch/x86/include/asm/arch-ivybridge/pch.h |   2 -
 arch/x86/include/asm/lpc_common.h         |  59 +++++++++++++++++
 6 files changed, 168 insertions(+), 85 deletions(-)
 create mode 100644 arch/x86/cpu/intel_common/lpc_common.c
 create mode 100644 arch/x86/include/asm/lpc_common.h

arch/x86/cpu/intel_common/Makefile +1 -0

index bc7c3ff..36c150d 100644
@@ -5,6 +5,7 @@
 #
 
 obj-$(CONFIG_HAVE_MRC) += car.o
+obj-y += lpc_common.o
 ifndef CONFIG_TARGET_EFI
 obj-y += microcode_intel.o
 endif

arch/x86/cpu/intel_common/lpc_common.c new file +11 -0

new file mode 100644
index 0000000..2a3b941
@@ -0,0 +1,102 @@
+/*
+ * Copyright (c) 2016 Google, Inc
+ *
+ * SPDX-License-Identifier:    GPL-2.0
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <errno.h>
+#include <fdtdec.h>
+#include <pch.h>

arch/x86/cpu/intel_common/lpc_common.c new file +81 -0

+static void enable_spi_prefetch(struct udevice *pch)
+{
+       u8 reg8;
+
+       dm_pci_read_config8(pch, 0xdc, &reg8);
+       reg8 &= ~(3 << 2);
+       reg8 |= (2 << 2); /* Prefetching and Caching Enabled */
+       dm_pci_write_config8(pch, 0xdc, reg8);
+}
+
+static void enable_port80_on_lpc(struct udevice *pch)
+{
+       /* Enable port 80 POST on LPC */
+       dm_pci_write_config32(pch, PCH_RCBA_BASE, RCB_BASE_ADDRESS | 1);
+       clrbits_le32(RCB_REG(GCS), 4);
+}
+
+/**
+ * lpc_early_init() - set up LPC serial ports and other early things
+ *
+ * @dev:       LPC device
+ * @return 0 if OK, -ve on error
+ */
+int lpc_common_early_init(struct udevice *dev)
+{
+       struct udevice *pch = dev->parent;
+       struct reg_info {
+               u32 base;
+               u32 size;
+       } values[4], *ptr;
+       int count;
+       int i;
+
+       count = fdtdec_get_int_array_count(gd->fdt_blob, dev->of_offset,
+                       "intel,gen-dec", (u32 *)values,
+                       sizeof(values) / sizeof(u32));
+       if (count < 0)
+               return -EINVAL;
+
+       /* Set COM1/COM2 decode range */
+       dm_pci_write_config16(pch, LPC_IO_DEC, 0x0010);
+
+       /* Enable PS/2 Keyboard/Mouse, EC areas and COM1 */
+       dm_pci_write_config16(pch, LPC_EN, KBC_LPC_EN | MC_LPC_EN |
+                             GAMEL_LPC_EN | COMA_LPC_EN);
+
+       /* Write all registers but use 0 if we run out of data */
+       count = count * sizeof(u32) / sizeof(values[0]);
+       for (i = 0, ptr = values; i < ARRAY_SIZE(values); i++, ptr++) {
+               u32 reg = 0;
+
+               if (i < count)
+                       reg = ptr->base | PCI_COMMAND_IO | (ptr->size << 16);
+               dm_pci_write_config32(pch, LPC_GENX_DEC(i), reg);
+       }
+
+       enable_spi_prefetch(pch);
+
+       /* This is already done in start.S, but let's do it in C */
+       enable_port80_on_lpc(pch);
+
+       return 0;
+}
+
+int lpc_set_spi_protect(struct udevice *dev, int bios_ctrl, bool protect)
+{
+       uint8_t bios_cntl;
+
+       /* Adjust the BIOS write protect and SMM BIOS Write Protect Disable */
+       dm_pci_read_config8(dev, bios_ctrl, &bios_cntl);
+       if (protect) {
+               bios_cntl &= ~BIOS_CTRL_BIOSWE;
+               bios_cntl |= BIT(5);
+       } else {
+               bios_cntl |= BIOS_CTRL_BIOSWE;
+               bios_cntl &= ~BIT(5);
+       }
+       dm_pci_write_config8(dev, bios_ctrl, bios_cntl);
+
+       return 0;
+}

arch/x86/cpu/ivybridge/bd82x6x.c +2 -14

index 55057e0..4c039ac 100644
@@ -14,6 +14,7 @@
 #include <asm/intel_regs.h>
 #include <asm/io.h>
 #include <asm/lapic.h>
+#include <asm/lpc_common.h>
 #include <asm/pci.h>
 #include <asm/arch/bd82x6x.h>
 #include <asm/arch/model_206ax.h>

@@ -188,20 +189,7 @@ static int bd82x6x_pch_get_spi_base(struct udevice *dev, ulong *sbasep)
 
 static int bd82x6x_set_spi_protect(struct udevice *dev, bool protect)
 {
-       uint8_t bios_cntl;
-
-       /* Adjust the BIOS write protect and SMM BIOS Write Protect Disable */
-       dm_pci_read_config8(dev, BIOS_CTRL, &bios_cntl);
-       if (protect) {
-               bios_cntl &= ~BIOS_CTRL_BIOSWE;
-               bios_cntl |= BIT(5);
-       } else {
-               bios_cntl |= BIOS_CTRL_BIOSWE;
-               bios_cntl &= ~BIT(5);
-       }
-       dm_pci_write_config8(dev, BIOS_CTRL, bios_cntl);
-
-       return 0;
+       return lpc_set_spi_protect(dev, BIOS_CTRL, protect);
 }
 
 static int bd82x6x_get_gpio_base(struct udevice *dev, u32 *gbasep)

arch/x86/cpu/ivybridge/lpc.c +4 -69

index 26ffaa0..88ab797 100644
@@ -17,6 +17,7 @@
 #include <asm/interrupt.h>
 #include <asm/io.h>
 #include <asm/ioapic.h>
+#include <asm/lpc_common.h>
 #include <asm/pci.h>
 #include <asm/arch/pch.h>
 

@@ -405,26 +406,6 @@ static void pch_fixups(struct udevice *pch)
        setbits_le32(RCB_REG(0x21a8), 0x3);
 }
 
-/*
- * Enable Prefetching and Caching.
- */
-static void enable_spi_prefetch(struct udevice *pch)
-{
-       u8 reg8;
-
-       dm_pci_read_config8(pch, 0xdc, &reg8);
-       reg8 &= ~(3 << 2);
-       reg8 |= (2 << 2); /* Prefetching and Caching Enabled */
-       dm_pci_write_config8(pch, 0xdc, reg8);
-}
-
-static void enable_port80_on_lpc(struct udevice *pch)
-{
-       /* Enable port 80 POST on LPC */
-       dm_pci_write_config32(pch, PCH_RCBA_BASE, RCB_BASE_ADDRESS | 1);
-       clrbits_le32(RCB_REG(GCS), 4);
-}
-
 static void set_spi_speed(void)
 {
        u32 fdod;

@@ -441,54 +422,6 @@ static void set_spi_speed(void)
        clrsetbits_8(RCB_REG(SPI_FREQ_SWSEQ), 7, fdod);
 }
 
-/**
- * lpc_early_init() - set up LPC serial ports and other early things
- *
- * @dev:       LPC device
- * @return 0 if OK, -ve on error
- */
-static int lpc_early_init(struct udevice *dev)
-{
-       struct reg_info {
-               u32 base;
-               u32 size;
-       } values[4], *ptr;
-       int count;
-       int i;
-
-       count = fdtdec_get_int_array_count(gd->fdt_blob, dev->of_offset,
-                       "intel,gen-dec", (u32 *)values,
-                       sizeof(values) / sizeof(u32));
-       if (count < 0)
-               return -EINVAL;
-
-       /* Set COM1/COM2 decode range */
-       dm_pci_write_config16(dev->parent, LPC_IO_DEC, 0x0010);
-
-       /* Enable PS/2 Keyboard/Mouse, EC areas and COM1 */
-       dm_pci_write_config16(dev->parent, LPC_EN, KBC_LPC_EN | MC_LPC_EN |
-                             GAMEL_LPC_EN | COMA_LPC_EN);
-
-       /* Write all registers but use 0 if we run out of data */
-       count = count * sizeof(u32) / sizeof(values[0]);
-       for (i = 0, ptr = values; i < ARRAY_SIZE(values); i++, ptr++) {
-               u32 reg = 0;
-
-               if (i < count)
-                       reg = ptr->base | PCI_COMMAND_IO | (ptr->size << 16);
-               dm_pci_write_config32(dev->parent, LPC_GENX_DEC(i), reg);
-       }
-
-       enable_spi_prefetch(dev->parent);
-
-       /* This is already done in start.S, but let's do it in C */
-       enable_port80_on_lpc(dev->parent);
-
-       set_spi_speed();
-
-       return 0;
-}
-
 static int lpc_init_extra(struct udevice *dev)
 {
        struct udevice *pch = dev->parent;

@@ -551,6 +484,8 @@ static int lpc_init_extra(struct udevice *dev)
 
 static int bd82x6x_lpc_early_init(struct udevice *dev)
 {
+       set_spi_speed();
+
        /* Setting up Southbridge. In the northbridge code. */
        debug("Setting up static southbridge registers\n");
        dm_pci_write_config32(dev->parent, PCH_RCBA_BASE,

@@ -575,7 +510,7 @@ static int bd82x6x_lpc_probe(struct udevice *dev)
        int ret;
 
        if (!(gd->flags & GD_FLG_RELOC)) {
-               ret = lpc_early_init(dev);
+               ret = lpc_common_early_init(dev);
                if (ret) {
                        debug("%s: lpc_early_init() failed\n", __func__);
                        return ret;

arch/x86/include/asm/arch-ivybridge/pch.h +0 -2

index 628b517..f96dc2b 100644
@@ -211,8 +211,6 @@
 
 #define SMBUS_TIMEOUT          (10 * 1000 * 100)
 
-#define PCH_RCBA_BASE          0xf0
-
 #define VCH            0x0000  /* 32bit */
 #define VCAP1          0x0004  /* 32bit */
 #define VCAP2          0x0008  /* 32bit */

arch/x86/include/asm/lpc_common.h new file +0 -0

new file mode 100644
index 0000000..bcfccaf

arch/x86/include/asm/lpc_common.h new file +42 -0

+
+#define PCH_RCBA_BASE          0xf0
+
+#define RC             0x3400  /* 32bit */
+#define GCS            0x3410  /* 32bit */
+
+#define PMBASE                 0x40
+#define ACPI_CNTL              0x44
+
+#define LPC_IO_DEC             0x80 /* IO Decode Ranges Register */
+#define  COMB_DEC_RANGE                (1 << 4)  /* 0x2f8-0x2ff (COM2) */
+#define  COMA_DEC_RANGE                (0 << 0)  /* 0x3f8-0x3ff (COM1) */
+#define LPC_EN                 0x82 /* LPC IF Enables Register */
+#define  CNF2_LPC_EN           (1 << 13) /* 0x4e/0x4f */
+#define  CNF1_LPC_EN           (1 << 12) /* 0x2e/0x2f */
+#define  MC_LPC_EN             (1 << 11) /* 0x62/0x66 */
+#define  KBC_LPC_EN            (1 << 10) /* 0x60/0x64 */
+#define  GAMEH_LPC_EN          (1 << 9)  /* 0x208/0x20f */
+#define  GAMEL_LPC_EN          (1 << 8)  /* 0x200/0x207 */
+#define  FDD_LPC_EN            (1 << 3)  /* LPC_IO_DEC[12] */
+#define  LPT_LPC_EN            (1 << 2)  /* LPC_IO_DEC[9:8] */
+#define  COMB_LPC_EN           (1 << 1)  /* LPC_IO_DEC[6:4] */
+#define  COMA_LPC_EN           (1 << 0)  /* LPC_IO_DEC[3:2] */
+#define LPC_GEN1_DEC           0x84 /* LPC IF Generic Decode Range 1 */
+#define LPC_GEN2_DEC           0x88 /* LPC IF Generic Decode Range 2 */
+#define LPC_GEN3_DEC           0x8c /* LPC IF Generic Decode Range 3 */
+#define LPC_GEN4_DEC           0x90 /* LPC IF Generic Decode Range 4 */
+#define LPC_GENX_DEC(x)                (0x84 + 4 * (x))
+#define  GEN_DEC_RANGE_256B    0xfc0000  /* 256 Bytes */
+#define  GEN_DEC_RANGE_128B    0x7c0000  /* 128 Bytes */
+#define  GEN_DEC_RANGE_64B     0x3c0000  /* 64 Bytes */
+#define  GEN_DEC_RANGE_32B     0x1c0000  /* 32 Bytes */
+#define  GEN_DEC_RANGE_16B     0x0c0000  /* 16 Bytes */
+#define  GEN_DEC_RANGE_8B      0x040000  /* 8 Bytes */
+#define  GEN_DEC_RANGE_4B      0x000000  /* 4 Bytes */
+#define  GEN_DEC_RANGE_EN      (1 << 0)  /* Range Enable */
+
+/**
+ * lpc_common_early_init() - Set up common LPC init
+ *
+ * This sets up the legacy decode areas, GEN_DEC, SPI prefetch and Port80. It
+ * also puts the RCB in the correct place so that RCB_REG() works.

Hi Simon,

Quoted 8 lines · Simon Glass

Some of the LPC code is common to several Intel LPC devices. Move it into a common location.

Signed-off-by Simon Glass <[email protected]>

---

 arch/x86/cpu/intel_common/Makefile        |   1 +
 arch/x86/cpu/intel_common/lpc_common.c    | 102 ++++++++++++++++++++++++++++++

Quoted 8 lines

 arch/x86/cpu/ivybridge/bd82x6x.c          |  16 +----
 arch/x86/cpu/ivybridge/lpc.c              |  73 ++-------------------
 arch/x86/include/asm/arch-ivybridge/pch.h |   2 -
 arch/x86/include/asm/lpc_common.h         |  59 +++++++++++++++++
 6 files changed, 168 insertions(+), 85 deletions(-)
 create mode 100644 arch/x86/cpu/intel_common/lpc_common.c
 create mode 100644 arch/x86/include/asm/lpc_common.h

Many of the model-specific indexes are common to several Intel CPUs. Add some more common ones, and remove them from the ivybridge-specific header file.

Signed-off-by Simon Glass <[email protected]>

---

 arch/x86/cpu/ivybridge/model_206ax.c              |  5 +--
 arch/x86/include/asm/arch-ivybridge/model_206ax.h | 17 ----------
 arch/x86/include/asm/msr-index.h                  | 41 ++++++++++++++++++++++-
 3 files changed, 43 insertions(+), 20 deletions(-)

Quoted 7 lines · Simon Glass

Many of the model-specific indexes are common to several Intel CPUs. Add some more common ones, and remove them from the ivybridge-specific header file.

Signed-off-by Simon Glass <[email protected]>

---

Quoted 5 lines

 arch/x86/cpu/ivybridge/model_206ax.c              |  5 +--
 arch/x86/include/asm/arch-ivybridge/model_206ax.h | 17 ----------
 arch/x86/include/asm/msr-index.h                  | 41 ++++++++++++++++++++++-
 3 files changed, 43 insertions(+), 20 deletions(-)

Reviewed-by Bin Meng <[email protected]>

Some of the Intel CPU code is common to several Intel CPUs. Move it into a common location along with required declarations.

Signed-off-by Simon Glass <[email protected]>

---

 arch/x86/cpu/intel_common/Makefile        |   1 +
 arch/x86/cpu/intel_common/cpu_common.c    | 111 ++++++++++++++++++++++++++++++
 arch/x86/cpu/ivybridge/cpu.c              |  82 ++--------------------
 arch/x86/include/asm/arch-ivybridge/pch.h |   2 -
 arch/x86/include/asm/cpu_common.h         |  35 ++++++++++
 arch/x86/include/asm/intel_regs.h         |   9 +++
 6 files changed, 162 insertions(+), 78 deletions(-)
 create mode 100644 arch/x86/cpu/intel_common/cpu_common.c
 create mode 100644 arch/x86/include/asm/cpu_common.h

arch/x86/cpu/intel_common/Makefile +0 -0

index 36c150d..e9a2b29 100644

arch/x86/cpu/intel_common/cpu_common.c new file +107 -0

+ */
+
+#include <common.h>
+#include <dm.h>
+#include <errno.h>
+#include <asm/cpu_common.h>
+#include <asm/intel_regs.h>
+#include <asm/lapic.h>
+#include <asm/lpc_common.h>
+#include <asm/msr.h>
+#include <asm/mtrr.h>
+#include <asm/post.h>
+#include <asm/microcode.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static int report_bist_failure(void)
+{
+       if (gd->arch.bist != 0) {
+               post_code(POST_BIST_FAILURE);
+               printf("BIST failed: %08x\n", gd->arch.bist);
+               return -EFAULT;
+       }
+
+       return 0;
+}
+
+int cpu_common_init(void)
+{
+       struct udevice *dev, *lpc;
+       int ret;
+
+       /* Halt if there was a built in self test failure */
+       ret = report_bist_failure();
+       if (ret)
+               return ret;
+
+       enable_lapic();
+
+       ret = microcode_update_intel();
+       if (ret && ret != -EEXIST)
+               return ret;
+
+       /* Enable upper 128bytes of CMOS */
+       writel(1 << 2, RCB_REG(RC));
+
+       /* Early chipset init required before RAM init can work */
+       uclass_first_device(UCLASS_NORTHBRIDGE, &dev);
+
+       ret = uclass_first_device(UCLASS_LPC, &lpc);
+       if (ret)
+               return ret;
+       if (!lpc)
+               return -ENODEV;
+
+       /* Cause the SATA device to do its early init */
+       uclass_first_device(UCLASS_DISK, &dev);
+
+       return 0;
+}
+
+int cpu_set_flex_ratio_to_tdp_nominal(void)
+{
+       msr_t flex_ratio, msr;
+       u8 nominal_ratio;
+
+       /* Check for Flex Ratio support */
+       flex_ratio = msr_read(MSR_FLEX_RATIO);
+       if (!(flex_ratio.lo & FLEX_RATIO_EN))
+               return -EINVAL;
+
+       /* Check for >0 configurable TDPs */
+       msr = msr_read(MSR_PLATFORM_INFO);
+       if (((msr.hi >> 1) & 3) == 0)
+               return -EINVAL;
+
+       /* Use nominal TDP ratio for flex ratio */
+       msr = msr_read(MSR_CONFIG_TDP_NOMINAL);
+       nominal_ratio = msr.lo & 0xff;
+
+       /* See if flex ratio is already set to nominal TDP ratio */
+       if (((flex_ratio.lo >> 8) & 0xff) == nominal_ratio)
+               return 0;
+
+       /* Set flex ratio to nominal TDP ratio */
+       flex_ratio.lo &= ~0xff00;
+       flex_ratio.lo |= nominal_ratio << 8;
+       flex_ratio.lo |= FLEX_RATIO_LOCK;
+       msr_write(MSR_FLEX_RATIO, flex_ratio);
+
+       /* Set flex ratio in soft reset data register bits 11:6 */
+       clrsetbits_le32(RCB_REG(SOFT_RESET_DATA), 0x3f << 6,
+                       (nominal_ratio & 0x3f) << 6);
+
+       debug("CPU: Soft reset to set up flex ratio\n");
+
+       /* Set soft reset control to use register value */
+       setbits_le32(RCB_REG(SOFT_RESET_CTRL), 1);
+
+       /* Issue warm reset, will be "CPU only" due to soft reset data */
+       outb(0x0, PORT_RESET);
+       outb(SYS_RST | RST_CPU, PORT_RESET);
+       cpu_hlt();
+
+       /* Not reached */
+       return -EINVAL;
+}

arch/x86/cpu/ivybridge/cpu.c +6 -76

index f847a2f..b8234ae 100644
@@ -17,6 +17,7 @@
 #include <fdtdec.h>
 #include <pch.h>
 #include <asm/cpu.h>
+#include <asm/cpu_common.h>
 #include <asm/intel_regs.h>
 #include <asm/io.h>
 #include <asm/lapic.h>

@@ -34,51 +35,11 @@ DECLARE_GLOBAL_DATA_PTR;
 
 static int set_flex_ratio_to_tdp_nominal(void)
 {
-       msr_t flex_ratio, msr;
-       u8 nominal_ratio;
-
        /* Minimum CPU revision for configurable TDP support */
        if (cpuid_eax(1) < IVB_CONFIG_TDP_MIN_CPUID)
                return -EINVAL;
 
-       /* Check for Flex Ratio support */
-       flex_ratio = msr_read(MSR_FLEX_RATIO);
-       if (!(flex_ratio.lo & FLEX_RATIO_EN))
-               return -EINVAL;
-
-       /* Check for >0 configurable TDPs */
-       msr = msr_read(MSR_PLATFORM_INFO);
-       if (((msr.hi >> 1) & 3) == 0)
-               return -EINVAL;
-
-       /* Use nominal TDP ratio for flex ratio */
-       msr = msr_read(MSR_CONFIG_TDP_NOMINAL);
-       nominal_ratio = msr.lo & 0xff;
-
-       /* See if flex ratio is already set to nominal TDP ratio */
-       if (((flex_ratio.lo >> 8) & 0xff) == nominal_ratio)
-               return 0;
-
-       /* Set flex ratio to nominal TDP ratio */
-       flex_ratio.lo &= ~0xff00;
-       flex_ratio.lo |= nominal_ratio << 8;
-       flex_ratio.lo |= FLEX_RATIO_LOCK;
-       msr_write(MSR_FLEX_RATIO, flex_ratio);
-
-       /* Set flex ratio in soft reset data register bits 11:6 */
-       clrsetbits_le32(RCB_REG(SOFT_RESET_DATA), 0x3f << 6,
-                       (nominal_ratio & 0x3f) << 6);
-
-       /* Set soft reset control to use register value */
-       setbits_le32(RCB_REG(SOFT_RESET_CTRL), 1);
-
-       /* Issue warm reset, will be "CPU only" due to soft reset data */
-       outb(0x0, PORT_RESET);
-       outb(SYS_RST | RST_CPU, PORT_RESET);
-       cpu_hlt();
-
-       /* Not reached */
-       return -EINVAL;
+       return cpu_set_flex_ratio_to_tdp_nominal();
 }
 
 int arch_cpu_init(void)

@@ -163,17 +124,6 @@ static void enable_usb_bar(struct udevice *bus)
        pci_bus_write_config(bus, usb3, PCI_COMMAND, cmd, PCI_SIZE_32);
 }
 
-static int report_bist_failure(void)
-{
-       if (gd->arch.bist != 0) {
-               post_code(POST_BIST_FAILURE);
-               printf("BIST failed: %08x\n", gd->arch.bist);
-               return -EFAULT;
-       }
-
-       return 0;
-}
-
 int print_cpuinfo(void)
 {
        enum pei_boot_mode_t boot_mode = PEI_BOOT_NONE;

@@ -184,20 +134,6 @@ int print_cpuinfo(void)
        uint16_t pm1_sts;
        int ret;
 
-       /* Halt if there was a built in self test failure */
-       ret = report_bist_failure();
-       if (ret)
-               return ret;
-
-       enable_lapic();
-
-       ret = microcode_update_intel();
-       if (ret)
-               return ret;
-
-       /* Enable upper 128bytes of CMOS */
-       writel(1 << 2, RCB_REG(RC));
-
        /* TODO: cmos_post_init() */
        if (readl(MCHBAR_REG(SSKPD)) == 0xCAFE) {
                debug("soft reset detected\n");

@@ -208,17 +144,9 @@ int print_cpuinfo(void)
                reset_cpu(0);
        }
 
-       /* Early chipset init required before RAM init can work */
-       uclass_first_device(UCLASS_NORTHBRIDGE, &dev);
-
-       ret = uclass_first_device(UCLASS_LPC, &lpc);
+       ret = cpu_common_init();
        if (ret)
                return ret;
-       if (!dev)
-               return -ENODEV;
-
-       /* Cause the SATA device to do its early init */
-       uclass_first_device(UCLASS_DISK, &dev);
 
        /* Check PM1_STS[15] to see if we are waking from Sx */
        pm1_sts = inw(DEFAULT_PMBASE + PM1_STS);

@@ -244,8 +172,10 @@ int print_cpuinfo(void)
                return -ENODEV;
 
        /* Prepare USB controller early in S3 resume */
-       if (boot_mode == PEI_BOOT_RESUME)
+       if (boot_mode == PEI_BOOT_RESUME) {
+               uclass_first_device(UCLASS_LPC, &lpc);
                enable_usb_bar(pci_get_controller(lpc->parent));
+       }
 
        gd->arch.pei_boot_mode = boot_mode;
 

arch/x86/include/asm/arch-ivybridge/pch.h +0 -2

index f96dc2b..e72ff2a 100644
@@ -332,8 +332,6 @@
 #define SPI_FREQ_SWSEQ 0x3893
 #define SPI_DESC_COMP0 0x38b0
 #define SPI_FREQ_WR_ERA        0x38b4
-#define SOFT_RESET_CTRL 0x38f4
-#define SOFT_RESET_DATA 0x38f8
 
 #define DIR_ROUTE(a, b, c, d) \
                (((d) << DIR_IDR) | ((c) << DIR_ICR) | \

arch/x86/include/asm/cpu_common.h new file +0 -0

new file mode 100644
index 0000000..9bf527e

arch/x86/include/asm/cpu_common.h new file +27 -0

+
+#define IA32_PERF_CTL                  0x199
+
+/**
+ * cpu_common_init() - Set up common CPU init
+ *
+ * This reports BIST failure, enables the LAPIC, updates microcode, enables
+ * the upper 128-bytes of CROM RAM, probes the northbridge, PCH, LPC and SATA.
+ *
+ * @return 0 if OK, -ve on error
+ */
+int cpu_common_init(void);
+
+/**
+ * cpu_set_flex_ratio_to_tdp_nominal() - Set up the maximum non-turbo rate
+ *
+ * If a change is needed, this function will do a soft reset so it takes
+ * effect.
+ *
+ * Some details are available here:
+ * http://forum.hwbot.org/showthread.php?t=76092
+ *
+ * @return 0 if OK, -ve on error
+ */
+int cpu_set_flex_ratio_to_tdp_nominal(void);
+
+#endif

arch/x86/include/asm/intel_regs.h +5 -0

index 0bc2fca..8ce33f5 100644
@@ -12,8 +12,17 @@
 #define MCH_BASE_SIZE          0x8000
 #define MCHBAR_REG(reg)                (MCH_BASE_ADDRESS + (reg))
 
+#define MCHBAR_PEI_VERSION     0x5034
+#define MCH_PKG_POWER_LIMIT_LO 0x59a0
+#define MCH_PKG_POWER_LIMIT_HI 0x59a4
+#define MCH_DDR_POWER_LIMIT_LO 0x58e0
+#define MCH_DDR_POWER_LIMIT_HI 0x58e4