ARM: keystone2: Split monitor code / command code

65 lines not on this page · raw message

index 33a2876..eb7aa93 100644
@@ -7,9 +7,11 @@
  * SPDX-License-Identifier:     GPL-2.0+
  */
 
-#ifndef _MON_H_
-#define _MON_H_
+#ifndef _MACH_MON_H_
+#define _MACH_MON_H_
 
+int mon_install(u32 addr, u32 dpsc, u32 freq);
+int mon_power_on(int core_id, void *ep);
 int mon_power_off(int core_id);
 
 #endif

63 lines not on this page · raw message

new file mode 100644
index 0000000..1b127a8
@@ -0,0 +1,28 @@
+/*
+ * Keystone EVM : Power off
+ *
+ * (C) Copyright 2014
+ *     Texas Instruments Incorporated, <www.ti.com>
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#include <common.h>
+#include <command.h>
+#include <asm/arch/mon.h>
+#include <asm/arch/psc_defs.h>
+#include <asm/arch/hardware.h>
+
+int do_poweroff(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	mon_power_off(0);
+
+	psc_disable_module(KS2_LPSC_TETRIS);
+	psc_disable_domain(KS2_TETRIS_PWR_DOMAIN);
+
+	asm volatile ("isb\n"
+		      "dsb\n"
+		      "wfi\n");
+
+	return 0;
+}

index a807127..beb8a76 100644
@@ -9,10 +9,8 @@
 
 #include <common.h>
 #include <asm/io.h>
-#include <asm/arch/mon.h>
 #include <asm/arch/psc_defs.h>
 #include <asm/arch/hardware.h>
-#include <asm/arch/hardware.h>
 
 /**
  * cpu_to_bus - swap bytes of the 32-bit data if the device is BE

@@ -30,22 +28,6 @@ int cpu_to_bus(u32 *ptr, u32 length)
 	return 0;
 }
 
-static int turn_off_myself(void)
-{
-	printf("Turning off ourselves\r\n");
-	mon_power_off(0);
-
-	psc_disable_module(KS2_LPSC_TETRIS);
-	psc_disable_domain(KS2_TETRIS_PWR_DOMAIN);
-
-	asm volatile ("isb\n"
-		      "dsb\n"
-		      "wfi\n");
-
-	printf("What! Should not see that\n");
-	return 0;
-}
-
 static void turn_off_all_dsps(int num_dsps)
 {
 	int i;

@@ -59,17 +41,6 @@ static void turn_off_all_dsps(int num_dsps)
 	}
 }
 
-int do_killme_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
-	return turn_off_myself();
-}
-
-U_BOOT_CMD(
-	killme, 1,      0,      do_killme_cmd,
-	"turn off main ARM core",
-	"turn off main ARM core. Should not live after that :(\n"
-);
-
 int misc_init_r(void)
 {
 	char *env;

index 951d1e5..8991125 100644
@@ -245,6 +245,7 @@ struct blk_desc *scsi_get_dev(int dev)
 }
 #endif
 
+#ifndef CONFIG_SPL_BUILD
 /******************************************************************************
  * scsi boot command intepreter. Derived from diskboot
  */

@@ -368,6 +369,27 @@ int do_scsi (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 	return CMD_RET_USAGE;
 }
 
+U_BOOT_CMD(
+	scsi, 5, 1, do_scsi,
+	"SCSI sub-system",
+	"reset - reset SCSI controller\n"
+	"scsi info  - show available SCSI devices\n"
+	"scsi scan  - (re-)scan SCSI bus\n"
+	"scsi device [dev] - show or set current device\n"
+	"scsi part [dev] - print partition table of one or all SCSI devices\n"
+	"scsi read addr blk# cnt - read `cnt' blocks starting at block `blk#'\n"
+	"     to memory address `addr'\n"
+	"scsi write addr blk# cnt - write `cnt' blocks starting at block\n"
+	"     `blk#' from memory address `addr'"
+);
+
+U_BOOT_CMD(
+	scsiboot, 3, 1, do_scsiboot,
+	"boot from SCSI device",
+	"loadAddr dev:part"
+);
+#endif
+
 /****************************************************************************************
  * scsi_read
  */

@@ -710,24 +732,3 @@ void scsi_setup_inquiry(ccb * pccb)
 	pccb->cmdlen=6;
 	pccb->msgout[0]=SCSI_IDENTIFY; /* NOT USED */
 }
-
-
-U_BOOT_CMD(
-	scsi, 5, 1, do_scsi,
-	"SCSI sub-system",
-	"reset - reset SCSI controller\n"
-	"scsi info  - show available SCSI devices\n"
-	"scsi scan  - (re-)scan SCSI bus\n"
-	"scsi device [dev] - show or set current device\n"
-	"scsi part [dev] - print partition table of one or all SCSI devices\n"
-	"scsi read addr blk# cnt - read `cnt' blocks starting at block `blk#'\n"
-	"     to memory address `addr'\n"
-	"scsi write addr blk# cnt - write `cnt' blocks starting at block\n"
-	"     `blk#' from memory address `addr'"
-);
-
-U_BOOT_CMD(
-	scsiboot, 3, 1, do_scsiboot,
-	"boot from SCSI device",
-	"loadAddr dev:part"
-);

index 697d6e0..9a9c764 100644
@@ -195,6 +195,7 @@ void emif_update_timings(u32 base, const struct emif_regs *regs)
 	}
 }
 
+#ifndef CONFIG_OMAP44XX
 static void omap5_ddr3_leveling(u32 base, const struct emif_regs *regs)
 {
 	struct emif_reg_struct *emif = (struct emif_reg_struct *)base;

@@ -405,6 +406,7 @@ static void ddr3_init(u32 base, const struct emif_regs *regs)
 	else
 		dra7_ddr3_init(base, regs);
 }
+#endif
 
 #ifndef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
 #define print_timing_reg(reg) debug(#reg" - 0x%08x\n", (reg))

@@ -1178,7 +1180,7 @@ static void do_sdram_init(u32 base)
 #endif /* CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS */
 
 	/*
-	 * Initializing the LPDDR2 device can not happen from SDRAM.
+	 * Initializing the DDR device can not happen from SDRAM.
 	 * Changing the timing registers in EMIF can happen(going from one
 	 * OPP to another)
 	 */

@@ -1186,15 +1188,19 @@ static void do_sdram_init(u32 base)
 		if (emif_sdram_type(regs->sdram_config) ==
 		    EMIF_SDRAM_TYPE_LPDDR2)
 			lpddr2_init(base, regs);
+#ifndef CONFIG_OMAP44XX
 		else
 			ddr3_init(base, regs);
+#endif
 	}
+#ifdef CONFIG_OMAP54X
 	if (warm_reset() && (emif_sdram_type(regs->sdram_config) ==
 	    EMIF_SDRAM_TYPE_DDR3) && !is_dra7xx()) {
 		set_lpmode_selfrefresh(base);
 		emif_reset_phy(base);
 		omap5_ddr3_leveling(base, regs);
 	}
+#endif
 
 	/* Write to the shadow registers */
 	emif_update_timings(base, regs);