clk: mvebu: clock drivers for Marvell Armada 7K/8K
Subsystems (3)
v4 cover clk: mvebu: clock drivers for Marvell Armada 7K/8K
Hello,
Here is a new version of the clock drivers for the Marvell Armada 7K/8K. Changes since v3:
- Addition of a driver for the CP110 system controller, which provides clocks. The CP110 is the other big HW block contained in the Armada 7K/8K, next to the AP806.
- Everything rebase on v4.6-rc1.
- Addition of Rob Herring Acked-by on the AP806 DT bindings.
- Minor adjustements to the A806 DT binding documentation: the proposed clock names have been changed with a "ap-" suffix, so that we don't have any naming conflicts between the clocks provided by the AP806 and the clocks provided by the CP110. Since only the proposed clock names were changed, I kept Rob Herring Acked-by. Rob, let me know if there is any issue with this.
Thanks!
Thomas
Thomas Petazzoni (5):
clk: unconditionally recurse into clk/mvebu/
dt-bindings: arm: add DT binding for Marvell AP806 system controller
clk: mvebu: new driver for Armada AP806 system controller
dt-bindings: arm: add DT binding for Marvell CP110 system controller
clk: mvebu: new driver for Armada CP110 system controller
.../arm/marvell/ap806-system-controller.txt | 35 +++ .../arm/marvell/cp110-system-controller0.txt | 88 +++++++ drivers/clk/Makefile | 2 +- drivers/clk/mvebu/Kconfig | 6 + drivers/clk/mvebu/Makefile | 2 + drivers/clk/mvebu/ap806-system-controller.c | 106 +++++++++ drivers/clk/mvebu/cp110-system-controller.c | 265 +++++++++++++++++++++ 7 files changed, 503 insertions(+), 1 deletion(-) create mode 100644 Documentation/devicetree/bindings/arm/marvell/ap806-system-controller.txt create mode 100644 Documentation/devicetree/bindings/arm/marvell/cp110-system-controller0.txt create mode 100644 drivers/clk/mvebu/ap806-system-controller.c create mode 100644 drivers/clk/mvebu/cp110-system-controller.c
Signature · 1 line
2.6.4
PATCH v4 1/5 clk: unconditionally recurse into clk/mvebu/
The drivers/clk/mvebu directory is only being built when CONFIG_PLAT_ORION=y. As we are going to support additional mvebu platforms in drivers/clk/mvebu, which don't have CONFIG_PLAT_ORION=y, we need to recurse into this directory regardless of the value of CONFIG_PLAT_ORION.
Since all files in drivers/clk/mvebu/ are already conditionally compiled depending on various Kconfig options, we can recurse unconditionally into drivers/clk/mvebu without any other change.
--- drivers/clk/Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
drivers/clk/Makefile +1 -1
@@ -61,7 +61,7 @@ obj-$(CONFIG_ARCH_MEDIATEK) += mediatek/ ifeq ($(CONFIG_COMMON_CLK), y) obj-$(CONFIG_ARCH_MMP) += mmp/ endif -obj-$(CONFIG_PLAT_ORION) += mvebu/ +obj-y += mvebu/ obj-$(CONFIG_ARCH_MESON) += meson/ obj-$(CONFIG_ARCH_MXS) += mxs/ obj-$(CONFIG_MACH_PISTACHIO) += pistachio/
Signature · 1 line
2.6.4
Stephen Boyd
AppliedPATCH v4 1/5 clk: unconditionally recurse into clk/mvebu/
Quoted 6 lines · Thomas Petazzoni
The
drivers/clk/mvebudirectory is only being built whenCONFIG_PLAT_ORION=y. As we are going to support additional mvebu platforms indrivers/clk/mvebu, which don't haveCONFIG_PLAT_ORION=y, we need to recurse into this directory regardless of the value ofCONFIG_PLAT_ORION.
Quoted 6 lines
Since all files in
drivers/clk/mvebu/are already conditionally compiled depending on variousKconfigoptions, we can recurse unconditionally intodrivers/clk/mvebuwithout any other change.Signed-off-by Thomas Petazzoni <[email protected]>---
Applied to clk-next
Signature · 2 lines
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, a Linux Foundation Collaborative Project
PATCH v4 2/5 dt-bindings: arm: add DT binding for Marvell AP806 system controller
In reply to Thomas PetazzoniThis commit adds the Device Tree binding documentation for the system controller found in Marvell AP806 HW block, which is one of the core HW blocks of the 64-bits Marvell Armada 7K/8K family.
--- .../arm/marvell/ap806-system-controller.txt | 35 ++++++++++++++++++++++ 1 file changed, 35 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/marvell/ap806-system-controller.txt
Documentation/devicetree/bindings/arm/marvell/ap806-system-controller.txt new file +35 -0
@@ -0,0 +1,35 @@ +Marvell Armada AP806 System Controller +====================================== + +The AP806 is one of the two core HW blocks of the Marvell Armada 7K/8K +SoCs. It contains a system controller, which provides a number +registers giving access to numerous features: clocks, pin-muxing and +many other SoC configuration items. This DT binding allows to describe +this system controller. + +The Device Tree node representing the AP806 system controller provides +a number of clocks: + + - 0: clock of CPU cluster 0 + - 1: clock of CPU cluster 1 + - 2: fixed PLL at 1200 Mhz + - 3: MSS clock, derived from the fixed PLL + +Required properties: + + - compatible: must be: + "marvell,ap806-system-controller", "syscon" + - reg: register area of the AP806 system controller + - #clock-cells: must be set to 1 + - clock-output-names: must be defined to: + "ap-cpu-cluster-0", "ap-cpu-cluster-1", "ap-fixed", "ap-mss" + +Example: + + syscon: system-controller at 6f4000 { + compatible = "marvell,ap806-system-controller", "syscon"; + #clock-cells = <1>; + clock-output-names = "ap-cpu-cluster-0", "ap-cpu-cluster-1", + "ap-fixed", "ap-mss"; + reg = <0x6f4000 0x1000>; + };
Signature · 1 line
2.6.4
Stephen Boyd
AppliedPATCH v4 2/5 dt-bindings: arm: add DT binding for Marvell AP806 system controller
Quoted 7 lines · Thomas Petazzoni
This commit adds the Device Tree binding documentation for the system controller found in Marvell AP806 HW block, which is one of the core HW blocks of the 64-bits Marvell Armada 7K/8K family.
Signed-off-by Thomas Petazzoni <[email protected]>Acked-by Rob Herring <[email protected]>---
Applied to clk-next
Signature · 2 lines
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, a Linux Foundation Collaborative Project
PATCH v4 3/5 clk: mvebu: new driver for Armada AP806 system controller
In reply to Thomas PetazzoniThe Armada AP806 system controller, amongst other things, provides a number of clocks for the platform: the CPU cluster clocks, whose frequencies are found by reading the Sample At Reset register, one fixed clock, and another clock derived from the fixed clock, which is the one used by most peripherals in AP806.
The AP806 is one of the two core HW blocks used in the Marvell 7K/8K SoCs.
--- drivers/clk/mvebu/Kconfig | 3 + drivers/clk/mvebu/Makefile | 1 + drivers/clk/mvebu/ap806-system-controller.c | 106 ++++++++++++++++++++++++++++ 3 files changed, 110 insertions(+) create mode 100644 drivers/clk/mvebu/ap806-system-controller.c
drivers/clk/mvebu/Kconfig +3 -0
@@ -29,6 +29,9 @@ config ARMADA_XP_CLK select MVEBU_CLK_COMMON select MVEBU_CLK_CPU +config ARMADA_AP806_SYSCON + bool + config DOVE_CLK bool select MVEBU_CLK_COMMON
drivers/clk/mvebu/Makefile +1 -0
@@ -7,6 +7,7 @@ obj-$(CONFIG_ARMADA_375_CLK) += armada-375.o obj-$(CONFIG_ARMADA_38X_CLK) += armada-38x.o obj-$(CONFIG_ARMADA_39X_CLK) += armada-39x.o obj-$(CONFIG_ARMADA_XP_CLK) += armada-xp.o +obj-$(CONFIG_ARMADA_AP806_SYSCON) += ap806-system-controller.o obj-$(CONFIG_DOVE_CLK) += dove.o dove-divider.o obj-$(CONFIG_KIRKWOOD_CLK) += kirkwood.o obj-$(CONFIG_ORION_CLK) += orion.o
drivers/clk/mvebu/ap806-system-controller.c new file +106 -0
106 lines not on this page · raw message
Signature · 1 line
2.6.4
PATCH v4 3/5 clk: mvebu: new driver for Armada AP806 system controller
drivers/clk/mvebu/ap806-system-controller.c line 5
Quoted 11 lines · Thomas Petazzoni
drivers/clk/mvebu/ap806-system-controller.c new file +5
-0@@ -0,0 +1,106 @@ + +#define pr_fmt (fmt) "ap806-system-controller: " fmt + +#include <linux/kernel.h> +#include <linux/clk.h>
Is this used?
drivers/clk/mvebu/ap806-system-controller.c line 18
Quoted 2 lines
drivers/clk/mvebu/ap806-system-controller.c new file +2
-0+#include <linux/clk-provider.h> +#include <linux/io.h>
Is this used?
Quoted 8 lines
drivers/clk/mvebu/ap806-system-controller.c new file +8
-0+#include <linux/mfd/syscon.h> +#include <linux/of.h> +#include <linux/of_address.h> +#include <linux/regmap.h> + +#define AP806_SAR_REG 0x400 +#define AP806_SAR_CLKFREQ_MODE_MASK 0x1f +
drivers/clk/mvebu/ap806-system-controller.c line 36
Quoted 10 lines
drivers/clk/mvebu/ap806-system-controller.c new file +10
-0+#define AP806_CLK_NUM 4 + +static struct clk *ap806_clks[AP806_CLK_NUM ]; + +static struct clk_onecell_data ap806_clk_data = { + .clks = ap806_clks, + .clk_num =AP806_CLK_NUM , +}; + +static void __init ap806_syscon_clk_init (struct device_node *np)
Can this be a platform driver instead?
Signature · 2 lines
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, a Linux Foundation Collaborative Project
PATCH v4 3/5 clk: mvebu: new driver for Armada AP806 system controller
Hello,
Quoted 4 lines · Stephen Boyd
drivers/clk/mvebu/ap806-system-controller.c line 16
Quoted 2 lines
drivers/clk/mvebu/ap806-system-controller.c new file +2
-0+#include <linux/kernel.h> +#include <linux/clk.h> Is this used?
No, fixed!
Quoted 4 lines
drivers/clk/mvebu/ap806-system-controller.c line 18
Quoted 2 lines
drivers/clk/mvebu/ap806-system-controller.c new file +2
-0+#include <linux/clk-provider.h> +#include <linux/io.h> Is this used?
Ditto!
Quoted 3 lines
Quoted 1 line
+static void
__initap806_syscon_clk_init(struct device_node *np)Can this be a platform driver instead?
I've moved to a platform driver, and it seems to work fine. Will be in v5. Thanks for the review!
Thomas
Signature · 3 lines
Thomas Petazzoni, CTO, Free Electrons Embedded Linux, Kernel and Android engineering http://free-electrons.com
PATCH v4 4/5 dt-bindings: arm: add DT binding for Marvell CP110 system controller
In reply to Thomas PetazzoniThis commit adds the DT binding documentation for the Marvell CP110 system controller, which is part of the CP110 HW block, itself used in the Marvell Armada 7K and 8K SoCs.
--- .../arm/marvell/cp110-system-controller0.txt | 88 ++++++++++++++++++++++ 1 file changed, 88 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/marvell/cp110-system-controller0.txt
Documentation/devicetree/bindings/arm/marvell/cp110-system-controller0.txt new file +88 -0
@@ -0,0 +1,88 @@ +Marvell Armada CP110 System Controller 0 +======================================== + +The CP110 is one of the two core HW blocks of the Marvell Armada 7K/8K +SoCs. It contains two sets of system control registers, System +Controller 0 and System Controller 1. This Device Tree binding allows +to describe the first system controller, which provides registers to +configure various aspects of the SoC. + +The Device Tree node representing this System Controller 0 provides a +number of clocks: + + - a set of core clocks + - a set of gatable clocks + +Those clocks can be referenced by other Device Tree nodes using two +cells: + - The first cell must be 0 or 1. 0 for the core clocks and 1 for the + gatable clocks. + - The second cell identifies the particular core clock or gatable + clocks. + +The following clocks are available: + - Core clocks + - 0 0 APLL + - 0 1 PPv2 core + - 0 2 EIP + - 0 3 Core + - 0 4 NAND core + - Gatable clocks + - 1 0 Audio + - 1 1 Comm Unit + - 1 2 NAND + - 1 3 PPv2 + - 1 4 SDIO + - 1 5 MG Domain + - 1 6 MG Core + - 1 7 XOR1 + - 1 8 XOR0 + - 1 9 GOP DP + - 1 11 PCIe x1 0 + - 1 12 PCIe x1 1 + - 1 13 PCIe x4 + - 1 14 PCIe / XOR + - 1 15 SATA + - 1 16 SATA USB + - 1 18 GOP Macro + - 1 22 USB3H0 + - 1 23 USB3H1 + - 1 24 USB3 Device + - 1 25 EIP150 + - 1 26 EIP197 + +Required properties: + + - compatible: must be: + "marvell,cp110-system-controller0", "syscon"; + - reg: register area of the CP110 system controller 0 + - #clock-cells: must be set to 2 + - core-clock-output-names must be set to: + "cpm-apll", "cpm-ppv2-core", "cpm-eip", "cpm-core", "cpm-nand-core" + - gatable-clock-indices must be set to: + <0>, <1>, <2>, <3>, <4>, <5>, <6>, <7>, <8>, + <9>, <11>, <12>, <13>, <14>, <15>, <16>, <18>, + <22>, <23>, <24>, <25>, <26> + - gatable-clock-output-names must be set to: + "cpm-audio", "cpm-communit", "cpm-nand", "cpm-ppv2", "cpm-sdio", + "cpm-mg-domain", "cpm-mg-core", "cpm-xor1", "cpm-xor0", "cpm-gop-dp", "cpm-pcie_x10", + "cpm-pcie_x11", "cpm-pcie_x4", "cpm-pcie-xor", "cpm-sata", "cpm-sata-usb", + "cpm-gop-macro", "cpm-usb3h0", "cpm-usb3h1", "cpm-usb3dev", "cpm-eip150", + "cpm-eip197" + +Example: + + cpm_syscon0: system-controller at 440000 { + compatible = "marvell,cp110-system-controller0", "syscon"; + reg = <0x440000 0x1000>; + #clock-cells = <2>; + core-clock-output-names = "cpm-apll", "cpm-ppv2-core", "cpm-eip", "cpm-core", "cpm-nand-core"; + gate-clock-indices = <0>, <1>, <2>, <3>, <4>, <5>, <6>, <7>, <8>, + <9>, <11>, <12>, <13>, <14>, <15>, <16>, <18>, + <22>, <23>, <24>, <25>, <26>; + gate-clock-output-names = "cpm-audio", "cpm-communit", "cpm-nand", "cpm-ppv2", "cpm-sdio", + "cpm-mg-domain", "cpm-mg-core", "cpm-xor1", "cpm-xor0", "cpm-gop-dp", "cpm-pcie_x10", + "cpm-pcie_x11", "cpm-pcie_x4", "cpm-pcie-xor", "cpm-sata", "cpm-sata-usb", + "cpm-gop-macro", "cpm-usb3h0", "cpm-usb3h1", "cpm-usb3dev", "cpm-eip150", + "cpm-eip197"; + };
Signature · 1 line
2.6.4
Rob Herring
maintainerPATCH v4 4/5 dt-bindings: arm: add DT binding for Marvell CP110 system controller
Quoted 63 lines · Thomas Petazzoni
This commit adds the DT binding documentation for the Marvell CP110 system controller, which is part of the CP110 HW block, itself used in the Marvell Armada 7K and 8K SoCs.
Signed-off-by Thomas Petazzoni <[email protected]>--- .../arm/marvell/cp110-system-controller0.txt | 88 ++++++++++++++++++++++ 1 file changed, 88 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/marvell/cp110-system-controller0.txtDocumentation/devicetree/bindings/arm/marvell/cp110-system-controller0.txt new file +47
-0@@ -0,0 +1,88 @@ +Marvell Armada CP110 System Controller 0 +======================================== + +The CP110 is one of the two core HW blocks of the Marvell Armada 7K/8K +SoCs. It contains two sets of system control registers, System +Controller 0 and System Controller 1. This Device Tree binding allows +to describe the first system controller, which provides registers to +configure various aspects of the SoC. + +The Device Tree node representing this System Controller 0 provides a +number of clocks: + + - a set of core clocks + - a set of gatable clocks + +Those clocks can be referenced by other Device Tree nodes using two +cells: + - The first cell must be 0 or 1. 0 for the core clocks and 1 for the + gatable clocks. + - The second cell identifies the particular core clock or gatable + clocks. + +The following clocks are available: + - Core clocks + - 0 0 APLL + - 0 1 PPv2 core + - 0 2 EIP + - 0 3 Core + - 0 4 NAND core + - Gatable clocks + - 1 0 Audio + - 1 1 Comm Unit + - 1 2 NAND + - 1 3 PPv2 + - 1 4 SDIO + - 1 5 MG Domain + - 1 6 MG Core + - 1 7 XOR1 + - 1 8 XOR0 + - 1 9 GOP DP + - 1 11 PCIe x1 0 + - 1 12 PCIe x1 1 + - 1 13 PCIe x4 + - 1 14 PCIe / XOR + - 1 15 SATA + - 1 16 SATA USB + - 1 18 GOP Macro
Documentation/devicetree/bindings/arm/marvell/cp110-system-controller0.txt line 57
Quoted 10 lines
Documentation/devicetree/bindings/arm/marvell/cp110-system-controller0.txt new file +10
-0+ - 1 22 USB3H0 + - 1 23 USB3H1 + - 1 24 USB3 Device + - 1 25 EIP150 + - 1 26 EIP197 + +Required properties: + + - compatible: must be: + "marvell,cp110-system-controller0", "syscon";
This block is really the same across SoCs?
Documentation/devicetree/bindings/arm/marvell/cp110-system-controller0.txt line 65
Quoted 8 lines
Documentation/devicetree/bindings/arm/marvell/cp110-system-controller0.txt new file +8
-0+ - reg: register area of the CP110 system controller 0 + - #clock-cells: must be set to 2 + - core-clock-output-names must be set to: + "cpm-apll", "cpm-ppv2-core", "cpm-eip", "cpm-core", "cpm-nand-core" + - gatable-clock-indices must be set to: + <0>, <1>, <2>, <3>, <4>, <5>, <6>, <7>, <8>, + <9>, <11>, <12>, <13>, <14>, <15>, <16>, <18>, + <22>, <23>, <24>, <25>, <26>
You aren't skipping very many spots. I'd just fill the unused names in with "none" or something.
Quoted 26 lines
Documentation/devicetree/bindings/arm/marvell/cp110-system-controller0.txt new file +23
-0+ - gatable-clock-output-names must be set to: + "cpm-audio", "cpm-communit", "cpm-nand", "cpm-ppv2", "cpm-sdio", + "cpm-mg-domain", "cpm-mg-core", "cpm-xor1", "cpm-xor0", "cpm-gop-dp", "cpm-pcie_x10", + "cpm-pcie_x11", "cpm-pcie_x4", "cpm-pcie-xor", "cpm-sata", "cpm-sata-usb", + "cpm-gop-macro", "cpm-usb3h0", "cpm-usb3h1", "cpm-usb3dev", "cpm-eip150", + "cpm-eip197" + +Example: + + cpm_syscon0: system-controller at 440000 { + compatible = "marvell,cp110-system-controller0", "syscon"; + reg = <0x440000 0x1000>; + #clock-cells = <2>; + core-clock-output-names = "cpm-apll", "cpm-ppv2-core", "cpm-eip", "cpm-core", "cpm-nand-core"; + gate-clock-indices = <0>, <1>, <2>, <3>, <4>, <5>, <6>, <7>, <8>, + <9>, <11>, <12>, <13>, <14>, <15>, <16>, <18>, + <22>, <23>, <24>, <25>, <26>; + gate-clock-output-names = "cpm-audio", "cpm-communit", "cpm-nand", "cpm-ppv2", "cpm-sdio", + "cpm-mg-domain", "cpm-mg-core", "cpm-xor1", "cpm-xor0", "cpm-gop-dp", "cpm-pcie_x10", + "cpm-pcie_x11", "cpm-pcie_x4", "cpm-pcie-xor", "cpm-sata", "cpm-sata-usb", + "cpm-gop-macro", "cpm-usb3h0", "cpm-usb3h1", "cpm-usb3dev", "cpm-eip150", + "cpm-eip197"; + };Signature · 1 line
2.6.4
PATCH v4 4/5 dt-bindings: arm: add DT binding for Marvell CP110 system controller
Hello,
Quoted 6 lines · Rob Herring
Documentation/devicetree/bindings/arm/marvell/cp110-system-controller0.txt line 57
Quoted 4 lines
Documentation/devicetree/bindings/arm/marvell/cp110-system-controller0.txt new file +4
-0+Required properties: + + - compatible: must be: + "marvell,cp110-system-controller0", "syscon";This block is really the same across SoCs?
As per my knowledge, it is the same across 7020, 7040, 8020 and 8040, where the CP part is named CP110. My understanding is that in future SoCs, when the CP part will change, the CP part will have a different name, i.e CP115 or 120 or something (these are invented names, I have no idea how Marvell will name the future CPs).
So I believe cp110-system-controller0 properly uniquely identifies this IP block.
Quoted 11 lines
Documentation/devicetree/bindings/arm/marvell/cp110-system-controller0.txt line 65
Quoted 8 lines
+ - reg: register area of the CP110 system controller 0
+ - #clock-cells: must be set to 2
+ - core-clock-output-names must be set to:Documentation/devicetree/bindings/arm/marvell/cp110-system-controller0.txt new file +5
-0+ "cpm-apll", "cpm-ppv2-core", "cpm-eip", "cpm-core", "cpm-nand-core" + - gatable-clock-indices must be set to: + <0>, <1>, <2>, <3>, <4>, <5>, <6>, <7>, <8>, + <9>, <11>, <12>, <13>, <14>, <15>, <16>, <18>, + <22>, <23>, <24>, <25>, <26>You aren't skipping very many spots. I'd just fill the unused names in with "none" or something.
and then remove the gatable-clock-indices property altogether?
Thanks for the review!
Thomas
Signature · 3 lines
Thomas Petazzoni, CTO, Free Electrons Embedded Linux, Kernel and Android engineering http://free-electrons.com
PATCH v4 4/5 dt-bindings: arm: add DT binding for Marvell CP110 system controller
In reply to Rob HerringHello,
Quoted 12 lines · Rob Herring
Documentation/devicetree/bindings/arm/marvell/cp110-system-controller0.txt line 65
Quoted 8 lines
+ - reg: register area of the CP110 system controller 0
+ - #clock-cells: must be set to 2
+ - core-clock-output-names must be set to:Documentation/devicetree/bindings/arm/marvell/cp110-system-controller0.txt new file +5
-0+ "cpm-apll", "cpm-ppv2-core", "cpm-eip", "cpm-core", "cpm-nand-core" + - gatable-clock-indices must be set to: + <0>, <1>, <2>, <3>, <4>, <5>, <6>, <7>, <8>, + <9>, <11>, <12>, <13>, <14>, <15>, <16>, <18>, + <22>, <23>, <24>, <25>, <26>You aren't skipping very many spots. I'd just fill the unused names in with "none" or something.
Quoted 6 lines
Documentation/devicetree/bindings/arm/marvell/cp110-system-controller0.txt line 71
Quoted 6 lines
+ - gatable-clock-output-names must be set to:
Documentation/devicetree/bindings/arm/marvell/cp110-system-controller0.txt new file +5
-0+ "cpm-audio", "cpm-communit", "cpm-nand", "cpm-ppv2", "cpm-sdio", + "cpm-mg-domain", "cpm-mg-core", "cpm-xor1", "cpm-xor0", "cpm-gop-dp", "cpm-pcie_x10", + "cpm-pcie_x11", "cpm-pcie_x4", "cpm-pcie-xor", "cpm-sata", "cpm-sata-usb", + "cpm-gop-macro", "cpm-usb3h0", "cpm-usb3h1", "cpm-usb3dev", "cpm-eip150", + "cpm-eip197"
In fact, the more I think of it, the less I find encoding the clock output names in the DT to be useful for such a driver. For generic clock drivers, it makes complete sense, but here the driver is really tied to the specific system controller of that SoC, so the clock names will not change.
In addition, those gatable clocks are not independent from each other:
many of them are parent from others (this wasn't encoded into the driver until now, because I didn't had this info until now). So the driver will anyway have to have a lot of knowledge about which clock is child/parent of which one. Which means the driver is anyway really tied to that specific system controller.
Does it still make sense to encode the clock names in the DT in such a case, or should the driver be providing the clock names?
(I don't have a strong opinion either way, I'm just asking what is the preference of the DT and clock maintainers on the matter.).
Thanks!
Thomas
Signature · 3 lines
Thomas Petazzoni, CTO, Free Electrons Embedded Linux, Kernel and Android engineering http://free-electrons.com
PATCH v4 4/5 dt-bindings: arm: add DT binding for Marvell CP110 system controller
Hello,
Quoted 5 lines · Thomas Petazzoni
In fact, the more I think of it, the less I find encoding the clock output names in the DT to be useful for such a driver. For generic clock drivers, it makes complete sense, but here the driver is really tied to the specific system controller of that SoC, so the clock names will not change.
My bad: there will be two instances of the CP110 system controller, one for the master CP110 and one for the slave CP110. So having the possibility of setting the clock names in the DT is actually a good thing, so I'll keep it.
Thanks!
Thomas
Signature · 3 lines
Thomas Petazzoni, CTO, Free Electrons Embedded Linux, Kernel and Android engineering http://free-electrons.com
PATCH v4 4/5 dt-bindings: arm: add DT binding for Marvell CP110 system controller
In reply to Thomas PetazzoniBonsoir Thomas,
Quoted 34 lines · Thomas Petazzoni
Quoted 9 lines · Rob Herring
Documentation/devicetree/bindings/arm/marvell/cp110-system-controller0.txt line 65
Quoted 8 lines
+ - reg: register area of the CP110 system controller 0
+ - #clock-cells: must be set to 2
+ - core-clock-output-names must be set to:Documentation/devicetree/bindings/arm/marvell/cp110-system-controller0.txt new file +5
-0+ "cpm-apll", "cpm-ppv2-core", "cpm-eip", "cpm-core", "cpm-nand-core" + - gatable-clock-indices must be set to: + <0>, <1>, <2>, <3>, <4>, <5>, <6>, <7>, <8>, + <9>, <11>, <12>, <13>, <14>, <15>, <16>, <18>, + <22>, <23>, <24>, <25>, <26>Quoted 9 lines
You aren't skipping very many spots. I'd just fill the unused names in with "none" or something.
Quoted 6 lines
+ - gatable-clock-output-names must be set to:
Documentation/devicetree/bindings/arm/marvell/cp110-system-controller0.txt new file +5
-0+ "cpm-audio", "cpm-communit", "cpm-nand", "cpm-ppv2", "cpm-sdio", + "cpm-mg-domain", "cpm-mg-core", "cpm-xor1", "cpm-xor0", "cpm-gop-dp", "cpm-pcie_x10", + "cpm-pcie_x11", "cpm-pcie_x4", "cpm-pcie-xor", "cpm-sata", "cpm-sata-usb", + "cpm-gop-macro", "cpm-usb3h0", "cpm-usb3h1", "cpm-usb3dev", "cpm-eip150", + "cpm-eip197"In fact, the more I think of it, the less I find encoding the clock output names in the DT to be useful for such a driver. For generic clock drivers, it makes complete sense, but here the driver is really tied to the specific system controller of that SoC, so the clock names will not change.
In addition, those gatable clocks are not independent from each other:
many of them are parent from others (this wasn't encoded into the driver until now, because I didn't had this info until now). So the driver will anyway have to have a lot of knowledge about which clock is child/parent of which one. Which means the driver is anyway really tied to that specific system controller.
Quoted 7 lines
Does it still make sense to encode the clock names in the DT in such a case, or should the driver be providing the clock names?
(I don't have a strong opinion either way, I'm just asking what is the preference of the DT and clock maintainers on the matter.).
From my experience with clock drivers for Renesas SoCs, life is much easier
when handling all of this (clock names, parents, ...) in C. The same is true BTW for PM Domains.
The clock controllers of r8a7791 and r8a7795 are very similar, and could be handled similarly.
Compare the DT hierarchy for CPG and MSTP/MSSR in arch/arm/boot/dts/r8a7791.dtsi and arch/arm64/boot/dts/renesas/r8a7795.dtsi.
Binding definitions are
include/dt-bindings/clock/r8a7791-clock.h
vs
include/dt-bindings/clock/r8a7795-cpg-mssr.hCorresponding drivers are
drivers/clk/renesas/clk-rcar-gen2.c
drivers/clk/renesas/clk-mstp.c
vs.
drivers/clk/renesas/r8a7795-cpg-mssr.c
drivers/clk/renesas/renesas-cpg-mssr.c
drivers/clk/renesas/renesas-cpg-mssr.hGr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert at linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
PATCH v4 4/5 dt-bindings: arm: add DT binding for Marvell CP110 system controller
Hello,
Quoted 8 lines · Geert Uytterhoeven
From my experience with clock drivers for Renesas SoCs, life is much easier when handling all of this (clock names, parents, ...) in C. The same is true BTW for PM Domains.
The clock controllers of r8a7791 and r8a7795 are very similar, and could be handled similarly.
Compare the DT hierarchy for CPG and MSTP/MSSR inarch/arm/boot/dts/r8a7791.dtsiandarch/arm64/boot/dts/renesas/r8a7795.dtsi.
Thanks for your feedback. However in practice, there will ultimately be two instances of this clock controller, as some variants of the SoC will contain two CP parts. Due to this, it is going to be quite convenient to have the clock names configurable from the DT, as I will be able to give the same clock on the master CP and the slave CP a different name.
That's actually why my binding documentation uses names like "cpm-<foo>" for all the clocks, where "cpm" stands for "CP Master". In the future, another instance will have clocks named "cps-<foo>" for "CP Slave".
Best regards,
Thomas
Signature · 3 lines
Thomas Petazzoni, CTO, Free Electrons Embedded Linux, Kernel and Android engineering http://free-electrons.com
PATCH v4 4/5 dt-bindings: arm: add DT binding for Marvell CP110 system controller
Hi Thomas,
Quoted 10 lines · Thomas Petazzoni
Quoted 8 lines · Geert Uytterhoeven
From my experience with clock drivers for Renesas SoCs, life is much easier when handling all of this (clock names, parents, ...) in C. The same is true BTW for PM Domains.
The clock controllers of r8a7791 and r8a7795 are very similar, and could be handled similarly.
Compare the DT hierarchy for CPG and MSTP/MSSR inarch/arm/boot/dts/r8a7791.dtsiandarch/arm64/boot/dts/renesas/r8a7795.dtsi.
Quoted 6 lines
Thanks for your feedback. However in practice, there will ultimately be two instances of this clock controller, as some variants of the SoC will contain two CP parts. Due to this, it is going to be quite convenient to have the clock names configurable from the DT, as I will be able to give the same clock on the master CP and the slave CP a different name.
You could still prefix the names by e.g. an instance number.
Quoted 4 lines
That's actually why my binding documentation uses names like "cpm-<foo>" for all the clocks, where "cpm" stands for "CP Master". In the future, another instance will have clocks named "cps-<foo>" for "CP Slave".
So the names are actually part of the binding, while nothing really relies on the actual names, right? Clocks are referred to by clock specifier (phandle
+ some optonal bits).
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert at linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
PATCH v4 5/5 clk: mvebu: new driver for Armada CP110 system controller
In reply to Thomas PetazzoniThe Armada CP110 system controller provides, amongst other things, a number of clocks for the platform: a small number of core clocks, and then a number of gatable clocks, derived from some of the core clocks. Those clocks are configured via registers of the CP110 System Controller.
The CP110 is the other core HW block (next to the AP806) used in the Marvel Armada 7K and 8K SoCs.
--- drivers/clk/mvebu/Kconfig | 3 + drivers/clk/mvebu/Makefile | 1 + drivers/clk/mvebu/cp110-system-controller.c | 265 ++++++++++++++++++++++++++++ 3 files changed, 269 insertions(+) create mode 100644 drivers/clk/mvebu/cp110-system-controller.c
drivers/clk/mvebu/Kconfig +3 -0
@@ -32,6 +32,9 @@ config ARMADA_XP_CLK config ARMADA_AP806_SYSCON bool +config ARMADA_CP110_SYSCON + bool + config DOVE_CLK bool select MVEBU_CLK_COMMON
drivers/clk/mvebu/Makefile +1 -0
@@ -8,6 +8,7 @@ obj-$(CONFIG_ARMADA_38X_CLK) += armada-38x.o obj-$(CONFIG_ARMADA_39X_CLK) += armada-39x.o obj-$(CONFIG_ARMADA_XP_CLK) += armada-xp.o obj-$(CONFIG_ARMADA_AP806_SYSCON) += ap806-system-controller.o +obj-$(CONFIG_ARMADA_CP110_SYSCON) += cp110-system-controller.o obj-$(CONFIG_DOVE_CLK) += dove.o dove-divider.o obj-$(CONFIG_KIRKWOOD_CLK) += kirkwood.o obj-$(CONFIG_ORION_CLK) += orion.o
drivers/clk/mvebu/cp110-system-controller.c new file +265 -0
265 lines not on this page · raw message
Signature · 1 line
2.6.4
PATCH v4 5/5 clk: mvebu: new driver for Armada CP110 system controller
drivers/clk/mvebu/cp110-system-controller.c line 3
Quoted 9 lines · Thomas Petazzoni
drivers/clk/mvebu/cp110-system-controller.c new file +3
-0@@ -0,0 +1,265 @@ +/* +#include <linux/kernel.h> +#include <linux/clk.h>
What's this for?
drivers/clk/mvebu/cp110-system-controller.c line 38
Quoted 2 lines
drivers/clk/mvebu/cp110-system-controller.c new file +2
-0+#include <linux/clk-provider.h> +#include <linux/io.h>
What's this for?
Quoted 6 lines
drivers/clk/mvebu/cp110-system-controller.c new file +6
-0+#include <linux/mfd/syscon.h> +#include <linux/of.h> +#include <linux/of_address.h> +#include <linux/regmap.h> +#include <linux/slab.h> +
[..]
drivers/clk/mvebu/cp110-system-controller.c line 82
Quoted 4 lines
drivers/clk/mvebu/cp110-system-controller.c new file +4
-0+static int cp110_gate_enable (struct clk_hw *hw) +{ +struct cp110_gate_clk *gate = + container_of(hw, struct cp110_gate_clk, hw);
Consider a macro to make this fit on one line.
Quoted 4 lines
drivers/clk/mvebu/cp110-system-controller.c new file +4
-0+ +regmap_update_bits (gate->regmap,CP110_PM_CLOCK_GATING_REG , +BIT (gate->bit_idx),BIT (gate->bit_idx)); +
[..]
Quoted 4 lines
drivers/clk/mvebu/cp110-system-controller.c new file +4
-0+static struct clk *cp110_register_gate (const char *name,const char *parent_name, +struct regmap *regmap,u8 bit_idx) +{ +struct cp110_gate_clk *gate;
drivers/clk/mvebu/cp110-system-controller.c line 128
Quoted 10 lines
drivers/clk/mvebu/cp110-system-controller.c new file +10
-0+struct clk *clk; +struct clk_init_data init; + + gate =kzalloc (sizeof (*gate),GFP_KERNEL ); +if (!gate) +return ERR_PTR (-ENOMEM ); + + init.name = name; + init.ops = &cp110_gate_ops; + init.flags =CLK_IS_BASIC ;
No basic please.
Quoted 24 lines
drivers/clk/mvebu/cp110-system-controller.c new file +24
-0+ init.parent_names = &parent_name; + init.num_parents =1 ; + + gate->regmap = regmap; + gate->bit_idx = bit_idx; + gate->hw.init = &init; + + clk =clk_register (NULL , &gate->hw); +if (IS_ERR (clk)) +kfree (gate); + +return clk; +} + +static struct clk *cp110_of_clk_get (struct of_phandle_args *clkspec,void *data) +{ +struct clk_onecell_data *clk_data = data; +unsigned int type = clkspec->args[0 ]; +unsigned int idx = clkspec->args[1 ]; + +if (type ==CP110_CLK_TYPE_CORE ) { +if (idx >CP110_MAX_CORE_CLOCKS ) +return ERR_PTR (-EINVAL ); +return clk_data->clks[idx];
drivers/clk/mvebu/cp110-system-controller.c line 162
Quoted 10 lines
drivers/clk/mvebu/cp110-system-controller.c new file +10
-0+ }else if (type ==CP110_CLK_TYPE_GATABLE ) { +if (idx >CP110_MAX_GATABLE_CLOCKS ) +return ERR_PTR (-EINVAL ); +return clk_data->clks[CP110_MAX_CORE_CLOCKS + idx]; + } + +return ERR_PTR (-EINVAL ); +} + +static void __init cp110_syscon_clk_init (struct device_node *np)
Any reason this can't be a platform driver?
drivers/clk/mvebu/cp110-system-controller.c line 169
Quoted 7 lines
drivers/clk/mvebu/cp110-system-controller.c new file +7
-0+{ +struct regmap *regmap; +const char *name, *apll_name, *core_name, *eip_name, *nand_name; +u32 nand_clk_ctrl; +int clkidx =0 , i; + + regmap =syscon_node_to_regmap (np);
Isn't this the only driver for the node? Why not just make the regmap ourselves in the driver here?
drivers/clk/mvebu/cp110-system-controller.c line 182
Quoted 13 lines
drivers/clk/mvebu/cp110-system-controller.c new file +13
-0+if (IS_ERR (regmap)) { +pr_err ("cannot get regmap\n" ); +return ; + } + +if (regmap_read (regmap,CP110_NAND_FLASH_CLK_CTRL_REG , &nand_clk_ctrl)) { +pr_err ("cannot read from regmap\n" ); +return ; + } + +/* +* Register core clocks +*/
Ok. Not really useful comment.
Quoted 25 lines
drivers/clk/mvebu/cp110-system-controller.c new file +25
-0+ +/* Register the APLL which is the root of the clk tree */ +of_property_read_string_index (np,"core-clock-output-names" , +0 , &apll_name); + cp110_clks[0 ] = +clk_register_fixed_rate (NULL , apll_name,NULL ,0 , +1000 *1000 *1000 ); + +/* PPv2 is APLL/3 */ +of_property_read_string_index (np,"core-clock-output-names" , +1 , &name); + cp110_clks[1 ] = +clk_register_fixed_factor (NULL , name, apll_name, +0 ,1 ,3 ); + clkidx++; + +/* EIP clock is APLL/2 */ +of_property_read_string_index (np,"core-clock-output-names" , +2 , &eip_name); + cp110_clks[2 ] = +clk_register_fixed_factor (NULL , eip_name, apll_name,0 ,1 ,2 ); + clkidx++; + +/* Core clock is EIP/2 */ + of_property_read_string_index(np, "core-clock-output-names",
drivers/clk/mvebu/cp110-system-controller.c line 217
Quoted 10 lines
drivers/clk/mvebu/cp110-system-controller.c new file +10
-0+ 3, &core_name); + cp110_clks[3 ] = +clk_register_fixed_factor (NULL , core_name, eip_name,0 ,1 ,2 ); + clkidx++; + +/* NAND can be either APLL/2.5 or core clock */ +of_property_read_string_index (np,"core-clock-output-names" , +4 , &nand_name); +if (nand_clk_ctrl &NF_CLOCK_SEL_400_MASK ) + cp110_clks[4] =
Weird indentation here. Please use tabs throughout.
Quoted 34 lines
drivers/clk/mvebu/cp110-system-controller.c new file +34
-0+clk_register_fixed_factor (NULL , nand_name, + apll_name,0 ,2 ,5 ); + else + cp110_clks[4 ] = +clk_register_fixed_factor (NULL , nand_name, + core_name,0 ,1 ,1 ); + +/* +* Register gatable clocks +*/ +for (i =0 ; i <CP110_MAX_GATABLE_CLOCKS ; i++) { +const char *parent; +int clkidx, ret; + + ret =of_property_read_string_index (np,"gate-clock-output-names" , + i, &name); +/* Reached the end of the list? */ +if (ret <0 ) +break ; + +of_property_read_u32_index (np,"gate-clock-indices" , i, &clkidx); + +switch (clkidx) { +case CP110_GATE_NAND : + parent = nand_name; +break ; +case CP110_GATE_PPV2 : + parent ="ppv2-core" ; +break ; +case CP110_GATE_EIP150 : +case CP110_GATE_EIP197 : + parent ="eip" ; +break ; +default :
drivers/clk/mvebu/cp110-system-controller.c line 261
Quoted 10 lines
drivers/clk/mvebu/cp110-system-controller.c new file +10
-0+ parent ="core" ; +break ; + } + + cp110_clks[CP110_MAX_CORE_CLOCKS + clkidx] = +cp110_register_gate (name, parent, + regmap, clkidx); + } + +of_clk_add_provider (np, cp110_of_clk_get, &cp110_clk_data);
What if this fails?
Signature · 2 lines
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, a Linux Foundation Collaborative Project
PATCH v4 5/5 clk: mvebu: new driver for Armada CP110 system controller
Hello,
Quoted 9 lines · Stephen Boyd
drivers/clk/mvebu/cp110-system-controller.c line 36
Quoted 2 lines
drivers/clk/mvebu/cp110-system-controller.c new file +2
-0+#include <linux/kernel.h> +#include <linux/clk.h> What's this for?
drivers/clk/mvebu/cp110-system-controller.c line 38
Quoted 2 lines
drivers/clk/mvebu/cp110-system-controller.c new file +2
-0+#include <linux/clk-provider.h> +#include <linux/io.h> What's this for?
Both removed.
Quoted 6 lines
drivers/clk/mvebu/cp110-system-controller.c line 82
Quoted 4 lines
drivers/clk/mvebu/cp110-system-controller.c new file +4
-0+static int cp110_gate_enable (struct clk_hw *hw) +{ +struct cp110_gate_clk *gate = + container_of(hw, struct cp110_gate_clk, hw);Consider a macro to make this fit on one line.
Done!
Quoted 5 lines
drivers/clk/mvebu/cp110-system-controller.c line 128
Quoted 3 lines
drivers/clk/mvebu/cp110-system-controller.c new file +3
-0+ init.name = name; + init.ops = &cp110_gate_ops; + init.flags =CLK_IS_BASIC ;No basic please.
Fixed!
Quoted 3 lines
Quoted 1 line
+static void
__initcp110_syscon_clk_init(struct device_node *np)Any reason this can't be a platform driver?
Changed to be a platform driver.
Quoted 10 lines
drivers/clk/mvebu/cp110-system-controller.c line 169
Quoted 7 lines
drivers/clk/mvebu/cp110-system-controller.c new file +7
-0+{ +struct regmap *regmap; +const char *name, *apll_name, *core_name, *eip_name, *nand_name; +u32 nand_clk_ctrl; +int clkidx =0 , i; + + regmap =syscon_node_to_regmap (np);Isn't this the only driver for the node? Why not just make the regmap ourselves in the driver here?
It is for now. However, I expect that we will probably have sub-nodes for various other devices whose registers belong to this system controller. More specifically, there are some pin-muxing registers in there. Using the syscon facility entirely automates the creation of the regmap, and makes it easily accessible to other devices who might want to poke into some of the system controller registers.
Quoted 5 lines
drivers/clk/mvebu/cp110-system-controller.c line 182
Quoted 3 lines
drivers/clk/mvebu/cp110-system-controller.c new file +3
-0+/* +* Register core clocks +*/ Ok. Not really useful comment.
Removed!
Quoted 7 lines
drivers/clk/mvebu/cp110-system-controller.c line 217
Quoted 5 lines
drivers/clk/mvebu/cp110-system-controller.c new file +5
-0+/* NAND can be either APLL/2.5 or core clock */ +of_property_read_string_index (np,"core-clock-output-names" , +4 , &nand_name); +if (nand_clk_ctrl &NF_CLOCK_SEL_400_MASK ) + cp110_clks[4] =Weird indentation here. Please use tabs throughout.
Yeah, seems like I copy/pasted or something. Fixed to use tabs.
Quoted 3 lines
drivers/clk/mvebu/cp110-system-controller.c line 261
Quoted 1 line
drivers/clk/mvebu/cp110-system-controller.c new file +1
-0+of_clk_add_provider (np, cp110_of_clk_get, &cp110_clk_data);What if this fails?
Error checking added everywhere. There are numerous other clk drivers that don't do error checking, so I did the same, especially since a failure to register a clock is most likely going to be fatal to the system booting. No clock -> no UART, no UART -> the system doesn't boot up to userspace.
But fair enough, I've added error checking in the ->probe() function (of both the AP806 and CP110 clk drivers).
Thanks again for the review!
Thomas
Signature · 3 lines
Thomas Petazzoni, CTO, Free Electrons Embedded Linux, Kernel and Android engineering http://free-electrons.com