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Add PCIe driver support for imx6sx

PATCH Applied Christoph Fritz 5 participants 18 messages Feb 25, 2016 – Apr 5, 2016

Subsystems (5)
Device tree bindings Arm i.MX and Layerscape PCI Multifunction devices (MFD) +1 more subsystems
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Christoph Fritz

author
#0 lore raw

v3 cover Add PCIe driver support for imx6sx

v3:
* adapt devicetree bindings documentation fsl,imx6q-pcie.txt
v2:
* leave out regulator handling from driver, will be done later in PM subsystem
* use BIT() macro for MFD

Christoph Fritz (2):
MFD: imx6sx: Add PCIe register definitions for iomuxc gpr
PCI: imx6: add initial imx6sx support

 .../devicetree/bindings/pci/fsl,imx6q-pcie.txt     |   6 +-
 drivers/pci/host/pci-imx6.c                        | 130 ++++++++++++++-------
 include/linux/mfd/syscon/imx6q-iomuxc-gpr.h        |   5 +
 3 files changed, 101 insertions(+), 40 deletions(-)
Signature · 1 line
2.1.4
author
#1 lore raw

PATCH v3 1/2 MFD: imx6sx: Add PCIe register definitions for iomuxc gpr

This patch adds macros to define masks and bits for imx6sx PCIe registers. This is based on a patch by Richard Zhu.

Signed-off-by Christoph Fritz <[email protected]>
---
 include/linux/mfd/syscon/imx6q-iomuxc-gpr.h | 5 +++++
 1 file changed, 5 insertions(+)
include/linux/mfd/syscon/imx6q-iomuxc-gpr.h +5 -0
index 558a485..238c8db 100644
@@ -422,6 +422,7 @@
 #define IMX6SX_GPR5_VADC_TO_CSI_CAPTURE_EN_MASK		(0x1 << 26)
 #define IMX6SX_GPR5_VADC_TO_CSI_CAPTURE_EN_ENABLE	(0x1 << 26)
 #define IMX6SX_GPR5_VADC_TO_CSI_CAPTURE_EN_DISABLE	(0x0 << 26)
+#define IMX6SX_GPR5_PCIE_BTNRST_RESET			BIT(19)
 #define IMX6SX_GPR5_CSI1_MUX_CTRL_MASK			(0x3 << 4)
 #define IMX6SX_GPR5_CSI1_MUX_CTRL_EXT_PIN		(0x0 << 4)
 #define IMX6SX_GPR5_CSI1_MUX_CTRL_CVD			(0x1 << 4)

@@ -435,6 +436,10 @@
 #define IMX6SX_GPR5_DISP_MUX_DCIC1_LVDS			(0x1 << 1)
 #define IMX6SX_GPR5_DISP_MUX_DCIC1_MASK			(0x1 << 1)
 
+#define IMX6SX_GPR12_PCIE_TEST_POWERDOWN		BIT(30)
+#define IMX6SX_GPR12_PCIE_RX_EQ_MASK			(0x7 << 0)
+#define IMX6SX_GPR12_PCIE_RX_EQ_2			(0x2 << 0)
+
 /* For imx6ul iomux gpr register field define */
 #define IMX6UL_GPR1_ENET1_CLK_DIR		(0x1 << 17)
 #define IMX6UL_GPR1_ENET2_CLK_DIR		(0x1 << 18)
Signature · 1 line
2.1.4
#2 lore raw

PATCH v3 1/2 MFD: imx6sx: Add PCIe register definitions for iomuxc gpr

Quoted 7 lines · Christoph Fritz

This patch adds macros to define masks and bits for imx6sx PCIe registers. This is based on a patch by Richard Zhu.

Signed-off-by Christoph Fritz <[email protected]>
---
 include/linux/mfd/syscon/imx6q-iomuxc-gpr.h | 5 +++++
 1 file changed, 5 insertions(+)

I will change the non-conformant $SUBJECT line for you this time, but please be more vigilant in the future.

Patch applied.

Quoted 23 lines
include/linux/mfd/syscon/imx6q-iomuxc-gpr.h +5 -0
index 558a485..238c8db 100644
@@ -422,6 +422,7 @@
 #define IMX6SX_GPR5_VADC_TO_CSI_CAPTURE_EN_MASK		(0x1 << 26)
 #define IMX6SX_GPR5_VADC_TO_CSI_CAPTURE_EN_ENABLE	(0x1 << 26)
 #define IMX6SX_GPR5_VADC_TO_CSI_CAPTURE_EN_DISABLE	(0x0 << 26)
+#define IMX6SX_GPR5_PCIE_BTNRST_RESET			BIT(19)
 #define IMX6SX_GPR5_CSI1_MUX_CTRL_MASK			(0x3 << 4)
 #define IMX6SX_GPR5_CSI1_MUX_CTRL_EXT_PIN		(0x0 << 4)
 #define IMX6SX_GPR5_CSI1_MUX_CTRL_CVD			(0x1 << 4)

@@ -435,6 +436,10 @@
 #define IMX6SX_GPR5_DISP_MUX_DCIC1_LVDS			(0x1 << 1)
 #define IMX6SX_GPR5_DISP_MUX_DCIC1_MASK			(0x1 << 1)
 
+#define IMX6SX_GPR12_PCIE_TEST_POWERDOWN		BIT(30)
+#define IMX6SX_GPR12_PCIE_RX_EQ_MASK			(0x7 << 0)
+#define IMX6SX_GPR12_PCIE_RX_EQ_2			(0x2 << 0)
+
 /* For imx6ul iomux gpr register field define */
 #define IMX6UL_GPR1_ENET1_CLK_DIR		(0x1 << 17)
 #define IMX6UL_GPR1_ENET2_CLK_DIR		(0x1 << 18)
Signature · 4 lines
Lee Jones
Linaro STMicroelectronics Landing Team Lead
Linaro.org ? Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog
author
#3 lore raw

PATCH v3 2/2 PCI: imx6: add initial imx6sx support

In reply to Christoph Fritz

This patch adds initial PCIe support for the imx6 SoC derivate imx6sx. PCI_MSI support is untested as its necessary suspend/resume quirk is left out of this patch.
This patch is heavily based on patches by Richard Zhu.

Signed-off-by Christoph Fritz <[email protected]>
---
 .../devicetree/bindings/pci/fsl,imx6q-pcie.txt     |   6 +-
 drivers/pci/host/pci-imx6.c                        | 130 ++++++++++++++-------
 2 files changed, 96 insertions(+), 40 deletions(-)
Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt +5 -1
index 6fbba53..c4323be 100644
@@ -4,7 +4,7 @@ This PCIe host controller is based on the Synopsis Designware PCIe IP
 and thus inherits all the common properties defined in designware-pcie.txt.
 
 Required properties:
-- compatible: "fsl,imx6q-pcie"
+- compatible: "fsl,imx6q-pcie", "fsl,imx6sx-pcie"
 - reg: base addresse and length of the pcie controller
 - interrupts: A list of interrupt outputs of the controller. Must contain an
   entry for each entry in the interrupt-names property.

@@ -13,6 +13,10 @@ Required properties:
 - clock-names: Must include the following additional entries:
 	- "pcie_phy"
 
+Additional required properties for imx6sx-pcie:
+- clock names: Must include the following additional entries:
+	- "pcie_inbound_axi"
+
 Example:
 
 	pcie at 0x01000000 {
drivers/pci/host/pci-imx6.c +91 -39

185 lines not on this page · raw message

Signature · 1 line
2.1.4
#4 lore raw

PATCH v3 2/2 PCI: imx6: add initial imx6sx support

Hi Christoph (and Lee; there's a question for you below, too),

Quoted 16 lines · Christoph Fritz

This patch adds initial PCIe support for the imx6 SoC derivate imx6sx. PCI_MSI support is untested as its necessary suspend/resume quirk is left out of this patch.
This patch is heavily based on patches by Richard Zhu.

Signed-off-by Christoph Fritz <[email protected]>
---
 .../devicetree/bindings/pci/fsl,imx6q-pcie.txt     |   6 +-
 drivers/pci/host/pci-imx6.c                        | 130 ++++++++++++++-------
 2 files changed, 96 insertions(+), 40 deletions(-)
Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt +0 -0
index 6fbba53..c4323be 100644

Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt This PCIe host controller is based on the Synopsis Designware PCIe IP · line 8

Quoted 6 lines
Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt +1 -1
@@ -4,7 +4,7 @@ This PCIe host controller is based on the Synopsis Designware PCIe IP
 and thus inherits all the common properties defined in designware-pcie.txt.
 
 Required properties:
-- compatible: "fsl,imx6q-pcie"
+- compatible: "fsl,imx6q-pcie", "fsl,imx6sx-pcie"
 - reg: base addresse and length of the pcie controller

I folded in a typo fix for "addresse".

Quoted 54 lines
Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt +4 -0
 - interrupts: A list of interrupt outputs of the controller. Must contain an
   entry for each entry in the interrupt-names property.

@@ -13,6 +13,10 @@ Required properties:
 - clock-names: Must include the following additional entries:
 	- "pcie_phy"
 
+Additional required properties for imx6sx-pcie:
+- clock names: Must include the following additional entries:
+	- "pcie_inbound_axi"
+
 Example:
 
 	pcie at 0x01000000 {
drivers/pci/host/pci-imx6.c +2 -21
index fe60096..7e634a6 100644
@@ -35,9 +35,11 @@ struct imx6_pcie {
 	struct gpio_desc	*reset_gpio;
 	struct clk		*pcie_bus;
 	struct clk		*pcie_phy;
+	struct clk		*pcie_inbound_axi;
 	struct clk		*pcie;
 	struct pcie_port	pp;
 	struct regmap		*iomuxc_gpr;
+	bool			is_imx6sx;
 	void __iomem		*mem_base;
 };
 

@@ -214,35 +216,46 @@ static int imx6_pcie_assert_core_reset(struct pcie_port *pp)
 	struct imx6_pcie *imx6_pcie = to_imx6_pcie(pp);
 	u32 val, gpr1, gpr12;
 
-	/*
-	 * If the bootloader already enabled the link we need some special
-	 * handling to get the core back into a state where it is safe to
-	 * touch it for configuration.  As there is no dedicated reset signal
-	 * wired up for MX6QDL, we need to manually force LTSSM into "detect"
-	 * state before completely disabling LTSSM, which is a prerequisite
-	 * for core configuration.
-	 *
-	 * If both LTSSM_ENABLE and REF_SSP_ENABLE are active we have a strong
-	 * indication that the bootloader activated the link.
-	 */
-	regmap_read(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1, &gpr1);
-	regmap_read(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, &gpr12);
-
-	if ((gpr1 & IMX6Q_GPR1_PCIE_REF_CLK_EN) &&
-	    (gpr12 & IMX6Q_GPR12_PCIE_CTL_2)) {
-		val = readl(pp->dbi_base + PCIE_PL_PFLR);
-		val &= ~PCIE_PL_PFLR_LINK_STATE_MASK;
-		val |= PCIE_PL_PFLR_FORCE_LINK;
-		writel(val, pp->dbi_base + PCIE_PL_PFLR);
-

drivers/pci/host/pci-imx6.c static int imx6_pcie_assert_core_reset(struct pcie_port *pp) · line 226

Quoted 10 lines
drivers/pci/host/pci-imx6.c +7 -2
+	if (imx6_pcie->is_imx6sx) {
 		regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
-				IMX6Q_GPR12_PCIE_CTL_2, 0 << 10);
-	}
+				IMX6SX_GPR12_PCIE_TEST_POWERDOWN,
+				IMX6SX_GPR12_PCIE_TEST_POWERDOWN);
+		/* Force PCIe PHY reset */
+		regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR5,
+					IMX6SX_GPR5_PCIE_BTNRST_RESET,
+					IMX6SX_GPR5_PCIE_BTNRST_RESET);

Since there's nothing after the "else" clause, I think it's better to return immediately here. Then we don't have extra diffs that merely indent the original function. I did make this change (I'll attach my resulting patch), and that made some other changes to the indented code more visible.

drivers/pci/host/pci-imx6.c static int imx6_pcie_assert_core_reset(struct pcie_port *pp) · line 234

Quoted 8 lines
drivers/pci/host/pci-imx6.c +8 -0
+	} else {
+		/*
+		 * If the bootloader already enabled the link we need some
+		 * special handling to get the core back into a state where
+		 * it is safe to touch it for configuration.  As there is no
+		 * dedicated reset signal to manually force LTSSM into "detect"
+		 * state before completely disabling LTSSM, which is a
+		 * prerequisite for core configuration.

For example, you changed this comment, and now the last sentence is no longer a sentence. I don't know if this was an editing mistake or if this comment really does need to change. If it does need to change, it needs to stay a sentence.

Quoted 16 lines
drivers/pci/host/pci-imx6.c +16 -0
+		 * If both LTSSM_ENABLE and REF_SSP_ENABLE are active we have
+		 * a strong indication that the bootloader activated the link.
+		 */
+		regmap_read(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1, &gpr1);
+		regmap_read(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, &gpr12);
+
+		if ((gpr1 & IMX6Q_GPR1_PCIE_REF_CLK_EN) &&
+				(gpr12 & IMX6Q_GPR12_PCIE_CTL_2)) {
+			val = readl(pp->dbi_base + PCIE_PL_PFLR);
+			val &= ~PCIE_PL_PFLR_LINK_STATE_MASK;
+			val |= PCIE_PL_PFLR_FORCE_LINK;
+			writel(val, pp->dbi_base + PCIE_PL_PFLR);
+
+			regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
+				IMX6Q_GPR12_PCIE_CTL_2, 0);
+		}

drivers/pci/host/pci-imx6.c static int imx6_pcie_assert_core_reset(struct pcie_port *pp) · line 256

Quoted 10 lines
drivers/pci/host/pci-imx6.c +5 -4
 
-	regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
-			IMX6Q_GPR1_PCIE_TEST_PD, 1 << 18);
-	regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
-			IMX6Q_GPR1_PCIE_REF_CLK_EN, 0 << 16);
+		regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
+			IMX6Q_GPR1_PCIE_TEST_PD,
+			IMX6Q_GPR1_PCIE_TEST_PD);
+		regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
+			IMX6Q_GPR1_PCIE_REF_CLK_EN, 0);

And there are subtle changes here (changing "1 << 18" to IMX6Q_GPR1_PCIE_TEST_PD, etc.) These are fine, but should be in a separate patch because (a) they're not related to imx6sx and (b) it makes them obvious and easy to review. As it is, they just get snuck in under the radar.

Quoted 34 lines
drivers/pci/host/pci-imx6.c +15 -12
+	}
 
 	return 0;
 }

@@ -270,18 +283,30 @@ static int imx6_pcie_deassert_core_reset(struct pcie_port *pp)
 		goto err_pcie;
 	}
 
-	/* power up core phy and enable ref clock */
-	regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
-			IMX6Q_GPR1_PCIE_TEST_PD, 0 << 18);
-	/*
-	 * the async reset input need ref clock to sync internally,
-	 * when the ref clock comes after reset, internal synced
-	 * reset time is too short, cannot meet the requirement.
-	 * add one ~10us delay here.
-	 */
-	udelay(10);
-	regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
-			IMX6Q_GPR1_PCIE_REF_CLK_EN, 1 << 16);
+	if (imx6_pcie->is_imx6sx) {
+		ret = clk_prepare_enable(imx6_pcie->pcie_inbound_axi);
+		if (ret) {
+			dev_err(pp->dev, "unable to enable pcie_axi clock\n");
+			goto err_inbound_axi;
+		}
+
+		regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
+			IMX6SX_GPR12_PCIE_TEST_POWERDOWN, 0);
+	} else {
+		/* power up core phy and enable ref clock */
+		regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
+				IMX6Q_GPR1_PCIE_TEST_PD, 0);
+		/*

drivers/pci/host/pci-imx6.c static int imx6_pcie_deassert_core_reset(struct pcie_port *pp) · line 309

Quoted 10 lines
drivers/pci/host/pci-imx6.c +10 -0
+		 * the async reset input need ref clock to sync internally,
+		 * when the ref clock comes after reset, internal synced
+		 * reset time is too short , cannot meet the requirement.
+		 * add one ~10us delay here.
+		 */
+		udelay(10);
+		regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
+			IMX6Q_GPR1_PCIE_REF_CLK_EN,
+			IMX6Q_GPR1_PCIE_REF_CLK_EN);
+	}

Here again the diff is bigger than necessary because it re-indents the original code (and makes another unrelated "1 << 16" to IMX6Q_GPR1_PCIE_REF_CLK_EN change). I'll show a different proposal in my patch below.

Quoted 19 lines
drivers/pci/host/pci-imx6.c +7 -0
 	/* allow the clocks to stabilize */
 	usleep_range(200, 500);

@@ -292,8 +317,15 @@ static int imx6_pcie_deassert_core_reset(struct pcie_port *pp)
 		msleep(100);
 		gpiod_set_value_cansleep(imx6_pcie->reset_gpio, 1);
 	}
+
+	if (imx6_pcie->is_imx6sx)
+		regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR5,
+			IMX6SX_GPR5_PCIE_BTNRST_RESET, 0);
+
 	return 0;
 
+err_inbound_axi:
+	clk_disable_unprepare(imx6_pcie->pcie);
 err_pcie:
 	clk_disable_unprepare(imx6_pcie->pcie_bus);
 err_pcie_bus:

drivers/pci/host/pci-imx6.c static void imx6_pcie_init_phy(struct pcie_port *pp) · line 345

Quoted 7 lines
drivers/pci/host/pci-imx6.c +4 -0
@@ -307,6 +339,12 @@ static void imx6_pcie_init_phy(struct pcie_port *pp)
 {
 	struct imx6_pcie *imx6_pcie = to_imx6_pcie(pp);
 
+	if (imx6_pcie->is_imx6sx) {
+		regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
+			IMX6SX_GPR12_PCIE_RX_EQ_MASK,
+			IMX6SX_GPR12_PCIE_RX_EQ_2);

I see that you added definitions for IMX6SX_GPR12_PCIE_RX_EQ_MASK and IMX6SX_GPR12_PCIE_RX_EQ_2 in the first patch of this series, but doing that separately creates a merge problem. I can't put this change in my tree by itself because it won't build. If Lee applied the first patch to a git branch, I guess I could pull that into my tree. But it would be far simpler to just include those new definitions in this patch.

Quoted 33 lines
drivers/pci/host/pci-imx6.c +15 -0
+	}
+
 	regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
 			IMX6Q_GPR12_PCIE_CTL_2, 0 << 10);
 

@@ -571,6 +609,9 @@ static int __init imx6_pcie_probe(struct platform_device *pdev)
 	pp = &imx6_pcie->pp;
 	pp->dev = &pdev->dev;
 
+	imx6_pcie->is_imx6sx = of_device_is_compatible(pp->dev->of_node,
+					"fsl,imx6sx-pcie");
+
 	/* Added for PCI abort handling */
 	hook_fault_code(16 + 6, imx6q_pcie_abort_handler, SIGBUS, 0,
 		"imprecise external abort");

@@ -606,6 +647,16 @@ static int __init imx6_pcie_probe(struct platform_device *pdev)
 		return PTR_ERR(imx6_pcie->pcie);
 	}
 
+	if (imx6_pcie->is_imx6sx) {
+		imx6_pcie->pcie_inbound_axi = devm_clk_get(&pdev->dev,
+			"pcie_inbound_axi");
+		if (IS_ERR(imx6_pcie->pcie_inbound_axi)) {
+			dev_err(&pdev->dev,
+				"pcie_incbound_axi clock missing or invalid\n");
+			return PTR_ERR(imx6_pcie->pcie_inbound_axi);
+		}
+	}
+
 	/* Grab GPR config register range */
 	imx6_pcie->iomuxc_gpr =
 		 syscon_regmap_lookup_by_compatible("fsl,imx6q-iomuxc-gpr");

drivers/pci/host/pci-imx6.c static void imx6_pcie_shutdown(struct platform_device *pdev) · line 689

Quoted 7 lines
drivers/pci/host/pci-imx6.c +1 -0
@@ -632,6 +683,7 @@ static void imx6_pcie_shutdown(struct platform_device *pdev)
 
 static const struct of_device_id imx6_pcie_of_match[] = {
 	{ .compatible = "fsl,imx6q-pcie", },
+	{ .compatible = "fsl,imx6sx-pcie", },
 	{},
 };
 MODULE_DEVICE_TABLE(of, imx6_pcie_of_match);

The patches below are what I currently have in my tree, but they're not ready for v4.6 (yet).

Note that the second one is very clearly imx6sx-only. It's obvious there are no tweaks to the existing imx6 code, which makes it easier to review, backport, bisect, revert, etc.

Obviously, I can't apply these directly. First we have to:

- Fix the LTSSM comment
- Figure out how to get the IMX6SX_GPR12_PCIE_RX_EQ_MASK definitions

commit 78abf60b815a8f28207d029d61f7809647faa43a

Author: Bjorn Helgaas <[email protected]>
Date:   Fri Mar 11 11:15:36 2016 -0600

PCI: imx6: Factor out ref clock enable

Factor out ref clock enable to make it cleaner to add imx6sx support. No functional change intended.

Signed-off-by Bjorn Helgaas <[email protected]>
drivers/pci/host/pci-imx6.c +24 -12
index 8c9b389..ecc8537 100644
@@ -269,6 +269,23 @@ static int imx6_pcie_assert_core_reset(struct pcie_port *pp)
 	return 0;
 }
 
+static int imx6_pcie_enable_ref_clk(struct imx6_pcie *imx6_pcie)
+{
+	/* power up core phy and enable ref clock */
+	regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
+			IMX6Q_GPR1_PCIE_TEST_PD, 0 << 18);
+	/*
+	 * the async reset input need ref clock to sync internally,
+	 * when the ref clock comes after reset, internal synced
+	 * reset time is too short, cannot meet the requirement.
+	 * add one ~10us delay here.
+	 */
+	udelay(10);
+	regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
+			IMX6Q_GPR1_PCIE_REF_CLK_EN, 1 << 16);
+	return 0;
+}
+
 static int imx6_pcie_deassert_core_reset(struct pcie_port *pp)
 {
 	struct imx6_pcie *imx6_pcie = to_imx6_pcie(pp);

@@ -292,18 +309,11 @@ static int imx6_pcie_deassert_core_reset(struct pcie_port *pp)
 		goto err_pcie;
 	}
 
-	/* power up core phy and enable ref clock */
-	regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
-			IMX6Q_GPR1_PCIE_TEST_PD, 0 << 18);
-	/*
-	 * the async reset input need ref clock to sync internally,
-	 * when the ref clock comes after reset, internal synced
-	 * reset time is too short, cannot meet the requirement.
-	 * add one ~10us delay here.
-	 */
-	udelay(10);
-	regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
-			IMX6Q_GPR1_PCIE_REF_CLK_EN, 1 << 16);
+	ret = imx6_pcie_enable_ref_clk(imx6_pcie);
+	if (ret)
+		dev_err(pp->dev, "unable to enable pcie ref clock\n");
+		goto err_ref_clk;
+	}
 
 	/* allow the clocks to stabilize */
 	usleep_range(200, 500);

@@ -316,6 +326,8 @@ static int imx6_pcie_deassert_core_reset(struct pcie_port *pp)
 	}
 	return 0;
 
+err_ref_clk:
+	clk_disable_unprepare(imx6_pcie->pcie);
 err_pcie:
 	clk_disable_unprepare(imx6_pcie->pcie_bus);
 err_pcie_bus:

commit d061033570b7fd22a3ed8c029d4793e5df7324e1

Author: Christoph Fritz <[email protected]>
Date:   Thu Mar 10 15:04:25 2016 -0600

PCI: imx6: Add initial imx6sx support

Add initial PCIe support for the imx6 SoC derivate imx6sx. PCI MSI support is untested as the necessary suspend/resume quirk is not included in this patch.

This patch is heavily based on patches by Richard Zhu.

[bhelgaas: factor out refclk enable, fix adjacent typos in fsl,imx6q-pcie.txt]
Signed-off-by Christoph Fritz <[email protected]>
Acked-by Richard Zhu <[email protected]>
Acked-by Lucas Stach <[email protected]>
Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt +6 -2
index 3be80c6..0561e88 100644
@@ -4,8 +4,8 @@ This PCIe host controller is based on the Synopsis Designware PCIe IP
 and thus inherits all the common properties defined in designware-pcie.txt.
 
 Required properties:
-- compatible: "fsl,imx6q-pcie"
-- reg: base addresse and length of the pcie controller
+- compatible: "fsl,imx6q-pcie", "fsl,imx6sx-pcie"
+- reg: base address and length of the PCIe controller
 - interrupts: A list of interrupt outputs of the controller. Must contain an
   entry for each entry in the interrupt-names property.
 - interrupt-names: Must include the following entries:

@@ -20,6 +20,10 @@ Optional properties:
 - fsl,tx-swing-full: Gen2 TX SWING FULL value. Default: 127
 - fsl,tx-swing-low: TX launch amplitude swing_low value. Default: 127
 
+Additional required properties for imx6sx-pcie:
+- clock names: Must include the following additional entries:
+	- "pcie_inbound_axi"
+
 Example:
 
 	pcie at 0x01000000 {
drivers/pci/host/pci-imx6.c +52 -3

110 lines not on this page · raw message

author
#5 lore raw

PATCH v3 2/2 PCI: imx6: add initial imx6sx support

Hi Bjorn

Quoted 1 line · Bjorn Helgaas

Hi Christoph (and Lee; there's a question for you below, too),

Thanks for your review, please see my answers and comments below.

Quoted 66 lines · Christoph Fritz
Quoted 16 lines

This patch adds initial PCIe support for the imx6 SoC derivate imx6sx. PCI_MSI support is untested as its necessary suspend/resume quirk is left out of this patch.
This patch is heavily based on patches by Richard Zhu.

Signed-off-by Christoph Fritz <[email protected]>
---
 .../devicetree/bindings/pci/fsl,imx6q-pcie.txt     |   6 +-
 drivers/pci/host/pci-imx6.c                        | 130 ++++++++++++++-------
 2 files changed, 96 insertions(+), 40 deletions(-)
Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt +0 -0
index 6fbba53..c4323be 100644

Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt This PCIe host controller is based on the Synopsis Designware PCIe IP · line 8

Quoted 6 lines
Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt +1 -1
@@ -4,7 +4,7 @@ This PCIe host controller is based on the Synopsis Designware PCIe IP
 and thus inherits all the common properties defined in designware-pcie.txt.
 
 Required properties:
-- compatible: "fsl,imx6q-pcie"
+- compatible: "fsl,imx6q-pcie", "fsl,imx6sx-pcie"
 - reg: base addresse and length of the pcie controller

I folded in a typo fix for "addresse".

Quoted 40 lines
Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt +4 -0
 - interrupts: A list of interrupt outputs of the controller. Must contain an
   entry for each entry in the interrupt-names property.

@@ -13,6 +13,10 @@ Required properties:
 - clock-names: Must include the following additional entries:
 	- "pcie_phy"
 
+Additional required properties for imx6sx-pcie:
+- clock names: Must include the following additional entries:
+	- "pcie_inbound_axi"
+
 Example:
 
 	pcie at 0x01000000 {
drivers/pci/host/pci-imx6.c +2 -7
index fe60096..7e634a6 100644
@@ -35,9 +35,11 @@ struct imx6_pcie {
 	struct gpio_desc	*reset_gpio;
 	struct clk		*pcie_bus;
 	struct clk		*pcie_phy;
+	struct clk		*pcie_inbound_axi;
 	struct clk		*pcie;
 	struct pcie_port	pp;
 	struct regmap		*iomuxc_gpr;
+	bool			is_imx6sx;
 	void __iomem		*mem_base;
 };
 

@@ -214,35 +216,46 @@ static int imx6_pcie_assert_core_reset(struct pcie_port *pp)
 	struct imx6_pcie *imx6_pcie = to_imx6_pcie(pp);
 	u32 val, gpr1, gpr12;
 
-	/*
-	 * If the bootloader already enabled the link we need some special
-	 * handling to get the core back into a state where it is safe to
-	 * touch it for configuration.  As there is no dedicated reset signal
-	 * wired up for MX6QDL, we need to manually force LTSSM into "detect"
-	 * state before completely disabling LTSSM, which is a prerequisite
-	 * for core configuration.

<snip>

Quoted 5 lines
Quoted 5 lines
drivers/pci/host/pci-imx6.c +5 -0
+	} else {
+		/*
+		 * If the bootloader already enabled the link we need some
+		 * special handling to get the core back into a state where
+		 * it is safe to touch it for configuration.  As there is no
Quoted 8 lines

drivers/pci/host/pci-imx6.c

Quoted 3 lines
drivers/pci/host/pci-imx6.c +3 -0
+		 * dedicated reset signal to manually force LTSSM into "detect"
+		 * state before completely disabling LTSSM, which is a
+		 * prerequisite for core configuration.

For example, you changed this comment, and now the last sentence is no longer a sentence. I don't know if this was an editing mistake or if this comment really does need to change. If it does need to change, it needs to stay a sentence.

I suppose Richard's intend was to get rid of the explicit mentioning of "MX6QDL".
Since I don't touch this code I'll drop this change and leave this comment as it is.

Quoted 18 lines
Quoted 18 lines
drivers/pci/host/pci-imx6.c +16 -0
+		 * If both LTSSM_ENABLE and REF_SSP_ENABLE are active we have
+		 * a strong indication that the bootloader activated the link.
+		 */
+		regmap_read(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1, &gpr1);
+		regmap_read(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, &gpr12);
+
+		if ((gpr1 & IMX6Q_GPR1_PCIE_REF_CLK_EN) &&
+				(gpr12 & IMX6Q_GPR12_PCIE_CTL_2)) {
+			val = readl(pp->dbi_base + PCIE_PL_PFLR);
+			val &= ~PCIE_PL_PFLR_LINK_STATE_MASK;
+			val |= PCIE_PL_PFLR_FORCE_LINK;
+			writel(val, pp->dbi_base + PCIE_PL_PFLR);
+
+			regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
+				IMX6Q_GPR12_PCIE_CTL_2, 0);
+		}
Quoted 15 lines

drivers/pci/host/pci-imx6.c

Quoted 9 lines
drivers/pci/host/pci-imx6.c +5 -4
-	regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
-			IMX6Q_GPR1_PCIE_TEST_PD, 1 << 18);
-	regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
-			IMX6Q_GPR1_PCIE_REF_CLK_EN, 0 << 16);
+		regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
+			IMX6Q_GPR1_PCIE_TEST_PD,
+			IMX6Q_GPR1_PCIE_TEST_PD);
+		regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
+			IMX6Q_GPR1_PCIE_REF_CLK_EN, 0);

And there are subtle changes here (changing "1 << 18" to IMX6Q_GPR1_PCIE_TEST_PD, etc.) These are fine, but should be in a separate patch because (a) they're not related to imx6sx and (b) it makes them obvious and easy to review. As it is, they just get snuck in under the radar.

OK

Quoted 42 lines
Quoted 42 lines
drivers/pci/host/pci-imx6.c +22 -12
+	}
 
 	return 0;
 }

@@ -270,18 +283,30 @@ static int imx6_pcie_deassert_core_reset(struct pcie_port *pp)
 		goto err_pcie;
 	}
 
-	/* power up core phy and enable ref clock */
-	regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
-			IMX6Q_GPR1_PCIE_TEST_PD, 0 << 18);
-	/*
-	 * the async reset input need ref clock to sync internally,
-	 * when the ref clock comes after reset, internal synced
-	 * reset time is too short, cannot meet the requirement.
-	 * add one ~10us delay here.
-	 */
-	udelay(10);
-	regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
-			IMX6Q_GPR1_PCIE_REF_CLK_EN, 1 << 16);
+	if (imx6_pcie->is_imx6sx) {
+		ret = clk_prepare_enable(imx6_pcie->pcie_inbound_axi);
+		if (ret) {
+			dev_err(pp->dev, "unable to enable pcie_axi clock\n");
+			goto err_inbound_axi;
+		}
+
+		regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
+			IMX6SX_GPR12_PCIE_TEST_POWERDOWN, 0);
+	} else {
+		/* power up core phy and enable ref clock */
+		regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
+				IMX6Q_GPR1_PCIE_TEST_PD, 0);
+		/*
+		 * the async reset input need ref clock to sync internally,
+		 * when the ref clock comes after reset, internal synced
+		 * reset time is too short , cannot meet the requirement.
+		 * add one ~10us delay here.
+		 */
+		udelay(10);
+		regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
Quoted 8 lines

drivers/pci/host/pci-imx6.c static int imx6_pcie_deassert_core_reset(struct pcie_port *pp) · line 309

Quoted 3 lines
drivers/pci/host/pci-imx6.c +3 -0
+			IMX6Q_GPR1_PCIE_REF_CLK_EN,
+			IMX6Q_GPR1_PCIE_REF_CLK_EN);
+	}

Here again the diff is bigger than necessary because it re-indents the original code (and makes another unrelated "1 << 16" to IMX6Q_GPR1_PCIE_REF_CLK_EN change). I'll show a different proposal in my patch below.

OK

Quoted 23 lines
Quoted 23 lines
drivers/pci/host/pci-imx6.c +7 -0
 	/* allow the clocks to stabilize */
 	usleep_range(200, 500);

@@ -292,8 +317,15 @@ static int imx6_pcie_deassert_core_reset(struct pcie_port *pp)
 		msleep(100);
 		gpiod_set_value_cansleep(imx6_pcie->reset_gpio, 1);
 	}
+
+	if (imx6_pcie->is_imx6sx)
+		regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR5,
+			IMX6SX_GPR5_PCIE_BTNRST_RESET, 0);
+
 	return 0;
 
+err_inbound_axi:
+	clk_disable_unprepare(imx6_pcie->pcie);
 err_pcie:
 	clk_disable_unprepare(imx6_pcie->pcie_bus);
 err_pcie_bus:

@@ -307,6 +339,12 @@ static void imx6_pcie_init_phy(struct pcie_port *pp)
 {
 	struct imx6_pcie *imx6_pcie = to_imx6_pcie(pp);
Quoted 12 lines

drivers/pci/host/pci-imx6.c static void imx6_pcie_init_phy(struct pcie_port *pp) · line 376

Quoted 4 lines
drivers/pci/host/pci-imx6.c +4 -0
+	if (imx6_pcie->is_imx6sx) {
+		regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
+			IMX6SX_GPR12_PCIE_RX_EQ_MASK,
+			IMX6SX_GPR12_PCIE_RX_EQ_2);

I see that you added definitions for IMX6SX_GPR12_PCIE_RX_EQ_MASK and IMX6SX_GPR12_PCIE_RX_EQ_2 in the first patch of this series, but doing that separately creates a merge problem. I can't put this change in my tree by itself because it won't build. If Lee applied the first patch to a git branch, I guess I could pull that into my tree. But it would be far simpler to just include those new definitions in this patch.

Sorry, Lee Jones already applied this patch to his public git repository:

git://git.kernel.org/pub/scm/linux/kernel/git/lee/mfd.git

Commit id:

987480efd6d39447981e96b438cf5a781b756712

currently in branch for-mfd-next

Is it okay for you to pull this commit?

It's also already in linux-next.

<snip>

Quoted 29 lines

The patches below are what I currently have in my tree, but they're not ready for v4.6 (yet).

Note that the second one is very clearly imx6sx-only. It's obvious there are no tweaks to the existing imx6 code, which makes it easier to review, backport, bisect, revert, etc.

Obviously, I can't apply these directly. First we have to:

- Fix the LTSSM comment
- Figure out how to get the IMX6SX_GPR12_PCIE_RX_EQ_MASK definitions

commit 78abf60b815a8f28207d029d61f7809647faa43a

Author: Bjorn Helgaas <[email protected]>
Date:   Fri Mar 11 11:15:36 2016 -0600

PCI: imx6: Factor out ref clock enable

Factor out ref clock enable to make it cleaner to add imx6sx support. No functional change intended.

Signed-off-by Bjorn Helgaas <[email protected]>
drivers/pci/host/pci-imx6.c +0 -0
index 8c9b389..ecc8537 100644
@@ -269,6 +269,23 @@ static int imx6_pcie_assert_core_reset(struct pcie_port *pp)

<snip>

drivers/pci/host/pci-imx6.c static int imx6_pcie_deassert_core_reset(struct pcie_port *pp) · line 313

Quoted 5 lines
drivers/pci/host/pci-imx6.c +2 -3
-	udelay(10);
-	regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
-			IMX6Q_GPR1_PCIE_REF_CLK_EN, 1 << 16);
+	ret = imx6_pcie_enable_ref_clk(imx6_pcie);
+	if (ret)

a '{ ' is missing

Quoted 33 lines
drivers/pci/host/pci-imx6.c +5 -0
+		dev_err(pp->dev, "unable to enable pcie ref clock\n");
+		goto err_ref_clk;
+	}
 
 	/* allow the clocks to stabilize */
 	usleep_range(200, 500);

@@ -316,6 +326,8 @@ static int imx6_pcie_deassert_core_reset(struct pcie_port *pp)
 	}
 	return 0;
 
+err_ref_clk:
+	clk_disable_unprepare(imx6_pcie->pcie);
 err_pcie:
 	clk_disable_unprepare(imx6_pcie->pcie_bus);
 err_pcie_bus:

commit d061033570b7fd22a3ed8c029d4793e5df7324e1

Author: Christoph Fritz <[email protected]>
Date:   Thu Mar 10 15:04:25 2016 -0600

PCI: imx6: Add initial imx6sx support

Add initial PCIe support for the imx6 SoC derivate imx6sx. PCI MSI support is untested as the necessary suspend/resume quirk is not included in this patch.

This patch is heavily based on patches by Richard Zhu.

[bhelgaas: factor out refclk enable, fix adjacent typos in fsl,imx6q-pcie.txt]
Signed-off-by Christoph Fritz <[email protected]>
Acked-by Richard Zhu <[email protected]>
Acked-by Lucas Stach <[email protected]>

<snip>

Quoted 8 lines
drivers/pci/host/pci-imx6.c +0 -0
index ecc8537..4d6af21 100644
@@ -35,9 +35,11 @@ struct imx6_pcie {
 	struct gpio_desc	*reset_gpio;
 	struct clk		*pcie_bus;
 	struct clk		*pcie_phy;

<snip>

Quoted 13 lines
drivers/pci/host/pci-imx6.c +2 -3
 	/*
 	 * If the bootloader already enabled the link we need some special
 	 * handling to get the core back into a state where it is safe to
 	 * touch it for configuration.  As there is no dedicated reset signal
-	 * wired up for MX6QDL, we need to manually force LTSSM into "detect"
-	 * state before completely disabling LTSSM, which is a prerequisite
-	 * for core configuration.
+	 * to manually force LTSSM into "detect" state before completely
+	 * disabling LTSSM, which is a prerequisite for core configuration.
 	 *
 	 * If both LTSSM_ENABLE and REF_SSP_ENABLE are active we have a strong
 	 * indication that the bootloader activated the link.

drivers/pci/host/pci-imx6.c static int imx6_pcie_assert_core_reset(struct pcie_port *pp) · line 285

Quoted 3 lines
drivers/pci/host/pci-imx6.c +0 -0
@@ -271,6 +283,18 @@ static int imx6_pcie_assert_core_reset(struct pcie_port *pp)
 
 static int imx6_pcie_enable_ref_clk(struct imx6_pcie *imx6_pcie)
 {

this is missing:

	struct pcie_port *pp = &imx6_pcie->pp;
	int ret;

drivers/pci/host/pci-imx6.c static int imx6_pcie_assert_core_reset(struct pcie_port *pp) · line 295

Quoted 10 lines
drivers/pci/host/pci-imx6.c +10 -0
+	if (imx6_pcie->is_imx6sx) {
+		ret = clk_prepare_enable(imx6_pcie->pcie_inbound_axi);
+		if (ret) {
+			dev_err(pp->dev, "unable to enable pcie_axi clock\n");
+			return ret;
+		}
+
+		regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
+				   IMX6SX_GPR12_PCIE_TEST_POWERDOWN, 0);
+		return 0;

then we can use

	return ret;

instead

drivers/pci/host/pci-imx6.c static int imx6_pcie_assert_core_reset(struct pcie_port *pp) · line 299

Quoted 4 lines
drivers/pci/host/pci-imx6.c +2 -0
+	}
+
 	/* power up core phy and enable ref clock */
 	regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,

<snip>

I'll fix these two patches and send them as follow up to this mail.

Thanks
-- Christoph

author
#6 lore raw

PCI: imx6: Factor out ref clock enable

commit dfcc1a16e6954e8ca6cadfc9dd309db6b6ef46b2
Author: Bjorn Helgaas <[email protected]>
Date: Fri, 11 Mar 2016 11:15:36 -0600

Factor out ref clock enable to make it cleaner to add imx6sx support. No functional change intended.

Signed-off-by Bjorn Helgaas <[email protected]>
Tested-by Christoph Fritz <[email protected]>
---
 drivers/pci/host/pci-imx6.c | 36 ++++++++++++++++++++++++------------
 1 file changed, 24 insertions(+), 12 deletions(-)
drivers/pci/host/pci-imx6.c +24 -12
index bd3f7d0..4e0e47f 100644
@@ -264,6 +264,23 @@ static int imx6_pcie_assert_core_reset(struct pcie_port *pp)
 	return 0;
 }
 
+static int imx6_pcie_enable_ref_clk(struct imx6_pcie *imx6_pcie)
+{
+	/* power up core phy and enable ref clock */
+	regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
+			IMX6Q_GPR1_PCIE_TEST_PD, 0 << 18);
+	/*
+	 * the async reset input need ref clock to sync internally,
+	 * when the ref clock comes after reset, internal synced
+	 * reset time is too short, cannot meet the requirement.
+	 * add one ~10us delay here.
+	 */
+	udelay(10);
+	regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
+			IMX6Q_GPR1_PCIE_REF_CLK_EN, 1 << 16);
+	return 0;
+}
+
 static int imx6_pcie_deassert_core_reset(struct pcie_port *pp)
 {
 	struct imx6_pcie *imx6_pcie = to_imx6_pcie(pp);

@@ -287,18 +304,11 @@ static int imx6_pcie_deassert_core_reset(struct pcie_port *pp)
 		goto err_pcie;
 	}
 
-	/* power up core phy and enable ref clock */
-	regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
-			IMX6Q_GPR1_PCIE_TEST_PD, 0 << 18);
-	/*
-	 * the async reset input need ref clock to sync internally,
-	 * when the ref clock comes after reset, internal synced
-	 * reset time is too short, cannot meet the requirement.
-	 * add one ~10us delay here.
-	 */
-	udelay(10);
-	regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
-			IMX6Q_GPR1_PCIE_REF_CLK_EN, 1 << 16);
+	ret = imx6_pcie_enable_ref_clk(imx6_pcie);
+	if (ret) {
+		dev_err(pp->dev, "unable to enable pcie ref clock\n");
+		goto err_ref_clk;
+	}
 
 	/* allow the clocks to stabilize */
 	usleep_range(200, 500);

@@ -311,6 +321,8 @@ static int imx6_pcie_deassert_core_reset(struct pcie_port *pp)
 	}
 	return 0;
 
+err_ref_clk:
+	clk_disable_unprepare(imx6_pcie->pcie);
 err_pcie:
 	clk_disable_unprepare(imx6_pcie->pcie_bus);
 err_pcie_bus:
Signature · 1 line
2.1.4
author
#7 lore raw

PCI: imx6: Factor out ref clock enable

*ping*

Quoted 74 lines · Christoph Fritz

commit dfcc1a16e6954e8ca6cadfc9dd309db6b6ef46b2
Author: Bjorn Helgaas <[email protected]>
Date: Fri, 11 Mar 2016 11:15:36 -0600

Factor out ref clock enable to make it cleaner to add imx6sx support. No functional change intended.

Signed-off-by Bjorn Helgaas <[email protected]>
Tested-by Christoph Fritz <[email protected]>
---
 drivers/pci/host/pci-imx6.c | 36 ++++++++++++++++++++++++------------
 1 file changed, 24 insertions(+), 12 deletions(-)
drivers/pci/host/pci-imx6.c +24 -12
index bd3f7d0..4e0e47f 100644
@@ -264,6 +264,23 @@ static int imx6_pcie_assert_core_reset(struct pcie_port *pp)
 	return 0;
 }
 
+static int imx6_pcie_enable_ref_clk(struct imx6_pcie *imx6_pcie)
+{
+	/* power up core phy and enable ref clock */
+	regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
+			IMX6Q_GPR1_PCIE_TEST_PD, 0 << 18);
+	/*
+	 * the async reset input need ref clock to sync internally,
+	 * when the ref clock comes after reset, internal synced
+	 * reset time is too short, cannot meet the requirement.
+	 * add one ~10us delay here.
+	 */
+	udelay(10);
+	regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
+			IMX6Q_GPR1_PCIE_REF_CLK_EN, 1 << 16);
+	return 0;
+}
+
 static int imx6_pcie_deassert_core_reset(struct pcie_port *pp)
 {
 	struct imx6_pcie *imx6_pcie = to_imx6_pcie(pp);

@@ -287,18 +304,11 @@ static int imx6_pcie_deassert_core_reset(struct pcie_port *pp)
 		goto err_pcie;
 	}
 
-	/* power up core phy and enable ref clock */
-	regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
-			IMX6Q_GPR1_PCIE_TEST_PD, 0 << 18);
-	/*
-	 * the async reset input need ref clock to sync internally,
-	 * when the ref clock comes after reset, internal synced
-	 * reset time is too short, cannot meet the requirement.
-	 * add one ~10us delay here.
-	 */
-	udelay(10);
-	regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
-			IMX6Q_GPR1_PCIE_REF_CLK_EN, 1 << 16);
+	ret = imx6_pcie_enable_ref_clk(imx6_pcie);
+	if (ret) {
+		dev_err(pp->dev, "unable to enable pcie ref clock\n");
+		goto err_ref_clk;
+	}
 
 	/* allow the clocks to stabilize */
 	usleep_range(200, 500);

@@ -311,6 +321,8 @@ static int imx6_pcie_deassert_core_reset(struct pcie_port *pp)
 	}
 	return 0;
 
+err_ref_clk:
+	clk_disable_unprepare(imx6_pcie->pcie);
 err_pcie:
 	clk_disable_unprepare(imx6_pcie->pcie_bus);
 err_pcie_bus:
Applied
#8 lore raw

PCI: imx6: Factor out ref clock enable

In reply to Christoph Fritz

Hi Christoph,

Quoted 9 lines · Christoph Fritz

commit dfcc1a16e6954e8ca6cadfc9dd309db6b6ef46b2
Author: Bjorn Helgaas <[email protected]>
Date: Fri, 11 Mar 2016 11:15:36 -0600

Factor out ref clock enable to make it cleaner to add imx6sx support. No functional change intended.

Signed-off-by Bjorn Helgaas <[email protected]>
Tested-by Christoph Fritz <[email protected]>

Applied to pci/host-imx6 for v4.7, thanks!

Quoted 73 lines
---
 drivers/pci/host/pci-imx6.c | 36 ++++++++++++++++++++++++------------
 1 file changed, 24 insertions(+), 12 deletions(-)
drivers/pci/host/pci-imx6.c +24 -12
index bd3f7d0..4e0e47f 100644
@@ -264,6 +264,23 @@ static int imx6_pcie_assert_core_reset(struct pcie_port *pp)
 	return 0;
 }
 
+static int imx6_pcie_enable_ref_clk(struct imx6_pcie *imx6_pcie)
+{
+	/* power up core phy and enable ref clock */
+	regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
+			IMX6Q_GPR1_PCIE_TEST_PD, 0 << 18);
+	/*
+	 * the async reset input need ref clock to sync internally,
+	 * when the ref clock comes after reset, internal synced
+	 * reset time is too short, cannot meet the requirement.
+	 * add one ~10us delay here.
+	 */
+	udelay(10);
+	regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
+			IMX6Q_GPR1_PCIE_REF_CLK_EN, 1 << 16);
+	return 0;
+}
+
 static int imx6_pcie_deassert_core_reset(struct pcie_port *pp)
 {
 	struct imx6_pcie *imx6_pcie = to_imx6_pcie(pp);

@@ -287,18 +304,11 @@ static int imx6_pcie_deassert_core_reset(struct pcie_port *pp)
 		goto err_pcie;
 	}
 
-	/* power up core phy and enable ref clock */
-	regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
-			IMX6Q_GPR1_PCIE_TEST_PD, 0 << 18);
-	/*
-	 * the async reset input need ref clock to sync internally,
-	 * when the ref clock comes after reset, internal synced
-	 * reset time is too short, cannot meet the requirement.
-	 * add one ~10us delay here.
-	 */
-	udelay(10);
-	regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
-			IMX6Q_GPR1_PCIE_REF_CLK_EN, 1 << 16);
+	ret = imx6_pcie_enable_ref_clk(imx6_pcie);
+	if (ret) {
+		dev_err(pp->dev, "unable to enable pcie ref clock\n");
+		goto err_ref_clk;
+	}
 
 	/* allow the clocks to stabilize */
 	usleep_range(200, 500);

@@ -311,6 +321,8 @@ static int imx6_pcie_deassert_core_reset(struct pcie_port *pp)
 	}
 	return 0;
 
+err_ref_clk:
+	clk_disable_unprepare(imx6_pcie->pcie);
 err_pcie:
 	clk_disable_unprepare(imx6_pcie->pcie_bus);
 err_pcie_bus:
Signature · 7 lines
2.1.4


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author
#9 lore raw

PATCH v4 1/1 PCI: imx6: Add initial imx6sx support

In reply to Christoph Fritz

Add initial PCIe support for the imx6 SoC derivate imx6sx. PCI MSI support is untested as the necessary suspend/resume quirk is not included in this patch.

This patch is heavily based on patches by Richard Zhu.

[bhelgaas: factor out refclk enable, fix adjacent typos in imx6q-pcie.txt]
Signed-off-by Christoph Fritz <[email protected]>
Acked-by Richard Zhu <[email protected]>
Acked-by Lucas Stach <[email protected]>
---
 .../devicetree/bindings/pci/fsl,imx6q-pcie.txt     |  8 +++-
 drivers/pci/host/pci-imx6.c                        | 53 ++++++++++++++++++++++
 2 files changed, 59 insertions(+), 2 deletions(-)
Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt +6 -2
index 6fbba53..6ee4439 100644
@@ -4,8 +4,8 @@ This PCIe host controller is based on the Synopsis Designware PCIe IP
 and thus inherits all the common properties defined in designware-pcie.txt.
 
 Required properties:
-- compatible: "fsl,imx6q-pcie"
-- reg: base addresse and length of the pcie controller
+- compatible: "fsl,imx6q-pcie", "fsl,imx6sx-pcie"
+- reg: base address and length of the PCIe controller
 - interrupts: A list of interrupt outputs of the controller. Must contain an
   entry for each entry in the interrupt-names property.
 - interrupt-names: Must include the following entries:

@@ -13,6 +13,10 @@ Required properties:
 - clock-names: Must include the following additional entries:
 	- "pcie_phy"
 
+Additional required properties for imx6sx-pcie:
+- clock names: Must include the following additional entries:
+	- "pcie_inbound_axi"
+
 Example:
 
 	pcie at 0x01000000 {
drivers/pci/host/pci-imx6.c +53 -0

104 lines not on this page · raw message

Signature · 1 line
2.1.4
author
#10 lore raw

PATCH v4 1/1 PCI: imx6: Add initial imx6sx support

*ping*

Quoted 157 lines · Christoph Fritz

Add initial PCIe support for the imx6 SoC derivate imx6sx. PCI MSI support is untested as the necessary suspend/resume quirk is not included in this patch.

This patch is heavily based on patches by Richard Zhu.

[bhelgaas: factor out refclk enable, fix adjacent typos in imx6q-pcie.txt]
Signed-off-by Christoph Fritz <[email protected]>
Acked-by Richard Zhu <[email protected]>
Acked-by Lucas Stach <[email protected]>
---
 .../devicetree/bindings/pci/fsl,imx6q-pcie.txt     |  8 +++-
 drivers/pci/host/pci-imx6.c                        | 53 ++++++++++++++++++++++
 2 files changed, 59 insertions(+), 2 deletions(-)
Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt +6 -2
index 6fbba53..6ee4439 100644
@@ -4,8 +4,8 @@ This PCIe host controller is based on the Synopsis Designware PCIe IP
 and thus inherits all the common properties defined in designware-pcie.txt.
 
 Required properties:
-- compatible: "fsl,imx6q-pcie"
-- reg: base addresse and length of the pcie controller
+- compatible: "fsl,imx6q-pcie", "fsl,imx6sx-pcie"
+- reg: base address and length of the PCIe controller
 - interrupts: A list of interrupt outputs of the controller. Must contain an
   entry for each entry in the interrupt-names property.
 - interrupt-names: Must include the following entries:

@@ -13,6 +13,10 @@ Required properties:
 - clock-names: Must include the following additional entries:
 	- "pcie_phy"
 
+Additional required properties for imx6sx-pcie:
+- clock names: Must include the following additional entries:
+	- "pcie_inbound_axi"
+
 Example:
 
 	pcie at 0x01000000 {
drivers/pci/host/pci-imx6.c +53 -0
index 4e0e47f..fa3a544 100644
@@ -35,9 +35,11 @@ struct imx6_pcie {
 	struct gpio_desc	*reset_gpio;
 	struct clk		*pcie_bus;
 	struct clk		*pcie_phy;
+	struct clk		*pcie_inbound_axi;
 	struct clk		*pcie;
 	struct pcie_port	pp;
 	struct regmap		*iomuxc_gpr;
+	bool			is_imx6sx;
 	void __iomem		*mem_base;
 };
 

@@ -231,6 +233,17 @@ static int imx6_pcie_assert_core_reset(struct pcie_port *pp)
 	struct imx6_pcie *imx6_pcie = to_imx6_pcie(pp);
 	u32 val, gpr1, gpr12;
 
+	if (imx6_pcie->is_imx6sx) {
+		regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
+				   IMX6SX_GPR12_PCIE_TEST_POWERDOWN,
+				   IMX6SX_GPR12_PCIE_TEST_POWERDOWN);
+		/* Force PCIe PHY reset */
+		regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR5,
+				   IMX6SX_GPR5_PCIE_BTNRST_RESET,
+				   IMX6SX_GPR5_PCIE_BTNRST_RESET);
+		return 0;
+	}
+
 	/*
 	 * If the bootloader already enabled the link we need some special
 	 * handling to get the core back into a state where it is safe to

@@ -266,6 +279,21 @@ static int imx6_pcie_assert_core_reset(struct pcie_port *pp)
 
 static int imx6_pcie_enable_ref_clk(struct imx6_pcie *imx6_pcie)
 {
+	struct pcie_port *pp = &imx6_pcie->pp;
+	int ret;
+
+	if (imx6_pcie->is_imx6sx) {
+		ret = clk_prepare_enable(imx6_pcie->pcie_inbound_axi);
+		if (ret) {
+			dev_err(pp->dev, "unable to enable pcie_axi clock\n");
+			return ret;
+		}
+
+		regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
+				   IMX6SX_GPR12_PCIE_TEST_POWERDOWN, 0);
+		return ret;
+	}
+
 	/* power up core phy and enable ref clock */
 	regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
 			IMX6Q_GPR1_PCIE_TEST_PD, 0 << 18);

@@ -319,6 +347,11 @@ static int imx6_pcie_deassert_core_reset(struct pcie_port *pp)
 		msleep(100);
 		gpiod_set_value_cansleep(imx6_pcie->reset_gpio, 1);
 	}
+
+	if (imx6_pcie->is_imx6sx)
+		regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR5,
+				   IMX6SX_GPR5_PCIE_BTNRST_RESET, 0);
+
 	return 0;
 
 err_ref_clk:

@@ -336,6 +369,12 @@ static void imx6_pcie_init_phy(struct pcie_port *pp)
 {
 	struct imx6_pcie *imx6_pcie = to_imx6_pcie(pp);
 
+	if (imx6_pcie->is_imx6sx) {
+		regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
+				   IMX6SX_GPR12_PCIE_RX_EQ_MASK,
+				   IMX6SX_GPR12_PCIE_RX_EQ_2);
+	}
+
 	regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
 			IMX6Q_GPR12_PCIE_CTL_2, 0 << 10);
 

@@ -554,6 +593,9 @@ static int __init imx6_pcie_probe(struct platform_device *pdev)
 	pp = &imx6_pcie->pp;
 	pp->dev = &pdev->dev;
 
+	imx6_pcie->is_imx6sx = of_device_is_compatible(pp->dev->of_node,
+						       "fsl,imx6sx-pcie");
+
 	/* Added for PCI abort handling */
 	hook_fault_code(16 + 6, imx6q_pcie_abort_handler, SIGBUS, 0,
 		"imprecise external abort");

@@ -589,6 +631,16 @@ static int __init imx6_pcie_probe(struct platform_device *pdev)
 		return PTR_ERR(imx6_pcie->pcie);
 	}
 
+	if (imx6_pcie->is_imx6sx) {
+		imx6_pcie->pcie_inbound_axi = devm_clk_get(&pdev->dev,
+							   "pcie_inbound_axi");
+		if (IS_ERR(imx6_pcie->pcie_inbound_axi)) {
+			dev_err(&pdev->dev,
+				"pcie_incbound_axi clock missing or invalid\n");
+			return PTR_ERR(imx6_pcie->pcie_inbound_axi);
+		}
+	}
+
 	/* Grab GPR config register range */
 	imx6_pcie->iomuxc_gpr =
 		 syscon_regmap_lookup_by_compatible("fsl,imx6q-iomuxc-gpr");

@@ -615,6 +667,7 @@ static void imx6_pcie_shutdown(struct platform_device *pdev)
 
 static const struct of_device_id imx6_pcie_of_match[] = {
 	{ .compatible = "fsl,imx6q-pcie", },
+	{ .compatible = "fsl,imx6sx-pcie", },
 	{},
 };
 MODULE_DEVICE_TABLE(of, imx6_pcie_of_match);
Applied
#11 lore raw

PATCH v4 1/1 PCI: imx6: Add initial imx6sx support

In reply to Christoph Fritz
Quoted 10 lines · Christoph Fritz

Add initial PCIe support for the imx6 SoC derivate imx6sx. PCI MSI support is untested as the necessary suspend/resume quirk is not included in this patch.

This patch is heavily based on patches by Richard Zhu.

[bhelgaas: factor out refclk enable, fix adjacent typos in imx6q-pcie.txt]
Signed-off-by Christoph Fritz <[email protected]>
Acked-by Richard Zhu <[email protected]>
Acked-by Lucas Stach <[email protected]>

Applied to pci/host-imx6 for v4.7, thanks!

Quoted 155 lines
---
 .../devicetree/bindings/pci/fsl,imx6q-pcie.txt     |  8 +++-
 drivers/pci/host/pci-imx6.c                        | 53 ++++++++++++++++++++++
 2 files changed, 59 insertions(+), 2 deletions(-)
Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt +6 -2
index 6fbba53..6ee4439 100644
@@ -4,8 +4,8 @@ This PCIe host controller is based on the Synopsis Designware PCIe IP
 and thus inherits all the common properties defined in designware-pcie.txt.
 
 Required properties:
-- compatible: "fsl,imx6q-pcie"
-- reg: base addresse and length of the pcie controller
+- compatible: "fsl,imx6q-pcie", "fsl,imx6sx-pcie"
+- reg: base address and length of the PCIe controller
 - interrupts: A list of interrupt outputs of the controller. Must contain an
   entry for each entry in the interrupt-names property.
 - interrupt-names: Must include the following entries:

@@ -13,6 +13,10 @@ Required properties:
 - clock-names: Must include the following additional entries:
 	- "pcie_phy"
 
+Additional required properties for imx6sx-pcie:
+- clock names: Must include the following additional entries:
+	- "pcie_inbound_axi"
+
 Example:
 
 	pcie at 0x01000000 {
drivers/pci/host/pci-imx6.c +53 -0
index 4e0e47f..fa3a544 100644
@@ -35,9 +35,11 @@ struct imx6_pcie {
 	struct gpio_desc	*reset_gpio;
 	struct clk		*pcie_bus;
 	struct clk		*pcie_phy;
+	struct clk		*pcie_inbound_axi;
 	struct clk		*pcie;
 	struct pcie_port	pp;
 	struct regmap		*iomuxc_gpr;
+	bool			is_imx6sx;
 	void __iomem		*mem_base;
 };
 

@@ -231,6 +233,17 @@ static int imx6_pcie_assert_core_reset(struct pcie_port *pp)
 	struct imx6_pcie *imx6_pcie = to_imx6_pcie(pp);
 	u32 val, gpr1, gpr12;
 
+	if (imx6_pcie->is_imx6sx) {
+		regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
+				   IMX6SX_GPR12_PCIE_TEST_POWERDOWN,
+				   IMX6SX_GPR12_PCIE_TEST_POWERDOWN);
+		/* Force PCIe PHY reset */
+		regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR5,
+				   IMX6SX_GPR5_PCIE_BTNRST_RESET,
+				   IMX6SX_GPR5_PCIE_BTNRST_RESET);
+		return 0;
+	}
+
 	/*
 	 * If the bootloader already enabled the link we need some special
 	 * handling to get the core back into a state where it is safe to

@@ -266,6 +279,21 @@ static int imx6_pcie_assert_core_reset(struct pcie_port *pp)
 
 static int imx6_pcie_enable_ref_clk(struct imx6_pcie *imx6_pcie)
 {
+	struct pcie_port *pp = &imx6_pcie->pp;
+	int ret;
+
+	if (imx6_pcie->is_imx6sx) {
+		ret = clk_prepare_enable(imx6_pcie->pcie_inbound_axi);
+		if (ret) {
+			dev_err(pp->dev, "unable to enable pcie_axi clock\n");
+			return ret;
+		}
+
+		regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
+				   IMX6SX_GPR12_PCIE_TEST_POWERDOWN, 0);
+		return ret;
+	}
+
 	/* power up core phy and enable ref clock */
 	regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
 			IMX6Q_GPR1_PCIE_TEST_PD, 0 << 18);

@@ -319,6 +347,11 @@ static int imx6_pcie_deassert_core_reset(struct pcie_port *pp)
 		msleep(100);
 		gpiod_set_value_cansleep(imx6_pcie->reset_gpio, 1);
 	}
+
+	if (imx6_pcie->is_imx6sx)
+		regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR5,
+				   IMX6SX_GPR5_PCIE_BTNRST_RESET, 0);
+
 	return 0;
 
 err_ref_clk:

@@ -336,6 +369,12 @@ static void imx6_pcie_init_phy(struct pcie_port *pp)
 {
 	struct imx6_pcie *imx6_pcie = to_imx6_pcie(pp);
 
+	if (imx6_pcie->is_imx6sx) {
+		regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
+				   IMX6SX_GPR12_PCIE_RX_EQ_MASK,
+				   IMX6SX_GPR12_PCIE_RX_EQ_2);
+	}
+
 	regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
 			IMX6Q_GPR12_PCIE_CTL_2, 0 << 10);
 

@@ -554,6 +593,9 @@ static int __init imx6_pcie_probe(struct platform_device *pdev)
 	pp = &imx6_pcie->pp;
 	pp->dev = &pdev->dev;
 
+	imx6_pcie->is_imx6sx = of_device_is_compatible(pp->dev->of_node,
+						       "fsl,imx6sx-pcie");
+
 	/* Added for PCI abort handling */
 	hook_fault_code(16 + 6, imx6q_pcie_abort_handler, SIGBUS, 0,
 		"imprecise external abort");

@@ -589,6 +631,16 @@ static int __init imx6_pcie_probe(struct platform_device *pdev)
 		return PTR_ERR(imx6_pcie->pcie);
 	}
 
+	if (imx6_pcie->is_imx6sx) {
+		imx6_pcie->pcie_inbound_axi = devm_clk_get(&pdev->dev,
+							   "pcie_inbound_axi");
+		if (IS_ERR(imx6_pcie->pcie_inbound_axi)) {
+			dev_err(&pdev->dev,
+				"pcie_incbound_axi clock missing or invalid\n");
+			return PTR_ERR(imx6_pcie->pcie_inbound_axi);
+		}
+	}
+
 	/* Grab GPR config register range */
 	imx6_pcie->iomuxc_gpr =
 		 syscon_regmap_lookup_by_compatible("fsl,imx6q-iomuxc-gpr");

@@ -615,6 +667,7 @@ static void imx6_pcie_shutdown(struct platform_device *pdev)
 
 static const struct of_device_id imx6_pcie_of_match[] = {
 	{ .compatible = "fsl,imx6q-pcie", },
+	{ .compatible = "fsl,imx6sx-pcie", },
 	{},
 };
 MODULE_DEVICE_TABLE(of, imx6_pcie_of_match);
Signature · 7 lines
2.1.4


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author
#12 lore raw

v3 cover Add PCIe driver support for imx6sx

In reply to Christoph Fritz

*ping*

Quoted 16 lines · Christoph Fritz

v3:
* adapt devicetree bindings documentation fsl,imx6q-pcie.txt
v2:
* leave out regulator handling from driver, will be done later in PM subsystem
* use BIT() macro for MFD

Christoph Fritz (2):
MFD: imx6sx: Add PCIe register definitions for iomuxc gpr
PCI: imx6: add initial imx6sx support

 .../devicetree/bindings/pci/fsl,imx6q-pcie.txt     |   6 +-
 drivers/pci/host/pci-imx6.c                        | 130 ++++++++++++++-------
 include/linux/mfd/syscon/imx6q-iomuxc-gpr.h        |   5 +
 3 files changed, 101 insertions(+), 40 deletions(-)
#13 lore raw

v3 cover Add PCIe driver support for imx6sx

Quoted 8 lines

-----Original Message-----
From: Christoph Fritz [mailto:chf.fritz at googlemail.com]
Sent: Thursday, March 03, 2016 9:41 AM
To: Richard Zhu; Shawn Guo; Lucas Stach
Cc: Fabio Estevam; Bjorn Helgaas; Lee Jones; linux-pci at vger.kernel.org; linux- arm-kernel at lists.infradead.org
Subject: Re: [PATCH v3 0/2] Add PCIe driver support for imx6sx

Quoted 21 lines

*ping*

Quoted 16 lines · Christoph Fritz

v3:
* adapt devicetree bindings documentation fsl,imx6q-pcie.txt
v2:
* leave out regulator handling from driver, will be done later in PM subsystem
* use BIT() macro for MFD

Christoph Fritz (2):
MFD: imx6sx: Add PCIe register definitions for iomuxc gpr
PCI: imx6: add initial imx6sx support

 .../devicetree/bindings/pci/fsl,imx6q-pcie.txt     |   6 +-
 drivers/pci/host/pci-imx6.c                        | 130 ++++++++++++++-------
 include/linux/mfd/syscon/imx6q-iomuxc-gpr.h        |   5 +
 3 files changed, 101 insertions(+), 40 deletions(-)

[Zhu hongxing] Hi Christoph:
I'm okay with this patch-set. Hope the regulator handing patch mandatory required by imx6sx pcie is merged in PM system asap. :).
Thanks.
Richard

#14 lore raw

v3 cover Add PCIe driver support for imx6sx

In reply to Christoph Fritz
Quoted 19 lines

-----Original Message-----
From: Christoph Fritz [mailto:chf.fritz at googlemail.com]
Sent: Thursday, February 25, 2016 10:48 PM
To: Richard Zhu; Lucas Stach; Shawn Guo; Fabio Estevam; Bjorn Helgaas; Lee Jones
Cc: linux-pci at vger.kernel.org; linux-arm-kernel at lists.infradead.org
Subject: [PATCH v3 0/2] Add PCIe driver support for imx6sx

v3:
* adapt devicetree bindings documentation fsl,imx6q-pcie.txt
v2:
* leave out regulator handling from driver, will be done later in PM subsystem
* use BIT() macro for MFD

Christoph Fritz (2):
MFD: imx6sx: Add PCIe register definitions for iomuxc gpr
PCI: imx6: add initial imx6sx support

Quoted 7 lines
 .../devicetree/bindings/pci/fsl,imx6q-pcie.txt     |   6 +-
 drivers/pci/host/pci-imx6.c                        | 130 ++++++++++++++-------
 include/linux/mfd/syscon/imx6q-iomuxc-gpr.h        |   5 +
 3 files changed, 101 insertions(+), 40 deletions(-)

--
2.1.4

[Zhu hongxing] Acked-by: Richard Zhu <[email protected]> Richard
Best Regards

author
#15 lore raw

v3 cover Add PCIe driver support for imx6sx

Quoted 24 lines · Richard Zhu
Quoted 24 lines

-----Original Message-----
From: Christoph Fritz [mailto:chf.fritz at googlemail.com]
Sent: Thursday, February 25, 2016 10:48 PM
To: Richard Zhu; Lucas Stach; Shawn Guo; Fabio Estevam; Bjorn Helgaas; Lee Jones
Cc: linux-pci at vger.kernel.org; linux-arm-kernel at lists.infradead.org
Subject: [PATCH v3 0/2] Add PCIe driver support for imx6sx

v3:
* adapt devicetree bindings documentation fsl,imx6q-pcie.txt
v2:
* leave out regulator handling from driver, will be done later in PM subsystem
* use BIT() macro for MFD

Christoph Fritz (2):
MFD: imx6sx: Add PCIe register definitions for iomuxc gpr
PCI: imx6: add initial imx6sx support

 .../devicetree/bindings/pci/fsl,imx6q-pcie.txt     |   6 +-
 drivers/pci/host/pci-imx6.c                        | 130 ++++++++++++++-------
 include/linux/mfd/syscon/imx6q-iomuxc-gpr.h        |   5 +
 3 files changed, 101 insertions(+), 40 deletions(-)
Quoted 6 lines
Quoted 2 lines

--
2.1.4

[Zhu hongxing] Acked-by: Richard Zhu <[email protected]> Richard
Best Regards

@Bjorn: I suppose the PCI patch need to go through your tree. Would you pick up this patch?

@Lee: What about the MFD patch, does this need to go through your tree?

Thanks
-- Christoph

author
#16 lore raw

v3 cover Add PCIe driver support for imx6sx

Quoted 28 lines · Christoph Fritz
Quoted 27 lines · Richard Zhu
Quoted 26 lines

-----Original Message-----
From: Christoph Fritz [mailto:chf.fritz at googlemail.com]
Sent: Thursday, February 25, 2016 10:48 PM
To: Richard Zhu; Lucas Stach; Shawn Guo; Fabio Estevam; Bjorn Helgaas; Lee Jones
Cc: linux-pci at vger.kernel.org; linux-arm-kernel at lists.infradead.org
Subject: [PATCH v3 0/2] Add PCIe driver support for imx6sx

v3:
* adapt devicetree bindings documentation fsl,imx6q-pcie.txt
v2:
* leave out regulator handling from driver, will be done later in PM subsystem
* use BIT() macro for MFD

Christoph Fritz (2):
MFD: imx6sx: Add PCIe register definitions for iomuxc gpr
PCI: imx6: add initial imx6sx support

 .../devicetree/bindings/pci/fsl,imx6q-pcie.txt     |   6 +-
 drivers/pci/host/pci-imx6.c                        | 130 ++++++++++++++-------
 include/linux/mfd/syscon/imx6q-iomuxc-gpr.h        |   5 +
 3 files changed, 101 insertions(+), 40 deletions(-)

--
2.1.4

Quoted 6 lines
Quoted 3 lines

[Zhu hongxing] Acked-by: Richard Zhu <[email protected]> Richard
Best Regards

@Bjorn: I suppose the PCI patch need to go through your tree. Would you pick up this patch?

*ping*
Do you want me to rebase my patch to your pci/host-imx6 branch?

Thanks
-- Christoph

#17 lore raw

v3 cover Add PCIe driver support for imx6sx

Am Mittwoch, den 09.03.2016, 16:39 +0100 schrieb Christoph Fritz:

Quoted 33 lines · Christoph Fritz
Quoted 32 lines · Richard Zhu
Quoted 30 lines
Quoted 19 lines

-----Original Message-----
From: Christoph Fritz [mailto:chf.fritz at googlemail.com]
Sent: Thursday, February 25, 2016 10:48 PM
To: Richard Zhu; Lucas Stach; Shawn Guo; Fabio Estevam; Bjorn Helgaas; Lee Jones
Cc: linux-pci at vger.kernel.org; linux-arm-kernel at lists.infradead.org
Subject: [PATCH v3 0/2] Add PCIe driver support for imx6sx

v3:
* adapt devicetree bindings documentation fsl,imx6q-pcie.txt
v2:
* leave out regulator handling from driver, will be done later in PM subsystem
* use BIT() macro for MFD

Christoph Fritz (2):
MFD: imx6sx: Add PCIe register definitions for iomuxc gpr
PCI: imx6: add initial imx6sx support

Quoted 7 lines
 .../devicetree/bindings/pci/fsl,imx6q-pcie.txt     |   6 +-
 drivers/pci/host/pci-imx6.c                        | 130 ++++++++++++++-------
 include/linux/mfd/syscon/imx6q-iomuxc-gpr.h        |   5 +
 3 files changed, 101 insertions(+), 40 deletions(-)

--
2.1.4

[Zhu hongxing] Acked-by: Richard Zhu <[email protected]> Richard
Best Regards

Quoted 6 lines
Quoted 2 lines

@Bjorn: I suppose the PCI patch need to go through your tree. Would you pick up this patch?

*ping*
Do you want me to rebase my patch to your pci/host-imx6 branch?

I was unsure if we are going to break DT stability at a later point if we pull this series in without the GPC changes. But after thinking a bit more about this it should be fine.

So series is:

Acked-by Lucas Stach <[email protected]>