i.MX6 LPDDR2 fixes

PATCH New Tom Rini 4 participants 11 messages Apr 1, 2016 – Apr 6, 2016 Arm i.MX and Layerscape

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Tom Rini

author

2016-04-01 21:54 UTC #0 lore raw

cover i.MX6 LPDDR2 fixes

Hey all,

The following two patches fix JEDEC violations that were observed when I was working on a board similar to the MX6SL EVK. Based on talking with Micron and reading up on what the code here is (and isn't) doing, I'm certain these issues exist on the reference platforms here. I'm publishing these for correctness. I'm also not updating the the SPL code as I haven't tested that (and only could for EVK anyhow) but would suggest it's worth a follow-up from tha maintainers.

Signature · 1 line

Tom

Tom Rini

author

2016-04-01 21:54 UTC #1 lore raw

PATCH 1/2 mx6qarm2: imximage_mx6dl.cfg update to fix tINIT3 violation

Cc Jason Liu <[email protected]>

Cc Ye Li <[email protected]>

Signed-off-by Tom Rini <[email protected]>

---
 board/freescale/mx6qarm2/imximage_mx6dl.cfg |    4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

board/freescale/mx6qarm2/imximage_mx6dl.cfg +2 -2

index ae8dcc6..1f5a0a5 100644
@@ -234,7 +234,7 @@ DATA 4 0x021b0018 0x0000174C
 /* MMDC0_MDRWD;*/
 DATA 4 0x021b002c 0x0f9f26d2
 /* MMDC0_MDOR */
-DATA 4 0x021b0030 0x0000020e
+DATA 4 0x021b0030 0x009f0e10
 /* MMDC0_MDCFG3LP */
 DATA 4 0x021b0038 0x00190778
 /* MMDC0_MDOTC */

@@ -263,7 +263,7 @@ DATA 4 0x021b4018 0x0000174C
 /* MMDC1_MDRWD;*/
 DATA 4 0x021b402c 0x0f9f26d2
 /* MMDC1_MDOR */
-DATA 4 0x021b4030 0x0000020e
+DATA 4 0x021b4030 0x009f0e10
 /* MMDC1_MDCFG3LP */
 DATA 4 0x021b4038 0x00190778
 /* MMDC1_MDOTC */

Signature · 1 line

1.7.9.5

Stefano Babic

2016-04-03 17:22 UTC #2 lore raw

PATCH 1/2 mx6qarm2: imximage_mx6dl.cfg update to fix tINIT3 violation

Quoted 27 lines · Tom Rini

Having had a similar board and memory part under logic analyzer, a tINIT3 violation was measured. The fix was involved keeping tXPR and SDE_to_RST at the power-on defaults and setting RST_to_CKE the JEDEC value for LPDDR2.
Cc Jason Liu <[email protected]>
Cc Ye Li <[email protected]>
Signed-off-by Tom Rini <[email protected]>
---
 board/freescale/mx6qarm2/imximage_mx6dl.cfg |    4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)
board/freescale/mx6qarm2/imximage_mx6dl.cfg +1 -1
index ae8dcc6..1f5a0a5 100644
@@ -234,7 +234,7 @@ DATA 4 0x021b0018 0x0000174C
 /* MMDC0_MDRWD;*/
 DATA 4 0x021b002c 0x0f9f26d2
 /* MMDC0_MDOR */
-DATA 4 0x021b0030 0x0000020e
+DATA 4 0x021b0030 0x009f0e10
 /* MMDC0_MDCFG3LP */
 DATA 4 0x021b0038 0x00190778
 /* MMDC0_MDOTC */

board/freescale/mx6qarm2/imximage_mx6dl.cfg DATA 4 0x021b4018 0x0000174C · line 269

Quoted 8 lines

board/freescale/mx6qarm2/imximage_mx6dl.cfg +1 -1

@@ -263,7 +263,7 @@ DATA 4 0x021b4018 0x0000174C
 /* MMDC1_MDRWD;*/
 DATA 4 0x021b402c 0x0f9f26d2
 /* MMDC1_MDOR */
-DATA 4 0x021b4030 0x0000020e
+DATA 4 0x021b4030 0x009f0e10
 /* MMDC1_MDCFG3LP */
 DATA 4 0x021b4038 0x00190778
 /* MMDC1_MDOTC */

Applied to u-boot-imx, thanks !

Best regards,
Stefano Babic

Signature · 5 lines

=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

Tom Rini

author

2016-04-01 21:54 UTC #3 lore raw

PATCH 2/2 mx6slevk: imximage.cfg: update to fix tINIT3 and tIH-CA violations

In reply to Tom Rini

Having had a similar board and memory part under logic analyzer, a tINIT3 violation was measured. The fix was involved keeping tXPR and SDE_to_RST at the power-on defaults and setting RST_to_CKE the JEDEC value for LPDDR2. There was also a tIH-CA violation and this was resolved by writing the default value in rather than what the script here uses.

Cc Fabio Estevam <[email protected]>

Cc Peng Fan <[email protected]>

Signed-off-by Tom Rini <[email protected]>

---
 board/freescale/mx6slevk/imximage.cfg |    4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

board/freescale/mx6slevk/imximage.cfg +2 -2

index 16ea597..c77bbde 100644
@@ -70,7 +70,7 @@ DATA 4 0x020e05d0 0x00080000
 DATA 4 0x021b001c 0x00008000
 DATA 4 0x021b085c 0x1b4700c7
 DATA 4 0x021b0800 0xa1390003
-DATA 4 0x021b0890 0x00300000
+DATA 4 0x021b0890 0x00400000
 DATA 4 0x021b08b8 0x00000800
 DATA 4 0x021b081c 0x33333333
 DATA 4 0x021b0820 0x33333333

@@ -92,7 +92,7 @@ DATA 4 0x021b0010 0x00100A82
 DATA 4 0x021b0014 0x00000093
 DATA 4 0x021b0018 0x00001688
 DATA 4 0x021b002c 0x0f9f26d2
-DATA 4 0x021b0030 0x0000020e
+DATA 4 0x021b0030 0x009f0e10
 DATA 4 0x021b0038 0x00190778
 DATA 4 0x021b0008 0x00000000
 DATA 4 0x021b0040 0x0000004f

Signature · 1 line

1.7.9.5

Fabio Estevam

reviewer

2016-04-01 23:58 UTC #4 lore raw

PATCH 2/2 mx6slevk: imximage.cfg: update to fix tINIT3 and tIH-CA violations

Quoted 10 lines · Tom Rini

Having had a similar board and memory part under logic analyzer, a tINIT3 violation was measured. The fix was involved keeping tXPR and SDE_to_RST at the power-on defaults and setting RST_to_CKE the JEDEC value for LPDDR2. There was also a tIH-CA violation and this was resolved by writing the default value in rather than what the script here uses.
Cc Fabio Estevam <[email protected]>
Cc Peng Fan <[email protected]>
Signed-off-by Tom Rini <[email protected]>

Good fix!

Reviewed-by Fabio Estevam <[email protected]>

Stefano Babic

2016-04-03 17:22 UTC #5 lore raw

PATCH 2/2 mx6slevk: imximage.cfg: update to fix tINIT3 and tIH-CA violations

In reply to Tom Rini

Quoted 29 lines · Tom Rini

Having had a similar board and memory part under logic analyzer, a tINIT3 violation was measured. The fix was involved keeping tXPR and SDE_to_RST at the power-on defaults and setting RST_to_CKE the JEDEC value for LPDDR2. There was also a tIH-CA violation and this was resolved by writing the default value in rather than what the script here uses.
Cc Fabio Estevam <[email protected]>
Cc Peng Fan <[email protected]>
Signed-off-by Tom Rini <[email protected]>
---
 board/freescale/mx6slevk/imximage.cfg |    4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)
board/freescale/mx6slevk/imximage.cfg +1 -1
index 16ea597..c77bbde 100644
@@ -70,7 +70,7 @@ DATA 4 0x020e05d0 0x00080000
 DATA 4 0x021b001c 0x00008000
 DATA 4 0x021b085c 0x1b4700c7
 DATA 4 0x021b0800 0xa1390003
-DATA 4 0x021b0890 0x00300000
+DATA 4 0x021b0890 0x00400000
 DATA 4 0x021b08b8 0x00000800
 DATA 4 0x021b081c 0x33333333
 DATA 4 0x021b0820 0x33333333

board/freescale/mx6slevk/imximage.cfg DATA 4 0x021b0010 0x00100A82 · line 98

Quoted 8 lines

board/freescale/mx6slevk/imximage.cfg +1 -1

@@ -92,7 +92,7 @@ DATA 4 0x021b0010 0x00100A82
 DATA 4 0x021b0014 0x00000093
 DATA 4 0x021b0018 0x00001688
 DATA 4 0x021b002c 0x0f9f26d2
-DATA 4 0x021b0030 0x0000020e
+DATA 4 0x021b0030 0x009f0e10
 DATA 4 0x021b0038 0x00190778
 DATA 4 0x021b0008 0x00000000
 DATA 4 0x021b0040 0x0000004f

Applied to u-boot-imx, thanks !

Best regards,
Stefano Babic

Signature · 5 lines

=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

Tom Rini

author

2016-04-03 18:06 UTC #6 lore raw

PATCH 2/2 mx6slevk: imximage.cfg: update to fix tINIT3 and tIH-CA violations

Quoted 33 lines · Stefano Babic

Quoted 30 lines · Tom Rini
Having had a similar board and memory part under logic analyzer, a tINIT3 violation was measured. The fix was involved keeping tXPR and SDE_to_RST at the power-on defaults and setting RST_to_CKE the JEDEC value for LPDDR2. There was also a tIH-CA violation and this was resolved by writing the default value in rather than what the script here uses.
Cc Fabio Estevam <[email protected]>
Cc Peng Fan <[email protected]>
Signed-off-by Tom Rini <[email protected]>
---
 board/freescale/mx6slevk/imximage.cfg |    4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)
board/freescale/mx6slevk/imximage.cfg +1 -1
index 16ea597..c77bbde 100644
@@ -70,7 +70,7 @@ DATA 4 0x020e05d0 0x00080000
 DATA 4 0x021b001c 0x00008000
 DATA 4 0x021b085c 0x1b4700c7
 DATA 4 0x021b0800 0xa1390003
-DATA 4 0x021b0890 0x00300000
+DATA 4 0x021b0890 0x00400000
 DATA 4 0x021b08b8 0x00000800
 DATA 4 0x021b081c 0x33333333
 DATA 4 0x021b0820 0x33333333
@@ -92,7 +92,7 @@ DATA 4 0x021b0010 0x00100A82
 DATA 4 0x021b0014 0x00000093
 DATA 4 0x021b0018 0x00001688

Quoted 8 lines

board/freescale/mx6slevk/imximage.cfg DATA 4 0x021b0010 0x00100A82 · line 98
Quoted 6 lines
board/freescale/mx6slevk/imximage.cfg +1 -1
 DATA 4 0x021b002c 0x0f9f26d2
-DATA 4 0x021b0030 0x0000020e
+DATA 4 0x021b0030 0x009f0e10
 DATA 4 0x021b0038 0x00190778
 DATA 4 0x021b0008 0x00000000
 DATA 4 0x021b0040 0x0000004f
Applied to u-boot-imx, thanks !

OK. But per 0/2 the SPL versions are out of sync and someone should take care of that :)

Signature · 8 lines

Tom
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Peng Fan

2016-04-05 08:53 UTC #7 lore raw

PATCH 2/2 mx6slevk: imximage.cfg: update to fix tINIT3 and tIH-CA violations

Hi Tom,

I know this already merged to i.mx tree. I still have a question for the tIH-CA violation.

In my side, the value is ok. clk is 400MHz.
(0x30 * 256.0) * (1000000000000.0/400000000.0) = 468.75ps. And according to spec, to 800M date rate, the minimum tIH value is 290ps.

So I wonder how in your side it is tIH-CA violation.

Regards,
Peng.

Quoted 55 lines · Tom Rini

Quoted 33 lines · Stefano Babic
Quoted 30 lines · Tom Rini
Having had a similar board and memory part under logic analyzer, a tINIT3 violation was measured. The fix was involved keeping tXPR and SDE_to_RST at the power-on defaults and setting RST_to_CKE the JEDEC value for LPDDR2. There was also a tIH-CA violation and this was resolved by writing the default value in rather than what the script here uses.
Cc Fabio Estevam <[email protected]>
Cc Peng Fan <[email protected]>
Signed-off-by Tom Rini <[email protected]>
---
 board/freescale/mx6slevk/imximage.cfg |    4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)
board/freescale/mx6slevk/imximage.cfg +1 -1
index 16ea597..c77bbde 100644
@@ -70,7 +70,7 @@ DATA 4 0x020e05d0 0x00080000
 DATA 4 0x021b001c 0x00008000
 DATA 4 0x021b085c 0x1b4700c7
 DATA 4 0x021b0800 0xa1390003
-DATA 4 0x021b0890 0x00300000
+DATA 4 0x021b0890 0x00400000
 DATA 4 0x021b08b8 0x00000800
 DATA 4 0x021b081c 0x33333333
 DATA 4 0x021b0820 0x33333333
@@ -92,7 +92,7 @@ DATA 4 0x021b0010 0x00100A82
 DATA 4 0x021b0014 0x00000093
 DATA 4 0x021b0018 0x00001688
Quoted 8 lines
board/freescale/mx6slevk/imximage.cfg DATA 4 0x021b0010 0x00100A82 · line 98
Quoted 6 lines
board/freescale/mx6slevk/imximage.cfg +1 -1
 DATA 4 0x021b002c 0x0f9f26d2
-DATA 4 0x021b0030 0x0000020e
+DATA 4 0x021b0030 0x009f0e10
 DATA 4 0x021b0038 0x00190778
 DATA 4 0x021b0008 0x00000000
 DATA 4 0x021b0040 0x0000004f
Applied to u-boot-imx, thanks !
OK. But per 0/2 the SPL versions are out of sync and someone should take care of that :)
Signature · 8 lines
Tom



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U-Boot at lists.denx.de
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Tom Rini

author

2016-04-05 13:43 UTC #8 lore raw

PATCH 2/2 mx6slevk: imximage.cfg: update to fix tINIT3 and tIH-CA violations

Quoted 4 lines · Peng Fan

Hi Tom,
I know this already merged to i.mx tree. I still have a question for the tIH-CA violation.

It's not in mainline 'tho so it can always come out :)

Quoted 5 lines

In my side, the value is ok. clk is 400MHz.
(0x30 * 256.0) * (1000000000000.0/400000000.0) = 468.75ps. And according to spec, to 800M date rate, the minimum tIH value is 290ps.
So I wonder how in your side it is tIH-CA violation.

The board we measured this on is based on the mx6slevk and this particular part of the board (layout, etc) is unchanged. Micron put the board under analysis and measured these violations (along with that we don't issue a reset before configuring CS1, I still might try and push that change up for the EVK at least, not armadillo tho).

Signature · 8 lines

Tom
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Stefano Babic

2016-04-05 14:01 UTC #9 lore raw

PATCH 2/2 mx6slevk: imximage.cfg: update to fix tINIT3 and tIH-CA violations

Quoted 7 lines · Tom Rini

Quoted 4 lines · Peng Fan
Hi Tom,
I know this already merged to i.mx tree. I still have a question for the tIH-CA violation.
It's not in mainline 'tho so it can always come out :)

Right - it is still in u-boot-imx, and I can revert it before my PR.

Quoted 5 lines

Quoted 5 lines
In my side, the value is ok. clk is 400MHz.
(0x30 * 256.0) * (1000000000000.0/400000000.0) = 468.75ps. And according to spec, to 800M date rate, the minimum tIH value is 290ps.

Quoted 7 lines

Quoted 1 line
So I wonder how in your side it is tIH-CA violation.
The board we measured this on is based on the mx6slevk and this particular part of the board (layout, etc) is unchanged. Micron put the board under analysis and measured these violations (along with that we don't issue a reset before configuring CS1, I still might try and push that change up for the EVK at least, not armadillo tho).

Stefano

Signature · 5 lines

=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

Peng Fan

2016-04-06 04:45 UTC #10 lore raw

PATCH 2/2 mx6slevk: imximage.cfg: update to fix tINIT3 and tIH-CA violations

In reply to Tom Rini

Hi Tom,

Quoted 12 lines · Tom Rini

Quoted 4 lines · Peng Fan
Hi Tom,
I know this already merged to i.mx tree. I still have a question for the tIH-CA violation.
It's not in mainline 'tho so it can always come out :)
Quoted 4 lines
In my side, the value is ok. clk is 400MHz.
(0x30 * 256.0) * (1000000000000.0/400000000.0) = 468.75ps. And according to spec, to 800M date rate, the minimum tIH value is 290ps.

Quoted 7 lines

Quoted 1 line
So I wonder how in your side it is tIH-CA violation.
The board we measured this on is based on the mx6slevk and this particular part of the board (layout, etc) is unchanged. Micron put the board under analysis and measured these violations (along with that we don't issue a reset before configuring CS1, I still might try and push that change up for the EVK at least, not armadillo tho).

I have no way to measure the signals (:.
So just formula computing:
If setting the value to 0x40, then tIH is (0x40 / 256.0) * (1000000000000.0/400000000.0) = 625ps. If setting the value to 0x30, then tIH is (0x30 / 256.0) * (1000000000000.0/400000000.0) = 468.75ps.

Both value does not violate the LPDDR2 spec, bigger that 290ps which 800M date rate requires the minimum value.

I can not say which value is better. Anyway different board may have different value.

since you measured the signals, and value 0x30 is not good, I am ok with your change.

Regards,
Peng.

Quoted 3 lines

Signature · 2 lines
-- 
Tom