ARM: dts: fixes for DT warnings on OMAP2+ platforms
cover ARM: dts: fixes for DT warnings on OMAP2+ platforms
Hi,
This set fixes the clock node related warnings for OMAP2+ platforms that are going to be introduced with the new version of DTC that does stricter checks on DT structure. Basically, the address component is currently missing on the node names that have a reg properly, which is illegal.
Set applied on top of 4.6-rc2. Pushed branch here also:
tree: https://github.com/t-kristo/linux-pm.git
branch: 4.6-rc2-clk-dt-warn-fixes
Boot tested on following boards:
: Board : Boot WRN version 1: am335x-evm : PASS 0 4.6.0-rc2-00008-gadb720d 2: am335x-evmsk : PASS 0 4.6.0-rc2-00008-gadb720d 3: am3517-evm : PASS 1 4.6.0-rc2-00008-gadb720d 4: am37x-evm : PASS 0 4.6.0-rc2-00008-gadb720d 5: am437x-sk : PASS 0 4.6.0-rc2-00008-gadb720d 6: am43x-epos-evm : FAIL 0 4.6.0-rc2-00008-gadb720d 7: am437x-gp-evm : PASS 0 4.6.0-rc2-00008-gadb720d 8: am57xx-evm : PASS 0 4.6.0-rc2-00008-gadb720d 9: omap3-beagle-xm : PASS 0 4.6.0-rc2-00008-gadb720d 10: omap3-beagle : PASS 0 4.6.0-rc2-00008-gadb720d 11: am335x-boneblack: PASS 0 4.6.0-rc2-00008-gadb720d 12: am335x-bone : PASS 0 4.6.0-rc2-00008-gadb720d 13: craneboard : PASS 1 4.6.0-rc2-00008-gadb720d 14: dra72x-evm : PASS 0 4.6.0-rc2-00008-gadb720d 15: dra7xx-evm : PASS 0 4.6.0-rc2-00008-gadb720d 16: ldp3430 : PASS 0 4.6.0-rc2-00008-gadb720d 17: omap3-n900 : FAIL 0 18: omap5-uevm : FAIL 0 19: omap4-panda-es : PASS 0 4.6.0-rc2-00008-gadb720d 20: omap4-panda : PASS 0 4.6.0-rc2-00008-gadb720d 21: omap2430-sdp : PASS 0 4.6.0-rc2-00008-gadb720d 22: omap3430-sdp : PASS 0 4.6.0-rc2-00008-gadb720d
23: omap4-sdp-es23plus: PASS 0 4.6.0-rc2-00008-gadb720d
TOTAL = 23 boards, Booted Boards = 20, No Boot boards = 3
The boot failures detected are caused by board defects on the test farm I am using, except for the am43xx-epos, which is a known issue (syntimer fix still missing from -rc2.)
Also ran a quick suspend/resume test on omap3/omap4 and that seems to be working fine also.
-Tero
PATCH 1/8 ARM: dts: omap3: fix clock node definitions to avoid build warnings
Upcoming change to DT compiler is going to complain about nodes which have a reg property, but have not defined the address in their name. This patch fixes following type of warnings for OMAP3 clock nodes:
Warning (unit_address_vs_reg): Node /ocp/cm at 48004000/clocks/dpll3_m2_ck has a reg or ranges property, but no unit name
Signed-off-by Tero Kristo <[email protected]>
--- arch/arm/boot/dts/am35xx-clocks.dtsi | 20 +- arch/arm/boot/dts/omap3430es1-clocks.dtsi | 30 +-- arch/arm/boot/dts/omap34xx-omap36xx-clocks.dtsi | 44 ++-- .../omap36xx-am35xx-omap3430es2plus-clocks.dtsi | 32 +-- arch/arm/boot/dts/omap36xx-clocks.dtsi | 14 +- .../boot/dts/omap36xx-omap3430es2plus-clocks.dtsi | 14 +- arch/arm/boot/dts/omap3xxx-clocks.dtsi | 276 ++++++++++---------- 7 files changed, 215 insertions(+), 215 deletions(-)
arch/arm/boot/dts/am35xx-clocks.dtsi +10 -10
@@ -8,7 +8,7 @@ * published by the Free Software Foundation. */ &scm_clocks { - emac_ick: emac_ick { + emac_ick: emac_ick at 32c { #clock-cells = <0>; compatible = "ti,am35xx-gate-clock"; clocks = <&ipss_ick>;
@@ -16,7 +16,7 @@ ti,bit-shift = <1>; }; - emac_fck: emac_fck { + emac_fck: emac_fck at 32c { #clock-cells = <0>; compatible = "ti,gate-clock"; clocks = <&rmii_ck>;
@@ -24,7 +24,7 @@ ti,bit-shift = <9>; }; - vpfe_ick: vpfe_ick { + vpfe_ick: vpfe_ick at 32c { #clock-cells = <0>; compatible = "ti,am35xx-gate-clock"; clocks = <&ipss_ick>;
@@ -32,7 +32,7 @@ ti,bit-shift = <2>; }; - vpfe_fck: vpfe_fck { + vpfe_fck: vpfe_fck at 32c { #clock-cells = <0>; compatible = "ti,gate-clock"; clocks = <&pclk_ck>;
@@ -40,7 +40,7 @@ ti,bit-shift = <10>; }; - hsotgusb_ick_am35xx: hsotgusb_ick_am35xx { + hsotgusb_ick_am35xx: hsotgusb_ick_am35xx at 32c { #clock-cells = <0>; compatible = "ti,am35xx-gate-clock"; clocks = <&ipss_ick>;
@@ -48,7 +48,7 @@ ti,bit-shift = <0>; }; - hsotgusb_fck_am35xx: hsotgusb_fck_am35xx { + hsotgusb_fck_am35xx: hsotgusb_fck_am35xx at 32c { #clock-cells = <0>; compatible = "ti,gate-clock"; clocks = <&sys_ck>;
@@ -56,7 +56,7 @@ ti,bit-shift = <8>; }; - hecc_ck: hecc_ck { + hecc_ck: hecc_ck at 32c { #clock-cells = <0>; compatible = "ti,am35xx-gate-clock"; clocks = <&sys_ck>;
@@ -65,7 +65,7 @@ }; }; &cm_clocks { - ipss_ick: ipss_ick { + ipss_ick: ipss_ick at a10 { #clock-cells = <0>; compatible = "ti,am35xx-interface-clock"; clocks = <&core_l3_ick>;
@@ -85,7 +85,7 @@ clock-frequency = <27000000>; }; - uart4_ick_am35xx: uart4_ick_am35xx { + uart4_ick_am35xx: uart4_ick_am35xx at a10 { #clock-cells = <0>; compatible = "ti,omap3-interface-clock"; clocks = <&core_l4_ick>;
@@ -93,7 +93,7 @@ ti,bit-shift = <23>; }; - uart4_fck_am35xx: uart4_fck_am35xx { + uart4_fck_am35xx: uart4_fck_am35xx at a00 { #clock-cells = <0>; compatible = "ti,wait-gate-clock"; clocks = <&core_48m_fck>;
arch/arm/boot/dts/omap3430es1-clocks.dtsi +15 -15
@@ -8,7 +8,7 @@ * published by the Free Software Foundation. */ &cm_clocks { - gfx_l3_ck: gfx_l3_ck { + gfx_l3_ck: gfx_l3_ck at b10 { #clock-cells = <0>; compatible = "ti,wait-gate-clock"; clocks = <&l3_ick>;
@@ -16,7 +16,7 @@ ti,bit-shift = <0>; }; - gfx_l3_fck: gfx_l3_fck { + gfx_l3_fck: gfx_l3_fck at b40 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&l3_ick>;
@@ -33,7 +33,7 @@ clock-div = <1>; }; - gfx_cg1_ck: gfx_cg1_ck { + gfx_cg1_ck: gfx_cg1_ck at b00 { #clock-cells = <0>; compatible = "ti,wait-gate-clock"; clocks = <&gfx_l3_fck>;
@@ -41,7 +41,7 @@ ti,bit-shift = <1>; }; - gfx_cg2_ck: gfx_cg2_ck { + gfx_cg2_ck: gfx_cg2_ck at b00 { #clock-cells = <0>; compatible = "ti,wait-gate-clock"; clocks = <&gfx_l3_fck>;
@@ -49,7 +49,7 @@ ti,bit-shift = <2>; }; - d2d_26m_fck: d2d_26m_fck { + d2d_26m_fck: d2d_26m_fck at a00 { #clock-cells = <0>; compatible = "ti,wait-gate-clock"; clocks = <&sys_ck>;
@@ -57,7 +57,7 @@ ti,bit-shift = <3>; }; - fshostusb_fck: fshostusb_fck { + fshostusb_fck: fshostusb_fck at a00 { #clock-cells = <0>; compatible = "ti,wait-gate-clock"; clocks = <&core_48m_fck>;
@@ -65,7 +65,7 @@ ti,bit-shift = <5>; }; - ssi_ssr_gate_fck_3430es1: ssi_ssr_gate_fck_3430es1 { + ssi_ssr_gate_fck_3430es1: ssi_ssr_gate_fck_3430es1 at a00 { #clock-cells = <0>; compatible = "ti,composite-no-wait-gate-clock"; clocks = <&corex2_fck>;
@@ -73,7 +73,7 @@ reg = <0x0a00>; }; - ssi_ssr_div_fck_3430es1: ssi_ssr_div_fck_3430es1 { + ssi_ssr_div_fck_3430es1: ssi_ssr_div_fck_3430es1 at a40 { #clock-cells = <0>; compatible = "ti,composite-divider-clock"; clocks = <&corex2_fck>;
@@ -96,7 +96,7 @@ clock-div = <2>; }; - hsotgusb_ick_3430es1: hsotgusb_ick_3430es1 { + hsotgusb_ick_3430es1: hsotgusb_ick_3430es1 at a10 { #clock-cells = <0>; compatible = "ti,omap3-no-wait-interface-clock"; clocks = <&core_l3_ick>;
@@ -104,7 +104,7 @@ ti,bit-shift = <4>; }; - fac_ick: fac_ick { + fac_ick: fac_ick at a10 { #clock-cells = <0>; compatible = "ti,omap3-interface-clock"; clocks = <&core_l4_ick>;
@@ -120,7 +120,7 @@ clock-div = <1>; }; - ssi_ick: ssi_ick_3430es1 { + ssi_ick: ssi_ick_3430es1 at a10 { #clock-cells = <0>; compatible = "ti,omap3-no-wait-interface-clock"; clocks = <&ssi_l4_ick>;
@@ -128,7 +128,7 @@ ti,bit-shift = <0>; }; - usb_l4_gate_ick: usb_l4_gate_ick { + usb_l4_gate_ick: usb_l4_gate_ick at a10 { #clock-cells = <0>; compatible = "ti,composite-interface-clock"; clocks = <&l4_ick>;
@@ -136,7 +136,7 @@ reg = <0x0a10>; }; - usb_l4_div_ick: usb_l4_div_ick { + usb_l4_div_ick: usb_l4_div_ick at a40 { #clock-cells = <0>; compatible = "ti,composite-divider-clock"; clocks = <&l4_ick>;
@@ -152,7 +152,7 @@ clocks = <&usb_l4_gate_ick>, <&usb_l4_div_ick>; }; - dss1_alwon_fck: dss1_alwon_fck_3430es1 { + dss1_alwon_fck: dss1_alwon_fck_3430es1 at e00 { #clock-cells = <0>; compatible = "ti,gate-clock"; clocks = <&dpll4_m4x2_ck>;
@@ -161,7 +161,7 @@ ti,set-rate-parent; }; - dss_ick: dss_ick_3430es1 { + dss_ick: dss_ick_3430es1 at e10 { #clock-cells = <0>; compatible = "ti,omap3-no-wait-interface-clock"; clocks = <&l4_ick>;
arch/arm/boot/dts/omap34xx-omap36xx-clocks.dtsi +22 -22
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arch/arm/boot/dts/omap36xx-am35xx-omap3430es2plus-clocks.dtsi +16 -16
@@ -25,7 +25,7 @@ }; }; &cm_clocks { - dpll5_ck: dpll5_ck { + dpll5_ck: dpll5_ck at d04 { #clock-cells = <0>; compatible = "ti,omap3-dpll-clock"; clocks = <&sys_ck>, <&sys_ck>;
@@ -34,7 +34,7 @@ ti,lock; }; - dpll5_m2_ck: dpll5_m2_ck { + dpll5_m2_ck: dpll5_m2_ck at d50 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll5_ck>;
@@ -43,7 +43,7 @@ ti,index-starts-at-one; }; - sgx_gate_fck: sgx_gate_fck { + sgx_gate_fck: sgx_gate_fck at b00 { #clock-cells = <0>; compatible = "ti,composite-gate-clock"; clocks = <&core_ck>;
@@ -91,7 +91,7 @@ clock-div = <2>; }; - sgx_mux_fck: sgx_mux_fck { + sgx_mux_fck: sgx_mux_fck at b40 { #clock-cells = <0>; compatible = "ti,composite-mux-clock"; clocks = <&core_d3_ck>, <&core_d4_ck>, <&core_d6_ck>, <&cm_96m_fck>, <&omap_192m_alwon_fck>, <&core_d2_ck>, <&corex2_d3_fck>, <&corex2_d5_fck>;
@@ -104,7 +104,7 @@ clocks = <&sgx_gate_fck>, <&sgx_mux_fck>; }; - sgx_ick: sgx_ick { + sgx_ick: sgx_ick at b10 { #clock-cells = <0>; compatible = "ti,wait-gate-clock"; clocks = <&l3_ick>;
@@ -112,7 +112,7 @@ ti,bit-shift = <0>; }; - cpefuse_fck: cpefuse_fck { + cpefuse_fck: cpefuse_fck at a08 { #clock-cells = <0>; compatible = "ti,gate-clock"; clocks = <&sys_ck>;
@@ -120,7 +120,7 @@ ti,bit-shift = <0>; }; - ts_fck: ts_fck { + ts_fck: ts_fck at a08 { #clock-cells = <0>; compatible = "ti,gate-clock"; clocks = <&omap_32k_fck>;
@@ -128,7 +128,7 @@ ti,bit-shift = <1>; }; - usbtll_fck: usbtll_fck { + usbtll_fck: usbtll_fck at a08 { #clock-cells = <0>; compatible = "ti,wait-gate-clock"; clocks = <&dpll5_m2_ck>;
@@ -136,7 +136,7 @@ ti,bit-shift = <2>; }; - usbtll_ick: usbtll_ick { + usbtll_ick: usbtll_ick at a18 { #clock-cells = <0>; compatible = "ti,omap3-interface-clock"; clocks = <&core_l4_ick>;
@@ -144,7 +144,7 @@ ti,bit-shift = <2>; }; - mmchs3_ick: mmchs3_ick { + mmchs3_ick: mmchs3_ick at a10 { #clock-cells = <0>; compatible = "ti,omap3-interface-clock"; clocks = <&core_l4_ick>;
@@ -152,7 +152,7 @@ ti,bit-shift = <30>; }; - mmchs3_fck: mmchs3_fck { + mmchs3_fck: mmchs3_fck at a00 { #clock-cells = <0>; compatible = "ti,wait-gate-clock"; clocks = <&core_96m_fck>;
@@ -160,7 +160,7 @@ ti,bit-shift = <30>; }; - dss1_alwon_fck: dss1_alwon_fck_3430es2 { + dss1_alwon_fck: dss1_alwon_fck_3430es2 at e00 { #clock-cells = <0>; compatible = "ti,dss-gate-clock"; clocks = <&dpll4_m4x2_ck>;
@@ -169,7 +169,7 @@ ti,set-rate-parent; }; - dss_ick: dss_ick_3430es2 { + dss_ick: dss_ick_3430es2 at e10 { #clock-cells = <0>; compatible = "ti,omap3-dss-interface-clock"; clocks = <&l4_ick>;
@@ -177,7 +177,7 @@ ti,bit-shift = <0>; }; - usbhost_120m_fck: usbhost_120m_fck { + usbhost_120m_fck: usbhost_120m_fck at 1400 { #clock-cells = <0>; compatible = "ti,gate-clock"; clocks = <&dpll5_m2_ck>;
@@ -185,7 +185,7 @@ ti,bit-shift = <1>; }; - usbhost_48m_fck: usbhost_48m_fck { + usbhost_48m_fck: usbhost_48m_fck at 1400 { #clock-cells = <0>; compatible = "ti,dss-gate-clock"; clocks = <&omap_48m_fck>;
@@ -193,7 +193,7 @@ ti,bit-shift = <0>; }; - usbhost_ick: usbhost_ick { + usbhost_ick: usbhost_ick at 1410 { #clock-cells = <0>; compatible = "ti,omap3-dss-interface-clock"; clocks = <&l4_ick>;
arch/arm/boot/dts/omap36xx-clocks.dtsi +7 -7
@@ -8,14 +8,14 @@ * published by the Free Software Foundation. */ &cm_clocks { - dpll4_ck: dpll4_ck { + dpll4_ck: dpll4_ck at d00 { #clock-cells = <0>; compatible = "ti,omap3-dpll-per-j-type-clock"; clocks = <&sys_ck>, <&sys_ck>; reg = <0x0d00>, <0x0d20>, <0x0d44>, <0x0d30>; }; - dpll4_m5x2_ck: dpll4_m5x2_ck { + dpll4_m5x2_ck: dpll4_m5x2_ck at d00 { #clock-cells = <0>; compatible = "ti,hsdiv-gate-clock"; clocks = <&dpll4_m5x2_mul_ck>;
@@ -25,7 +25,7 @@ ti,set-bit-to-disable; }; - dpll4_m2x2_ck: dpll4_m2x2_ck { + dpll4_m2x2_ck: dpll4_m2x2_ck at d00 { #clock-cells = <0>; compatible = "ti,hsdiv-gate-clock"; clocks = <&dpll4_m2x2_mul_ck>;
@@ -34,7 +34,7 @@ ti,set-bit-to-disable; }; - dpll3_m3x2_ck: dpll3_m3x2_ck { + dpll3_m3x2_ck: dpll3_m3x2_ck at d00 { #clock-cells = <0>; compatible = "ti,hsdiv-gate-clock"; clocks = <&dpll3_m3x2_mul_ck>;
@@ -43,7 +43,7 @@ ti,set-bit-to-disable; }; - dpll4_m3x2_ck: dpll4_m3x2_ck { + dpll4_m3x2_ck: dpll4_m3x2_ck at d00 { #clock-cells = <0>; compatible = "ti,hsdiv-gate-clock"; clocks = <&dpll4_m3x2_mul_ck>;
@@ -52,7 +52,7 @@ ti,set-bit-to-disable; }; - dpll4_m6x2_ck: dpll4_m6x2_ck { + dpll4_m6x2_ck: dpll4_m6x2_ck at d00 { #clock-cells = <0>; compatible = "ti,hsdiv-gate-clock"; clocks = <&dpll4_m6x2_mul_ck>;
@@ -61,7 +61,7 @@ ti,set-bit-to-disable; }; - uart4_fck: uart4_fck { + uart4_fck: uart4_fck at 1000 { #clock-cells = <0>; compatible = "ti,wait-gate-clock"; clocks = <&per_48m_fck>;
arch/arm/boot/dts/omap36xx-omap3430es2plus-clocks.dtsi +7 -7
@@ -8,7 +8,7 @@ * published by the Free Software Foundation. */ &cm_clocks { - ssi_ssr_gate_fck_3430es2: ssi_ssr_gate_fck_3430es2 { + ssi_ssr_gate_fck_3430es2: ssi_ssr_gate_fck_3430es2 at a00 { #clock-cells = <0>; compatible = "ti,composite-no-wait-gate-clock"; clocks = <&corex2_fck>;
@@ -16,7 +16,7 @@ reg = <0x0a00>; }; - ssi_ssr_div_fck_3430es2: ssi_ssr_div_fck_3430es2 { + ssi_ssr_div_fck_3430es2: ssi_ssr_div_fck_3430es2 at a40 { #clock-cells = <0>; compatible = "ti,composite-divider-clock"; clocks = <&corex2_fck>;
@@ -39,7 +39,7 @@ clock-div = <2>; }; - hsotgusb_ick_3430es2: hsotgusb_ick_3430es2 { + hsotgusb_ick_3430es2: hsotgusb_ick_3430es2 at a10 { #clock-cells = <0>; compatible = "ti,omap3-hsotgusb-interface-clock"; clocks = <&core_l3_ick>;
@@ -55,7 +55,7 @@ clock-div = <1>; }; - ssi_ick: ssi_ick_3430es2 { + ssi_ick: ssi_ick_3430es2 at a10 { #clock-cells = <0>; compatible = "ti,omap3-ssi-interface-clock"; clocks = <&ssi_l4_ick>;
@@ -63,7 +63,7 @@ ti,bit-shift = <0>; }; - usim_gate_fck: usim_gate_fck { + usim_gate_fck: usim_gate_fck at c00 { #clock-cells = <0>; compatible = "ti,composite-gate-clock"; clocks = <&omap_96m_fck>;
@@ -143,7 +143,7 @@ clock-div = <20>; }; - usim_mux_fck: usim_mux_fck { + usim_mux_fck: usim_mux_fck at c40 { #clock-cells = <0>; compatible = "ti,composite-mux-clock"; clocks = <&sys_ck>, <&sys_d2_ck>, <&omap_96m_d2_fck>, <&omap_96m_d4_fck>, <&omap_96m_d8_fck>, <&omap_96m_d10_fck>, <&dpll5_m2_d4_ck>, <&dpll5_m2_d8_ck>, <&dpll5_m2_d16_ck>, <&dpll5_m2_d20_ck>;
@@ -158,7 +158,7 @@ clocks = <&usim_gate_fck>, <&usim_mux_fck>; }; - usim_ick: usim_ick { + usim_ick: usim_ick at c10 { #clock-cells = <0>; compatible = "ti,omap3-interface-clock"; clocks = <&wkup_l4_ick>;
arch/arm/boot/dts/omap3xxx-clocks.dtsi +138 -138
1,104 lines not on this page · raw message
Signature · 1 line
1.7.9.5
PATCH 2/8 ARM: dts: omap2: fix clock node definitions to avoid build warnings
In reply to Tero KristoUpcoming change to DT compiler is going to complain about nodes which have a reg property, but have not defined the address in their name. This patch fixes following type of warnings for OMAP2 clock nodes:
Warning (unit_address_vs_reg): Node /ocp/cm at 48004000/clocks/dpll3_m2_ck has a reg or ranges property, but no unit name
Signed-off-by Tero Kristo <[email protected]>
--- arch/arm/boot/dts/omap2420-clocks.dtsi | 38 +++--- arch/arm/boot/dts/omap2430-clocks.dtsi | 58 ++++---- arch/arm/boot/dts/omap24xx-clocks.dtsi | 228 ++++++++++++++++---------------- 3 files changed, 162 insertions(+), 162 deletions(-)
arch/arm/boot/dts/omap2420-clocks.dtsi +19 -19
@@ -9,7 +9,7 @@ */ &prcm_clocks { - sys_clkout2_src_gate: sys_clkout2_src_gate { + sys_clkout2_src_gate: sys_clkout2_src_gate at 70 { #clock-cells = <0>; compatible = "ti,composite-no-wait-gate-clock"; clocks = <&core_ck>;
@@ -17,7 +17,7 @@ reg = <0x0070>; }; - sys_clkout2_src_mux: sys_clkout2_src_mux { + sys_clkout2_src_mux: sys_clkout2_src_mux at 70 { #clock-cells = <0>; compatible = "ti,composite-mux-clock"; clocks = <&core_ck>, <&sys_ck>, <&func_96m_ck>, <&func_54m_ck>;
@@ -31,7 +31,7 @@ clocks = <&sys_clkout2_src_gate>, <&sys_clkout2_src_mux>; }; - sys_clkout2: sys_clkout2 { + sys_clkout2: sys_clkout2 at 70 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&sys_clkout2_src>;
@@ -41,7 +41,7 @@ ti,index-power-of-two; }; - dsp_gate_ick: dsp_gate_ick { + dsp_gate_ick: dsp_gate_ick at 810 { #clock-cells = <0>; compatible = "ti,composite-interface-clock"; clocks = <&dsp_fck>;
@@ -49,7 +49,7 @@ reg = <0x0810>; }; - dsp_div_ick: dsp_div_ick { + dsp_div_ick: dsp_div_ick at 840 { #clock-cells = <0>; compatible = "ti,composite-divider-clock"; clocks = <&dsp_fck>;
@@ -65,7 +65,7 @@ clocks = <&dsp_gate_ick>, <&dsp_div_ick>; }; - iva1_gate_ifck: iva1_gate_ifck { + iva1_gate_ifck: iva1_gate_ifck at 800 { #clock-cells = <0>; compatible = "ti,composite-gate-clock"; clocks = <&core_ck>;
@@ -73,7 +73,7 @@ reg = <0x0800>; }; - iva1_div_ifck: iva1_div_ifck { + iva1_div_ifck: iva1_div_ifck at 840 { #clock-cells = <0>; compatible = "ti,composite-divider-clock"; clocks = <&core_ck>;
@@ -96,7 +96,7 @@ clock-div = <2>; }; - iva1_mpu_int_ifck: iva1_mpu_int_ifck { + iva1_mpu_int_ifck: iva1_mpu_int_ifck at 800 { #clock-cells = <0>; compatible = "ti,wait-gate-clock"; clocks = <&iva1_ifck_div>;
@@ -104,7 +104,7 @@ reg = <0x0800>; }; - wdt3_ick: wdt3_ick { + wdt3_ick: wdt3_ick at 210 { #clock-cells = <0>; compatible = "ti,omap3-interface-clock"; clocks = <&l4_ck>;
@@ -112,7 +112,7 @@ reg = <0x0210>; }; - wdt3_fck: wdt3_fck { + wdt3_fck: wdt3_fck at 200 { #clock-cells = <0>; compatible = "ti,wait-gate-clock"; clocks = <&func_32k_ck>;
@@ -120,7 +120,7 @@ reg = <0x0200>; }; - mmc_ick: mmc_ick { + mmc_ick: mmc_ick at 210 { #clock-cells = <0>; compatible = "ti,omap3-interface-clock"; clocks = <&l4_ck>;
@@ -128,7 +128,7 @@ reg = <0x0210>; }; - mmc_fck: mmc_fck { + mmc_fck: mmc_fck at 200 { #clock-cells = <0>; compatible = "ti,wait-gate-clock"; clocks = <&func_96m_ck>;
@@ -136,7 +136,7 @@ reg = <0x0200>; }; - eac_ick: eac_ick { + eac_ick: eac_ick at 210 { #clock-cells = <0>; compatible = "ti,omap3-interface-clock"; clocks = <&l4_ck>;
@@ -144,7 +144,7 @@ reg = <0x0210>; }; - eac_fck: eac_fck { + eac_fck: eac_fck at 200 { #clock-cells = <0>; compatible = "ti,wait-gate-clock"; clocks = <&func_96m_ck>;
@@ -152,7 +152,7 @@ reg = <0x0200>; }; - i2c1_fck: i2c1_fck { + i2c1_fck: i2c1_fck at 200 { #clock-cells = <0>; compatible = "ti,wait-gate-clock"; clocks = <&func_12m_ck>;
@@ -160,7 +160,7 @@ reg = <0x0200>; }; - i2c2_fck: i2c2_fck { + i2c2_fck: i2c2_fck at 200 { #clock-cells = <0>; compatible = "ti,wait-gate-clock"; clocks = <&func_12m_ck>;
@@ -168,7 +168,7 @@ reg = <0x0200>; }; - vlynq_ick: vlynq_ick { + vlynq_ick: vlynq_ick at 210 { #clock-cells = <0>; compatible = "ti,omap3-interface-clock"; clocks = <&core_l3_ck>;
@@ -176,7 +176,7 @@ reg = <0x0210>; }; - vlynq_gate_fck: vlynq_gate_fck { + vlynq_gate_fck: vlynq_gate_fck at 200 { #clock-cells = <0>; compatible = "ti,composite-gate-clock"; clocks = <&core_ck>;
@@ -192,7 +192,7 @@ clock-div = <18>; }; - vlynq_mux_fck: vlynq_mux_fck { + vlynq_mux_fck: vlynq_mux_fck at 240 { #clock-cells = <0>; compatible = "ti,composite-mux-clock"; clocks = <&func_96m_ck>, <&core_ck>, <&core_d2_ck>, <&core_d3_ck>, <&core_d4_ck>, <&dummy_ck>, <&core_d6_ck>, <&dummy_ck>, <&core_d8_ck>, <&core_d9_ck>, <&dummy_ck>, <&dummy_ck>, <&core_d12_ck>, <&dummy_ck>, <&dummy_ck>, <&dummy_ck>, <&core_d16_ck>, <&dummy_ck>, <&core_d18_ck>;
arch/arm/boot/dts/omap2430-clocks.dtsi +29 -29
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arch/arm/boot/dts/omap24xx-clocks.dtsi +114 -114
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1.7.9.5
PATCH 3/8 ARM: dts: omap4: fix clock node definitions to avoid build warnings
In reply to Tero KristoUpcoming change to DT compiler is going to complain about nodes which have a reg property, but have not defined the address in their name. This patch fixes following type of warnings for OMAP4 clock nodes:
Warning (unit_address_vs_reg): Node /ocp/cm at 48004000/clocks/dpll3_m2_ck has a reg or ranges property, but no unit name
Signed-off-by Tero Kristo <[email protected]>
--- arch/arm/boot/dts/omap443x-clocks.dtsi | 2 +- arch/arm/boot/dts/omap446x-clocks.dtsi | 4 +- arch/arm/boot/dts/omap44xx-clocks.dtsi | 316 ++++++++++++++++---------------- 3 files changed, 161 insertions(+), 161 deletions(-)
arch/arm/boot/dts/omap443x-clocks.dtsi +1 -1
@@ -8,7 +8,7 @@ * published by the Free Software Foundation. */ &prm_clocks { - bandgap_fclk: bandgap_fclk { + bandgap_fclk: bandgap_fclk at 1888 { #clock-cells = <0>; compatible = "ti,gate-clock"; clocks = <&sys_32k_ck>;
arch/arm/boot/dts/omap446x-clocks.dtsi +2 -2
@@ -8,7 +8,7 @@ * published by the Free Software Foundation. */ &prm_clocks { - div_ts_ck: div_ts_ck { + div_ts_ck: div_ts_ck at 1888 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&l4_wkup_clk_mux_ck>;
@@ -17,7 +17,7 @@ ti,dividers = <8>, <16>, <32>; }; - bandgap_ts_fclk: bandgap_ts_fclk { + bandgap_ts_fclk: bandgap_ts_fclk at 1888 { #clock-cells = <0>; compatible = "ti,gate-clock"; clocks = <&div_ts_ck>;
arch/arm/boot/dts/omap44xx-clocks.dtsi +158 -158
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1.7.9.5
PATCH 4/8 ARM: dts: am33xx: fix clock node definitions to avoid build warnings
In reply to Tero KristoUpcoming change to DT compiler is going to complain about nodes which have a reg property, but have not defined the address in their name. This patch fixes following type of warnings for AM33xx clock nodes:
Warning (unit_address_vs_reg): Node /ocp/cm at 48004000/clocks/dpll3_m2_ck has a reg or ranges property, but no unit name
Signed-off-by Tero Kristo <[email protected]>
--- arch/arm/boot/dts/am33xx-clocks.dtsi | 90 +++++++++++++++++----------------- 1 file changed, 45 insertions(+), 45 deletions(-)
arch/arm/boot/dts/am33xx-clocks.dtsi +45 -45
@@ -8,7 +8,7 @@ * published by the Free Software Foundation. */ &scm_clocks { - sys_clkin_ck: sys_clkin_ck { + sys_clkin_ck: sys_clkin_ck at 40 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&virt_19200000_ck>, <&virt_24000000_ck>, <&virt_25000000_ck>, <&virt_26000000_ck>;
@@ -163,7 +163,7 @@ clock-frequency = <12000000>; }; - dpll_core_ck: dpll_core_ck { + dpll_core_ck: dpll_core_ck at 490 { #clock-cells = <0>; compatible = "ti,am3-dpll-core-clock"; clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
@@ -176,7 +176,7 @@ clocks = <&dpll_core_ck>; }; - dpll_core_m4_ck: dpll_core_m4_ck { + dpll_core_m4_ck: dpll_core_m4_ck at 480 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_core_x2_ck>;
@@ -185,7 +185,7 @@ ti,index-starts-at-one; }; - dpll_core_m5_ck: dpll_core_m5_ck { + dpll_core_m5_ck: dpll_core_m5_ck at 484 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_core_x2_ck>;
@@ -194,7 +194,7 @@ ti,index-starts-at-one; }; - dpll_core_m6_ck: dpll_core_m6_ck { + dpll_core_m6_ck: dpll_core_m6_ck at 4d8 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_core_x2_ck>;
@@ -203,14 +203,14 @@ ti,index-starts-at-one; }; - dpll_mpu_ck: dpll_mpu_ck { + dpll_mpu_ck: dpll_mpu_ck at 488 { #clock-cells = <0>; compatible = "ti,am3-dpll-clock"; clocks = <&sys_clkin_ck>, <&sys_clkin_ck>; reg = <0x0488>, <0x0420>, <0x042c>; }; - dpll_mpu_m2_ck: dpll_mpu_m2_ck { + dpll_mpu_m2_ck: dpll_mpu_m2_ck at 4a8 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_mpu_ck>;
@@ -219,14 +219,14 @@ ti,index-starts-at-one; }; - dpll_ddr_ck: dpll_ddr_ck { + dpll_ddr_ck: dpll_ddr_ck at 494 { #clock-cells = <0>; compatible = "ti,am3-dpll-no-gate-clock"; clocks = <&sys_clkin_ck>, <&sys_clkin_ck>; reg = <0x0494>, <0x0434>, <0x0440>; }; - dpll_ddr_m2_ck: dpll_ddr_m2_ck { + dpll_ddr_m2_ck: dpll_ddr_m2_ck at 4a0 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_ddr_ck>;
@@ -243,14 +243,14 @@ clock-div = <2>; }; - dpll_disp_ck: dpll_disp_ck { + dpll_disp_ck: dpll_disp_ck at 498 { #clock-cells = <0>; compatible = "ti,am3-dpll-no-gate-clock"; clocks = <&sys_clkin_ck>, <&sys_clkin_ck>; reg = <0x0498>, <0x0448>, <0x0454>; }; - dpll_disp_m2_ck: dpll_disp_m2_ck { + dpll_disp_m2_ck: dpll_disp_m2_ck at 4a4 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_disp_ck>;
@@ -260,14 +260,14 @@ ti,set-rate-parent; }; - dpll_per_ck: dpll_per_ck { + dpll_per_ck: dpll_per_ck at 48c { #clock-cells = <0>; compatible = "ti,am3-dpll-no-gate-j-type-clock"; clocks = <&sys_clkin_ck>, <&sys_clkin_ck>; reg = <0x048c>, <0x0470>, <0x049c>; }; - dpll_per_m2_ck: dpll_per_m2_ck { + dpll_per_m2_ck: dpll_per_m2_ck at 4ac { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_per_ck>;
@@ -292,7 +292,7 @@ clock-div = <4>; }; - cefuse_fck: cefuse_fck { + cefuse_fck: cefuse_fck at a20 { #clock-cells = <0>; compatible = "ti,gate-clock"; clocks = <&sys_clkin_ck>;
@@ -316,7 +316,7 @@ clock-div = <732>; }; - clkdiv32k_ick: clkdiv32k_ick { + clkdiv32k_ick: clkdiv32k_ick at 14c { #clock-cells = <0>; compatible = "ti,gate-clock"; clocks = <&clkdiv32k_ck>;
@@ -332,14 +332,14 @@ clock-div = <1>; }; - pruss_ocp_gclk: pruss_ocp_gclk { + pruss_ocp_gclk: pruss_ocp_gclk at 530 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&l3_gclk>, <&dpll_disp_m2_ck>; reg = <0x0530>; }; - mmu_fck: mmu_fck { + mmu_fck: mmu_fck at 914 { #clock-cells = <0>; compatible = "ti,gate-clock"; clocks = <&dpll_core_m4_ck>;
@@ -347,56 +347,56 @@ reg = <0x0914>; }; - timer1_fck: timer1_fck { + timer1_fck: timer1_fck at 528 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&sys_clkin_ck>, <&clkdiv32k_ick>, <&tclkin_ck>, <&clk_rc32k_ck>, <&clk_32768_ck>; reg = <0x0528>; }; - timer2_fck: timer2_fck { + timer2_fck: timer2_fck at 508 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>; reg = <0x0508>; }; - timer3_fck: timer3_fck { + timer3_fck: timer3_fck at 50c { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>; reg = <0x050c>; }; - timer4_fck: timer4_fck { + timer4_fck: timer4_fck at 510 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>; reg = <0x0510>; }; - timer5_fck: timer5_fck { + timer5_fck: timer5_fck at 518 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>; reg = <0x0518>; }; - timer6_fck: timer6_fck { + timer6_fck: timer6_fck at 51c { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>; reg = <0x051c>; }; - timer7_fck: timer7_fck { + timer7_fck: timer7_fck at 504 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>; reg = <0x0504>; }; - usbotg_fck: usbotg_fck { + usbotg_fck: usbotg_fck at 47c { #clock-cells = <0>; compatible = "ti,gate-clock"; clocks = <&dpll_per_ck>;
@@ -412,7 +412,7 @@ clock-div = <2>; }; - ieee5000_fck: ieee5000_fck { + ieee5000_fck: ieee5000_fck at e4 { #clock-cells = <0>; compatible = "ti,gate-clock"; clocks = <&dpll_core_m4_div2_ck>;
@@ -420,7 +420,7 @@ reg = <0x00e4>; }; - wdt1_fck: wdt1_fck { + wdt1_fck: wdt1_fck at 538 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&clk_rc32k_ck>, <&clkdiv32k_ick>;
@@ -483,21 +483,21 @@ clock-div = <2>; }; - cpsw_cpts_rft_clk: cpsw_cpts_rft_clk { + cpsw_cpts_rft_clk: cpsw_cpts_rft_clk at 520 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&dpll_core_m5_ck>, <&dpll_core_m4_ck>; reg = <0x0520>; }; - gpio0_dbclk_mux_ck: gpio0_dbclk_mux_ck { + gpio0_dbclk_mux_ck: gpio0_dbclk_mux_ck at 53c { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&clk_rc32k_ck>, <&clk_32768_ck>, <&clkdiv32k_ick>; reg = <0x053c>; }; - gpio0_dbclk: gpio0_dbclk { + gpio0_dbclk: gpio0_dbclk at 408 { #clock-cells = <0>; compatible = "ti,gate-clock"; clocks = <&gpio0_dbclk_mux_ck>;
@@ -505,7 +505,7 @@ reg = <0x0408>; }; - gpio1_dbclk: gpio1_dbclk { + gpio1_dbclk: gpio1_dbclk at ac { #clock-cells = <0>; compatible = "ti,gate-clock"; clocks = <&clkdiv32k_ick>;
@@ -513,7 +513,7 @@ reg = <0x00ac>; }; - gpio2_dbclk: gpio2_dbclk { + gpio2_dbclk: gpio2_dbclk at b0 { #clock-cells = <0>; compatible = "ti,gate-clock"; clocks = <&clkdiv32k_ick>;
@@ -521,7 +521,7 @@ reg = <0x00b0>; }; - gpio3_dbclk: gpio3_dbclk { + gpio3_dbclk: gpio3_dbclk at b4 { #clock-cells = <0>; compatible = "ti,gate-clock"; clocks = <&clkdiv32k_ick>;
@@ -529,7 +529,7 @@ reg = <0x00b4>; }; - lcd_gclk: lcd_gclk { + lcd_gclk: lcd_gclk at 534 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&dpll_disp_m2_ck>, <&dpll_core_m5_ck>, <&dpll_per_m2_ck>;
@@ -545,7 +545,7 @@ clock-div = <2>; }; - gfx_fclk_clksel_ck: gfx_fclk_clksel_ck { + gfx_fclk_clksel_ck: gfx_fclk_clksel_ck at 52c { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&dpll_core_m4_ck>, <&dpll_per_m2_ck>;
@@ -553,7 +553,7 @@ reg = <0x052c>; }; - gfx_fck_div_ck: gfx_fck_div_ck { + gfx_fck_div_ck: gfx_fck_div_ck at 52c { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&gfx_fclk_clksel_ck>;
@@ -561,14 +561,14 @@ ti,max-div = <2>; }; - sysclkout_pre_ck: sysclkout_pre_ck { + sysclkout_pre_ck: sysclkout_pre_ck at 700 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&clk_32768_ck>, <&l3_gclk>, <&dpll_ddr_m2_ck>, <&dpll_per_m2_ck>, <&lcd_gclk>; reg = <0x0700>; }; - clkout2_div_ck: clkout2_div_ck { + clkout2_div_ck: clkout2_div_ck at 700 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&sysclkout_pre_ck>;
@@ -577,7 +577,7 @@ reg = <0x0700>; }; - dbg_sysclk_ck: dbg_sysclk_ck { + dbg_sysclk_ck: dbg_sysclk_ck at 414 { #clock-cells = <0>; compatible = "ti,gate-clock"; clocks = <&sys_clkin_ck>;
@@ -585,7 +585,7 @@ reg = <0x0414>; }; - dbg_clka_ck: dbg_clka_ck { + dbg_clka_ck: dbg_clka_ck at 414 { #clock-cells = <0>; compatible = "ti,gate-clock"; clocks = <&dpll_core_m4_ck>;
@@ -593,7 +593,7 @@ reg = <0x0414>; }; - stm_pmd_clock_mux_ck: stm_pmd_clock_mux_ck { + stm_pmd_clock_mux_ck: stm_pmd_clock_mux_ck at 414 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&dbg_sysclk_ck>, <&dbg_clka_ck>;
@@ -601,7 +601,7 @@ reg = <0x0414>; }; - trace_pmd_clk_mux_ck: trace_pmd_clk_mux_ck { + trace_pmd_clk_mux_ck: trace_pmd_clk_mux_ck at 414 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&dbg_sysclk_ck>, <&dbg_clka_ck>;
@@ -609,7 +609,7 @@ reg = <0x0414>; }; - stm_clk_div_ck: stm_clk_div_ck { + stm_clk_div_ck: stm_clk_div_ck at 414 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&stm_pmd_clock_mux_ck>;
@@ -619,7 +619,7 @@ ti,index-power-of-two; }; - trace_clk_div_ck: trace_clk_div_ck { + trace_clk_div_ck: trace_clk_div_ck at 414 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&trace_pmd_clk_mux_ck>;
@@ -629,7 +629,7 @@ ti,index-power-of-two; }; - clkout2_ck: clkout2_ck { + clkout2_ck: clkout2_ck at 700 { #clock-cells = <0>; compatible = "ti,gate-clock"; clocks = <&clkout2_div_ck>;
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1.7.9.5
PATCH 5/8 ARM: dts: am43xx: fix clock node definitions to avoid build warnings
In reply to Tero KristoUpcoming change to DT compiler is going to complain about nodes which have a reg property, but have not defined the address in their name. This patch fixes following type of warnings for AM43xx clock nodes:
Warning (unit_address_vs_reg): Node /ocp/cm at 48004000/clocks/dpll3_m2_ck has a reg or ranges property, but no unit name
Signed-off-by Tero Kristo <[email protected]>
--- arch/arm/boot/dts/am43xx-clocks.dtsi | 116 +++++++++++++++++----------------- 1 file changed, 58 insertions(+), 58 deletions(-)
arch/arm/boot/dts/am43xx-clocks.dtsi +58 -58
@@ -8,7 +8,7 @@ * published by the Free Software Foundation. */ &scm_clocks { - sys_clkin_ck: sys_clkin_ck { + sys_clkin_ck: sys_clkin_ck at 40 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&sysboot_freq_sel_ck>, <&crystal_freq_sel_ck>;
@@ -16,7 +16,7 @@ reg = <0x0040>; }; - crystal_freq_sel_ck: crystal_freq_sel_ck { + crystal_freq_sel_ck: crystal_freq_sel_ck at 40 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&virt_19200000_ck>, <&virt_24000000_ck>, <&virt_25000000_ck>, <&virt_26000000_ck>;
@@ -104,7 +104,7 @@ clock-div = <1>; }; - ehrpwm0_tbclk: ehrpwm0_tbclk { + ehrpwm0_tbclk: ehrpwm0_tbclk at 664 { #clock-cells = <0>; compatible = "ti,gate-clock"; clocks = <&l4ls_gclk>;
@@ -112,7 +112,7 @@ reg = <0x0664>; }; - ehrpwm1_tbclk: ehrpwm1_tbclk { + ehrpwm1_tbclk: ehrpwm1_tbclk at 664 { #clock-cells = <0>; compatible = "ti,gate-clock"; clocks = <&l4ls_gclk>;
@@ -120,7 +120,7 @@ reg = <0x0664>; }; - ehrpwm2_tbclk: ehrpwm2_tbclk { + ehrpwm2_tbclk: ehrpwm2_tbclk at 664 { #clock-cells = <0>; compatible = "ti,gate-clock"; clocks = <&l4ls_gclk>;
@@ -128,7 +128,7 @@ reg = <0x0664>; }; - ehrpwm3_tbclk: ehrpwm3_tbclk { + ehrpwm3_tbclk: ehrpwm3_tbclk at 664 { #clock-cells = <0>; compatible = "ti,gate-clock"; clocks = <&l4ls_gclk>;
@@ -136,7 +136,7 @@ reg = <0x0664>; }; - ehrpwm4_tbclk: ehrpwm4_tbclk { + ehrpwm4_tbclk: ehrpwm4_tbclk at 664 { #clock-cells = <0>; compatible = "ti,gate-clock"; clocks = <&l4ls_gclk>;
@@ -144,7 +144,7 @@ reg = <0x0664>; }; - ehrpwm5_tbclk: ehrpwm5_tbclk { + ehrpwm5_tbclk: ehrpwm5_tbclk at 664 { #clock-cells = <0>; compatible = "ti,gate-clock"; clocks = <&l4ls_gclk>;
@@ -195,7 +195,7 @@ clock-frequency = <26000000>; }; - dpll_core_ck: dpll_core_ck { + dpll_core_ck: dpll_core_ck at 2d20 { #clock-cells = <0>; compatible = "ti,am3-dpll-core-clock"; clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
@@ -208,7 +208,7 @@ clocks = <&dpll_core_ck>; }; - dpll_core_m4_ck: dpll_core_m4_ck { + dpll_core_m4_ck: dpll_core_m4_ck at 2d38 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_core_x2_ck>;
@@ -219,7 +219,7 @@ ti,invert-autoidle-bit; }; - dpll_core_m5_ck: dpll_core_m5_ck { + dpll_core_m5_ck: dpll_core_m5_ck at 2d3c { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_core_x2_ck>;
@@ -230,7 +230,7 @@ ti,invert-autoidle-bit; }; - dpll_core_m6_ck: dpll_core_m6_ck { + dpll_core_m6_ck: dpll_core_m6_ck at 2d40 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_core_x2_ck>;
@@ -241,14 +241,14 @@ ti,invert-autoidle-bit; }; - dpll_mpu_ck: dpll_mpu_ck { + dpll_mpu_ck: dpll_mpu_ck at 2d60 { #clock-cells = <0>; compatible = "ti,am3-dpll-clock"; clocks = <&sys_clkin_ck>, <&sys_clkin_ck>; reg = <0x2d60>, <0x2d64>, <0x2d6c>; }; - dpll_mpu_m2_ck: dpll_mpu_m2_ck { + dpll_mpu_m2_ck: dpll_mpu_m2_ck at 2d70 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_mpu_ck>;
@@ -267,14 +267,14 @@ clock-div = <2>; }; - dpll_ddr_ck: dpll_ddr_ck { + dpll_ddr_ck: dpll_ddr_ck at 2da0 { #clock-cells = <0>; compatible = "ti,am3-dpll-clock"; clocks = <&sys_clkin_ck>, <&sys_clkin_ck>; reg = <0x2da0>, <0x2da4>, <0x2dac>; }; - dpll_ddr_m2_ck: dpll_ddr_m2_ck { + dpll_ddr_m2_ck: dpll_ddr_m2_ck at 2db0 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_ddr_ck>;
@@ -285,14 +285,14 @@ ti,invert-autoidle-bit; }; - dpll_disp_ck: dpll_disp_ck { + dpll_disp_ck: dpll_disp_ck at 2e20 { #clock-cells = <0>; compatible = "ti,am3-dpll-clock"; clocks = <&sys_clkin_ck>, <&sys_clkin_ck>; reg = <0x2e20>, <0x2e24>, <0x2e2c>; }; - dpll_disp_m2_ck: dpll_disp_m2_ck { + dpll_disp_m2_ck: dpll_disp_m2_ck at 2e30 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_disp_ck>;
@@ -304,14 +304,14 @@ ti,set-rate-parent; }; - dpll_per_ck: dpll_per_ck { + dpll_per_ck: dpll_per_ck at 2de0 { #clock-cells = <0>; compatible = "ti,am3-dpll-j-type-clock"; clocks = <&sys_clkin_ck>, <&sys_clkin_ck>; reg = <0x2de0>, <0x2de4>, <0x2dec>; }; - dpll_per_m2_ck: dpll_per_m2_ck { + dpll_per_m2_ck: dpll_per_m2_ck at 2df0 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_per_ck>;
@@ -354,7 +354,7 @@ clock-div = <732>; }; - clkdiv32k_ick: clkdiv32k_ick { + clkdiv32k_ick: clkdiv32k_ick at 2a38 { #clock-cells = <0>; compatible = "ti,gate-clock"; clocks = <&clkdiv32k_ck>;
@@ -370,7 +370,7 @@ clock-div = <1>; }; - pruss_ocp_gclk: pruss_ocp_gclk { + pruss_ocp_gclk: pruss_ocp_gclk at 4248 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&sysclk_div>, <&dpll_disp_m2_ck>;
@@ -383,56 +383,56 @@ clock-frequency = <32768>; }; - timer1_fck: timer1_fck { + timer1_fck: timer1_fck at 4200 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&sys_clkin_ck>, <&clkdiv32k_ick>, <&tclkin_ck>, <&clk_rc32k_ck>, <&clk_32768_ck>, <&clk_32k_tpm_ck>; reg = <0x4200>; }; - timer2_fck: timer2_fck { + timer2_fck: timer2_fck at 4204 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>; reg = <0x4204>; }; - timer3_fck: timer3_fck { + timer3_fck: timer3_fck at 4208 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>; reg = <0x4208>; }; - timer4_fck: timer4_fck { + timer4_fck: timer4_fck at 420c { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>; reg = <0x420c>; }; - timer5_fck: timer5_fck { + timer5_fck: timer5_fck at 4210 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>; reg = <0x4210>; }; - timer6_fck: timer6_fck { + timer6_fck: timer6_fck at 4214 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>; reg = <0x4214>; }; - timer7_fck: timer7_fck { + timer7_fck: timer7_fck at 4218 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>; reg = <0x4218>; }; - wdt1_fck: wdt1_fck { + wdt1_fck: wdt1_fck at 422c { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&clk_rc32k_ck>, <&clkdiv32k_ick>;
@@ -487,14 +487,14 @@ clock-div = <2>; }; - cpsw_cpts_rft_clk: cpsw_cpts_rft_clk { + cpsw_cpts_rft_clk: cpsw_cpts_rft_clk at 4238 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&sysclk_div>, <&dpll_core_m5_ck>, <&dpll_disp_m2_ck>; reg = <0x4238>; }; - dpll_clksel_mac_clk: dpll_clksel_mac_clk { + dpll_clksel_mac_clk: dpll_clksel_mac_clk at 4234 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_core_m5_ck>;
@@ -509,14 +509,14 @@ clock-frequency = <32768>; }; - gpio0_dbclk_mux_ck: gpio0_dbclk_mux_ck { + gpio0_dbclk_mux_ck: gpio0_dbclk_mux_ck at 4240 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&clk_rc32k_ck>, <&clk_32768_ck>, <&clkdiv32k_ick>, <&clk_32k_mosc_ck>, <&clk_32k_tpm_ck>; reg = <0x4240>; }; - gpio0_dbclk: gpio0_dbclk { + gpio0_dbclk: gpio0_dbclk at 2b68 { #clock-cells = <0>; compatible = "ti,gate-clock"; clocks = <&gpio0_dbclk_mux_ck>;
@@ -524,7 +524,7 @@ reg = <0x2b68>; }; - gpio1_dbclk: gpio1_dbclk { + gpio1_dbclk: gpio1_dbclk at 8c78 { #clock-cells = <0>; compatible = "ti,gate-clock"; clocks = <&clkdiv32k_ick>;
@@ -532,7 +532,7 @@ reg = <0x8c78>; }; - gpio2_dbclk: gpio2_dbclk { + gpio2_dbclk: gpio2_dbclk at 8c80 { #clock-cells = <0>; compatible = "ti,gate-clock"; clocks = <&clkdiv32k_ick>;
@@ -540,7 +540,7 @@ reg = <0x8c80>; }; - gpio3_dbclk: gpio3_dbclk { + gpio3_dbclk: gpio3_dbclk at 8c88 { #clock-cells = <0>; compatible = "ti,gate-clock"; clocks = <&clkdiv32k_ick>;
@@ -548,7 +548,7 @@ reg = <0x8c88>; }; - gpio4_dbclk: gpio4_dbclk { + gpio4_dbclk: gpio4_dbclk at 8c90 { #clock-cells = <0>; compatible = "ti,gate-clock"; clocks = <&clkdiv32k_ick>;
@@ -556,7 +556,7 @@ reg = <0x8c90>; }; - gpio5_dbclk: gpio5_dbclk { + gpio5_dbclk: gpio5_dbclk at 8c98 { #clock-cells = <0>; compatible = "ti,gate-clock"; clocks = <&clkdiv32k_ick>;
@@ -572,7 +572,7 @@ clock-div = <2>; }; - gfx_fclk_clksel_ck: gfx_fclk_clksel_ck { + gfx_fclk_clksel_ck: gfx_fclk_clksel_ck at 423c { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&sysclk_div>, <&dpll_per_m2_ck>;
@@ -580,7 +580,7 @@ reg = <0x423c>; }; - gfx_fck_div_ck: gfx_fck_div_ck { + gfx_fck_div_ck: gfx_fck_div_ck at 423c { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&gfx_fclk_clksel_ck>;
@@ -588,7 +588,7 @@ ti,max-div = <2>; }; - disp_clk: disp_clk { + disp_clk: disp_clk at 4244 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&dpll_disp_m2_ck>, <&dpll_core_m5_ck>, <&dpll_per_m2_ck>;
@@ -596,14 +596,14 @@ ti,set-rate-parent; }; - dpll_extdev_ck: dpll_extdev_ck { + dpll_extdev_ck: dpll_extdev_ck at 2e60 { #clock-cells = <0>; compatible = "ti,am3-dpll-clock"; clocks = <&sys_clkin_ck>, <&sys_clkin_ck>; reg = <0x2e60>, <0x2e64>, <0x2e6c>; }; - dpll_extdev_m2_ck: dpll_extdev_m2_ck { + dpll_extdev_m2_ck: dpll_extdev_m2_ck at 2e70 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_extdev_ck>;
@@ -614,14 +614,14 @@ ti,invert-autoidle-bit; }; - mux_synctimer32k_ck: mux_synctimer32k_ck { + mux_synctimer32k_ck: mux_synctimer32k_ck at 4230 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&clk_32768_ck>, <&clk_32k_tpm_ck>, <&clkdiv32k_ick>; reg = <0x4230>; }; - synctimer_32kclk: synctimer_32kclk { + synctimer_32kclk: synctimer_32kclk at 2a30 { #clock-cells = <0>; compatible = "ti,gate-clock"; clocks = <&mux_synctimer32k_ck>;
@@ -629,28 +629,28 @@ reg = <0x2a30>; }; - timer8_fck: timer8_fck { + timer8_fck: timer8_fck at 421c { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>, <&clk_32k_tpm_ck>; reg = <0x421c>; }; - timer9_fck: timer9_fck { + timer9_fck: timer9_fck at 4220 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>, <&clk_32k_tpm_ck>; reg = <0x4220>; }; - timer10_fck: timer10_fck { + timer10_fck: timer10_fck at 4224 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>, <&clk_32k_tpm_ck>; reg = <0x4224>; }; - timer11_fck: timer11_fck { + timer11_fck: timer11_fck at 4228 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>, <&clk_32k_tpm_ck>;
@@ -679,7 +679,7 @@ clocks = <&dpll_ddr_ck>; }; - dpll_ddr_m4_ck: dpll_ddr_m4_ck { + dpll_ddr_m4_ck: dpll_ddr_m4_ck at 2db8 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_ddr_x2_ck>;
@@ -690,7 +690,7 @@ ti,invert-autoidle-bit; }; - dpll_per_clkdcoldo: dpll_per_clkdcoldo { + dpll_per_clkdcoldo: dpll_per_clkdcoldo at 2e14 { #clock-cells = <0>; compatible = "ti,fixed-factor-clock"; clocks = <&dpll_per_ck>;
@@ -701,7 +701,7 @@ ti,invert-autoidle-bit; }; - dll_aging_clk_div: dll_aging_clk_div { + dll_aging_clk_div: dll_aging_clk_div at 4250 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&sys_clkin_ck>;
@@ -733,14 +733,14 @@ clock-div = <2>; }; - usbphy_32khz_clkmux: usbphy_32khz_clkmux { + usbphy_32khz_clkmux: usbphy_32khz_clkmux at 4260 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&clk_32768_ck>, <&clk_32k_tpm_ck>; reg = <0x4260>; }; - usb_phy0_always_on_clk32k: usb_phy0_always_on_clk32k { + usb_phy0_always_on_clk32k: usb_phy0_always_on_clk32k at 2a40 { #clock-cells = <0>; compatible = "ti,gate-clock"; clocks = <&usbphy_32khz_clkmux>;
@@ -748,7 +748,7 @@ reg = <0x2a40>; }; - usb_phy1_always_on_clk32k: usb_phy1_always_on_clk32k { + usb_phy1_always_on_clk32k: usb_phy1_always_on_clk32k at 2a48 { #clock-cells = <0>; compatible = "ti,gate-clock"; clocks = <&usbphy_32khz_clkmux>;
@@ -756,7 +756,7 @@ reg = <0x2a48>; }; - usb_otg_ss0_refclk960m: usb_otg_ss0_refclk960m { + usb_otg_ss0_refclk960m: usb_otg_ss0_refclk960m at 8a60 { #clock-cells = <0>; compatible = "ti,gate-clock"; clocks = <&dpll_per_clkdcoldo>;
@@ -764,7 +764,7 @@ reg = <0x8a60>; }; - usb_otg_ss1_refclk960m: usb_otg_ss1_refclk960m { + usb_otg_ss1_refclk960m: usb_otg_ss1_refclk960m at 8a68 { #clock-cells = <0>; compatible = "ti,gate-clock"; clocks = <&dpll_per_clkdcoldo>;
Signature · 1 line
1.7.9.5
PATCH 6/8 ARM: dts: dm81x: fix clock node definitions to avoid build warnings
In reply to Tero KristoUpcoming change to DT compiler is going to complain about nodes which have a reg property, but have not defined the address in their name. This patch fixes following type of warnings for DM81x clock nodes:
Warning (unit_address_vs_reg): Node /ocp/cm at 48004000/clocks/dpll3_m2_ck has a reg or ranges property, but no unit name
Signed-off-by Tero Kristo <[email protected]>
--- arch/arm/boot/dts/dm814x-clocks.dtsi | 10 ++++---- arch/arm/boot/dts/dm816x-clocks.dtsi | 42 +++++++++++++++++----------------- 2 files changed, 26 insertions(+), 26 deletions(-)
arch/arm/boot/dts/dm814x-clocks.dtsi +5 -5
@@ -5,7 +5,7 @@ */ &pllss_clocks { - timer1_fck: timer1_fck { + timer1_fck: timer1_fck at 2e0 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&sysclk18_ck &aud_clkin0_ck &aud_clkin1_ck
@@ -14,7 +14,7 @@ reg = <0x2e0>; }; - timer2_fck: timer2_fck { + timer2_fck: timer2_fck at 2e0 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&sysclk18_ck &aud_clkin0_ck &aud_clkin1_ck
@@ -23,7 +23,7 @@ reg = <0x2e0>; }; - sysclk18_ck: sysclk18_ck { + sysclk18_ck: sysclk18_ck at 2f0 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&rtcosc_ck>, <&rtcdivider_ck>;
@@ -33,7 +33,7 @@ }; &scm_clocks { - devosc_ck: devosc_ck { + devosc_ck: devosc_ck at 40 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&virt_20000000_ck>, <&virt_19200000_ck>;
@@ -121,7 +121,7 @@ clock-div = <1>; }; - mpu_clksrc_ck: mpu_clksrc_ck { + mpu_clksrc_ck: mpu_clksrc_ck at 40 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&devosc_ck>, <&rtcdivider_ck>;
arch/arm/boot/dts/dm816x-clocks.dtsi +21 -21
168 lines not on this page · raw message
Signature · 1 line
1.7.9.5
PATCH 7/8 ARM: dts: dra7: fix clock node definitions to avoid build warnings
In reply to Tero KristoUpcoming change to DT compiler is going to complain about nodes which have a reg property, but have not defined the address in their name. This patch fixes following type of warnings for DRA7 clock nodes:
Warning (unit_address_vs_reg): Node /ocp/cm at 48004000/clocks/dpll3_m2_ck has a reg or ranges property, but no unit name
Signed-off-by Tero Kristo <[email protected]>
--- arch/arm/boot/dts/dra7xx-clocks.dtsi | 376 +++++++++++++++++----------------- 1 file changed, 188 insertions(+), 188 deletions(-)
arch/arm/boot/dts/dra7xx-clocks.dtsi +188 -188
@@ -188,7 +188,7 @@ clock-frequency = <0>; }; - dpll_abe_ck: dpll_abe_ck { + dpll_abe_ck: dpll_abe_ck at 1e0 { #clock-cells = <0>; compatible = "ti,omap4-dpll-m4xen-clock"; clocks = <&abe_dpll_clk_mux>, <&abe_dpll_bypass_clk_mux>;
@@ -201,7 +201,7 @@ clocks = <&dpll_abe_ck>; }; - dpll_abe_m2x2_ck: dpll_abe_m2x2_ck { + dpll_abe_m2x2_ck: dpll_abe_m2x2_ck at 1f0 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_abe_x2_ck>;
@@ -212,7 +212,7 @@ ti,invert-autoidle-bit; }; - abe_clk: abe_clk { + abe_clk: abe_clk at 108 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_abe_m2x2_ck>;
@@ -221,7 +221,7 @@ ti,index-power-of-two; }; - dpll_abe_m2_ck: dpll_abe_m2_ck { + dpll_abe_m2_ck: dpll_abe_m2_ck at 1f0 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_abe_ck>;
@@ -232,7 +232,7 @@ ti,invert-autoidle-bit; }; - dpll_abe_m3x2_ck: dpll_abe_m3x2_ck { + dpll_abe_m3x2_ck: dpll_abe_m3x2_ck at 1f4 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_abe_x2_ck>;
@@ -243,7 +243,7 @@ ti,invert-autoidle-bit; }; - dpll_core_byp_mux: dpll_core_byp_mux { + dpll_core_byp_mux: dpll_core_byp_mux at 12c { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>;
@@ -251,7 +251,7 @@ reg = <0x012c>; }; - dpll_core_ck: dpll_core_ck { + dpll_core_ck: dpll_core_ck at 120 { #clock-cells = <0>; compatible = "ti,omap4-dpll-core-clock"; clocks = <&sys_clkin1>, <&dpll_core_byp_mux>;
@@ -264,7 +264,7 @@ clocks = <&dpll_core_ck>; }; - dpll_core_h12x2_ck: dpll_core_h12x2_ck { + dpll_core_h12x2_ck: dpll_core_h12x2_ck at 13c { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_core_x2_ck>;
@@ -283,14 +283,14 @@ clock-div = <1>; }; - dpll_mpu_ck: dpll_mpu_ck { + dpll_mpu_ck: dpll_mpu_ck at 160 { #clock-cells = <0>; compatible = "ti,omap5-mpu-dpll-clock"; clocks = <&sys_clkin1>, <&mpu_dpll_hs_clk_div>; reg = <0x0160>, <0x0164>, <0x016c>, <0x0168>; }; - dpll_mpu_m2_ck: dpll_mpu_m2_ck { + dpll_mpu_m2_ck: dpll_mpu_m2_ck at 170 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_mpu_ck>;
@@ -317,7 +317,7 @@ clock-div = <1>; }; - dpll_dsp_byp_mux: dpll_dsp_byp_mux { + dpll_dsp_byp_mux: dpll_dsp_byp_mux at 240 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&sys_clkin1>, <&dsp_dpll_hs_clk_div>;
@@ -325,14 +325,14 @@ reg = <0x0240>; }; - dpll_dsp_ck: dpll_dsp_ck { + dpll_dsp_ck: dpll_dsp_ck at 234 { #clock-cells = <0>; compatible = "ti,omap4-dpll-clock"; clocks = <&sys_clkin1>, <&dpll_dsp_byp_mux>; reg = <0x0234>, <0x0238>, <0x0240>, <0x023c>; }; - dpll_dsp_m2_ck: dpll_dsp_m2_ck { + dpll_dsp_m2_ck: dpll_dsp_m2_ck at 244 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_dsp_ck>;
@@ -351,7 +351,7 @@ clock-div = <1>; }; - dpll_iva_byp_mux: dpll_iva_byp_mux { + dpll_iva_byp_mux: dpll_iva_byp_mux at 1ac { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&sys_clkin1>, <&iva_dpll_hs_clk_div>;
@@ -359,14 +359,14 @@ reg = <0x01ac>; }; - dpll_iva_ck: dpll_iva_ck { + dpll_iva_ck: dpll_iva_ck at 1a0 { #clock-cells = <0>; compatible = "ti,omap4-dpll-clock"; clocks = <&sys_clkin1>, <&dpll_iva_byp_mux>; reg = <0x01a0>, <0x01a4>, <0x01ac>, <0x01a8>; }; - dpll_iva_m2_ck: dpll_iva_m2_ck { + dpll_iva_m2_ck: dpll_iva_m2_ck at 1b0 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_iva_ck>;
@@ -385,7 +385,7 @@ clock-div = <1>; }; - dpll_gpu_byp_mux: dpll_gpu_byp_mux { + dpll_gpu_byp_mux: dpll_gpu_byp_mux at 2e4 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>;
@@ -393,14 +393,14 @@ reg = <0x02e4>; }; - dpll_gpu_ck: dpll_gpu_ck { + dpll_gpu_ck: dpll_gpu_ck at 2d8 { #clock-cells = <0>; compatible = "ti,omap4-dpll-clock"; clocks = <&sys_clkin1>, <&dpll_gpu_byp_mux>; reg = <0x02d8>, <0x02dc>, <0x02e4>, <0x02e0>; }; - dpll_gpu_m2_ck: dpll_gpu_m2_ck { + dpll_gpu_m2_ck: dpll_gpu_m2_ck at 2e8 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_gpu_ck>;
@@ -411,7 +411,7 @@ ti,invert-autoidle-bit; }; - dpll_core_m2_ck: dpll_core_m2_ck { + dpll_core_m2_ck: dpll_core_m2_ck at 130 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_core_ck>;
@@ -430,7 +430,7 @@ clock-div = <1>; }; - dpll_ddr_byp_mux: dpll_ddr_byp_mux { + dpll_ddr_byp_mux: dpll_ddr_byp_mux at 21c { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>;
@@ -438,14 +438,14 @@ reg = <0x021c>; }; - dpll_ddr_ck: dpll_ddr_ck { + dpll_ddr_ck: dpll_ddr_ck at 210 { #clock-cells = <0>; compatible = "ti,omap4-dpll-clock"; clocks = <&sys_clkin1>, <&dpll_ddr_byp_mux>; reg = <0x0210>, <0x0214>, <0x021c>, <0x0218>; }; - dpll_ddr_m2_ck: dpll_ddr_m2_ck { + dpll_ddr_m2_ck: dpll_ddr_m2_ck at 220 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_ddr_ck>;
@@ -456,7 +456,7 @@ ti,invert-autoidle-bit; }; - dpll_gmac_byp_mux: dpll_gmac_byp_mux { + dpll_gmac_byp_mux: dpll_gmac_byp_mux at 2b4 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>;
@@ -464,14 +464,14 @@ reg = <0x02b4>; }; - dpll_gmac_ck: dpll_gmac_ck { + dpll_gmac_ck: dpll_gmac_ck at 2a8 { #clock-cells = <0>; compatible = "ti,omap4-dpll-clock"; clocks = <&sys_clkin1>, <&dpll_gmac_byp_mux>; reg = <0x02a8>, <0x02ac>, <0x02b4>, <0x02b0>; }; - dpll_gmac_m2_ck: dpll_gmac_m2_ck { + dpll_gmac_m2_ck: dpll_gmac_m2_ck at 2b8 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_gmac_ck>;
@@ -530,7 +530,7 @@ clock-div = <1>; }; - dpll_eve_byp_mux: dpll_eve_byp_mux { + dpll_eve_byp_mux: dpll_eve_byp_mux at 290 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&sys_clkin1>, <&eve_dpll_hs_clk_div>;
@@ -538,14 +538,14 @@ reg = <0x0290>; }; - dpll_eve_ck: dpll_eve_ck { + dpll_eve_ck: dpll_eve_ck at 284 { #clock-cells = <0>; compatible = "ti,omap4-dpll-clock"; clocks = <&sys_clkin1>, <&dpll_eve_byp_mux>; reg = <0x0284>, <0x0288>, <0x0290>, <0x028c>; }; - dpll_eve_m2_ck: dpll_eve_m2_ck { + dpll_eve_m2_ck: dpll_eve_m2_ck at 294 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_eve_ck>;
@@ -564,7 +564,7 @@ clock-div = <1>; }; - dpll_core_h13x2_ck: dpll_core_h13x2_ck { + dpll_core_h13x2_ck: dpll_core_h13x2_ck at 140 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_core_x2_ck>;
@@ -575,7 +575,7 @@ ti,invert-autoidle-bit; }; - dpll_core_h14x2_ck: dpll_core_h14x2_ck { + dpll_core_h14x2_ck: dpll_core_h14x2_ck at 144 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_core_x2_ck>;
@@ -586,7 +586,7 @@ ti,invert-autoidle-bit; }; - dpll_core_h22x2_ck: dpll_core_h22x2_ck { + dpll_core_h22x2_ck: dpll_core_h22x2_ck at 154 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_core_x2_ck>;
@@ -597,7 +597,7 @@ ti,invert-autoidle-bit; }; - dpll_core_h23x2_ck: dpll_core_h23x2_ck { + dpll_core_h23x2_ck: dpll_core_h23x2_ck at 158 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_core_x2_ck>;
@@ -608,7 +608,7 @@ ti,invert-autoidle-bit; }; - dpll_core_h24x2_ck: dpll_core_h24x2_ck { + dpll_core_h24x2_ck: dpll_core_h24x2_ck at 15c { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_core_x2_ck>;
@@ -625,7 +625,7 @@ clocks = <&dpll_ddr_ck>; }; - dpll_ddr_h11x2_ck: dpll_ddr_h11x2_ck { + dpll_ddr_h11x2_ck: dpll_ddr_h11x2_ck at 228 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_ddr_x2_ck>;
@@ -642,7 +642,7 @@ clocks = <&dpll_dsp_ck>; }; - dpll_dsp_m3x2_ck: dpll_dsp_m3x2_ck { + dpll_dsp_m3x2_ck: dpll_dsp_m3x2_ck at 248 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_dsp_x2_ck>;
@@ -659,7 +659,7 @@ clocks = <&dpll_gmac_ck>; }; - dpll_gmac_h11x2_ck: dpll_gmac_h11x2_ck { + dpll_gmac_h11x2_ck: dpll_gmac_h11x2_ck at 2c0 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_gmac_x2_ck>;
@@ -670,7 +670,7 @@ ti,invert-autoidle-bit; }; - dpll_gmac_h12x2_ck: dpll_gmac_h12x2_ck { + dpll_gmac_h12x2_ck: dpll_gmac_h12x2_ck at 2c4 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_gmac_x2_ck>;
@@ -681,7 +681,7 @@ ti,invert-autoidle-bit; }; - dpll_gmac_h13x2_ck: dpll_gmac_h13x2_ck { + dpll_gmac_h13x2_ck: dpll_gmac_h13x2_ck at 2c8 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_gmac_x2_ck>;
@@ -692,7 +692,7 @@ ti,invert-autoidle-bit; }; - dpll_gmac_m3x2_ck: dpll_gmac_m3x2_ck { + dpll_gmac_m3x2_ck: dpll_gmac_m3x2_ck at 2bc { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_gmac_x2_ck>;
@@ -727,7 +727,7 @@ clock-div = <1>; }; - l3_iclk_div: l3_iclk_div { + l3_iclk_div: l3_iclk_div at 100 { #clock-cells = <0>; compatible = "ti,divider-clock"; ti,max-div = <2>;
@@ -777,7 +777,7 @@ clock-div = <1>; }; - ipu1_gfclk_mux: ipu1_gfclk_mux { + ipu1_gfclk_mux: ipu1_gfclk_mux at 520 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&dpll_abe_m2x2_ck>, <&dpll_core_h22x2_ck>;
@@ -785,7 +785,7 @@ reg = <0x0520>; }; - mcasp1_ahclkr_mux: mcasp1_ahclkr_mux { + mcasp1_ahclkr_mux: mcasp1_ahclkr_mux at 550 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
@@ -793,7 +793,7 @@ reg = <0x0550>; }; - mcasp1_ahclkx_mux: mcasp1_ahclkx_mux { + mcasp1_ahclkx_mux: mcasp1_ahclkx_mux at 550 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
@@ -801,7 +801,7 @@ reg = <0x0550>; }; - mcasp1_aux_gfclk_mux: mcasp1_aux_gfclk_mux { + mcasp1_aux_gfclk_mux: mcasp1_aux_gfclk_mux at 550 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>;
@@ -809,7 +809,7 @@ reg = <0x0550>; }; - timer5_gfclk_mux: timer5_gfclk_mux { + timer5_gfclk_mux: timer5_gfclk_mux at 558 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>, <&clkoutmux0_clk_mux>;
@@ -817,7 +817,7 @@ reg = <0x0558>; }; - timer6_gfclk_mux: timer6_gfclk_mux { + timer6_gfclk_mux: timer6_gfclk_mux at 560 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>, <&clkoutmux0_clk_mux>;
@@ -825,7 +825,7 @@ reg = <0x0560>; }; - timer7_gfclk_mux: timer7_gfclk_mux { + timer7_gfclk_mux: timer7_gfclk_mux at 568 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>, <&clkoutmux0_clk_mux>;
@@ -833,7 +833,7 @@ reg = <0x0568>; }; - timer8_gfclk_mux: timer8_gfclk_mux { + timer8_gfclk_mux: timer8_gfclk_mux at 570 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>, <&clkoutmux0_clk_mux>;
@@ -841,7 +841,7 @@ reg = <0x0570>; }; - uart6_gfclk_mux: uart6_gfclk_mux { + uart6_gfclk_mux: uart6_gfclk_mux at 580 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
@@ -856,7 +856,7 @@ }; }; &prm_clocks { - sys_clkin1: sys_clkin1 { + sys_clkin1: sys_clkin1 at 110 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&virt_12000000_ck>, <&virt_20000000_ck>, <&virt_16800000_ck>, <&virt_19200000_ck>, <&virt_26000000_ck>, <&virt_27000000_ck>, <&virt_38400000_ck>;
@@ -864,28 +864,28 @@ ti,index-starts-at-one; }; - abe_dpll_sys_clk_mux: abe_dpll_sys_clk_mux { + abe_dpll_sys_clk_mux: abe_dpll_sys_clk_mux at 118 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&sys_clkin1>, <&sys_clkin2>; reg = <0x0118>; }; - abe_dpll_bypass_clk_mux: abe_dpll_bypass_clk_mux { + abe_dpll_bypass_clk_mux: abe_dpll_bypass_clk_mux at 114 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&abe_dpll_sys_clk_mux>, <&sys_32k_ck>; reg = <0x0114>; }; - abe_dpll_clk_mux: abe_dpll_clk_mux { + abe_dpll_clk_mux: abe_dpll_clk_mux at 10c { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&abe_dpll_sys_clk_mux>, <&sys_32k_ck>; reg = <0x010c>; }; - abe_24m_fclk: abe_24m_fclk { + abe_24m_fclk: abe_24m_fclk at 11c { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_abe_m2x2_ck>;
@@ -893,7 +893,7 @@ ti,dividers = <8>, <16>; }; - aess_fclk: aess_fclk { + aess_fclk: aess_fclk at 178 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&abe_clk>;
@@ -901,7 +901,7 @@ ti,max-div = <2>; }; - abe_giclk_div: abe_giclk_div { + abe_giclk_div: abe_giclk_div at 174 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&aess_fclk>;
@@ -909,7 +909,7 @@ ti,max-div = <2>; }; - abe_lp_clk_div: abe_lp_clk_div { + abe_lp_clk_div: abe_lp_clk_div at 1d8 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_abe_m2x2_ck>;
@@ -917,7 +917,7 @@ ti,dividers = <16>, <32>; }; - abe_sys_clk_div: abe_sys_clk_div { + abe_sys_clk_div: abe_sys_clk_div at 120 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&sys_clkin1>;
@@ -925,14 +925,14 @@ ti,max-div = <2>; }; - adc_gfclk_mux: adc_gfclk_mux { + adc_gfclk_mux: adc_gfclk_mux at 1dc { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&sys_clkin1>, <&sys_clkin2>, <&sys_32k_ck>; reg = <0x01dc>; }; - sys_clk1_dclk_div: sys_clk1_dclk_div { + sys_clk1_dclk_div: sys_clk1_dclk_div at 1c8 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&sys_clkin1>;
@@ -941,7 +941,7 @@ ti,index-power-of-two; }; - sys_clk2_dclk_div: sys_clk2_dclk_div { + sys_clk2_dclk_div: sys_clk2_dclk_div at 1cc { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&sys_clkin2>;
@@ -950,7 +950,7 @@ ti,index-power-of-two; }; - per_abe_x1_dclk_div: per_abe_x1_dclk_div { + per_abe_x1_dclk_div: per_abe_x1_dclk_div at 1bc { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_abe_m2_ck>;
@@ -959,7 +959,7 @@ ti,index-power-of-two; }; - dsp_gclk_div: dsp_gclk_div { + dsp_gclk_div: dsp_gclk_div at 18c { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_dsp_m2_ck>;
@@ -968,7 +968,7 @@ ti,index-power-of-two; }; - gpu_dclk: gpu_dclk { + gpu_dclk: gpu_dclk at 1a0 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_gpu_m2_ck>;
@@ -977,7 +977,7 @@ ti,index-power-of-two; }; - emif_phy_dclk_div: emif_phy_dclk_div { + emif_phy_dclk_div: emif_phy_dclk_div at 190 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_ddr_m2_ck>;
@@ -986,7 +986,7 @@ ti,index-power-of-two; }; - gmac_250m_dclk_div: gmac_250m_dclk_div { + gmac_250m_dclk_div: gmac_250m_dclk_div at 19c { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_gmac_m2_ck>;
@@ -995,7 +995,7 @@ ti,index-power-of-two; }; - l3init_480m_dclk_div: l3init_480m_dclk_div { + l3init_480m_dclk_div: l3init_480m_dclk_div at 1ac { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_usb_m2_ck>;
@@ -1004,7 +1004,7 @@ ti,index-power-of-two; }; - usb_otg_dclk_div: usb_otg_dclk_div { + usb_otg_dclk_div: usb_otg_dclk_div at 184 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&usb_otg_clkin_ck>;
@@ -1013,7 +1013,7 @@ ti,index-power-of-two; }; - sata_dclk_div: sata_dclk_div { + sata_dclk_div: sata_dclk_div at 1c0 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&sys_clkin1>;
@@ -1022,7 +1022,7 @@ ti,index-power-of-two; }; - pcie2_dclk_div: pcie2_dclk_div { + pcie2_dclk_div: pcie2_dclk_div at 1b8 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_pcie_ref_m2_ck>;
@@ -1031,7 +1031,7 @@ ti,index-power-of-two; }; - pcie_dclk_div: pcie_dclk_div { + pcie_dclk_div: pcie_dclk_div at 1b4 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&apll_pcie_m2_ck>;
@@ -1040,7 +1040,7 @@ ti,index-power-of-two; }; - emu_dclk_div: emu_dclk_div { + emu_dclk_div: emu_dclk_div at 194 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&sys_clkin1>;
@@ -1049,7 +1049,7 @@ ti,index-power-of-two; }; - secure_32k_dclk_div: secure_32k_dclk_div { + secure_32k_dclk_div: secure_32k_dclk_div at 1c4 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&secure_32k_clk_src_ck>;
@@ -1058,21 +1058,21 @@ ti,index-power-of-two; }; - clkoutmux0_clk_mux: clkoutmux0_clk_mux { + clkoutmux0_clk_mux: clkoutmux0_clk_mux at 158 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&sys_clk1_dclk_div>, <&sys_clk2_dclk_div>, <&per_abe_x1_dclk_div>, <&mpu_dclk_div>, <&dsp_gclk_div>, <&iva_dclk>, <&gpu_dclk>, <&core_dpll_out_dclk_div>, <&emif_phy_dclk_div>, <&gmac_250m_dclk_div>, <&video2_dclk_div>, <&video1_dclk_div>, <&hdmi_dclk_div>, <&func_96m_aon_dclk_div>, <&l3init_480m_dclk_div>, <&usb_otg_dclk_div>, <&sata_dclk_div>, <&pcie2_dclk_div>, <&pcie_dclk_div>, <&emu_dclk_div>, <&secure_32k_dclk_div>, <&eve_dclk_div>; reg = <0x0158>; }; - clkoutmux1_clk_mux: clkoutmux1_clk_mux { + clkoutmux1_clk_mux: clkoutmux1_clk_mux at 15c { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&sys_clk1_dclk_div>, <&sys_clk2_dclk_div>, <&per_abe_x1_dclk_div>, <&mpu_dclk_div>, <&dsp_gclk_div>, <&iva_dclk>, <&gpu_dclk>, <&core_dpll_out_dclk_div>, <&emif_phy_dclk_div>, <&gmac_250m_dclk_div>, <&video2_dclk_div>, <&video1_dclk_div>, <&hdmi_dclk_div>, <&func_96m_aon_dclk_div>, <&l3init_480m_dclk_div>, <&usb_otg_dclk_div>, <&sata_dclk_div>, <&pcie2_dclk_div>, <&pcie_dclk_div>, <&emu_dclk_div>, <&secure_32k_dclk_div>, <&eve_dclk_div>; reg = <0x015c>; }; - clkoutmux2_clk_mux: clkoutmux2_clk_mux { + clkoutmux2_clk_mux: clkoutmux2_clk_mux at 160 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&sys_clk1_dclk_div>, <&sys_clk2_dclk_div>, <&per_abe_x1_dclk_div>, <&mpu_dclk_div>, <&dsp_gclk_div>, <&iva_dclk>, <&gpu_dclk>, <&core_dpll_out_dclk_div>, <&emif_phy_dclk_div>, <&gmac_250m_dclk_div>, <&video2_dclk_div>, <&video1_dclk_div>, <&hdmi_dclk_div>, <&func_96m_aon_dclk_div>, <&l3init_480m_dclk_div>, <&usb_otg_dclk_div>, <&sata_dclk_div>, <&pcie2_dclk_div>, <&pcie_dclk_div>, <&emu_dclk_div>, <&secure_32k_dclk_div>, <&eve_dclk_div>;
@@ -1087,21 +1087,21 @@ clock-div = <2>; }; - eve_clk: eve_clk { + eve_clk: eve_clk at 180 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&dpll_eve_m2_ck>, <&dpll_dsp_m3x2_ck>; reg = <0x0180>; }; - hdmi_dpll_clk_mux: hdmi_dpll_clk_mux { + hdmi_dpll_clk_mux: hdmi_dpll_clk_mux at 164 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&sys_clkin1>, <&sys_clkin2>; reg = <0x0164>; }; - mlb_clk: mlb_clk { + mlb_clk: mlb_clk at 134 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&mlb_clkin_ck>;
@@ -1110,7 +1110,7 @@ ti,index-power-of-two; }; - mlbp_clk: mlbp_clk { + mlbp_clk: mlbp_clk at 130 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&mlbp_clkin_ck>;
@@ -1119,7 +1119,7 @@ ti,index-power-of-two; }; - per_abe_x1_gfclk2_div: per_abe_x1_gfclk2_div { + per_abe_x1_gfclk2_div: per_abe_x1_gfclk2_div at 138 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_abe_m2_ck>;
@@ -1128,7 +1128,7 @@ ti,index-power-of-two; }; - timer_sys_clk_div: timer_sys_clk_div { + timer_sys_clk_div: timer_sys_clk_div at 144 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&sys_clkin1>;
@@ -1136,28 +1136,28 @@ ti,max-div = <2>; }; - video1_dpll_clk_mux: video1_dpll_clk_mux { + video1_dpll_clk_mux: video1_dpll_clk_mux at 168 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&sys_clkin1>, <&sys_clkin2>; reg = <0x0168>; }; - video2_dpll_clk_mux: video2_dpll_clk_mux { + video2_dpll_clk_mux: video2_dpll_clk_mux at 16c { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&sys_clkin1>, <&sys_clkin2>; reg = <0x016c>; }; - wkupaon_iclk_mux: wkupaon_iclk_mux { + wkupaon_iclk_mux: wkupaon_iclk_mux at 108 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&sys_clkin1>, <&abe_lp_clk_div>; reg = <0x0108>; }; - gpio1_dbclk: gpio1_dbclk { + gpio1_dbclk: gpio1_dbclk at 1838 { #clock-cells = <0>; compatible = "ti,gate-clock"; clocks = <&sys_32k_ck>;
@@ -1165,7 +1165,7 @@ reg = <0x1838>; }; - dcan1_sys_clk_mux: dcan1_sys_clk_mux { + dcan1_sys_clk_mux: dcan1_sys_clk_mux at 1888 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&sys_clkin1>, <&sys_clkin2>;
@@ -1173,7 +1173,7 @@ reg = <0x1888>; }; - timer1_gfclk_mux: timer1_gfclk_mux { + timer1_gfclk_mux: timer1_gfclk_mux at 1840 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
@@ -1181,7 +1181,7 @@ reg = <0x1840>; }; - uart10_gfclk_mux: uart10_gfclk_mux { + uart10_gfclk_mux: uart10_gfclk_mux at 1880 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
@@ -1190,14 +1190,14 @@ }; }; &cm_core_clocks { - dpll_pcie_ref_ck: dpll_pcie_ref_ck { + dpll_pcie_ref_ck: dpll_pcie_ref_ck at 200 { #clock-cells = <0>; compatible = "ti,omap4-dpll-clock"; clocks = <&sys_clkin1>, <&sys_clkin1>; reg = <0x0200>, <0x0204>, <0x020c>, <0x0208>; }; - dpll_pcie_ref_m2ldo_ck: dpll_pcie_ref_m2ldo_ck { + dpll_pcie_ref_m2ldo_ck: dpll_pcie_ref_m2ldo_ck at 210 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_pcie_ref_ck>;
@@ -1216,7 +1216,7 @@ ti,bit-shift = <7>; }; - apll_pcie_ck: apll_pcie_ck { + apll_pcie_ck: apll_pcie_ck at 21c { #clock-cells = <0>; compatible = "ti,dra7-apll-clock"; clocks = <&apll_pcie_in_clk_mux>, <&dpll_pcie_ref_ck>;
@@ -1305,7 +1305,7 @@ clock-div = <1>; }; - dpll_per_byp_mux: dpll_per_byp_mux { + dpll_per_byp_mux: dpll_per_byp_mux at 14c { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&sys_clkin1>, <&per_dpll_hs_clk_div>;
@@ -1313,14 +1313,14 @@ reg = <0x014c>; }; - dpll_per_ck: dpll_per_ck { + dpll_per_ck: dpll_per_ck at 140 { #clock-cells = <0>; compatible = "ti,omap4-dpll-clock"; clocks = <&sys_clkin1>, <&dpll_per_byp_mux>; reg = <0x0140>, <0x0144>, <0x014c>, <0x0148>; }; - dpll_per_m2_ck: dpll_per_m2_ck { + dpll_per_m2_ck: dpll_per_m2_ck at 150 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_per_ck>;
@@ -1339,7 +1339,7 @@ clock-div = <1>; }; - dpll_usb_byp_mux: dpll_usb_byp_mux { + dpll_usb_byp_mux: dpll_usb_byp_mux at 18c { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&sys_clkin1>, <&usb_dpll_hs_clk_div>;
@@ -1347,14 +1347,14 @@ reg = <0x018c>; }; - dpll_usb_ck: dpll_usb_ck { + dpll_usb_ck: dpll_usb_ck at 180 { #clock-cells = <0>; compatible = "ti,omap4-dpll-j-type-clock"; clocks = <&sys_clkin1>, <&dpll_usb_byp_mux>; reg = <0x0180>, <0x0184>, <0x018c>, <0x0188>; }; - dpll_usb_m2_ck: dpll_usb_m2_ck { + dpll_usb_m2_ck: dpll_usb_m2_ck at 190 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_usb_ck>;
@@ -1365,7 +1365,7 @@ ti,invert-autoidle-bit; }; - dpll_pcie_ref_m2_ck: dpll_pcie_ref_m2_ck { + dpll_pcie_ref_m2_ck: dpll_pcie_ref_m2_ck at 210 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_pcie_ref_ck>;
@@ -1382,7 +1382,7 @@ clocks = <&dpll_per_ck>; }; - dpll_per_h11x2_ck: dpll_per_h11x2_ck { + dpll_per_h11x2_ck: dpll_per_h11x2_ck at 158 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_per_x2_ck>;
@@ -1393,7 +1393,7 @@ ti,invert-autoidle-bit; }; - dpll_per_h12x2_ck: dpll_per_h12x2_ck { + dpll_per_h12x2_ck: dpll_per_h12x2_ck at 15c { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_per_x2_ck>;
@@ -1404,7 +1404,7 @@ ti,invert-autoidle-bit; }; - dpll_per_h13x2_ck: dpll_per_h13x2_ck { + dpll_per_h13x2_ck: dpll_per_h13x2_ck at 160 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_per_x2_ck>;
@@ -1415,7 +1415,7 @@ ti,invert-autoidle-bit; }; - dpll_per_h14x2_ck: dpll_per_h14x2_ck { + dpll_per_h14x2_ck: dpll_per_h14x2_ck at 164 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_per_x2_ck>;
@@ -1426,7 +1426,7 @@ ti,invert-autoidle-bit; }; - dpll_per_m2x2_ck: dpll_per_m2x2_ck { + dpll_per_m2x2_ck: dpll_per_m2x2_ck at 150 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_per_x2_ck>;
@@ -1485,7 +1485,7 @@ clock-div = <2>; }; - l3init_60m_fclk: l3init_60m_fclk { + l3init_60m_fclk: l3init_60m_fclk at 104 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_usb_m2_ck>;
@@ -1493,7 +1493,7 @@ ti,dividers = <1>, <8>; }; - clkout2_clk: clkout2_clk { + clkout2_clk: clkout2_clk at 6b0 { #clock-cells = <0>; compatible = "ti,gate-clock"; clocks = <&clkoutmux2_clk_mux>;
@@ -1501,7 +1501,7 @@ reg = <0x06b0>; }; - l3init_960m_gfclk: l3init_960m_gfclk { + l3init_960m_gfclk: l3init_960m_gfclk at 6c0 { #clock-cells = <0>; compatible = "ti,gate-clock"; clocks = <&dpll_usb_clkdcoldo>;
@@ -1509,7 +1509,7 @@ reg = <0x06c0>; }; - dss_32khz_clk: dss_32khz_clk { + dss_32khz_clk: dss_32khz_clk at 1120 { #clock-cells = <0>; compatible = "ti,gate-clock"; clocks = <&sys_32k_ck>;
@@ -1517,7 +1517,7 @@ reg = <0x1120>; }; - dss_48mhz_clk: dss_48mhz_clk { + dss_48mhz_clk: dss_48mhz_clk at 1120 { #clock-cells = <0>; compatible = "ti,gate-clock"; clocks = <&func_48m_fclk>;
@@ -1525,7 +1525,7 @@ reg = <0x1120>; }; - dss_dss_clk: dss_dss_clk { + dss_dss_clk: dss_dss_clk at 1120 { #clock-cells = <0>; compatible = "ti,gate-clock"; clocks = <&dpll_per_h12x2_ck>;
@@ -1534,7 +1534,7 @@ ti,set-rate-parent; }; - dss_hdmi_clk: dss_hdmi_clk { + dss_hdmi_clk: dss_hdmi_clk at 1120 { #clock-cells = <0>; compatible = "ti,gate-clock"; clocks = <&hdmi_dpll_clk_mux>;
@@ -1542,7 +1542,7 @@ reg = <0x1120>; }; - dss_video1_clk: dss_video1_clk { + dss_video1_clk: dss_video1_clk at 1120 { #clock-cells = <0>; compatible = "ti,gate-clock"; clocks = <&video1_dpll_clk_mux>;
@@ -1550,7 +1550,7 @@ reg = <0x1120>; }; - dss_video2_clk: dss_video2_clk { + dss_video2_clk: dss_video2_clk at 1120 { #clock-cells = <0>; compatible = "ti,gate-clock"; clocks = <&video2_dpll_clk_mux>;
@@ -1558,7 +1558,7 @@ reg = <0x1120>; }; - gpio2_dbclk: gpio2_dbclk { + gpio2_dbclk: gpio2_dbclk at 1760 { #clock-cells = <0>; compatible = "ti,gate-clock"; clocks = <&sys_32k_ck>;
@@ -1566,7 +1566,7 @@ reg = <0x1760>; }; - gpio3_dbclk: gpio3_dbclk { + gpio3_dbclk: gpio3_dbclk at 1768 { #clock-cells = <0>; compatible = "ti,gate-clock"; clocks = <&sys_32k_ck>;
@@ -1574,7 +1574,7 @@ reg = <0x1768>; }; - gpio4_dbclk: gpio4_dbclk { + gpio4_dbclk: gpio4_dbclk at 1770 { #clock-cells = <0>; compatible = "ti,gate-clock"; clocks = <&sys_32k_ck>;
@@ -1582,7 +1582,7 @@ reg = <0x1770>; }; - gpio5_dbclk: gpio5_dbclk { + gpio5_dbclk: gpio5_dbclk at 1778 { #clock-cells = <0>; compatible = "ti,gate-clock"; clocks = <&sys_32k_ck>;
@@ -1590,7 +1590,7 @@ reg = <0x1778>; }; - gpio6_dbclk: gpio6_dbclk { + gpio6_dbclk: gpio6_dbclk at 1780 { #clock-cells = <0>; compatible = "ti,gate-clock"; clocks = <&sys_32k_ck>;
@@ -1598,7 +1598,7 @@ reg = <0x1780>; }; - gpio7_dbclk: gpio7_dbclk { + gpio7_dbclk: gpio7_dbclk at 1810 { #clock-cells = <0>; compatible = "ti,gate-clock"; clocks = <&sys_32k_ck>;
@@ -1606,7 +1606,7 @@ reg = <0x1810>; }; - gpio8_dbclk: gpio8_dbclk { + gpio8_dbclk: gpio8_dbclk at 1818 { #clock-cells = <0>; compatible = "ti,gate-clock"; clocks = <&sys_32k_ck>;
@@ -1614,7 +1614,7 @@ reg = <0x1818>; }; - mmc1_clk32k: mmc1_clk32k { + mmc1_clk32k: mmc1_clk32k at 1328 { #clock-cells = <0>; compatible = "ti,gate-clock"; clocks = <&sys_32k_ck>;
@@ -1622,7 +1622,7 @@ reg = <0x1328>; }; - mmc2_clk32k: mmc2_clk32k { + mmc2_clk32k: mmc2_clk32k at 1330 { #clock-cells = <0>; compatible = "ti,gate-clock"; clocks = <&sys_32k_ck>;
@@ -1630,7 +1630,7 @@ reg = <0x1330>; }; - mmc3_clk32k: mmc3_clk32k { + mmc3_clk32k: mmc3_clk32k at 1820 { #clock-cells = <0>; compatible = "ti,gate-clock"; clocks = <&sys_32k_ck>;
@@ -1638,7 +1638,7 @@ reg = <0x1820>; }; - mmc4_clk32k: mmc4_clk32k { + mmc4_clk32k: mmc4_clk32k at 1828 { #clock-cells = <0>; compatible = "ti,gate-clock"; clocks = <&sys_32k_ck>;
@@ -1646,7 +1646,7 @@ reg = <0x1828>; }; - sata_ref_clk: sata_ref_clk { + sata_ref_clk: sata_ref_clk at 1388 { #clock-cells = <0>; compatible = "ti,gate-clock"; clocks = <&sys_clkin1>;
@@ -1654,7 +1654,7 @@ reg = <0x1388>; }; - usb_otg_ss1_refclk960m: usb_otg_ss1_refclk960m { + usb_otg_ss1_refclk960m: usb_otg_ss1_refclk960m at 13f0 { #clock-cells = <0>; compatible = "ti,gate-clock"; clocks = <&l3init_960m_gfclk>;
@@ -1662,7 +1662,7 @@ reg = <0x13f0>; }; - usb_otg_ss2_refclk960m: usb_otg_ss2_refclk960m { + usb_otg_ss2_refclk960m: usb_otg_ss2_refclk960m at 1340 { #clock-cells = <0>; compatible = "ti,gate-clock"; clocks = <&l3init_960m_gfclk>;
@@ -1670,7 +1670,7 @@ reg = <0x1340>; }; - usb_phy1_always_on_clk32k: usb_phy1_always_on_clk32k { + usb_phy1_always_on_clk32k: usb_phy1_always_on_clk32k at 640 { #clock-cells = <0>; compatible = "ti,gate-clock"; clocks = <&sys_32k_ck>;
@@ -1678,7 +1678,7 @@ reg = <0x0640>; }; - usb_phy2_always_on_clk32k: usb_phy2_always_on_clk32k { + usb_phy2_always_on_clk32k: usb_phy2_always_on_clk32k at 688 { #clock-cells = <0>; compatible = "ti,gate-clock"; clocks = <&sys_32k_ck>;
@@ -1686,7 +1686,7 @@ reg = <0x0688>; }; - usb_phy3_always_on_clk32k: usb_phy3_always_on_clk32k { + usb_phy3_always_on_clk32k: usb_phy3_always_on_clk32k at 698 { #clock-cells = <0>; compatible = "ti,gate-clock"; clocks = <&sys_32k_ck>;
@@ -1694,7 +1694,7 @@ reg = <0x0698>; }; - atl_dpll_clk_mux: atl_dpll_clk_mux { + atl_dpll_clk_mux: atl_dpll_clk_mux at c00 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&sys_32k_ck>, <&video1_clkin_ck>, <&video2_clkin_ck>, <&hdmi_clkin_ck>;
@@ -1702,7 +1702,7 @@ reg = <0x0c00>; }; - atl_gfclk_mux: atl_gfclk_mux { + atl_gfclk_mux: atl_gfclk_mux at c00 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&l3_iclk_div>, <&dpll_abe_m2_ck>, <&atl_dpll_clk_mux>;
@@ -1710,7 +1710,7 @@ reg = <0x0c00>; }; - gmac_gmii_ref_clk_div: gmac_gmii_ref_clk_div { + gmac_gmii_ref_clk_div: gmac_gmii_ref_clk_div at 13d0 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_gmac_m2_ck>;
@@ -1719,7 +1719,7 @@ ti,dividers = <2>; }; - gmac_rft_clk_mux: gmac_rft_clk_mux { + gmac_rft_clk_mux: gmac_rft_clk_mux at 13d0 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&video1_clkin_ck>, <&video2_clkin_ck>, <&dpll_abe_m2_ck>, <&hdmi_clkin_ck>, <&l3_iclk_div>;
@@ -1727,7 +1727,7 @@ reg = <0x13d0>; }; - gpu_core_gclk_mux: gpu_core_gclk_mux { + gpu_core_gclk_mux: gpu_core_gclk_mux at 1220 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&dpll_core_h14x2_ck>, <&dpll_per_h14x2_ck>, <&dpll_gpu_m2_ck>;
@@ -1735,7 +1735,7 @@ reg = <0x1220>; }; - gpu_hyd_gclk_mux: gpu_hyd_gclk_mux { + gpu_hyd_gclk_mux: gpu_hyd_gclk_mux at 1220 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&dpll_core_h14x2_ck>, <&dpll_per_h14x2_ck>, <&dpll_gpu_m2_ck>;
@@ -1743,7 +1743,7 @@ reg = <0x1220>; }; - l3instr_ts_gclk_div: l3instr_ts_gclk_div { + l3instr_ts_gclk_div: l3instr_ts_gclk_div at e50 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&wkupaon_iclk_mux>;
@@ -1752,7 +1752,7 @@ ti,dividers = <8>, <16>, <32>; }; - mcasp2_ahclkr_mux: mcasp2_ahclkr_mux { + mcasp2_ahclkr_mux: mcasp2_ahclkr_mux at 1860 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
@@ -1760,7 +1760,7 @@ reg = <0x1860>; }; - mcasp2_ahclkx_mux: mcasp2_ahclkx_mux { + mcasp2_ahclkx_mux: mcasp2_ahclkx_mux at 1860 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
@@ -1768,7 +1768,7 @@ reg = <0x1860>; }; - mcasp2_aux_gfclk_mux: mcasp2_aux_gfclk_mux { + mcasp2_aux_gfclk_mux: mcasp2_aux_gfclk_mux at 1860 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>;
@@ -1776,7 +1776,7 @@ reg = <0x1860>; }; - mcasp3_ahclkx_mux: mcasp3_ahclkx_mux { + mcasp3_ahclkx_mux: mcasp3_ahclkx_mux at 1868 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
@@ -1784,7 +1784,7 @@ reg = <0x1868>; }; - mcasp3_aux_gfclk_mux: mcasp3_aux_gfclk_mux { + mcasp3_aux_gfclk_mux: mcasp3_aux_gfclk_mux at 1868 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>;
@@ -1792,7 +1792,7 @@ reg = <0x1868>; }; - mcasp4_ahclkx_mux: mcasp4_ahclkx_mux { + mcasp4_ahclkx_mux: mcasp4_ahclkx_mux at 1898 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
@@ -1800,7 +1800,7 @@ reg = <0x1898>; }; - mcasp4_aux_gfclk_mux: mcasp4_aux_gfclk_mux { + mcasp4_aux_gfclk_mux: mcasp4_aux_gfclk_mux at 1898 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>;
@@ -1808,7 +1808,7 @@ reg = <0x1898>; }; - mcasp5_ahclkx_mux: mcasp5_ahclkx_mux { + mcasp5_ahclkx_mux: mcasp5_ahclkx_mux at 1878 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
@@ -1816,7 +1816,7 @@ reg = <0x1878>; }; - mcasp5_aux_gfclk_mux: mcasp5_aux_gfclk_mux { + mcasp5_aux_gfclk_mux: mcasp5_aux_gfclk_mux at 1878 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>;
@@ -1824,7 +1824,7 @@ reg = <0x1878>; }; - mcasp6_ahclkx_mux: mcasp6_ahclkx_mux { + mcasp6_ahclkx_mux: mcasp6_ahclkx_mux at 1904 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
@@ -1832,7 +1832,7 @@ reg = <0x1904>; }; - mcasp6_aux_gfclk_mux: mcasp6_aux_gfclk_mux { + mcasp6_aux_gfclk_mux: mcasp6_aux_gfclk_mux at 1904 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>;
@@ -1840,7 +1840,7 @@ reg = <0x1904>; }; - mcasp7_ahclkx_mux: mcasp7_ahclkx_mux { + mcasp7_ahclkx_mux: mcasp7_ahclkx_mux at 1908 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
@@ -1848,7 +1848,7 @@ reg = <0x1908>; }; - mcasp7_aux_gfclk_mux: mcasp7_aux_gfclk_mux { + mcasp7_aux_gfclk_mux: mcasp7_aux_gfclk_mux at 1908 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>;
@@ -1856,7 +1856,7 @@ reg = <0x1908>; }; - mcasp8_ahclk_mux: mcasp8_ahclk_mux { + mcasp8_ahclk_mux: mcasp8_ahclk_mux at 1890 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
@@ -1864,7 +1864,7 @@ reg = <0x1890>; }; - mcasp8_aux_gfclk_mux: mcasp8_aux_gfclk_mux { + mcasp8_aux_gfclk_mux: mcasp8_aux_gfclk_mux at 1890 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>;
@@ -1872,7 +1872,7 @@ reg = <0x1890>; }; - mmc1_fclk_mux: mmc1_fclk_mux { + mmc1_fclk_mux: mmc1_fclk_mux at 1328 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&func_128m_clk>, <&dpll_per_m2x2_ck>;
@@ -1880,7 +1880,7 @@ reg = <0x1328>; }; - mmc1_fclk_div: mmc1_fclk_div { + mmc1_fclk_div: mmc1_fclk_div at 1328 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&mmc1_fclk_mux>;
@@ -1890,7 +1890,7 @@ ti,index-power-of-two; }; - mmc2_fclk_mux: mmc2_fclk_mux { + mmc2_fclk_mux: mmc2_fclk_mux at 1330 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&func_128m_clk>, <&dpll_per_m2x2_ck>;
@@ -1898,7 +1898,7 @@ reg = <0x1330>; }; - mmc2_fclk_div: mmc2_fclk_div { + mmc2_fclk_div: mmc2_fclk_div at 1330 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&mmc2_fclk_mux>;
@@ -1908,7 +1908,7 @@ ti,index-power-of-two; }; - mmc3_gfclk_mux: mmc3_gfclk_mux { + mmc3_gfclk_mux: mmc3_gfclk_mux at 1820 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
@@ -1916,7 +1916,7 @@ reg = <0x1820>; }; - mmc3_gfclk_div: mmc3_gfclk_div { + mmc3_gfclk_div: mmc3_gfclk_div at 1820 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&mmc3_gfclk_mux>;
@@ -1926,7 +1926,7 @@ ti,index-power-of-two; }; - mmc4_gfclk_mux: mmc4_gfclk_mux { + mmc4_gfclk_mux: mmc4_gfclk_mux at 1828 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
@@ -1934,7 +1934,7 @@ reg = <0x1828>; }; - mmc4_gfclk_div: mmc4_gfclk_div { + mmc4_gfclk_div: mmc4_gfclk_div at 1828 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&mmc4_gfclk_mux>;
@@ -1944,7 +1944,7 @@ ti,index-power-of-two; }; - qspi_gfclk_mux: qspi_gfclk_mux { + qspi_gfclk_mux: qspi_gfclk_mux at 1838 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&func_128m_clk>, <&dpll_per_h13x2_ck>;
@@ -1952,7 +1952,7 @@ reg = <0x1838>; }; - qspi_gfclk_div: qspi_gfclk_div { + qspi_gfclk_div: qspi_gfclk_div at 1838 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&qspi_gfclk_mux>;
@@ -1962,7 +1962,7 @@ ti,index-power-of-two; }; - timer10_gfclk_mux: timer10_gfclk_mux { + timer10_gfclk_mux: timer10_gfclk_mux at 1728 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
@@ -1970,7 +1970,7 @@ reg = <0x1728>; }; - timer11_gfclk_mux: timer11_gfclk_mux { + timer11_gfclk_mux: timer11_gfclk_mux at 1730 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
@@ -1978,7 +1978,7 @@ reg = <0x1730>; }; - timer13_gfclk_mux: timer13_gfclk_mux { + timer13_gfclk_mux: timer13_gfclk_mux at 17c8 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
@@ -1986,7 +1986,7 @@ reg = <0x17c8>; }; - timer14_gfclk_mux: timer14_gfclk_mux { + timer14_gfclk_mux: timer14_gfclk_mux at 17d0 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
@@ -1994,7 +1994,7 @@ reg = <0x17d0>; }; - timer15_gfclk_mux: timer15_gfclk_mux { + timer15_gfclk_mux: timer15_gfclk_mux at 17d8 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
@@ -2002,7 +2002,7 @@ reg = <0x17d8>; }; - timer16_gfclk_mux: timer16_gfclk_mux { + timer16_gfclk_mux: timer16_gfclk_mux at 1830 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
@@ -2010,7 +2010,7 @@ reg = <0x1830>; }; - timer2_gfclk_mux: timer2_gfclk_mux { + timer2_gfclk_mux: timer2_gfclk_mux at 1738 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
@@ -2018,7 +2018,7 @@ reg = <0x1738>; }; - timer3_gfclk_mux: timer3_gfclk_mux { + timer3_gfclk_mux: timer3_gfclk_mux at 1740 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
@@ -2026,7 +2026,7 @@ reg = <0x1740>; }; - timer4_gfclk_mux: timer4_gfclk_mux { + timer4_gfclk_mux: timer4_gfclk_mux at 1748 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
@@ -2034,7 +2034,7 @@ reg = <0x1748>; }; - timer9_gfclk_mux: timer9_gfclk_mux { + timer9_gfclk_mux: timer9_gfclk_mux at 1750 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
@@ -2042,7 +2042,7 @@ reg = <0x1750>; }; - uart1_gfclk_mux: uart1_gfclk_mux { + uart1_gfclk_mux: uart1_gfclk_mux at 1840 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
@@ -2050,7 +2050,7 @@ reg = <0x1840>; }; - uart2_gfclk_mux: uart2_gfclk_mux { + uart2_gfclk_mux: uart2_gfclk_mux at 1848 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
@@ -2058,7 +2058,7 @@ reg = <0x1848>; }; - uart3_gfclk_mux: uart3_gfclk_mux { + uart3_gfclk_mux: uart3_gfclk_mux at 1850 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
@@ -2066,7 +2066,7 @@ reg = <0x1850>; }; - uart4_gfclk_mux: uart4_gfclk_mux { + uart4_gfclk_mux: uart4_gfclk_mux at 1858 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
@@ -2074,7 +2074,7 @@ reg = <0x1858>; }; - uart5_gfclk_mux: uart5_gfclk_mux { + uart5_gfclk_mux: uart5_gfclk_mux at 1870 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
@@ -2082,7 +2082,7 @@ reg = <0x1870>; }; - uart7_gfclk_mux: uart7_gfclk_mux { + uart7_gfclk_mux: uart7_gfclk_mux at 18d0 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
@@ -2090,7 +2090,7 @@ reg = <0x18d0>; }; - uart8_gfclk_mux: uart8_gfclk_mux { + uart8_gfclk_mux: uart8_gfclk_mux at 18e0 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
@@ -2098,7 +2098,7 @@ reg = <0x18e0>; }; - uart9_gfclk_mux: uart9_gfclk_mux { + uart9_gfclk_mux: uart9_gfclk_mux at 18e8 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
@@ -2106,7 +2106,7 @@ reg = <0x18e8>; }; - vip1_gclk_mux: vip1_gclk_mux { + vip1_gclk_mux: vip1_gclk_mux at 1020 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&l3_iclk_div>, <&dpll_core_h23x2_ck>;
@@ -2114,7 +2114,7 @@ reg = <0x1020>; }; - vip2_gclk_mux: vip2_gclk_mux { + vip2_gclk_mux: vip2_gclk_mux at 1028 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&l3_iclk_div>, <&dpll_core_h23x2_ck>;
@@ -2122,7 +2122,7 @@ reg = <0x1028>; }; - vip3_gclk_mux: vip3_gclk_mux { + vip3_gclk_mux: vip3_gclk_mux at 1030 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&l3_iclk_div>, <&dpll_core_h23x2_ck>;
@@ -2139,7 +2139,7 @@ }; &scm_conf_clocks { - dss_deshdcp_clk: dss_deshdcp_clk { + dss_deshdcp_clk: dss_deshdcp_clk at 558 { #clock-cells = <0>; compatible = "ti,gate-clock"; clocks = <&l3_iclk_div>;
@@ -2147,7 +2147,7 @@ reg = <0x558>; }; - ehrpwm0_tbclk: ehrpwm0_tbclk { + ehrpwm0_tbclk: ehrpwm0_tbclk at 558 { #clock-cells = <0>; compatible = "ti,gate-clock"; clocks = <&l4_root_clk_div>;
@@ -2155,7 +2155,7 @@ reg = <0x0558>; }; - ehrpwm1_tbclk: ehrpwm1_tbclk { + ehrpwm1_tbclk: ehrpwm1_tbclk at 558 { #clock-cells = <0>; compatible = "ti,gate-clock"; clocks = <&l4_root_clk_div>;
@@ -2163,7 +2163,7 @@ reg = <0x0558>; }; - ehrpwm2_tbclk: ehrpwm2_tbclk { + ehrpwm2_tbclk: ehrpwm2_tbclk at 558 { #clock-cells = <0>; compatible = "ti,gate-clock"; clocks = <&l4_root_clk_div>;
Signature · 1 line
1.7.9.5
PATCH 8/8 ARM: dts: omap5: fix clock node definitions to avoid build warnings
In reply to Tero KristoUpcoming change to DT compiler is going to complain about nodes which have a reg property, but have not defined the address in their name. This patch fixes following type of warnings for OMAP5 clock nodes:
Warning (unit_address_vs_reg): Node /ocp/cm at 48004000/clocks/dpll3_m2_ck has a reg or ranges property, but no unit name
Signed-off-by Tero Kristo <[email protected]>
--- arch/arm/boot/dts/omap54xx-clocks.dtsi | 260 ++++++++++++++++---------------- 1 file changed, 130 insertions(+), 130 deletions(-)
arch/arm/boot/dts/omap54xx-clocks.dtsi +130 -130
@@ -14,7 +14,7 @@ clock-frequency = <12000000>; }; - pad_clks_ck: pad_clks_ck { + pad_clks_ck: pad_clks_ck at 108 { #clock-cells = <0>; compatible = "ti,gate-clock"; clocks = <&pad_clks_src_ck>;
@@ -34,7 +34,7 @@ clock-frequency = <12000000>; }; - slimbus_clk: slimbus_clk { + slimbus_clk: slimbus_clk at 108 { #clock-cells = <0>; compatible = "ti,gate-clock"; clocks = <&slimbus_src_clk>;
@@ -102,7 +102,7 @@ clock-frequency = <60000000>; }; - dpll_abe_ck: dpll_abe_ck { + dpll_abe_ck: dpll_abe_ck at 1e0 { #clock-cells = <0>; compatible = "ti,omap4-dpll-m4xen-clock"; clocks = <&abe_dpll_clk_mux>, <&abe_dpll_bypass_clk_mux>;
@@ -115,7 +115,7 @@ clocks = <&dpll_abe_ck>; }; - dpll_abe_m2x2_ck: dpll_abe_m2x2_ck { + dpll_abe_m2x2_ck: dpll_abe_m2x2_ck at 1f0 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_abe_x2_ck>;
@@ -132,7 +132,7 @@ clock-div = <8>; }; - abe_clk: abe_clk { + abe_clk: abe_clk at 108 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_abe_m2x2_ck>;
@@ -141,7 +141,7 @@ ti,index-power-of-two; }; - abe_iclk: abe_iclk { + abe_iclk: abe_iclk at 528 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&aess_fclk>;
@@ -158,7 +158,7 @@ clock-div = <16>; }; - dpll_abe_m3x2_ck: dpll_abe_m3x2_ck { + dpll_abe_m3x2_ck: dpll_abe_m3x2_ck at 1f4 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_abe_x2_ck>;
@@ -167,7 +167,7 @@ ti,index-starts-at-one; }; - dpll_core_byp_mux: dpll_core_byp_mux { + dpll_core_byp_mux: dpll_core_byp_mux at 12c { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&sys_clkin>, <&dpll_abe_m3x2_ck>;
@@ -175,7 +175,7 @@ reg = <0x012c>; }; - dpll_core_ck: dpll_core_ck { + dpll_core_ck: dpll_core_ck at 120 { #clock-cells = <0>; compatible = "ti,omap4-dpll-core-clock"; clocks = <&sys_clkin>, <&dpll_core_byp_mux>;
@@ -188,7 +188,7 @@ clocks = <&dpll_core_ck>; }; - dpll_core_h21x2_ck: dpll_core_h21x2_ck { + dpll_core_h21x2_ck: dpll_core_h21x2_ck at 150 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_core_x2_ck>;
@@ -213,7 +213,7 @@ clock-div = <2>; }; - dpll_core_h11x2_ck: dpll_core_h11x2_ck { + dpll_core_h11x2_ck: dpll_core_h11x2_ck at 138 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_core_x2_ck>;
@@ -222,7 +222,7 @@ ti,index-starts-at-one; }; - dpll_core_h12x2_ck: dpll_core_h12x2_ck { + dpll_core_h12x2_ck: dpll_core_h12x2_ck at 13c { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_core_x2_ck>;
@@ -231,7 +231,7 @@ ti,index-starts-at-one; }; - dpll_core_h13x2_ck: dpll_core_h13x2_ck { + dpll_core_h13x2_ck: dpll_core_h13x2_ck at 140 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_core_x2_ck>;
@@ -240,7 +240,7 @@ ti,index-starts-at-one; }; - dpll_core_h14x2_ck: dpll_core_h14x2_ck { + dpll_core_h14x2_ck: dpll_core_h14x2_ck at 144 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_core_x2_ck>;
@@ -249,7 +249,7 @@ ti,index-starts-at-one; }; - dpll_core_h22x2_ck: dpll_core_h22x2_ck { + dpll_core_h22x2_ck: dpll_core_h22x2_ck at 154 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_core_x2_ck>;
@@ -258,7 +258,7 @@ ti,index-starts-at-one; }; - dpll_core_h23x2_ck: dpll_core_h23x2_ck { + dpll_core_h23x2_ck: dpll_core_h23x2_ck at 158 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_core_x2_ck>;
@@ -267,7 +267,7 @@ ti,index-starts-at-one; }; - dpll_core_h24x2_ck: dpll_core_h24x2_ck { + dpll_core_h24x2_ck: dpll_core_h24x2_ck at 15c { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_core_x2_ck>;
@@ -276,7 +276,7 @@ ti,index-starts-at-one; }; - dpll_core_m2_ck: dpll_core_m2_ck { + dpll_core_m2_ck: dpll_core_m2_ck at 130 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_core_ck>;
@@ -285,7 +285,7 @@ ti,index-starts-at-one; }; - dpll_core_m3x2_ck: dpll_core_m3x2_ck { + dpll_core_m3x2_ck: dpll_core_m3x2_ck at 134 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_core_x2_ck>;
@@ -302,7 +302,7 @@ clock-div = <1>; }; - dpll_iva_byp_mux: dpll_iva_byp_mux { + dpll_iva_byp_mux: dpll_iva_byp_mux at 1ac { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&sys_clkin>, <&iva_dpll_hs_clk_div>;
@@ -310,7 +310,7 @@ reg = <0x01ac>; }; - dpll_iva_ck: dpll_iva_ck { + dpll_iva_ck: dpll_iva_ck at 1a0 { #clock-cells = <0>; compatible = "ti,omap4-dpll-clock"; clocks = <&sys_clkin>, <&dpll_iva_byp_mux>;
@@ -323,7 +323,7 @@ clocks = <&dpll_iva_ck>; }; - dpll_iva_h11x2_ck: dpll_iva_h11x2_ck { + dpll_iva_h11x2_ck: dpll_iva_h11x2_ck at 1b8 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_iva_x2_ck>;
@@ -332,7 +332,7 @@ ti,index-starts-at-one; }; - dpll_iva_h12x2_ck: dpll_iva_h12x2_ck { + dpll_iva_h12x2_ck: dpll_iva_h12x2_ck at 1bc { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_iva_x2_ck>;
@@ -349,14 +349,14 @@ clock-div = <1>; }; - dpll_mpu_ck: dpll_mpu_ck { + dpll_mpu_ck: dpll_mpu_ck at 160 { #clock-cells = <0>; compatible = "ti,omap5-mpu-dpll-clock"; clocks = <&sys_clkin>, <&mpu_dpll_hs_clk_div>; reg = <0x0160>, <0x0164>, <0x016c>, <0x0168>; }; - dpll_mpu_m2_ck: dpll_mpu_m2_ck { + dpll_mpu_m2_ck: dpll_mpu_m2_ck at 170 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_mpu_ck>;
@@ -381,7 +381,7 @@ clock-div = <3>; }; - l3_iclk_div: l3_iclk_div { + l3_iclk_div: l3_iclk_div at 100 { #clock-cells = <0>; compatible = "ti,divider-clock"; ti,max-div = <2>;
@@ -399,7 +399,7 @@ clock-div = <1>; }; - l4_root_clk_div: l4_root_clk_div { + l4_root_clk_div: l4_root_clk_div at 100 { #clock-cells = <0>; compatible = "ti,divider-clock"; ti,max-div = <2>;
@@ -409,7 +409,7 @@ ti,index-power-of-two; }; - slimbus1_slimbus_clk: slimbus1_slimbus_clk { + slimbus1_slimbus_clk: slimbus1_slimbus_clk at 560 { #clock-cells = <0>; compatible = "ti,gate-clock"; clocks = <&slimbus_clk>;
@@ -417,7 +417,7 @@ reg = <0x0560>; }; - aess_fclk: aess_fclk { + aess_fclk: aess_fclk at 528 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&abe_clk>;
@@ -426,7 +426,7 @@ reg = <0x0528>; }; - dmic_sync_mux_ck: dmic_sync_mux_ck { + dmic_sync_mux_ck: dmic_sync_mux_ck at 538 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&abe_24m_fclk>, <&dss_syc_gfclk_div>, <&func_24m_clk>;
@@ -434,7 +434,7 @@ reg = <0x0538>; }; - dmic_gfclk: dmic_gfclk { + dmic_gfclk: dmic_gfclk at 538 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&dmic_sync_mux_ck>, <&pad_clks_ck>, <&slimbus_clk>;
@@ -442,7 +442,7 @@ reg = <0x0538>; }; - mcasp_sync_mux_ck: mcasp_sync_mux_ck { + mcasp_sync_mux_ck: mcasp_sync_mux_ck at 540 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&abe_24m_fclk>, <&dss_syc_gfclk_div>, <&func_24m_clk>;
@@ -450,7 +450,7 @@ reg = <0x0540>; }; - mcasp_gfclk: mcasp_gfclk { + mcasp_gfclk: mcasp_gfclk at 540 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&mcasp_sync_mux_ck>, <&pad_clks_ck>, <&slimbus_clk>;
@@ -458,7 +458,7 @@ reg = <0x0540>; }; - mcbsp1_sync_mux_ck: mcbsp1_sync_mux_ck { + mcbsp1_sync_mux_ck: mcbsp1_sync_mux_ck at 548 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&abe_24m_fclk>, <&dss_syc_gfclk_div>, <&func_24m_clk>;
@@ -466,7 +466,7 @@ reg = <0x0548>; }; - mcbsp1_gfclk: mcbsp1_gfclk { + mcbsp1_gfclk: mcbsp1_gfclk at 548 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&mcbsp1_sync_mux_ck>, <&pad_clks_ck>, <&slimbus_clk>;
@@ -474,7 +474,7 @@ reg = <0x0548>; }; - mcbsp2_sync_mux_ck: mcbsp2_sync_mux_ck { + mcbsp2_sync_mux_ck: mcbsp2_sync_mux_ck at 550 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&abe_24m_fclk>, <&dss_syc_gfclk_div>, <&func_24m_clk>;
@@ -482,7 +482,7 @@ reg = <0x0550>; }; - mcbsp2_gfclk: mcbsp2_gfclk { + mcbsp2_gfclk: mcbsp2_gfclk at 550 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&mcbsp2_sync_mux_ck>, <&pad_clks_ck>, <&slimbus_clk>;
@@ -490,7 +490,7 @@ reg = <0x0550>; }; - mcbsp3_sync_mux_ck: mcbsp3_sync_mux_ck { + mcbsp3_sync_mux_ck: mcbsp3_sync_mux_ck at 558 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&abe_24m_fclk>, <&dss_syc_gfclk_div>, <&func_24m_clk>;
@@ -498,7 +498,7 @@ reg = <0x0558>; }; - mcbsp3_gfclk: mcbsp3_gfclk { + mcbsp3_gfclk: mcbsp3_gfclk at 558 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&mcbsp3_sync_mux_ck>, <&pad_clks_ck>, <&slimbus_clk>;
@@ -506,7 +506,7 @@ reg = <0x0558>; }; - timer5_gfclk_mux: timer5_gfclk_mux { + timer5_gfclk_mux: timer5_gfclk_mux at 568 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&dss_syc_gfclk_div>, <&sys_32k_ck>;
@@ -514,7 +514,7 @@ reg = <0x0568>; }; - timer6_gfclk_mux: timer6_gfclk_mux { + timer6_gfclk_mux: timer6_gfclk_mux at 570 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&dss_syc_gfclk_div>, <&sys_32k_ck>;
@@ -522,7 +522,7 @@ reg = <0x0570>; }; - timer7_gfclk_mux: timer7_gfclk_mux { + timer7_gfclk_mux: timer7_gfclk_mux at 578 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&dss_syc_gfclk_div>, <&sys_32k_ck>;
@@ -530,7 +530,7 @@ reg = <0x0578>; }; - timer8_gfclk_mux: timer8_gfclk_mux { + timer8_gfclk_mux: timer8_gfclk_mux at 580 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&dss_syc_gfclk_div>, <&sys_32k_ck>;
@@ -545,7 +545,7 @@ }; }; &prm_clocks { - sys_clkin: sys_clkin { + sys_clkin: sys_clkin at 110 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&virt_12000000_ck>, <&virt_13000000_ck>, <&virt_16800000_ck>, <&virt_19200000_ck>, <&virt_26000000_ck>, <&virt_27000000_ck>, <&virt_38400000_ck>;
@@ -553,14 +553,14 @@ ti,index-starts-at-one; }; - abe_dpll_bypass_clk_mux: abe_dpll_bypass_clk_mux { + abe_dpll_bypass_clk_mux: abe_dpll_bypass_clk_mux at 108 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&sys_clkin>, <&sys_32k_ck>; reg = <0x0108>; }; - abe_dpll_clk_mux: abe_dpll_clk_mux { + abe_dpll_clk_mux: abe_dpll_clk_mux at 10c { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&sys_clkin>, <&sys_32k_ck>;
@@ -583,7 +583,7 @@ clock-div = <1>; }; - wkupaon_iclk_mux: wkupaon_iclk_mux { + wkupaon_iclk_mux: wkupaon_iclk_mux at 108 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&sys_clkin>, <&abe_lp_clk_div>;
@@ -598,7 +598,7 @@ clock-div = <1>; }; - gpio1_dbclk: gpio1_dbclk { + gpio1_dbclk: gpio1_dbclk at 1938 { #clock-cells = <0>; compatible = "ti,gate-clock"; clocks = <&sys_32k_ck>;
@@ -606,7 +606,7 @@ reg = <0x1938>; }; - timer1_gfclk_mux: timer1_gfclk_mux { + timer1_gfclk_mux: timer1_gfclk_mux at 1940 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&sys_clkin>, <&sys_32k_ck>;
@@ -616,7 +616,7 @@ }; &cm_core_clocks { - dpll_per_byp_mux: dpll_per_byp_mux { + dpll_per_byp_mux: dpll_per_byp_mux at 14c { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&sys_clkin>, <&per_dpll_hs_clk_div>;
@@ -624,7 +624,7 @@ reg = <0x014c>; }; - dpll_per_ck: dpll_per_ck { + dpll_per_ck: dpll_per_ck at 140 { #clock-cells = <0>; compatible = "ti,omap4-dpll-clock"; clocks = <&sys_clkin>, <&dpll_per_byp_mux>;
@@ -637,7 +637,7 @@ clocks = <&dpll_per_ck>; }; - dpll_per_h11x2_ck: dpll_per_h11x2_ck { + dpll_per_h11x2_ck: dpll_per_h11x2_ck at 158 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_per_x2_ck>;
@@ -646,7 +646,7 @@ ti,index-starts-at-one; }; - dpll_per_h12x2_ck: dpll_per_h12x2_ck { + dpll_per_h12x2_ck: dpll_per_h12x2_ck at 15c { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_per_x2_ck>;
@@ -655,7 +655,7 @@ ti,index-starts-at-one; }; - dpll_per_h14x2_ck: dpll_per_h14x2_ck { + dpll_per_h14x2_ck: dpll_per_h14x2_ck at 164 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_per_x2_ck>;
@@ -664,7 +664,7 @@ ti,index-starts-at-one; }; - dpll_per_m2_ck: dpll_per_m2_ck { + dpll_per_m2_ck: dpll_per_m2_ck at 150 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_per_ck>;
@@ -673,7 +673,7 @@ ti,index-starts-at-one; }; - dpll_per_m2x2_ck: dpll_per_m2x2_ck { + dpll_per_m2x2_ck: dpll_per_m2x2_ck at 150 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_per_x2_ck>;
@@ -682,7 +682,7 @@ ti,index-starts-at-one; }; - dpll_per_m3x2_ck: dpll_per_m3x2_ck { + dpll_per_m3x2_ck: dpll_per_m3x2_ck at 154 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_per_x2_ck>;
@@ -691,7 +691,7 @@ ti,index-starts-at-one; }; - dpll_unipro1_ck: dpll_unipro1_ck { + dpll_unipro1_ck: dpll_unipro1_ck at 200 { #clock-cells = <0>; compatible = "ti,omap4-dpll-clock"; clocks = <&sys_clkin>, <&sys_clkin>;
@@ -706,7 +706,7 @@ clock-div = <1>; }; - dpll_unipro1_m2_ck: dpll_unipro1_m2_ck { + dpll_unipro1_m2_ck: dpll_unipro1_m2_ck at 210 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_unipro1_ck>;
@@ -715,7 +715,7 @@ ti,index-starts-at-one; }; - dpll_unipro2_ck: dpll_unipro2_ck { + dpll_unipro2_ck: dpll_unipro2_ck at 1c0 { #clock-cells = <0>; compatible = "ti,omap4-dpll-clock"; clocks = <&sys_clkin>, <&sys_clkin>;
@@ -730,7 +730,7 @@ clock-div = <1>; }; - dpll_unipro2_m2_ck: dpll_unipro2_m2_ck { + dpll_unipro2_m2_ck: dpll_unipro2_m2_ck at 1d0 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_unipro2_ck>;
@@ -739,7 +739,7 @@ ti,index-starts-at-one; }; - dpll_usb_byp_mux: dpll_usb_byp_mux { + dpll_usb_byp_mux: dpll_usb_byp_mux at 18c { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&sys_clkin>, <&usb_dpll_hs_clk_div>;
@@ -747,7 +747,7 @@ reg = <0x018c>; }; - dpll_usb_ck: dpll_usb_ck { + dpll_usb_ck: dpll_usb_ck at 180 { #clock-cells = <0>; compatible = "ti,omap4-dpll-j-type-clock"; clocks = <&sys_clkin>, <&dpll_usb_byp_mux>;
@@ -762,7 +762,7 @@ clock-div = <1>; }; - dpll_usb_m2_ck: dpll_usb_m2_ck { + dpll_usb_m2_ck: dpll_usb_m2_ck at 190 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_usb_ck>;
@@ -811,7 +811,7 @@ clock-div = <2>; }; - l3init_60m_fclk: l3init_60m_fclk { + l3init_60m_fclk: l3init_60m_fclk at 104 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_usb_m2_ck>;
@@ -819,7 +819,7 @@ ti,dividers = <1>, <8>; }; - dss_32khz_clk: dss_32khz_clk { + dss_32khz_clk: dss_32khz_clk at 1420 { #clock-cells = <0>; compatible = "ti,gate-clock"; clocks = <&sys_32k_ck>;
@@ -827,7 +827,7 @@ reg = <0x1420>; }; - dss_48mhz_clk: dss_48mhz_clk { + dss_48mhz_clk: dss_48mhz_clk at 1420 { #clock-cells = <0>; compatible = "ti,gate-clock"; clocks = <&func_48m_fclk>;
@@ -835,7 +835,7 @@ reg = <0x1420>; }; - dss_dss_clk: dss_dss_clk { + dss_dss_clk: dss_dss_clk at 1420 { #clock-cells = <0>; compatible = "ti,gate-clock"; clocks = <&dpll_per_h12x2_ck>;
@@ -844,7 +844,7 @@ ti,set-rate-parent; }; - dss_sys_clk: dss_sys_clk { + dss_sys_clk: dss_sys_clk at 1420 { #clock-cells = <0>; compatible = "ti,gate-clock"; clocks = <&dss_syc_gfclk_div>;
@@ -852,7 +852,7 @@ reg = <0x1420>; }; - gpio2_dbclk: gpio2_dbclk { + gpio2_dbclk: gpio2_dbclk at 1060 { #clock-cells = <0>; compatible = "ti,gate-clock"; clocks = <&sys_32k_ck>;
@@ -860,7 +860,7 @@ reg = <0x1060>; }; - gpio3_dbclk: gpio3_dbclk { + gpio3_dbclk: gpio3_dbclk at 1068 { #clock-cells = <0>; compatible = "ti,gate-clock"; clocks = <&sys_32k_ck>;
@@ -868,7 +868,7 @@ reg = <0x1068>; }; - gpio4_dbclk: gpio4_dbclk { + gpio4_dbclk: gpio4_dbclk at 1070 { #clock-cells = <0>; compatible = "ti,gate-clock"; clocks = <&sys_32k_ck>;
@@ -876,7 +876,7 @@ reg = <0x1070>; }; - gpio5_dbclk: gpio5_dbclk { + gpio5_dbclk: gpio5_dbclk at 1078 { #clock-cells = <0>; compatible = "ti,gate-clock"; clocks = <&sys_32k_ck>;
@@ -884,7 +884,7 @@ reg = <0x1078>; }; - gpio6_dbclk: gpio6_dbclk { + gpio6_dbclk: gpio6_dbclk at 1080 { #clock-cells = <0>; compatible = "ti,gate-clock"; clocks = <&sys_32k_ck>;
@@ -892,7 +892,7 @@ reg = <0x1080>; }; - gpio7_dbclk: gpio7_dbclk { + gpio7_dbclk: gpio7_dbclk at 1110 { #clock-cells = <0>; compatible = "ti,gate-clock"; clocks = <&sys_32k_ck>;
@@ -900,7 +900,7 @@ reg = <0x1110>; }; - gpio8_dbclk: gpio8_dbclk { + gpio8_dbclk: gpio8_dbclk at 1118 { #clock-cells = <0>; compatible = "ti,gate-clock"; clocks = <&sys_32k_ck>;
@@ -908,7 +908,7 @@ reg = <0x1118>; }; - iss_ctrlclk: iss_ctrlclk { + iss_ctrlclk: iss_ctrlclk at 1320 { #clock-cells = <0>; compatible = "ti,gate-clock"; clocks = <&func_96m_fclk>;
@@ -916,7 +916,7 @@ reg = <0x1320>; }; - lli_txphy_clk: lli_txphy_clk { + lli_txphy_clk: lli_txphy_clk at f20 { #clock-cells = <0>; compatible = "ti,gate-clock"; clocks = <&dpll_unipro1_clkdcoldo>;
@@ -924,7 +924,7 @@ reg = <0x0f20>; }; - lli_txphy_ls_clk: lli_txphy_ls_clk { + lli_txphy_ls_clk: lli_txphy_ls_clk at f20 { #clock-cells = <0>; compatible = "ti,gate-clock"; clocks = <&dpll_unipro1_m2_ck>;
@@ -932,7 +932,7 @@ reg = <0x0f20>; }; - mmc1_32khz_clk: mmc1_32khz_clk { + mmc1_32khz_clk: mmc1_32khz_clk at 1628 { #clock-cells = <0>; compatible = "ti,gate-clock"; clocks = <&sys_32k_ck>;
@@ -940,7 +940,7 @@ reg = <0x1628>; }; - sata_ref_clk: sata_ref_clk { + sata_ref_clk: sata_ref_clk at 1688 { #clock-cells = <0>; compatible = "ti,gate-clock"; clocks = <&sys_clkin>;
@@ -948,7 +948,7 @@ reg = <0x1688>; }; - usb_host_hs_hsic480m_p1_clk: usb_host_hs_hsic480m_p1_clk { + usb_host_hs_hsic480m_p1_clk: usb_host_hs_hsic480m_p1_clk at 1658 { #clock-cells = <0>; compatible = "ti,gate-clock"; clocks = <&dpll_usb_m2_ck>;
@@ -956,7 +956,7 @@ reg = <0x1658>; }; - usb_host_hs_hsic480m_p2_clk: usb_host_hs_hsic480m_p2_clk { + usb_host_hs_hsic480m_p2_clk: usb_host_hs_hsic480m_p2_clk at 1658 { #clock-cells = <0>; compatible = "ti,gate-clock"; clocks = <&dpll_usb_m2_ck>;
@@ -964,7 +964,7 @@ reg = <0x1658>; }; - usb_host_hs_hsic480m_p3_clk: usb_host_hs_hsic480m_p3_clk { + usb_host_hs_hsic480m_p3_clk: usb_host_hs_hsic480m_p3_clk at 1658 { #clock-cells = <0>; compatible = "ti,gate-clock"; clocks = <&dpll_usb_m2_ck>;
@@ -972,7 +972,7 @@ reg = <0x1658>; }; - usb_host_hs_hsic60m_p1_clk: usb_host_hs_hsic60m_p1_clk { + usb_host_hs_hsic60m_p1_clk: usb_host_hs_hsic60m_p1_clk at 1658 { #clock-cells = <0>; compatible = "ti,gate-clock"; clocks = <&l3init_60m_fclk>;
@@ -980,7 +980,7 @@ reg = <0x1658>; }; - usb_host_hs_hsic60m_p2_clk: usb_host_hs_hsic60m_p2_clk { + usb_host_hs_hsic60m_p2_clk: usb_host_hs_hsic60m_p2_clk at 1658 { #clock-cells = <0>; compatible = "ti,gate-clock"; clocks = <&l3init_60m_fclk>;
@@ -988,7 +988,7 @@ reg = <0x1658>; }; - usb_host_hs_hsic60m_p3_clk: usb_host_hs_hsic60m_p3_clk { + usb_host_hs_hsic60m_p3_clk: usb_host_hs_hsic60m_p3_clk at 1658 { #clock-cells = <0>; compatible = "ti,gate-clock"; clocks = <&l3init_60m_fclk>;
@@ -996,7 +996,7 @@ reg = <0x1658>; }; - utmi_p1_gfclk: utmi_p1_gfclk { + utmi_p1_gfclk: utmi_p1_gfclk at 1658 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&l3init_60m_fclk>, <&xclk60mhsp1_ck>;
@@ -1004,7 +1004,7 @@ reg = <0x1658>; }; - usb_host_hs_utmi_p1_clk: usb_host_hs_utmi_p1_clk { + usb_host_hs_utmi_p1_clk: usb_host_hs_utmi_p1_clk at 1658 { #clock-cells = <0>; compatible = "ti,gate-clock"; clocks = <&utmi_p1_gfclk>;
@@ -1012,7 +1012,7 @@ reg = <0x1658>; }; - utmi_p2_gfclk: utmi_p2_gfclk { + utmi_p2_gfclk: utmi_p2_gfclk at 1658 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&l3init_60m_fclk>, <&xclk60mhsp2_ck>;
@@ -1020,7 +1020,7 @@ reg = <0x1658>; }; - usb_host_hs_utmi_p2_clk: usb_host_hs_utmi_p2_clk { + usb_host_hs_utmi_p2_clk: usb_host_hs_utmi_p2_clk at 1658 { #clock-cells = <0>; compatible = "ti,gate-clock"; clocks = <&utmi_p2_gfclk>;
@@ -1028,7 +1028,7 @@ reg = <0x1658>; }; - usb_host_hs_utmi_p3_clk: usb_host_hs_utmi_p3_clk { + usb_host_hs_utmi_p3_clk: usb_host_hs_utmi_p3_clk at 1658 { #clock-cells = <0>; compatible = "ti,gate-clock"; clocks = <&l3init_60m_fclk>;
@@ -1036,7 +1036,7 @@ reg = <0x1658>; }; - usb_otg_ss_refclk960m: usb_otg_ss_refclk960m { + usb_otg_ss_refclk960m: usb_otg_ss_refclk960m at 16f0 { #clock-cells = <0>; compatible = "ti,gate-clock"; clocks = <&dpll_usb_clkdcoldo>;
@@ -1044,7 +1044,7 @@ reg = <0x16f0>; }; - usb_phy_cm_clk32k: usb_phy_cm_clk32k { + usb_phy_cm_clk32k: usb_phy_cm_clk32k at 640 { #clock-cells = <0>; compatible = "ti,gate-clock"; clocks = <&sys_32k_ck>;
@@ -1052,7 +1052,7 @@ reg = <0x0640>; }; - usb_tll_hs_usb_ch0_clk: usb_tll_hs_usb_ch0_clk { + usb_tll_hs_usb_ch0_clk: usb_tll_hs_usb_ch0_clk at 1668 { #clock-cells = <0>; compatible = "ti,gate-clock"; clocks = <&l3init_60m_fclk>;
@@ -1060,7 +1060,7 @@ reg = <0x1668>; }; - usb_tll_hs_usb_ch1_clk: usb_tll_hs_usb_ch1_clk { + usb_tll_hs_usb_ch1_clk: usb_tll_hs_usb_ch1_clk at 1668 { #clock-cells = <0>; compatible = "ti,gate-clock"; clocks = <&l3init_60m_fclk>;
@@ -1068,7 +1068,7 @@ reg = <0x1668>; }; - usb_tll_hs_usb_ch2_clk: usb_tll_hs_usb_ch2_clk { + usb_tll_hs_usb_ch2_clk: usb_tll_hs_usb_ch2_clk at 1668 { #clock-cells = <0>; compatible = "ti,gate-clock"; clocks = <&l3init_60m_fclk>;
@@ -1076,7 +1076,7 @@ reg = <0x1668>; }; - fdif_fclk: fdif_fclk { + fdif_fclk: fdif_fclk at 1328 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_per_h11x2_ck>;
@@ -1085,7 +1085,7 @@ reg = <0x1328>; }; - gpu_core_gclk_mux: gpu_core_gclk_mux { + gpu_core_gclk_mux: gpu_core_gclk_mux at 1520 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&dpll_core_h14x2_ck>, <&dpll_per_h14x2_ck>;
@@ -1093,7 +1093,7 @@ reg = <0x1520>; }; - gpu_hyd_gclk_mux: gpu_hyd_gclk_mux { + gpu_hyd_gclk_mux: gpu_hyd_gclk_mux at 1520 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&dpll_core_h14x2_ck>, <&dpll_per_h14x2_ck>;
@@ -1101,7 +1101,7 @@ reg = <0x1520>; }; - hsi_fclk: hsi_fclk { + hsi_fclk: hsi_fclk at 1638 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_per_m2x2_ck>;
@@ -1110,7 +1110,7 @@ reg = <0x1638>; }; - mmc1_fclk_mux: mmc1_fclk_mux { + mmc1_fclk_mux: mmc1_fclk_mux at 1628 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&func_128m_clk>, <&dpll_per_m2x2_ck>;
@@ -1118,7 +1118,7 @@ reg = <0x1628>; }; - mmc1_fclk: mmc1_fclk { + mmc1_fclk: mmc1_fclk at 1628 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&mmc1_fclk_mux>;
@@ -1127,7 +1127,7 @@ reg = <0x1628>; }; - mmc2_fclk_mux: mmc2_fclk_mux { + mmc2_fclk_mux: mmc2_fclk_mux at 1630 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&func_128m_clk>, <&dpll_per_m2x2_ck>;
@@ -1135,7 +1135,7 @@ reg = <0x1630>; }; - mmc2_fclk: mmc2_fclk { + mmc2_fclk: mmc2_fclk at 1630 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&mmc2_fclk_mux>;
@@ -1144,7 +1144,7 @@ reg = <0x1630>; }; - timer10_gfclk_mux: timer10_gfclk_mux { + timer10_gfclk_mux: timer10_gfclk_mux at 1028 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&sys_clkin>, <&sys_32k_ck>;
@@ -1152,7 +1152,7 @@ reg = <0x1028>; }; - timer11_gfclk_mux: timer11_gfclk_mux { + timer11_gfclk_mux: timer11_gfclk_mux at 1030 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&sys_clkin>, <&sys_32k_ck>;
@@ -1160,7 +1160,7 @@ reg = <0x1030>; }; - timer2_gfclk_mux: timer2_gfclk_mux { + timer2_gfclk_mux: timer2_gfclk_mux at 1038 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&sys_clkin>, <&sys_32k_ck>;
@@ -1168,7 +1168,7 @@ reg = <0x1038>; }; - timer3_gfclk_mux: timer3_gfclk_mux { + timer3_gfclk_mux: timer3_gfclk_mux at 1040 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&sys_clkin>, <&sys_32k_ck>;
@@ -1176,7 +1176,7 @@ reg = <0x1040>; }; - timer4_gfclk_mux: timer4_gfclk_mux { + timer4_gfclk_mux: timer4_gfclk_mux at 1048 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&sys_clkin>, <&sys_32k_ck>;
@@ -1184,7 +1184,7 @@ reg = <0x1048>; }; - timer9_gfclk_mux: timer9_gfclk_mux { + timer9_gfclk_mux: timer9_gfclk_mux at 1050 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&sys_clkin>, <&sys_32k_ck>;
@@ -1201,7 +1201,7 @@ }; &scrm_clocks { - auxclk0_src_gate_ck: auxclk0_src_gate_ck { + auxclk0_src_gate_ck: auxclk0_src_gate_ck at 310 { #clock-cells = <0>; compatible = "ti,composite-no-wait-gate-clock"; clocks = <&dpll_core_m3x2_ck>;
@@ -1209,7 +1209,7 @@ reg = <0x0310>; }; - auxclk0_src_mux_ck: auxclk0_src_mux_ck { + auxclk0_src_mux_ck: auxclk0_src_mux_ck at 310 { #clock-cells = <0>; compatible = "ti,composite-mux-clock"; clocks = <&sys_clkin>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>;
@@ -1223,7 +1223,7 @@ clocks = <&auxclk0_src_gate_ck>, <&auxclk0_src_mux_ck>; }; - auxclk0_ck: auxclk0_ck { + auxclk0_ck: auxclk0_ck at 310 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&auxclk0_src_ck>;
@@ -1232,7 +1232,7 @@ reg = <0x0310>; }; - auxclk1_src_gate_ck: auxclk1_src_gate_ck { + auxclk1_src_gate_ck: auxclk1_src_gate_ck at 314 { #clock-cells = <0>; compatible = "ti,composite-no-wait-gate-clock"; clocks = <&dpll_core_m3x2_ck>;
@@ -1240,7 +1240,7 @@ reg = <0x0314>; }; - auxclk1_src_mux_ck: auxclk1_src_mux_ck { + auxclk1_src_mux_ck: auxclk1_src_mux_ck at 314 { #clock-cells = <0>; compatible = "ti,composite-mux-clock"; clocks = <&sys_clkin>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>;
@@ -1254,7 +1254,7 @@ clocks = <&auxclk1_src_gate_ck>, <&auxclk1_src_mux_ck>; }; - auxclk1_ck: auxclk1_ck { + auxclk1_ck: auxclk1_ck at 314 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&auxclk1_src_ck>;
@@ -1263,7 +1263,7 @@ reg = <0x0314>; }; - auxclk2_src_gate_ck: auxclk2_src_gate_ck { + auxclk2_src_gate_ck: auxclk2_src_gate_ck at 318 { #clock-cells = <0>; compatible = "ti,composite-no-wait-gate-clock"; clocks = <&dpll_core_m3x2_ck>;
@@ -1271,7 +1271,7 @@ reg = <0x0318>; }; - auxclk2_src_mux_ck: auxclk2_src_mux_ck { + auxclk2_src_mux_ck: auxclk2_src_mux_ck at 318 { #clock-cells = <0>; compatible = "ti,composite-mux-clock"; clocks = <&sys_clkin>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>;
@@ -1285,7 +1285,7 @@ clocks = <&auxclk2_src_gate_ck>, <&auxclk2_src_mux_ck>; }; - auxclk2_ck: auxclk2_ck { + auxclk2_ck: auxclk2_ck at 318 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&auxclk2_src_ck>;
@@ -1294,7 +1294,7 @@ reg = <0x0318>; }; - auxclk3_src_gate_ck: auxclk3_src_gate_ck { + auxclk3_src_gate_ck: auxclk3_src_gate_ck at 31c { #clock-cells = <0>; compatible = "ti,composite-no-wait-gate-clock"; clocks = <&dpll_core_m3x2_ck>;
@@ -1302,7 +1302,7 @@ reg = <0x031c>; }; - auxclk3_src_mux_ck: auxclk3_src_mux_ck { + auxclk3_src_mux_ck: auxclk3_src_mux_ck at 31c { #clock-cells = <0>; compatible = "ti,composite-mux-clock"; clocks = <&sys_clkin>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>;
@@ -1316,7 +1316,7 @@ clocks = <&auxclk3_src_gate_ck>, <&auxclk3_src_mux_ck>; }; - auxclk3_ck: auxclk3_ck { + auxclk3_ck: auxclk3_ck at 31c { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&auxclk3_src_ck>;
@@ -1325,7 +1325,7 @@ reg = <0x031c>; }; - auxclk4_src_gate_ck: auxclk4_src_gate_ck { + auxclk4_src_gate_ck: auxclk4_src_gate_ck at 320 { #clock-cells = <0>; compatible = "ti,composite-no-wait-gate-clock"; clocks = <&dpll_core_m3x2_ck>;
@@ -1333,7 +1333,7 @@ reg = <0x0320>; }; - auxclk4_src_mux_ck: auxclk4_src_mux_ck { + auxclk4_src_mux_ck: auxclk4_src_mux_ck at 320 { #clock-cells = <0>; compatible = "ti,composite-mux-clock"; clocks = <&sys_clkin>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>;
@@ -1347,7 +1347,7 @@ clocks = <&auxclk4_src_gate_ck>, <&auxclk4_src_mux_ck>; }; - auxclk4_ck: auxclk4_ck { + auxclk4_ck: auxclk4_ck at 320 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&auxclk4_src_ck>;
@@ -1356,7 +1356,7 @@ reg = <0x0320>; }; - auxclkreq0_ck: auxclkreq0_ck { + auxclkreq0_ck: auxclkreq0_ck at 210 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>;
@@ -1364,7 +1364,7 @@ reg = <0x0210>; }; - auxclkreq1_ck: auxclkreq1_ck { + auxclkreq1_ck: auxclkreq1_ck at 214 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>;
@@ -1372,7 +1372,7 @@ reg = <0x0214>; }; - auxclkreq2_ck: auxclkreq2_ck { + auxclkreq2_ck: auxclkreq2_ck at 218 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>;
@@ -1380,7 +1380,7 @@ reg = <0x0218>; }; - auxclkreq3_ck: auxclkreq3_ck { + auxclkreq3_ck: auxclkreq3_ck at 21c { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>;
Signature · 1 line
1.7.9.5
cover ARM: dts: fixes for DT warnings on OMAP2+ platforms
In reply to Tero KristoQuoted 7 lines · Tero Kristo
Hi,
This set fixes the clock node related warnings for OMAP2+ platforms that are going to be introduced with the new version of DTC that does stricter checks on DT structure. Basically, the address component is currently missing on the node names that have a reg properly, which is illegal.
Applying into omap-for-v4.7/dt thanks.
Tony