P9 ldmx support

Previously we just saved the FSCR, but only restored it in some settings, and never copied it thread to thread. This patch always restores the FSCR and formalizes new threads inheriting its setting so that later we can manipulate FSCR bits in start_thread.

Previously we just saved the FSCR, but only restored it in some settings, and never copied it thread to thread. This patch always restores the FSCR and formalizes new threads inheriting its setting so that later we can manipulate FSCR bits in start_thread.

Hi Jack,

Quoted 4 lines

Previously we just saved the FSCR, but only restored it in some settings, and never copied it thread to thread. This patch always restores the FSCR and formalizes new threads inheriting its setting so that later we can manipulate FSCR bits in start_thread.

Will this break the existing FSCR_DSCR bit handling?

         if (cpu_has_feature(CPU_FTR_DSCR)) {
                u64 dscr = get_paca()->dscr_default;
                u64 fscr = old_thread->fscr & ~FSCR_DSCR;

                if (new_thread->dscr_inherit) {
                        dscr = new_thread->dscr;
                        fscr |= FSCR_DSCR;
                }

                if (old_thread->dscr != dscr)
                        mtspr(SPRN_DSCR, dscr);

                if (old_thread->fscr != fscr)
                        mtspr(SPRN_FSCR, fscr);
        }

If not, we should modify the above so we don't write the FSCR twice.

Hi Anton.
=20

Quoted 6 lines · Anton Blanchard

Hi Jack,
=20

Quoted 3 lines

Previously we just saved the FSCR, but only restored it in some settings, and never copied it thread to thread. This patch always restores the FSCR and formalizes new threads inheriting its setting s=

Quoted 19 lines

Quoted 1 line

that later we can manipulate FSCR bits in start_thread.

=20
Will this break the existing FSCR_DSCR bit handling? =20

         if (cpu_has_feature(CPU_FTR_DSCR)) {
                u64 dscr =3D get_paca()->dscr_default;
                u64 fscr =3D old_thread->fscr & ~FSCR_DSCR;
=20
                if (new_thread->dscr_inherit) {
                        dscr =3D new_thread->dscr;
                        fscr |=3D FSCR_DSCR;
                }
=20
                if (old_thread->dscr !=3D dscr)
                        mtspr(SPRN_DSCR, dscr);
=20
                if (old_thread->fscr !=3D fscr)
                        mtspr(SPRN_FSCR, fscr);
        }

Quoted 2 lines

=20
If not, we should modify the above so we don't write the FSCR twice.

=20
I think this code is just partially redundant. I think it's trying to predict the right FSCR value based on this dscr_inherit flag. Now that we fully switch it, we could skip setting FSCR here, and just set DSCR if FSCR.DSCR is set (similar to what my patches do with FSCR.LM). In fact, we might be able to just entirely get rid of the dscr_inherit flag, but I'd have to look harder at that.

Right now the FSCR switch is conditional on FTR_ARCH_207S which is more exclusive than FTR_DSCR, but I guess the actual FSCR register is universal to PPC64 like the fscr field in the thread struct? If so, I can just move the FSCR save/restore out of the 207 conditional.

=20
Anyway, I'll clean this up a bit, add the little asm tweak from Segher, and put another spin on the list.
=20
- Jack
=20

I'm not sure that works on processes before power8.

There DSCR SPR number 0x11 will always trap and emulate from userspace (see arch/powerpc/kernel/traps.c:emulate_instruction()). That is not controlled by FSCR and should work on POWER7 where FSCR is not present. We need to set the inherit bit there too.

DSCR SPR number 0x3 is controlled by fscr, but it's only avaliable on POWER8.

Quoted 4 lines

Right now the FSCR switch is conditional on FTR_ARCH_207S which is more exclusive than FTR_DSCR, but I guess the actual FSCR register is universal to PPC64 like the fscr field in the thread struct? If so, I can just move the FSCR save/restore out of the 207 conditional.

FSCR was only introduced in power8, so it needs to be 207 conditional

Quoted 15 lines

I'm not sure that works on processes before power8.
=20
There DSCR SPR number 0x11 will always trap and emulate from userspace (see arch/powerpc/kernel/traps.c:emulate_instruction()). That is not controlled by FSCR and should work on POWER7 where FSCR is not present. We need to set the inherit bit there too.
=20
DSCR SPR number 0x3 is controlled by fscr, but it's only avaliable on POWER8.
=20

Quoted 4 lines

Right now the FSCR switch is conditional on FTR_ARCH_207S which is more exclusive than FTR_DSCR, but I guess the actual FSCR register is universal to PPC64 like the fscr field in the thread struct? If so, I can just move the FSCR save/restore out of the 207 conditional.

Quoted 3 lines

=20
FSCR was only introduced in power8, so it needs to be 207 conditional =20

=20
So on P6/P7 (which have FTR_DSCR) set we're potentially mtspr'ing to a non-existent register? Yuck. Can at least strip that logic out thanks to the full context switch, I think, even if dscr_inherit actually has a use.

Hi,

Quoted 6 lines · Jack Miller

__init_FSCR:

      mfspr   r3,SPRN_FSCR
+     andi.   r3,r3,(~FSCR_LM)@L
      ori     r3,r3,FSCR_TAR|FSCR_DSCR|FSCR_EBB
      mtspr   SPRN_FSCR,r3

blr

This clears the top 48 bits as well. Shouldn't matter currently; but more robust (and easier to read, if you know the idiom) is

ori r3,r3,FSCR_LM|FSCR_TAR|FSCR_DSCR|FSCR_EBB
xori r3,r3,FSCR_LM

Segher

Adds two tests. One is a simple test to ensure that the new registers LMRR and LMSER are properly maintained. The other actually uses the existing EBB test infrastructure to test that LMRR and LMSER behave as documented.

Signed-off-by Jack Miller <[email protected]>

---
 tools/testing/selftests/powerpc/pmu/ebb/Makefile   |   2 +-
 tools/testing/selftests/powerpc/pmu/ebb/ebb_lmr.c  | 144 +++++++++++++++++++++
 tools/testing/selftests/powerpc/pmu/ebb/ebb_lmr.h  |  39 ++++++
 .../selftests/powerpc/pmu/ebb/ebb_lmr_regs.c       |  38 ++++++
 tools/testing/selftests/powerpc/pmu/ebb/reg.h      |   5 +
 5 files changed, 227 insertions(+), 1 deletion(-)
 create mode 100644 tools/testing/selftests/powerpc/pmu/ebb/ebb_lmr.c
 create mode 100644 tools/testing/selftests/powerpc/pmu/ebb/ebb_lmr.h
 create mode 100644 tools/testing/selftests/powerpc/pmu/ebb/ebb_lmr_regs.c

tools/testing/selftests/powerpc/pmu/ebb/Makefile +1 -1

index 8d2279c4..6b0453e 100644
@@ -14,7 +14,7 @@ TEST_PROGS := reg_access_test event_attributes_test cycles_test	\
 	 fork_cleanup_test ebb_on_child_test			\
 	 ebb_on_willing_child_test back_to_back_ebbs_test	\
 	 lost_exception_test no_handler_test			\
-	 cycles_with_mmcr2_test
+	 cycles_with_mmcr2_test ebb_lmr ebb_lmr_regs
 
 all: $(TEST_PROGS)
 

tools/testing/selftests/powerpc/pmu/ebb/ebb_lmr.c new file +87 -0

new file mode 100644
index 0000000..266062b7
@@ -0,0 +1,144 @@
+/*
+ * Copyright 2016, Jack Miller, IBM Corp.
+ * Licensed under GPLv2.
+ */
+
+#include <stdlib.h>
+#include <stdio.h>
+
+#include "ebb.h"
+#include "ebb_lmr.h"
+
+#define SIZE		(32 * 1024 * 1024)	/* 32M */
+#define LM_SIZE		0	/* Smallest encoding, 32M */
+
+#define SECTIONS	64	/* 1 per bit in LMSER */
+#define SECTION_SIZE	(SIZE / SECTIONS)
+#define SECTION_LONGS   (SECTION_SIZE / sizeof(long))
+
+static unsigned long *test_mem;
+
+static int lmr_count = 0;
+
+void ebb_lmr_handler(void)
+{
+	lmr_count++;
+}
+
+void ldmx_full_section(unsigned long *mem, int section)
+{
+	unsigned long *ptr;
+	int i;
+
+	for (i = 0; i < SECTION_LONGS; i++) {
+		ptr = &mem[(SECTION_LONGS * section) + i];
+		ldmx((unsigned long) &ptr);
+		ebb_lmr_reset();
+	}
+}
+
+unsigned long section_masks[] = {
+	0x8000000000000000,
+	0xFF00000000000000,
+	0x0000000F70000000,
+	0x8000000000000001,
+	0xF0F0F0F0F0F0F0F0,
+	0x0F0F0F0F0F0F0F0F,
+	0x0
+};
+
+int ebb_lmr_section_test(unsigned long *mem)
+{
+	unsigned long *mask = section_masks;
+	int i;
+
+	for (; *mask; mask++) {
+		mtspr(SPRN_LMSER, *mask);
+		printf("Testing mask 0x%016lx\n", mfspr(SPRN_LMSER));
+
+		for (i = 0; i < 64; i++) {
+			lmr_count = 0;
+			ldmx_full_section(mem, i);
+			if (*mask & (1UL << (63 - i)))
+				FAIL_IF(lmr_count != SECTION_LONGS);
+			else
+				FAIL_IF(lmr_count);
+		}
+	}
+
+	return 0;
+}
+
+int ebb_lmr(void)
+{
+	int i;
+
+	SKIP_IF(!ebb_is_supported());
+	SKIP_IF(!lmr_is_supported());
+
+	setup_ebb_handler(ebb_lmr_handler);
+
+	ebb_global_enable();
+
+	FAIL_IF(posix_memalign((void **)&test_mem, SIZE, SIZE) != 0);
+
+	mtspr(SPRN_LMSER, 0);
+
+	FAIL_IF(mfspr(SPRN_LMSER) != 0);

tools/testing/selftests/powerpc/pmu/ebb/ebb_lmr.c new file +47 -0

+
+	/* Turn on the first section */
+
+	mtspr(SPRN_LMSER, (1UL << 63));
+	FAIL_IF(mfspr(SPRN_LMSER) != (1UL << 63));
+
+	/* Enable LM (BESCR) */
+
+	mtspr(SPRN_BESCR, mfspr(SPRN_BESCR) | BESCR_LME);
+	FAIL_IF(!(mfspr(SPRN_BESCR) & BESCR_LME));
+
+	ldmx((unsigned long)&test_mem);
+
+	FAIL_IF(lmr_count != 1);	// exactly one exception
+	FAIL_IF(mfspr(SPRN_BESCR) & BESCR_LME);	// LM now disabled
+	FAIL_IF(!(mfspr(SPRN_BESCR) & BESCR_LMEO));	// occurred bit set
+
+	printf("Simple LMR EBB OK\n");
+
+	/* This shouldn't cause an EBB since it's been disabled */
+	ldmx((unsigned long)&test_mem);
+	FAIL_IF(lmr_count != 1);
+
+	printf("LMR disable on EBB OK\n");
+
+	ebb_lmr_reset();
+
+	/* This should cause an EBB or reset is broken */
+	ldmx((unsigned long)&test_mem);
+	FAIL_IF(lmr_count != 2);
+
+	printf("LMR reset EBB OK\n");
+
+	ebb_lmr_reset();
+
+	return ebb_lmr_section_test(test_mem);
+}
+
+int main(void)
+{
+	int ret = test_harness(ebb_lmr, "ebb_lmr");
+
+	if (test_mem)
+		free(test_mem);
+
+	return ret;
+}

tools/testing/selftests/powerpc/pmu/ebb/ebb_lmr.h new file +39 -0

new file mode 100644
index 0000000..7911756
@@ -0,0 +1,39 @@
+#ifndef _SELFTESTS_POWERPC_PMU_EBB_LMR_H
+#define _SELFTESTS_POWERPC_PMU_EBB_LMR_H
+
+#include "reg.h"
+
+#ifndef PPC_FEATURE2_ARCH_3_00
+#define PPC_FEATURE2_ARCH_3_00 0x00800000
+#endif
+
+#define lmr_is_supported() have_hwcap2(PPC_FEATURE2_ARCH_3_00)
+
+static inline void ebb_lmr_reset(void)
+{
+	unsigned long bescr = mfspr(SPRN_BESCR);
+	bescr &= ~(BESCR_LMEO);
+	bescr |= BESCR_LME;
+	mtspr(SPRN_BESCR, bescr);
+}
+
+#define LDMX(t, a, b)\
+    (0x7c00026a |\
+    ((t & 0x1f) << 21) |\
+    ((a & 0x1f) << 16) |\
+    ((b & 0x1f) << 11))
+
+static inline unsigned long ldmx(unsigned long address)
+{
+	unsigned long ret;
+
+	asm volatile ("mr 9, %1\r\n"
+		      ".long " __stringify(LDMX(9, 0, 9)) "\r\n"
+		      "mr %0, 9\r\n":"=r"(ret)
+		      :"r"(address)
+		      :"r9");
+
+	return ret;
+}
+
+#endif

tools/testing/selftests/powerpc/pmu/ebb/ebb_lmr_regs.c new file +38 -0

new file mode 100644
index 0000000..d2a4898
@@ -0,0 +1,38 @@
+/*
+ * Copyright 2016, Jack Miller, IBM Corp.
+ * Licensed under GPLv2.
+ */
+
+#include <stdlib.h>
+#include <stdio.h>
+#include <unistd.h>
+
+#include "ebb.h"
+#include "ebb_lmr.h"
+
+#define CHECKS 10000
+
+int ebb_lmr_regs(void)
+{
+	int i;
+
+	SKIP_IF(!ebb_is_supported());
+	SKIP_IF(!lmr_is_supported());
+
+	ebb_global_enable();
+
+	for (i = 0; i < CHECKS; i++) {
+		mtspr(SPRN_LMRR, i << 25);	// skip size and rsvd bits
+		mtspr(SPRN_LMSER, i);
+
+		FAIL_IF(mfspr(SPRN_LMRR) != (i << 25));
+		FAIL_IF(mfspr(SPRN_LMSER) != i);
+	}
+
+	return 0;
+}
+
+int main(void)
+{
+	return test_harness(ebb_lmr_regs, "ebb_lmr_regs");
+}

tools/testing/selftests/powerpc/pmu/ebb/reg.h +5 -0

index 5921b0d..0659a7b 100644
@@ -34,6 +34,11 @@
 
 #define BESCR_PMEO     0x1     /* PMU Event-based exception Occurred */
 #define BESCR_PME      (0x1ul << 32) /* PMU Event-based exception Enable */
+#define BESCR_LME      (0x1ul << 34) /* Load Monitor Enable */
+#define BESCR_LMEO     (0x1ul << 2)  /* Load Monitor Exception Occurred */
+
+#define SPRN_LMRR      813     /* Load Monitor Region Register */
+#define SPRN_LMSER     814     /* Load Monitor Section Enable Register */
 
 #define SPRN_PMC1      771
 #define SPRN_PMC2      772

Re: [RFC] P9 ldmx support

These are patches based on next to support the forthcoming ldmx instruction through the existing P8 EBB infrastructure. Obviously it doesn't actually *work* without some other patches and a P9 system, but with the context switch change to FSCR it makes sense to get this upstream for testing ASAP.

The first patch context switches FSCR per thread so that the second patch=

lazily enable this feature (FSCR.LM) with a facility unavailable exceptio=

and context switch two new ldmx registers (LMRR / LMSER) per thread as we=

Third patch is a couple of basic tests.