DPLLs typically have a maximum rate they can support, and this varies from DPLL to DPLL. Add support of the maximum rate value to the DPLL data struct, and also add check for this in the DPLL round_rate function.

Signed-off-by Tero Kristo <[email protected]>

Cc Nishanth Menon <[email protected]>

Cc Tomi Valkeinen <[email protected]>

Cc Lokesh Vutla <[email protected]>

---
 drivers/clk/ti/clkt_dpll.c |    3 +++
 include/linux/clk/ti.h     |    2 ++
 2 files changed, 5 insertions(+)

drivers/clk/ti/clkt_dpll.c +3 -0

index b5cc6f6..7d97b07 100644
@@ -301,6 +301,9 @@ long omap2_dpll_round_rate(struct clk_hw *hw, unsigned long target_rate,
 
 	dd = clk->dpll_data;
 
+	if (dd->max_rate && target_rate > dd->max_rate)
+		target_rate = dd->max_rate;
+
 	ref_rate = clk_get_rate(dd->clk_ref);
 	clk_name = clk_hw_get_name(hw);
 	pr_debug("clock: %s: starting DPLL round_rate, target rate %lu\n",

include/linux/clk/ti.h +2 -0

index 9a63860..1a48ee2 100644
@@ -37,6 +37,7 @@
  * @last_rounded_n: cache of the last N result of omap2_dpll_round_rate()
  * @min_divider: minimum valid non-bypass divider value (actual)
  * @max_divider: maximum valid non-bypass divider value (actual)
+ * @max_rate: maximum clock rate for the DPLL
  * @modes: possible values of @enable_mask
  * @autoidle_reg: register containing the DPLL autoidle mode bitfield
  * @idlest_reg: register containing the DPLL idle status bitfield

@@ -81,6 +82,7 @@ struct dpll_data {
 	u8			last_rounded_n;
 	u8			min_divider;
 	u16			max_divider;
+	unsigned long		max_rate;
 	u8			modes;
 	void __iomem		*autoidle_reg;
 	void __iomem		*idlest_reg;

Signature · 1 line

1.7.9.5

Stephen Boyd

2016-04-01 19:27 UTC #2 lore raw

PATCH 1/3 clk: ti: dpll: add support for specifying max rate for DPLLs

Quoted 9 lines · Tero Kristo

DPLLs typically have a maximum rate they can support, and this varies from DPLL to DPLL. Add support of the maximum rate value to the DPLL data struct, and also add check for this in the DPLL round_rate function.
Signed-off-by Tero Kristo <[email protected]>
Cc Nishanth Menon <[email protected]>
Cc Tomi Valkeinen <[email protected]>
Cc Lokesh Vutla <[email protected]>
---

Acked-by Stephen Boyd <[email protected]>

Signature · 2 lines

Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project

Stephen Boyd

Applied

2016-04-16 00:26 UTC #3 lore raw

PATCH 1/3 clk: ti: dpll: add support for specifying max rate for DPLLs

In reply to Tero Kristo

Quoted 9 lines · Tero Kristo

DPLLs typically have a maximum rate they can support, and this varies from DPLL to DPLL. Add support of the maximum rate value to the DPLL data struct, and also add check for this in the DPLL round_rate function.
Signed-off-by Tero Kristo <[email protected]>
Cc Nishanth Menon <[email protected]>
Cc Tomi Valkeinen <[email protected]>
Cc Lokesh Vutla <[email protected]>
---

Applied to clk-next with some munging for clk_hw_get_rate()

Signature · 2 lines

Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project

Tero Kristo

author

2016-03-16 19:54 UTC #4 lore raw

PATCH 2/3 clk: ti: amx3xx: limit the maximum frequency of DPLLs based on spec

In reply to Tero Kristo

AM33xx/AM43xx devices use the same DPLL IP blocks, which only support maximum rate of 1GHz [1] for the default and 2GHz for the low-jitter type DPLLs [2]. Reflect this limitation in the DPLL init code by adding the max-rate parameter based on the DPLL types.

[1] Functional, integration & test specification for GS70 ADPLLS, Rev 1.0-01
[2] Functional, integration & test specification for GS70 ADPLLLJ, Rev 0.8-02

Signed-off-by Tero Kristo <[email protected]>

Cc Nishanth Menon <[email protected]>

Cc Tomi Valkeinen <[email protected]>

Cc Lokesh Vutla <[email protected]>

---
 drivers/clk/ti/dpll.c |    5 +++++
 1 file changed, 5 insertions(+)

drivers/clk/ti/dpll.c +5 -0

index 5519b38..4caadb9 100644
@@ -642,6 +642,7 @@ static void __init of_ti_am3_no_gate_dpll_setup(struct device_node *node)
 		.max_multiplier = 2047,
 		.max_divider = 128,
 		.min_divider = 1,
+		.max_rate = 1000000000,
 		.modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
 	};

@@ -661,6 +662,7 @@ static void __init of_ti_am3_jtype_dpll_setup(struct device_node *node)
 		.max_divider = 256,
 		.min_divider = 2,
 		.flags = DPLL_J_TYPE,
+		.max_rate = 2000000000,
 		.modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
 	};

@@ -679,6 +681,7 @@ static void __init of_ti_am3_no_gate_jtype_dpll_setup(struct device_node *node)
 		.max_multiplier = 2047,
 		.max_divider = 128,
 		.min_divider = 1,
+		.max_rate = 2000000000,
 		.flags = DPLL_J_TYPE,
 		.modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
 	};

@@ -699,6 +702,7 @@ static void __init of_ti_am3_dpll_setup(struct device_node *node)
 		.max_multiplier = 2047,
 		.max_divider = 128,
 		.min_divider = 1,
+		.max_rate = 1000000000,
 		.modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
 	};

@@ -716,6 +720,7 @@ static void __init of_ti_am3_core_dpll_setup(struct device_node *node)
 		.max_multiplier = 2047,
 		.max_divider = 128,
 		.min_divider = 1,
+		.max_rate = 1000000000,
 		.modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
 	};

Signature · 1 line

1.7.9.5

Stephen Boyd

2016-04-01 19:28 UTC #5 lore raw

PATCH 2/3 clk: ti: amx3xx: limit the maximum frequency of DPLLs based on spec

Quoted 5 lines · Tero Kristo

AM33xx/AM43xx devices use the same DPLL IP blocks, which only support maximum rate of 1GHz [1] for the default and 2GHz for the low-jitter type DPLLs [2]. Reflect this limitation in the DPLL init code by adding the max-rate parameter based on the DPLL types.

Quoted 8 lines

[1] Functional, integration & test specification for GS70 ADPLLS, Rev 1.0-01
[2] Functional, integration & test specification for GS70 ADPLLLJ, Rev 0.8-02
Signed-off-by Tero Kristo <[email protected]>
Cc Nishanth Menon <[email protected]>
Cc Tomi Valkeinen <[email protected]>
Cc Lokesh Vutla <[email protected]>
---

Acked-by Stephen Boyd <[email protected]>

Or I can apply these two targeting 4.7 if you like.

Signature · 2 lines

Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project

Tero Kristo

author

2016-04-13 12:51 UTC #6 lore raw

PATCH 2/3 clk: ti: amx3xx: limit the maximum frequency of DPLLs based on spec

Quoted 15 lines · Stephen Boyd

Quoted 5 lines · Tero Kristo
AM33xx/AM43xx devices use the same DPLL IP blocks, which only support maximum rate of 1GHz [1] for the default and 2GHz for the low-jitter type DPLLs [2]. Reflect this limitation in the DPLL init code by adding the max-rate parameter based on the DPLL types.
Quoted 8 lines
[1] Functional, integration & test specification for GS70 ADPLLS, Rev 1.0-01
[2] Functional, integration & test specification for GS70 ADPLLLJ, Rev 0.8-02
Signed-off-by Tero Kristo <[email protected]>
Cc Nishanth Menon <[email protected]>
Cc Tomi Valkeinen <[email protected]>
Cc Lokesh Vutla <[email protected]>
---

Quoted 3 lines

Acked-by Stephen Boyd <[email protected]>
Or I can apply these two targeting 4.7 if you like.

Yea I am fine with this. Want to pick up the old patch from Grygorii also?

-Tero

Stephen Boyd

2016-04-16 00:23 UTC #7 lore raw

PATCH 2/3 clk: ti: amx3xx: limit the maximum frequency of DPLLs based on spec

Quoted 16 lines · Tero Kristo

Quoted 15 lines · Stephen Boyd
Quoted 13 lines · Tero Kristo
AM33xx/AM43xx devices use the same DPLL IP blocks, which only support maximum rate of 1GHz [1] for the default and 2GHz for the low-jitter type DPLLs [2]. Reflect this limitation in the DPLL init code by adding the max-rate parameter based on the DPLL types.
[1] Functional, integration & test specification for GS70 ADPLLS, Rev 1.0-01
[2] Functional, integration & test specification for GS70 ADPLLLJ, Rev 0.8-02
Signed-off-by Tero Kristo <[email protected]>
Cc Nishanth Menon <[email protected]>
Cc Tomi Valkeinen <[email protected]>
Cc Lokesh Vutla <[email protected]>
---

Quoted 6 lines

Quoted 3 lines
Acked-by Stephen Boyd <[email protected]>
Or I can apply these two targeting 4.7 if you like.
Yea I am fine with this. Want to pick up the old patch from Grygorii also?

Ok let me find these two!

Signature · 2 lines

Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project

Stephen Boyd

Applied

2016-04-16 00:27 UTC #8 lore raw

PATCH 2/3 clk: ti: amx3xx: limit the maximum frequency of DPLLs based on spec

In reply to Tero Kristo

Quoted 5 lines · Tero Kristo

AM33xx/AM43xx devices use the same DPLL IP blocks, which only support maximum rate of 1GHz [1] for the default and 2GHz for the low-jitter type DPLLs [2]. Reflect this limitation in the DPLL init code by adding the max-rate parameter based on the DPLL types.

Quoted 8 lines

[1] Functional, integration & test specification for GS70 ADPLLS, Rev 1.0-01
[2] Functional, integration & test specification for GS70 ADPLLLJ, Rev 0.8-02
Signed-off-by Tero Kristo <[email protected]>
Cc Nishanth Menon <[email protected]>
Cc Tomi Valkeinen <[email protected]>
Cc Lokesh Vutla <[email protected]>
---

Applied to clk-next

Signature · 2 lines

Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project

Tero Kristo

author

2016-03-16 19:54 UTC #9 lore raw

PATCH 3/3 ARM: dts: am43xx: add support for clkout1 clock

In reply to Tero Kristo

clkout1 clock node and its generation tree was missing. Add this based on the data on TRM and PRCM functional spec.

Signed-off-by Tero Kristo <[email protected]>

Tested-by Benoit Parrot <[email protected]>

---
 arch/arm/boot/dts/am43xx-clocks.dtsi |   54 ++++++++++++++++++++++++++++++++++
 1 file changed, 54 insertions(+)

arch/arm/boot/dts/am43xx-clocks.dtsi +54 -0

index a38af2b..f16ffb5 100644
@@ -771,4 +771,58 @@
 		ti,bit-shift = <8>;
 		reg = <0x8a68>;
 	};
+
+	clkout1_osc_div_ck: clkout1_osc_div_ck {
+		#clock-cells = <0>;
+		compatible = "ti,divider-clock";
+		clocks = <&sys_clkin_ck>;
+		ti,bit-shift = <20>;
+		ti,max-div = <4>;
+		reg = <0x4100>;
+	};
+
+	clkout1_src2_mux_ck: clkout1_src2_mux_ck {
+		#clock-cells = <0>;
+		compatible = "ti,mux-clock";
+		clocks = <&clk_rc32k_ck>, <&sysclk_div>, <&dpll_ddr_m2_ck>,
+			 <&dpll_per_m2_ck>, <&dpll_disp_m2_ck>,
+			 <&dpll_mpu_m2_ck>;
+		reg = <0x4100>;
+	};
+
+	clkout1_src2_pre_div_ck: clkout1_src2_pre_div_ck {
+		#clock-cells = <0>;
+		compatible = "ti,divider-clock";
+		clocks = <&clkout1_src2_mux_ck>;
+		ti,bit-shift = <4>;
+		ti,max-div = <8>;
+		reg = <0x4100>;
+	};
+
+	clkout1_src2_post_div_ck: clkout1_src2_post_div_ck {
+		#clock-cells = <0>;
+		compatible = "ti,divider-clock";
+		clocks = <&clkout1_src2_pre_div_ck>;
+		ti,bit-shift = <8>;
+		ti,max-div = <32>;
+		ti,index-power-of-two;
+		reg = <0x4100>;
+	};
+
+	clkout1_mux_ck: clkout1_mux_ck {
+		#clock-cells = <0>;
+		compatible = "ti,mux-clock";
+		clocks = <&clkout1_osc_div_ck>, <&clk_rc32k_ck>,
+			 <&clkout1_src2_post_div_ck>, <&dpll_extdev_m2_ck>;
+		ti,bit-shift = <16>;
+		reg = <0x4100>;
+	};
+
+	clkout1_ck: clkout1_ck {
+		#clock-cells = <0>;
+		compatible = "ti,gate-clock";
+		clocks = <&clkout1_mux_ck>;
+		ti,bit-shift = <23>;
+		reg = <0x4100>;
+	};
 };

Signature · 1 line

1.7.9.5

Tony Lindgren

2016-04-12 21:05 UTC #10 lore raw

PATCH 3/3 ARM: dts: am43xx: add support for clkout1 clock

Quoted 2 lines · Tero Kristo

clkout1 clock node and its generation tree was missing. Add this based on the data on TRM and PRCM functional spec.

Can I pick this one separately?

Tony

Tero Kristo

author

2016-04-13 12:52 UTC #11 lore raw

PATCH 3/3 ARM: dts: am43xx: add support for clkout1 clock

Quoted 5 lines · Tony Lindgren

Quoted 2 lines · Tero Kristo
clkout1 clock node and its generation tree was missing. Add this based on the data on TRM and PRCM functional spec.
Can I pick this one separately?

Yes it has no dependencies towards the other patches.

-Tero

Quoted 3 lines

Tony

Tony Lindgren

2016-04-13 19:07 UTC #12 lore raw

PATCH 3/3 ARM: dts: am43xx: add support for clkout1 clock

Quoted 8 lines · Tero Kristo

Quoted 5 lines · Tony Lindgren
Quoted 2 lines · Tero Kristo
clkout1 clock node and its generation tree was missing. Add this based on the data on TRM and PRCM functional spec.
Can I pick this one separately?
Yes it has no dependencies towards the other patches.

OK applying into omap-for-v4.7/dt thanks.

Tony

Nishanth Menon

2016-03-16 22:33 UTC #13 lore raw

cover ARM: AMx3xx: misc clock fixes

In reply to Tero Kristo

Quoted 4 lines · Tero Kristo

Hi,
These patches add DPLL max rate support on AMx3xx SoCs, and add support for clkout1 clock on AM43xx. Targeted for 4.7 merge window.

This series looks good to me:

Reviewed-by Nishanth Menon <[email protected]>

Signature · 2 lines

Regards,
Nishanth Menon