advsync: Typo fix and vertical spacing tweaks

index e527def..965718c 100644
@@ -1508,7 +1508,7 @@ Read memory barriers imply data dependency barriers, and so can substitute
 for them.
 
 $\dagger$ Note that read barriers should normally be paired with write barriers;
-see Secton~\ref{sec:advsync:SMP Barrier Pairing}.
+see Section~\ref{sec:advsync:SMP Barrier Pairing}.
 
 \paragraph{General Memory Barriers}
 

index 965718c..0ef020f 100644
@@ -565,9 +565,11 @@ pairings that portable software may depend on.
 	by a memory barrier, while a second CPU executes a pair
 	of stores also separated by a memory barrier, as follows
 	(both A and B are initially equal to zero):
+
 	\vspace{5pt}
 	\begin{minipage}[t]{\columnwidth}
 	\tt
+	\scriptsize
 	\begin{tabular}{l|l}
 		CPU 1 &			CPU 2 \\
 		\hline

@@ -577,6 +579,7 @@ pairings that portable software may depend on.
 	\end{tabular}
 	\end{minipage}
 	\vspace{5pt}
+
 	After both CPUs have completed executing these code sequences,
 	if \co{Y==1}, then we must also have \co{X==1}.
 	In this case, the fact that \co{Y==1} means that

@@ -594,9 +597,11 @@ pairings that portable software may depend on.
 	In this pairing, each CPU executes a load followed by a
 	memory barrier followed by a store, as follows
 	(both A and B are initially equal to zero):
+
 	\vspace{5pt}
 	\begin{minipage}[t]{\columnwidth}
 	\tt
+	\scriptsize
 	\begin{tabular}{l|l}
 		CPU 1 &			CPU 2 \\
 		\hline

@@ -606,6 +611,7 @@ pairings that portable software may depend on.
 	\end{tabular}
 	\end{minipage}
 	\vspace{5pt}
+
 	After both CPUs have completed executing these code sequences,
 	if \co{X==1}, then we must also have \co{Y==0}.
 	In this case, the fact that \co{X==1} means that

@@ -628,9 +634,11 @@ pairings that portable software may depend on.
 	memory barrier followed by a store, while the other CPU
 	executes a pair of stores separated by a memory barrier,
 	as follows (both A and B are initially equal to zero):
+
 	\vspace{5pt}
 	\begin{minipage}[t]{\columnwidth}
 	\tt
+	\scriptsize
 	\begin{tabular}{l|l}
 		CPU 1 &			CPU 2 \\
 		\hline

@@ -640,6 +648,7 @@ pairings that portable software may depend on.
 	\end{tabular}
 	\end{minipage}
 	\vspace{5pt}
+
 	After both CPUs have completed executing these code sequences,
 	if \co{X==1}, then we must also have \co{B==1}.
 	In this case, the fact that \co{X==1} means that

@@ -710,6 +719,7 @@ keep in mind that they used to be a \emph{lot} harder on some systems!
 	\vspace{5pt}
 	\begin{minipage}[t]{\columnwidth}
 	\tt
+	\scriptsize
 	\begin{tabular}{l|l}
 		CPU 1 &			CPU 2 \\
 		\hline

index 0ef020f..505adc0 100644
@@ -1236,72 +1236,61 @@ There are some minimal guarantees that may be expected of a CPU:
 \item	On any given CPU, dependent memory accesses will be issued in order,
 	with respect to itself.  This means that for:
 
-\vspace{5pt}
 \begin{minipage}[t]{\columnwidth}
 \scriptsize
 \begin{verbatim}
 Q = P; D = *Q;
 \end{verbatim}
 \end{minipage}
-\vspace{5pt}
 
 	the CPU will issue the following memory operations:
 
-\vspace{5pt}
 \begin{minipage}[t]{\columnwidth}
 \scriptsize
 \begin{verbatim}
 Q = LOAD P, D = LOAD *Q
 \end{verbatim}
 \end{minipage}
-\vspace{5pt}
 
 	and always in that order.
 
 \item	Overlapping loads and stores within a particular CPU will appear to be
 	ordered within that CPU.  This means that for:
 
-\vspace{5pt}
 \begin{minipage}[t]{\columnwidth}
 \scriptsize
 \begin{verbatim}
 a = *X; *X = b;
 \end{verbatim}
 \end{minipage}
-\vspace{5pt}
 
 	the CPU will only issue the following sequence of memory operations:
 
-\vspace{5pt}
 \begin{minipage}[t]{\columnwidth}
 \scriptsize
 \begin{verbatim}
 a = LOAD *X, STORE *X = b
 \end{verbatim}
+\vspace{1pt}
 \end{minipage}
-\vspace{5pt}
 
 	And for:
 
-\vspace{5pt}
 \begin{minipage}[t]{\columnwidth}
 \scriptsize
 \begin{verbatim}
 *X = c; d = *X;
 \end{verbatim}
 \end{minipage}
-\vspace{5pt}
 
 	the CPU will only issue:
 
-\vspace{5pt}
 \begin{minipage}[t]{\columnwidth}
 \scriptsize
 \begin{verbatim}
 STORE *X = c, d = LOAD *X
 \end{verbatim}
 \end{minipage}
-\vspace{5pt}
 
 	(Loads and stores overlap if they are targeted at overlapping pieces of
 	memory).

@@ -1317,19 +1306,15 @@ And there are a number of things that \emph{must} or \emph{must not} be assumed:
 \item	It \emph{must not} be assumed that independent loads and stores will
 	be issued in the order given.  This means that for:
 
-\vspace{5pt}
 \begin{minipage}[t]{\columnwidth}
 \scriptsize
 \begin{verbatim}
 X = *A; Y = *B; *D = Z;
 \end{verbatim}
 \end{minipage}
-\vspace{5pt}
 
 	we may get any of the following sequences:
 
-
-\vspace{5pt}
 \begin{minipage}[t]{\columnwidth}
 \scriptsize
 \begin{verbatim}

@@ -1341,23 +1326,19 @@ STORE *D = Z,  X = LOAD *A,  Y = LOAD *B
 STORE *D = Z,  Y = LOAD *B,  X = LOAD *A
 \end{verbatim}
 \end{minipage}
-\vspace{5pt}
 
 \item	It \emph{must} be assumed that overlapping memory accesses may
 	be merged or discarded.  This means that for:
 
-\vspace{5pt}
 \begin{minipage}[t]{\columnwidth}
 \scriptsize
 \begin{verbatim}
 X = *A; Y = *(A + 4);
 \end{verbatim}
 \end{minipage}
-\vspace{5pt}
 
 	we may get any one of the following sequences:
 
-\vspace{5pt}
 \begin{minipage}[t]{\columnwidth}
 \scriptsize
 \begin{verbatim}

@@ -1365,23 +1346,20 @@ X = LOAD *A; Y = LOAD *(A + 4);
 Y = LOAD *(A + 4); X = LOAD *A;
 {X, Y} = LOAD {*A, *(A + 4) };
 \end{verbatim}
+\vspace{1pt}
 \end{minipage}
-\vspace{5pt}
 
 	And for:
 
-\vspace{5pt}
 \begin{minipage}[t]{\columnwidth}
 \scriptsize
 \begin{verbatim}
 *A = X; *(A + 4) = Y;
 \end{verbatim}
 \end{minipage}
-\vspace{5pt}
 
 	we may get any of:
 
-\vspace{5pt}
 \begin{minipage}[t]{\columnwidth}
 \scriptsize
 \begin{verbatim}

@@ -1389,23 +1367,20 @@ STORE *A = X; STORE *(A + 4) = Y;
 STORE *(A + 4) = Y; STORE *A = X;
 STORE {*A, *(A + 4) } = {X, Y};
 \end{verbatim}
+\vspace{1pt}
 \end{minipage}
-\vspace{5pt}
 
 	Finally, for:
 
-\vspace{5pt}
 \begin{minipage}[t]{\columnwidth}
 \scriptsize
 \begin{verbatim}
 *A = X; *A = Y;
 \end{verbatim}
 \end{minipage}
-\vspace{5pt}
 
 	we may get either of:
 
-\vspace{5pt}
 \begin{minipage}[t]{\columnwidth}
 \scriptsize
 \begin{verbatim}

@@ -1413,7 +1388,6 @@ STORE *A = X; STORE *A = Y;
 STORE *A = Y;
 \end{verbatim}
 \end{minipage}
-\vspace{5pt}
 
 \end{enumerate}