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documentation: ACQUIRE applies to loads, RELEASE applies to stores

PATCH Applied Will Deacon 3 participants 3 messages Apr 22, 2016

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PATCH 1/1 documentation: ACQUIRE applies to loads, RELEASE applies to stores

For compound atomics performing both a load and a store operation, make it clear that _acquire and _release variants refer only to the load and store portions of compound atomic. For example, xchg_acquire is an xchg operation where the load takes on ACQUIRE semantics.

Cc Paul E. McKenney <[email protected]>
Cc Peter Zijlstra <[email protected]>
---
 Documentation/memory-barriers.txt | 5 +++++
 1 file changed, 5 insertions(+)
Documentation/memory-barriers.txt +5 -0
index 3729cbe60e41..05f8011011be 100644
@@ -464,6 +464,11 @@ And a couple of implicit varieties:
      This means that ACQUIRE acts as a minimal "acquire" operation and
      RELEASE acts as a minimal "release" operation.
 
+A subset of the atomic operations described in atomic_ops.txt have ACQUIRE
+and RELEASE variants in addition to fully-ordered and relaxed (no barrier
+semantics) definitions.  For compound atomics performing both a load and a
+store, ACQUIRE semantics apply only to the load and RELEASE semantics apply
+only to the store portion of the operation.
 
 Memory barriers are only required where there's a possibility of interaction
 between two CPUs or between a CPU and a device.  If it can be guaranteed that
Signature · 1 line
2.1.4
maintainer Acked-by on v1 1/1
#1 lore raw
Quoted 6 lines · Will Deacon

For compound atomics performing both a load and a store operation, make it clear that _acquire and _release variants refer only to the load and store portions of compound atomic. For example, xchg_acquire is an xchg operation where the load takes on ACQUIRE semantics.

Cc Paul E. McKenney <[email protected]>

Thanks!

Quoted 24 lines
---
 Documentation/memory-barriers.txt | 5 +++++
 1 file changed, 5 insertions(+)
Documentation/memory-barriers.txt +5 -0
index 3729cbe60e41..05f8011011be 100644
@@ -464,6 +464,11 @@ And a couple of implicit varieties:
      This means that ACQUIRE acts as a minimal "acquire" operation and
      RELEASE acts as a minimal "release" operation.
 
+A subset of the atomic operations described in atomic_ops.txt have ACQUIRE
+and RELEASE variants in addition to fully-ordered and relaxed (no barrier
+semantics) definitions.  For compound atomics performing both a load and a
+store, ACQUIRE semantics apply only to the load and RELEASE semantics apply
+only to the store portion of the operation.
 
 Memory barriers are only required where there's a possibility of interaction
 between two CPUs or between a CPU and a device.  If it can be guaranteed that
Signature · 1 line
2.1.4
#2 lore raw
Quoted 11 lines · Peter Zijlstra
Quoted 6 lines · Will Deacon

For compound atomics performing both a load and a store operation, make it clear that _acquire and _release variants refer only to the load and store portions of compound atomic. For example, xchg_acquire is an xchg operation where the load takes on ACQUIRE semantics.

Cc Paul E. McKenney <[email protected]>

Thanks!

Queued, thank you both!

Thanx, Paul

Quoted 25 lines
Quoted 24 lines
---
 Documentation/memory-barriers.txt | 5 +++++
 1 file changed, 5 insertions(+)
Documentation/memory-barriers.txt +5 -0
index 3729cbe60e41..05f8011011be 100644
@@ -464,6 +464,11 @@ And a couple of implicit varieties:
      This means that ACQUIRE acts as a minimal "acquire" operation and
      RELEASE acts as a minimal "release" operation.
 
+A subset of the atomic operations described in atomic_ops.txt have ACQUIRE
+and RELEASE variants in addition to fully-ordered and relaxed (no barrier
+semantics) definitions.  For compound atomics performing both a load and a
+store, ACQUIRE semantics apply only to the load and RELEASE semantics apply
+only to the store portion of the operation.
 
 Memory barriers are only required where there's a possibility of interaction
 between two CPUs or between a CPU and a device.  If it can be guaranteed that
Signature · 1 line
2.1.4