ARM: dts: imx6q-b850v3: Remove ldb panel
Subsystems (2)
PATCH 1/3 ARM: dts: imx6q-b850v3: Remove ldb panel
Remove ldb panel entry for the following reasons:
- The b850v3 has an onboard LVDS to DisplayPort converter (STDP4028). So we should not limit the monitors that can be connected by hardcoding the auo,b133htn01 1080p panel.
- The default resolution on the LVDS interface needs to be WXGA or less. Otherwise when a 1080p monitor is connected to the HDMI port there is no output on both the LVDS and HDMI ports since a single IPU on i.MX6 can not handle two 1080p displays. With the panel entry removed from the devicetree, drm driver defaults the resolution on LVDS interface to XGA.
Once in userspace, applications can set the desired resolution on LVDS interface over IPU2 CRTC.
--- arch/arm/boot/dts/imx6q-b850v3.dts | 20 -------------------- 1 file changed, 20 deletions(-)
arch/arm/boot/dts/imx6q-b850v3.dts +0 -20
@@ -51,18 +51,6 @@ chosen { stdout-path = &uart3; }; - - panel-lvds0 { - compatible = "auo,b133htn01"; - backlight = <&backlight_lvds>; - ddc-i2c-bus = <&mux2_i2c2>; - - port { - panel_in_lvds0: endpoint { - remote-endpoint = <&lvds0_out>; - }; - }; - }; }; &ldb {
@@ -77,14 +65,6 @@ fsl,data-mapping = "spwg"; fsl,data-width = <24>; status = "okay"; - - port at 4 { - reg = <4>; - - lvds0_out: endpoint { - remote-endpoint = <&panel_in_lvds0>; - }; - }; }; };
Signature · 1 line
2.8.1
PATCH 2/3 ARM: dts: imx6q-b850v3: Update display clock source
The default monitor that ships with B850v3 requires a 65MHz pixel clock. 65MHz can not be achieved using PLL3 (480MHz/7=68.5MHz). Hence set the LDB_DIx clock source to PLL5. Since PLL5 is already in use by IPU1_DIx, set the clock source for IPU1_DIx to PLL2_PFD2 to allow simultaneous display on both LVDS and HDMI interface.
--- arch/arm/boot/dts/imx6q-b850v3.dts | 15 +++++++++++---- 1 file changed, 11 insertions(+), 4 deletions(-)
arch/arm/boot/dts/imx6q-b850v3.dts +11 -4
@@ -53,11 +53,18 @@ }; }; -&ldb { +&clks { assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, - <&clks IMX6QDL_CLK_LDB_DI1_SEL>; - assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>, - <&clks IMX6QDL_CLK_PLL3_USB_OTG>; + <&clks IMX6QDL_CLK_LDB_DI1_SEL>, + <&clks IMX6QDL_CLK_IPU1_DI0_PRE_SEL>, + <&clks IMX6QDL_CLK_IPU1_DI1_PRE_SEL>; + assigned-clock-parents = <&clks IMX6QDL_CLK_PLL5_VIDEO_DIV>, + <&clks IMX6QDL_CLK_PLL5_VIDEO_DIV>, + <&clks IMX6QDL_CLK_PLL2_PFD2_396M>, + <&clks IMX6QDL_CLK_PLL2_PFD2_396M>; +}; + +&ldb { fsl,dual-channel; status = "okay";
Signature · 1 line
2.8.1
PATCH 3/3 ARM: dts: imx: b450/b650v3: Move ldb_di clk assignment
In reply to Akshay BhatPreviously the LDB_DIx clocks could be specified in the ldb node. With the ERR009219 errata fix applied, the ldb_di clocks now needs to be specified in the clks node to ensure the clocks are setup early in the boot process.
--- arch/arm/boot/dts/imx6q-b450v3.dts | 5 ++++- arch/arm/boot/dts/imx6q-b650v3.dts | 5 ++++- 2 files changed, 8 insertions(+), 2 deletions(-)
arch/arm/boot/dts/imx6q-b450v3.dts +4 -1
@@ -65,11 +65,14 @@ }; }; -&ldb { +&clks { assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, <&clks IMX6QDL_CLK_LDB_DI1_SEL>; assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>, <&clks IMX6QDL_CLK_PLL3_USB_OTG>; +}; + +&ldb { status = "okay"; lvds0: lvds-channel at 0 {
arch/arm/boot/dts/imx6q-b650v3.dts +4 -1
@@ -65,11 +65,14 @@ }; }; -&ldb { +&clks { assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, <&clks IMX6QDL_CLK_LDB_DI1_SEL>; assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>, <&clks IMX6QDL_CLK_PLL3_USB_OTG>; +}; + +&ldb { status = "okay"; lvds0: lvds-channel at 0 {
Signature · 1 line
2.8.1
Shawn Guo
AppliedPATCH 1/3 ARM: dts: imx6q-b850v3: Remove ldb panel
In reply to Akshay BhatQuoted 10 lines · Akshay Bhat
Remove ldb panel entry for the following reasons:
- The b850v3 has an onboard LVDS to DisplayPort converter (STDP4028). So we should not limit the monitors that can be connected by hardcoding the auo,b133htn01 1080p panel.
- The default resolution on the LVDS interface needs to be WXGA or less. Otherwise when a 1080p monitor is connected to the HDMI port there is no output on both the LVDS and HDMI ports since a single IPU on i.MX6 can not handle two 1080p displays. With the panel entry removed from the devicetree, drm driver defaults the resolution on LVDS interface to XGA.
Quoted 4 lines
Once in userspace, applications can set the desired resolution on LVDS interface over IPU2 CRTC.
Signed-off-by Akshay Bhat <[email protected]>
Applied all, thanks.