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clk: Add drivers for Aspeed BMC SoCs

PATCH New Joel Stanley 3 participants 9 messages May 9, 2016 – May 12, 2016

Subsystems (4)
Device tree bindings Common clk Arm/Aspeed machine support Arm/Aspeed clock support
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Joel Stanley

author maintainer
#0 lore raw

cover clk: Add drivers for Aspeed BMC SoCs

Hello,

This adds support for the Aspeed ast2400 and ast2500 BMC SoCs. The drivers are basic in that they only create clock devices so other drivers know what frequency they are clocked at; there is no support for modifying the clocks.

Heiko and I exchanged some mail about the structure of the drivers. Thanks for the review Hieko! However, I still think the layout matches the hardware as we understand it so I did not make significant changes.

Cheers,

Joel

Joel Stanley (4):
doc/devicetree: Add Aspeed clock bindings drvers/clk: Support fourth generation Aspeed SoCs drvers/clk: Support fifth generation Aspeed SoCs drivers/clk: Support Aspeed UART clock divisor

 .../devicetree/bindings/clock/aspeed-clock.txt     | 156 +++++++++++++++++
 drivers/clk/Makefile                               |   1 +
 drivers/clk/aspeed/Makefile                        |   3 +
 drivers/clk/aspeed/clk-g4.c                        | 109 ++++++++++++
 drivers/clk/aspeed/clk-g5.c                        | 189 +++++++++++++++++++++
 drivers/clk/aspeed/clk-uart.c                      |  52 ++++++
 6 files changed, 510 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/clock/aspeed-clock.txt
 create mode 100644 drivers/clk/aspeed/Makefile
 create mode 100644 drivers/clk/aspeed/clk-g4.c
 create mode 100644 drivers/clk/aspeed/clk-g5.c
 create mode 100644 drivers/clk/aspeed/clk-uart.c
Signature · 1 line
2.8.1
author maintainer
#1 lore raw

PATCH 1/4 doc/devicetree: Add Aspeed clock bindings

Signed-off-by Joel Stanley <[email protected]>
---
 .../devicetree/bindings/clock/aspeed-clock.txt     | 156 +++++++++++++++++++++
 1 file changed, 156 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/clock/aspeed-clock.txt
Documentation/devicetree/bindings/clock/aspeed-clock.txt new file +156 -0
new file mode 100644
index 000000000000..968329406435
@@ -0,0 +1,156 @@
+Device Tree Clock bindings for the Aspeed SoCs
+
+Aspeed SoCs have a fixed frequency input osciallator is used to create the PLL
+and APB clocks. We can determine these frequencies by reading registers that
+are set according to strapping bits.
+
+Forth generation boards
+-----------------------
+
+eg, ast2400.
+
+CLKIN:
+ - compatible : Must be "fixed-clock"
+ - #clock-cells : Should be 0
+ - clock-frequency: 48e6, 25e6 or 24e6 depending on the input clock
+
+PLL:
+
+Required properties:
+ - compatible : Must be "aspeed,g4-hpll-clock"
+ - #clock-cells : Should be 0
+ - reg : Should contain registers location and length
+ - clocks : Should contain phandle + clock-specifier for the input clock (clkin)
+
+Optional properties:
+ - clock-output-names : Should contain clock name
+
+
+APB:
+
+Required properties:
+ - compatible : Must be "aspeed,g4-apb-clock"
+ - #clock-cells : Should be 0
+ - reg : Should contain registers location and length
+ - clocks : Should contain phandle + clock-specifier for the h-pll
+
+Optional properties:
+ - clock-output-names : Should contain clock name
+
+
+For example:
+
+	clk_clkin: clk_clkin {
+		#clock-cells = <0>;
+		compatible = "fixed-clock";
+		clock-frequency = <48000000>;
+	};
+
+	clk_hpll: clk_hpll {
+		compatible = "aspeed,g4-hpll-clock";
+		#clock-cells = <0>;
+		reg = <0x1e6e2008 0x4>;
+	};
+
+	clk_apb: clk_apb at 1e6e2008 {
+		#clock-cells = <0>;
+		compatible = "aspeed,g4-apb-clock";
+		reg = <0x1e6e2008 0x4>;
+		clocks = <&clk_hpll>;
+	};
+
+
+
+Fifth generation boards
+-----------------------
+
+eg, ast2500.
+
+CLKIN:
+Required properties:
+ - compatible : Must be "fixed-clock"
+ - #clock-cells : Should be 0
+ - clock-frequency: 25000000 or 24000000 depending on the input clock
+
+H-PLL:
+
+Required properties:
+ - compatible : Must be "aspeed,g5-hpll-clock"
+ - #clock-cells : Should be 0
+ - reg : Should contain registers location and length
+ - clocks : Should contain phandle + clock-specifier for the input clock (clkin)
+
+Optional properties:
+ - clock-output-names : Should contain clock name
+
+AHB:
+
+Required properties:
+ - compatible : Must be "aspeed,g5-ahb-clock"
+ - #clock-cells : Should be 0
+ - reg : Should contain registers location and length
+ - clocks : Should contain phandle + clock-specifier for the the h-pll
+
+Optional properties:
+ - clock-output-names : Should contain clock name
+
+APB:
+
+Required properties:
+ - compatible : Must be "aspeed,g4-apb-clock"
+ - #clock-cells : Should be 0
+ - reg : Should contain registers location and length
+ - clocks : Should contain phandle + clock-specifier for the the h-pll
+
+Optional properties:
+ - clock-output-names : Should contain clock name
+
+For example:
+	clk_clkin: clk_clkin at 1e6e2070 {
+		#clock-cells = <0>;
+		compatible = "aspeed,g5-clkin-clock";
+		reg = <0x1e6e2070 0x04>;
+	};
+
+	clk_hpll: clk_hpll at 1e6e2024 {
+		#clock-cells = <0>;
+		compatible = "aspeed,g5-hpll-clock";
+		reg = <0x1e6e2024 0x4>;
+		clocks = <&clk_clkin>;
+	};
+
+	clk_ahb: clk_ahb at 1e6e2070 {
+		#clock-cells = <0>;
+		compatible = "aspeed,g5-ahb-clock";
+		reg = <0x1e6e2070 0x4>;
+		clocks = <&clk_hpll>;
+	};
+
+	clk_apb: clk_apb at 1e6e2008 {
+		#clock-cells = <0>;
+		compatible = "aspeed,g5-apb-clock";
+		reg = <0x1e6e2008 0x4>;
+		clocks = <&clk_hpll>;
+	};
+
+Common clocks
+-------------
+
+UART:
+
+All supported boards have a uart clock that is derived from a 24MHz reference.
+We have a clock driver for it as there is a register in the SCU that controls
+weather it will be divided down by 13 or not.
+
+Required properties:
+ - compatible : Must be "aspeed,uart-clock"
+ - #clock-cells : Should be 0
+ - reg : Should contain registers location and length
+
+For example:
+
+	clk_uart: clk_uart at 1e6e2008 {
+		#clock-cells = <0>;
+		compatible = "aspeed,uart-clock";
+		reg = <0x1e6e202c 0x4>;
+	};
Signature · 1 line
2.8.1
maintainer
#2 lore raw

PATCH 1/4 doc/devicetree: Add Aspeed clock bindings

Quoted 60 lines · Joel Stanley
Signed-off-by Joel Stanley <[email protected]>
---
 .../devicetree/bindings/clock/aspeed-clock.txt     | 156 +++++++++++++++++++++
 1 file changed, 156 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/clock/aspeed-clock.txt
Documentation/devicetree/bindings/clock/aspeed-clock.txt new file +48 -0
new file mode 100644
index 000000000000..968329406435
@@ -0,0 +1,156 @@
+Device Tree Clock bindings for the Aspeed SoCs
+
+Aspeed SoCs have a fixed frequency input osciallator is used to create the PLL
+and APB clocks. We can determine these frequencies by reading registers that
+are set according to strapping bits.
+
+Forth generation boards
+-----------------------
+
+eg, ast2400.
+
+CLKIN:
+ - compatible : Must be "fixed-clock"
+ - #clock-cells : Should be 0
+ - clock-frequency: 48e6, 25e6 or 24e6 depending on the input clock
+
+PLL:
+
+Required properties:
+ - compatible : Must be "aspeed,g4-hpll-clock"
+ - #clock-cells : Should be 0
+ - reg : Should contain registers location and length
+ - clocks : Should contain phandle + clock-specifier for the input clock (clkin)
+
+Optional properties:
+ - clock-output-names : Should contain clock name
+
+
+APB:
+
+Required properties:
+ - compatible : Must be "aspeed,g4-apb-clock"
+ - #clock-cells : Should be 0
+ - reg : Should contain registers location and length
+ - clocks : Should contain phandle + clock-specifier for the h-pll
+
+Optional properties:
+ - clock-output-names : Should contain clock name
+
+
+For example:
+
+	clk_clkin: clk_clkin {
+		#clock-cells = <0>;
+		compatible = "fixed-clock";
+		clock-frequency = <48000000>;
+	};
+

Documentation/devicetree/bindings/clock/aspeed-clock.txt line 58

Quoted 10 lines
Documentation/devicetree/bindings/clock/aspeed-clock.txt new file +10 -0
+	clk_hpll: clk_hpll {
+		compatible = "aspeed,g4-hpll-clock";
+		#clock-cells = <0>;
+		reg = <0x1e6e2008 0x4>;
+	};
+
+	clk_apb: clk_apb at 1e6e2008 {
+		#clock-cells = <0>;
+		compatible = "aspeed,g4-apb-clock";
+		reg = <0x1e6e2008 0x4>;

You have overlapping register regions which we try to avoid (it would through errors, but doesn't because of existing platforms).

Just define the h/w block controlling these clocks and support multiple clocks.

Is this really all the clocks the SOC has?

Rob

author maintainer
#3 lore raw

PATCH 2/4 drvers/clk: Support fourth generation Aspeed SoCs

In reply to Joel Stanley

A basic driver to create fixed rate clock devices from strapping registers.

The clocks on the ast2400 are derived from an external oscillator and the frequency of this can be derived from the strapping of the processor. The frequency of internal clocks can be derived from other registers in the SCU (System Control Unit).

Signed-off-by Joel Stanley <[email protected]>
---
 drivers/clk/Makefile        |   1 +
 drivers/clk/aspeed/Makefile |   1 +
 drivers/clk/aspeed/clk-g4.c | 109 ++++++++++++++++++++++++++++++++++++++++++++
 3 files changed, 111 insertions(+)
 create mode 100644 drivers/clk/aspeed/Makefile
 create mode 100644 drivers/clk/aspeed/clk-g4.c
drivers/clk/Makefile +1 -0
index 46869d696e4d..8eaaef013a28 100644
@@ -84,3 +84,4 @@ obj-$(CONFIG_X86)			+= x86/
 obj-$(CONFIG_ARCH_ZX)			+= zte/
 obj-$(CONFIG_ARCH_ZYNQ)			+= zynq/
 obj-$(CONFIG_H8300)		+= h8300/
+obj-$(CONFIG_ARCH_ASPEED)		+= aspeed/
drivers/clk/aspeed/Makefile new file +1 -0
new file mode 100644
index 000000000000..d3457fbe3019
@@ -0,0 +1 @@
+obj-$(CONFIG_MACH_ASPEED_G4) += clk-g4.o
drivers/clk/aspeed/clk-g4.c new file +109 -0

109 lines not on this page · raw message

Signature · 1 line
2.8.1
#4 lore raw

PATCH 2/4 drvers/clk: Support fourth generation Aspeed SoCs

Quoted 6 lines · Joel Stanley
drivers/clk/aspeed/clk-g4.c new file +0 -0
new file mode 100644
index 000000000000..91677e9177f5

drivers/clk/aspeed/clk-g4.c line 10

Quoted 10 lines
drivers/clk/aspeed/clk-g4.c new file +10 -0
@@ -0,0 +1,109 @@
+/*
+ * Copyright 2016 IBM Corporation
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ */
+
+#include <linux/clk.h>

Hopefully this include isn't needed.

Quoted 39 lines
drivers/clk/aspeed/clk-g4.c new file +39 -0
+#include <linux/clk-provider.h>
+#include <linux/io.h>
+#include <linux/of_address.h>
+#include <linux/clkdev.h>
+
+static void __init aspeed_of_hpll_clk_init(struct device_node *node)
+{
+	struct clk *clk, *clkin_clk;
+	void __iomem *base;
+	int reg, rate, clkin;
+	const char *name = node->name;
+	const char *parent_name;
+	const int rates[][4] = {
+		{384, 360, 336, 408},
+		{400, 375, 350, 425},
+	};
+
+	of_property_read_string(node, "clock-output-names", &name);
+	parent_name = of_clk_get_parent_name(node, 0);
+
+	base = of_iomap(node, 0);
+	if (!base) {
+		pr_err("%s: of_iomap failed\n", node->full_name);
+		return;
+	}
+	reg = readl(base);
+	iounmap(base);
+
+	clkin_clk = of_clk_get(node, 0);
+	if (IS_ERR(clkin_clk)) {
+		pr_err("%s: of_clk_get failed\n", node->full_name);
+		return;
+	}
+
+	clkin = clk_get_rate(clkin_clk);
+
+	reg = (reg >> 8) & 0x2;
+
+	if (clkin == 48000000 || clkin == 24000000)

drivers/clk/aspeed/clk-g4.c line 59

Quoted 10 lines
drivers/clk/aspeed/clk-g4.c new file +10 -0
+		rate = rates[0][reg] * 1000000;
+	else if (clkin == 25000000)
+		rate = rates[1][reg] * 1000000;
+	else {
+		pr_err("%s: unknown clkin frequency %dHz\n",
+				node->full_name, clkin);
+		WARN_ON(1);
+	}
+
+	clk = clk_register_fixed_rate(NULL, name, parent_name, 0, rate);

Please write a proper clk driver that sets clkin to be the parent of this clk registered here and then calculates the frequency based on the parent clk rate and the strapping registers via the recalc rate callback. Also please move this to a platform driver instead of using CLK_OF_DECLARE assuming this isn't required for any timers in the system.

drivers/clk/aspeed/clk-g4.c line 65

Quoted 6 lines
drivers/clk/aspeed/clk-g4.c new file +6 -0
+	if (IS_ERR(clk)) {
+		pr_err("%s: failed to register clock\n", node->full_name);
+		return;
+	}
+
+	clk_register_clkdev(clk, NULL, name);

Do you have clkdev users? If not then please drop this.

Quoted 34 lines
drivers/clk/aspeed/clk-g4.c new file +34 -0
+	of_clk_add_provider(node, of_clk_src_simple_get, clk);
+}
+CLK_OF_DECLARE(aspeed_hpll_clock, "aspeed,g4-hpll-clock",
+	       aspeed_of_hpll_clk_init);
+
+static void __init aspeed_of_apb_clk_init(struct device_node *node)
+{
+	struct clk *clk, *hpll_clk;
+	void __iomem *base;
+	int reg, rate;
+	const char *name = node->name;
+	const char *parent_name;
+
+	of_property_read_string(node, "clock-output-names", &name);
+	parent_name = of_clk_get_parent_name(node, 0);
+
+	base = of_iomap(node, 0);
+	if (!base) {
+		pr_err("%s: of_iomap failed\n", node->full_name);
+		return;
+	}
+	reg = readl(base);
+	iounmap(base);
+
+	hpll_clk = of_clk_get(node, 0);
+	if (IS_ERR(hpll_clk)) {
+		pr_err("%s: of_clk_get failed\n", node->full_name);
+		return;
+	}
+
+	reg = (reg >> 23) & 0x3;
+	rate = clk_get_rate(hpll_clk) / (2 + 2 * reg);
+
+	clk = clk_register_fixed_rate(NULL, name, parent_name, 0, rate);

drivers/clk/aspeed/clk-g4.c line 109

Quoted 10 lines
drivers/clk/aspeed/clk-g4.c new file +10 -0
+	if (IS_ERR(clk)) {
+		pr_err("%s: failed to register clock\n", node->full_name);
+		return;
+	}
+
+	clk_register_clkdev(clk, NULL, name);
+	of_clk_add_provider(node, of_clk_src_simple_get, clk);
+}
+CLK_OF_DECLARE(aspeed_apb_clock, "aspeed,g4-apb-clock",
+	       aspeed_of_apb_clk_init);

Following on Rob's comment, please combine this into one driver instead of having different DT nodes for different clks that are all really part of one clock controller hw block.

Signature · 2 lines
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
author maintainer
#5 lore raw

PATCH 2/4 drvers/clk: Support fourth generation Aspeed SoCs

Quoted 11 lines · Stephen Boyd
Quoted 10 lines · Joel Stanley
drivers/clk/aspeed/clk-g4.c new file +4 -0
new file mode 100644
index 000000000000..91677e9177f5
@@ -0,0 +1,109 @@
+/*
+ * Copyright 2016 IBM Corporation
+ *
+ * This program is free software; you can redistribute it and/or
Quoted 8 lines

drivers/clk/aspeed/clk-g4.c line 10

Quoted 6 lines
drivers/clk/aspeed/clk-g4.c new file +6 -0
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ */
+
+#include <linux/clk.h>

Hopefully this include isn't needed.

It was required for clk_get_rate in aspeed_of_pclk_clk_init. As I mention below, I reworked it to avoid this.

Quoted 47 lines
Quoted 47 lines
drivers/clk/aspeed/clk-g4.c new file +46 -0
+#include <linux/clk-provider.h>
+#include <linux/io.h>
+#include <linux/of_address.h>
+#include <linux/clkdev.h>
+
+static void __init aspeed_of_hpll_clk_init(struct device_node *node)
+{
+     struct clk *clk, *clkin_clk;
+     void __iomem *base;
+     int reg, rate, clkin;
+     const char *name = node->name;
+     const char *parent_name;
+     const int rates[][4] = {
+             {384, 360, 336, 408},
+             {400, 375, 350, 425},
+     };
+
+     of_property_read_string(node, "clock-output-names", &name);
+     parent_name = of_clk_get_parent_name(node, 0);
+
+     base = of_iomap(node, 0);
+     if (!base) {
+             pr_err("%s: of_iomap failed\n", node->full_name);
+             return;
+     }
+     reg = readl(base);
+     iounmap(base);
+
+     clkin_clk = of_clk_get(node, 0);
+     if (IS_ERR(clkin_clk)) {
+             pr_err("%s: of_clk_get failed\n", node->full_name);
+             return;
+     }
+
+     clkin = clk_get_rate(clkin_clk);
+
+     reg = (reg >> 8) & 0x2;
+
+     if (clkin == 48000000 || clkin == 24000000)
+             rate = rates[0][reg] * 1000000;
+     else if (clkin == 25000000)
+             rate = rates[1][reg] * 1000000;
+     else {
+             pr_err("%s: unknown clkin frequency %dHz\n",
+                             node->full_name, clkin);
+             WARN_ON(1);
Quoted 8 lines

drivers/clk/aspeed/clk-g4.c line 59

Quoted 3 lines
drivers/clk/aspeed/clk-g4.c new file +3 -0
+     }
+
+     clk = clk_register_fixed_rate(NULL, name, parent_name, 0, rate);

Please write a proper clk driver that sets clkin to be the parent of this clk registered here and then calculates the frequency based on the parent clk rate and the strapping registers via the recalc rate callback.

After a few goes I understood what you meant here.

Is the pclk part okay? I modified the pclk part use a fixed factor clock instead of the fixed clock, so I could drop the pclk_get_rate call below.

Quoted 3 lines

Also please move this to a platform driver
instead of using CLK_OF_DECLARE assuming this isn't required for any timers in the system.

Can you clarify here? We do use the rate of pclk (the apb clock) in the clocksource driver to calculate our count_per_tick value.

Quoted 9 lines

drivers/clk/aspeed/clk-g4.c line 65

Quoted 7 lines
drivers/clk/aspeed/clk-g4.c new file +6 -0
+     if (IS_ERR(clk)) {
+             pr_err("%s: failed to register clock\n", node->full_name);
+             return;
+     }
+
+     clk_register_clkdev(clk, NULL, name);

Do you have clkdev users? If not then please drop this.

I think the answer is no. I will drop.

Quoted 40 lines
Quoted 40 lines
drivers/clk/aspeed/clk-g4.c new file +40 -0
+     of_clk_add_provider(node, of_clk_src_simple_get, clk);
+}
+CLK_OF_DECLARE(aspeed_hpll_clock, "aspeed,g4-hpll-clock",
+            aspeed_of_hpll_clk_init);
+
+static void __init aspeed_of_apb_clk_init(struct device_node *node)
+{
+     struct clk *clk, *hpll_clk;
+     void __iomem *base;
+     int reg, rate;
+     const char *name = node->name;
+     const char *parent_name;
+
+     of_property_read_string(node, "clock-output-names", &name);
+     parent_name = of_clk_get_parent_name(node, 0);
+
+     base = of_iomap(node, 0);
+     if (!base) {
+             pr_err("%s: of_iomap failed\n", node->full_name);
+             return;
+     }
+     reg = readl(base);
+     iounmap(base);
+
+     hpll_clk = of_clk_get(node, 0);
+     if (IS_ERR(hpll_clk)) {
+             pr_err("%s: of_clk_get failed\n", node->full_name);
+             return;
+     }
+
+     reg = (reg >> 23) & 0x3;
+     rate = clk_get_rate(hpll_clk) / (2 + 2 * reg);
+
+     clk = clk_register_fixed_rate(NULL, name, parent_name, 0, rate);
+     if (IS_ERR(clk)) {
+             pr_err("%s: failed to register clock\n", node->full_name);
+             return;
+     }
+
+     clk_register_clkdev(clk, NULL, name);
Quoted 8 lines

drivers/clk/aspeed/clk-g4.c line 109

Quoted 4 lines
drivers/clk/aspeed/clk-g4.c new file +4 -0
+     of_clk_add_provider(node, of_clk_src_simple_get, clk);
+}
+CLK_OF_DECLARE(aspeed_apb_clock, "aspeed,g4-apb-clock",
+            aspeed_of_apb_clk_init);

Following on Rob's comment, please combine this into one driver instead of having different DT nodes for different clks that are all really part of one clock controller hw block.

Ok, I have had a go at this. In our case the clock registers are part of the "SCU" IP; a collection of disparate functions that happen to include clock control. Is syscon the right thing to use here?

regmap = syscon_regmap_lookup_by_compatible("aspeed,ast2400-syscon-scu"); ret = regmap_read(hpll->regmap, 0x70, &reg);

Cheers,

Joel

#6 lore raw

PATCH 2/4 drvers/clk: Support fourth generation Aspeed SoCs

Quoted 11 lines · Joel Stanley
Quoted 4 lines · Stephen Boyd

Please write a proper clk driver that sets clkin to be the parent of this clk registered here and then calculates the frequency based on the parent clk rate and the strapping registers via the recalc rate callback.

After a few goes I understood what you meant here.

Is the pclk part okay? I modified the pclk part use a fixed factor clock instead of the fixed clock, so I could drop the pclk_get_rate call below.

Sorry what's the pclk part? Using a fixed factor is OK, as long as we don't have to call clk_get_rate() in this driver it's a better design.

Quoted 7 lines
Quoted 4 lines

Also please move this to a platform driver
instead of using CLK_OF_DECLARE assuming this isn't required for any timers in the system.

Can you clarify here? We do use the rate of pclk (the apb clock) in the clocksource driver to calculate our count_per_tick value.

Ok. I was hoping that this wasn't providing any clks required in the timer driver. Even if that's true, we could just register the part of the clk tree that needs to be ready for the timer from CLK_OF_DECLARE() and then register the other clks from a regular platform driver. Some people have already started doing this, so there are some examples around (clk/nxp/clk-lpc18xx-creg.c is one example).

Quoted 11 lines
Quoted 3 lines

Following on Rob's comment, please combine this into one driver instead of having different DT nodes for different clks that are all really part of one clock controller hw block.

Ok, I have had a go at this. In our case the clock registers are part of the "SCU" IP; a collection of disparate functions that happen to include clock control. Is syscon the right thing to use here?

regmap = syscon_regmap_lookup_by_compatible("aspeed,ast2400-syscon-scu"); ret = regmap_read(hpll->regmap, 0x70, &reg);

In that case I don't have a problem with a toplevel MFD node in DT with a child node for the clk part and a child node for other logical driver parts. Or it could all be one MFD driver and node that knows to add a clk device as a child of the MFD purely in software so that we can fork control of the clk part over to the drivers/clk directory. If you have the clk driver attach to some child device then you can always get the regmap from the parent MFD via the dev->parent pointer.

Maybe Rob can chime in here too with the proper design, because I've seen both styles.

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Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
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author maintainer
#7 lore raw

PATCH 3/4 drvers/clk: Support fifth generation Aspeed SoCs

In reply to Joel Stanley

A basic driver to create fixed rate clock devices from strapping registers.

Like the ast2400, the ast2500 clocks are derived from an external oscillator and the frequency of this can be determined from the strapping of the processor.

The frequency of internal clocks can be derived from other registers in the SCU (System Control Unit). The layout of the internal clocks is a bit different to the ast2400, as are the divisor reigisters, so it has it's own driver.

Signed-off-by Joel Stanley <[email protected]>
---
 drivers/clk/aspeed/Makefile |   1 +
 drivers/clk/aspeed/clk-g5.c | 189 ++++++++++++++++++++++++++++++++++++++++++++
 2 files changed, 190 insertions(+)
 create mode 100644 drivers/clk/aspeed/clk-g5.c
drivers/clk/aspeed/Makefile +1 -0
index d3457fbe3019..9ddb0f8f4356 100644
@@ -1 +1,2 @@
 obj-$(CONFIG_MACH_ASPEED_G4) += clk-g4.o
+obj-$(CONFIG_MACH_ASPEED_G5) += clk-g5.o
drivers/clk/aspeed/clk-g5.c new file +189 -0

189 lines not on this page · raw message

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2.8.1
author maintainer
#8 lore raw

PATCH 4/4 drivers/clk: Support Aspeed UART clock divisor

In reply to Joel Stanley

The Aspeed BMC SoCs have UART IP that derive their clocks from a 24MHz reference. It's not clear where this reference comes from, so it is hard coded in the driver.

This clock may be divided down by 13 if a certain register is set. This driver reads this register and creates a struct clk for the UARTs to consume.

Signed-off-by Joel Stanley <[email protected]>
---
 drivers/clk/aspeed/Makefile   |  1 +
 drivers/clk/aspeed/clk-uart.c | 52 +++++++++++++++++++++++++++++++++++++++++++
 2 files changed, 53 insertions(+)
 create mode 100644 drivers/clk/aspeed/clk-uart.c
drivers/clk/aspeed/Makefile +1 -0
index 9ddb0f8f4356..9d5754c086eb 100644
@@ -1,2 +1,3 @@
+obj-y += clk-uart.o
 obj-$(CONFIG_MACH_ASPEED_G4) += clk-g4.o
 obj-$(CONFIG_MACH_ASPEED_G5) += clk-g5.o
drivers/clk/aspeed/clk-uart.c new file +52 -0

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2.8.1