ARMv7: PSCI: add PSCI v1.0 support
Subsystems (4)
v3 cover ARMv7: PSCI: add PSCI v1.0 support
From: Hongbo Zhang <[email protected]>
Previous v2 patch set was sent out for a long time but got no comments, this time I send a v3 with minor updates and with more people in list, they are contributors for Linux kernel PSCI codes.
v3 changes:
- patch 3/11, re-init the stack pointer to address like start of page instead of page end, because for ARM push operation, the stack pointer is encreased before storing data.
- patch 10/11, delete the previous un-implemented cpu_suspend function for ls1 platform, because there is default blank functions for all those are not implemented in specific platform.
v2 changes:
- re-organize psci_cpu_on_common, this code should be called by each platform's psci_cpu_on, should not be a function calling each psci_cpu_on, all related functions are updated due to this change
- update some registers usage, e.g. if r10 is used without push/pop, u-boot cannot launch rt-kernel
- update some comments to be clearer, re-organize all patches for easier review
- add patch to check already_on or on_pending for LS102XA
This patch set contains two parts:
ARMv7 PSCI common framework: fix some issues and add v1.0 support NXP (was Freescale) LS102XA: codes enhancement and add v1.0 implementation And this patch set was initially created by Dongsheng Wang.
Hongbo Zhang (9):
Wang Dongsheng (2):
ARMv7: PSCI: update function psci_get_cpu_stack_top
ARMv7: PSCI: update the place of saving target PC
ARMv7: PSCI: add codes to save context ID for CPU_ON
ARMv7: PSCI: factor out reusable psci_cpu_on_common
ARMv7: PSCI: add PSCI v1.0 functions skeleton
ARMv7: PSCI: ls102xa: check target CPU ID before further operations
ARMv7: PSCI: ls102xa: check ALREADY_ON or ON_PENDING for CPU_ON
ARMv7: PSCI: ls102xa: add more PSCI v1.0 functions implemention
ARMv7: PSCI: ls102xa: move secure text section into OCRAM
ARM: PSCI: change PSCI function IDs base and offsets
ARM: PSCI: change PSCI related macros definition style
arch/arm/cpu/armv7/ls102xa/psci.S | 172 +++++++++++++++++++++++++++-- arch/arm/cpu/armv7/mx7/psci.S | 7 +- arch/arm/cpu/armv7/nonsec_virt.S | 7 ++ arch/arm/cpu/armv7/psci.S | 110 ++++++++++++++++-- arch/arm/cpu/armv7/sunxi/psci_sun6i.S | 8 +- arch/arm/cpu/armv7/sunxi/psci_sun7i.S | 8 +- arch/arm/cpu/armv7/virt-dt.c | 54 ++++++--- arch/arm/include/asm/arch-ls102xa/config.h | 3 +- arch/arm/include/asm/psci.h | 62 ++++++++--- arch/arm/mach-tegra/psci.S | 7 +- board/freescale/ls1021aqds/Makefile | 1 + board/freescale/ls1021aqds/psci.S | 36 ++++++ board/freescale/ls1021atwr/Makefile | 1 + board/freescale/ls1021atwr/psci.S | 28 +++++ include/configs/ls1021aqds.h | 3 + include/configs/ls1021atwr.h | 3 + 16 files changed, 443 insertions(+), 67 deletions(-) create mode 100644 board/freescale/ls1021aqds/psci.S create mode 100644 board/freescale/ls1021atwr/psci.S
Signature · 1 line
2.1.4
PATCH v3 1/11 ARM: PSCI: change PSCI function IDs base and offsets
From: Wang Dongsheng <[email protected]>
According to PSCI specification v1.0, the PSCI functions should start from 0x84000000 for SMC32, this patch changes this base value as well as other function offset values.
--- arch/arm/include/asm/psci.h | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-)
arch/arm/include/asm/psci.h +5 -5
@@ -19,13 +19,13 @@#define __ARM_PSCI_H__/* PSCI interface */ -#define ARM_PSCI_FN_BASE 0x95c1ba5e +#define ARM_PSCI_FN_BASE 0x84000000#define ARM_PSCI_FN (n) (ARM_PSCI_FN_BASE + (n)) -#define ARM_PSCI_FN_CPU_SUSPEND ARM_PSCI_FN(0) -#define ARM_PSCI_FN_CPU_OFF ARM_PSCI_FN(1) -#define ARM_PSCI_FN_CPU_ON ARM_PSCI_FN(2) -#define ARM_PSCI_FN_MIGRATE ARM_PSCI_FN(3) +#define ARM_PSCI_FN_CPU_SUSPEND ARM_PSCI_FN(1) +#define ARM_PSCI_FN_CPU_OFF ARM_PSCI_FN(2) +#define ARM_PSCI_FN_CPU_ON ARM_PSCI_FN(3) +#define ARM_PSCI_FN_MIGRATE ARM_PSCI_FN(5)#define ARM_PSCI_RET_SUCCESS 0#define ARM_PSCI_RET_NI (-1)
Signature · 1 line
2.1.4
PATCH v3 1/11 ARM: PSCI: change PSCI function IDs base and offsets
Hi,
Quoted 5 lines · On Wed, May 18, 2016 at 5:10 PM, <[email protected]> wrote:
From: Wang Dongsheng <[email protected]>
According to PSCI specification v1.0, the PSCI functions should start from
0x84000000for SMC32, this patch changes this base value as well as other function offset values.
I think you should squash this into the PSCI v1.0 skeleton patch. Otherwise between these 2 patches, we get a function ID and version mismatch?
ChenYu
Quoted 33 lines
Signed-off-by Wang Dongsheng <[email protected]>Signed-off-by Hongbo Zhang <[email protected]>--- arch/arm/include/asm/psci.h | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-)arch/arm/include/asm/psci.h +5
-6@@ -19,13 +19,13 @@#define __ARM_PSCI_H__/* PSCI interface */ -#define ARM_PSCI_FN_BASE 0x95c1ba5e +#define ARM_PSCI_FN_BASE 0x84000000#define ARM_PSCI_FN (n) (ARM_PSCI_FN_BASE + (n)) -#define ARM_PSCI_FN_CPU_SUSPEND ARM_PSCI_FN(0) -#define ARM_PSCI_FN_CPU_OFF ARM_PSCI_FN(1) -#define ARM_PSCI_FN_CPU_ON ARM_PSCI_FN(2) -#define ARM_PSCI_FN_MIGRATE ARM_PSCI_FN(3) +#define ARM_PSCI_FN_CPU_SUSPEND ARM_PSCI_FN(1) +#define ARM_PSCI_FN_CPU_OFF ARM_PSCI_FN(2) +#define ARM_PSCI_FN_CPU_ON ARM_PSCI_FN(3) +#define ARM_PSCI_FN_MIGRATE ARM_PSCI_FN(5)#define ARM_PSCI_RET_SUCCESS 0#define ARM_PSCI_RET_NI (-1) --2.1.4
PATCH v3 1/11 ARM: PSCI: change PSCI function IDs base and offsets
Quoted 5 lines · Chen-Yu Tsai
Hi,
Quoted 2 lines · On Wed, May 18, 2016 at 5:10 PM, <[email protected]> wrote:
From: Wang Dongsheng <[email protected]>
Quoted 9 lines
Quoted 3 lines
According to PSCI specification v1.0, the PSCI functions should start from
0x84000000for SMC32, this patch changes this base value as well as other function offset values.I think you should squash this into the PSCI v1.0 skeleton patch. Otherwise between these 2 patches, we get a function ID and version mismatch?
ChenYu
Thanks.
But there won't be the mismatch you mentioned, because in v0.1 the function IDs are implementation defined, the can be set to any values, here we just make a step forward to adapt legacy v0.1 function IDs compatible with the coming v1.0.
This patch is updating legacy ID definitions and the coming v1.0 skeleton patch is to add new IDs, it is OK to separate them since there won't be mismatch you pointed, what's more we've already gotten the Reviewed-by: tag :)
Quoted 33 lines
Quoted 33 lines
Signed-off-by Wang Dongsheng <[email protected]>Signed-off-by Hongbo Zhang <[email protected]>--- arch/arm/include/asm/psci.h | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-)arch/arm/include/asm/psci.h +5
-6@@ -19,13 +19,13 @@#define __ARM_PSCI_H__/* PSCI interface */ -#define ARM_PSCI_FN_BASE 0x95c1ba5e +#define ARM_PSCI_FN_BASE 0x84000000#define ARM_PSCI_FN (n) (ARM_PSCI_FN_BASE + (n)) -#define ARM_PSCI_FN_CPU_SUSPEND ARM_PSCI_FN(0) -#define ARM_PSCI_FN_CPU_OFF ARM_PSCI_FN(1) -#define ARM_PSCI_FN_CPU_ON ARM_PSCI_FN(2) -#define ARM_PSCI_FN_MIGRATE ARM_PSCI_FN(3) +#define ARM_PSCI_FN_CPU_SUSPEND ARM_PSCI_FN(1) +#define ARM_PSCI_FN_CPU_OFF ARM_PSCI_FN(2) +#define ARM_PSCI_FN_CPU_ON ARM_PSCI_FN(3) +#define ARM_PSCI_FN_MIGRATE ARM_PSCI_FN(5)#define ARM_PSCI_RET_SUCCESS 0#define ARM_PSCI_RET_NI (-1) --2.1.4
PATCH v3 1/11 ARM: PSCI: change PSCI function IDs base and offsets
Quoted 22 lines · Hongbo Zhang
Quoted 5 lines · Chen-Yu Tsai
Hi,
Quoted 2 lines · On Wed, May 18, 2016 at 5:10 PM, <[email protected]> wrote:
From: Wang Dongsheng <[email protected]>
Quoted 9 lines
Quoted 3 lines
According to PSCI specification v1.0, the PSCI functions should start from
0x84000000for SMC32, this patch changes this base value as well as other function offset values.I think you should squash this into the PSCI v1.0 skeleton patch. Otherwise between these 2 patches, we get a function ID and version mismatch?
ChenYu
Thanks.
But there won't be the mismatch you mentioned, because in v0.1 the function IDs are implementation defined, the can be set to any values, here we just make a step forward to adapt legacy v0.1 function IDs compatible with the coming v1.0.
Quoted 4 lines
This patch is updating legacy ID definitions and the coming v1.0 skeleton patch is to add new IDs, it is OK to separate them since there won't be mismatch you pointed, what's more we've already gotten the Reviewed-by: tag :)
Great! Thanks for the explanation. I'm not that familiar with the PSCI spec myself.
ChenYu
Quoted 33 lines
Quoted 33 lines
Quoted 33 lines
Signed-off-by Wang Dongsheng <[email protected]>Signed-off-by Hongbo Zhang <[email protected]>--- arch/arm/include/asm/psci.h | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-)arch/arm/include/asm/psci.h +5
-6@@ -19,13 +19,13 @@#define __ARM_PSCI_H__/* PSCI interface */ -#define ARM_PSCI_FN_BASE 0x95c1ba5e +#define ARM_PSCI_FN_BASE 0x84000000#define ARM_PSCI_FN (n) (ARM_PSCI_FN_BASE + (n)) -#define ARM_PSCI_FN_CPU_SUSPEND ARM_PSCI_FN(0) -#define ARM_PSCI_FN_CPU_OFF ARM_PSCI_FN(1) -#define ARM_PSCI_FN_CPU_ON ARM_PSCI_FN(2) -#define ARM_PSCI_FN_MIGRATE ARM_PSCI_FN(3) +#define ARM_PSCI_FN_CPU_SUSPEND ARM_PSCI_FN(1) +#define ARM_PSCI_FN_CPU_OFF ARM_PSCI_FN(2) +#define ARM_PSCI_FN_CPU_ON ARM_PSCI_FN(3) +#define ARM_PSCI_FN_MIGRATE ARM_PSCI_FN(5)#define ARM_PSCI_RET_SUCCESS 0#define ARM_PSCI_RET_NI (-1) --2.1.4
PATCH v3 1/11 ARM: PSCI: change PSCI function IDs base and offsets
In reply to macro.wave.z at gmail.comHi,
Quoted 5 lines · macro.wave.z at gmail.com
From: Wang Dongsheng <[email protected]>
According to PSCI specification v1.0, the PSCI functions should start from
0x84000000for SMC32, this patch changes this base value as well as other function offset values.
Out of curiosity: Do you plan to ever support ARMv8 boards with PSCI services in U-Boot as well?
Then we would need to think about adjusting the function IDs, because they use a "64-bit" flag for some functions.
Quoted 2 lines
Signed-off-by Wang Dongsheng <[email protected]>Signed-off-by Hongbo Zhang <[email protected]>
Otherwise:
Quoted 28 lines
--- arch/arm/include/asm/psci.h | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-)arch/arm/include/asm/psci.h +5
-5@@ -19,13 +19,13 @@#define __ARM_PSCI_H__/* PSCI interface */ -#define ARM_PSCI_FN_BASE 0x95c1ba5e +#define ARM_PSCI_FN_BASE 0x84000000#define ARM_PSCI_FN (n) (ARM_PSCI_FN_BASE + (n)) -#define ARM_PSCI_FN_CPU_SUSPEND ARM_PSCI_FN(0) -#define ARM_PSCI_FN_CPU_OFF ARM_PSCI_FN(1) -#define ARM_PSCI_FN_CPU_ON ARM_PSCI_FN(2) -#define ARM_PSCI_FN_MIGRATE ARM_PSCI_FN(3) +#define ARM_PSCI_FN_CPU_SUSPEND ARM_PSCI_FN(1) +#define ARM_PSCI_FN_CPU_OFF ARM_PSCI_FN(2) +#define ARM_PSCI_FN_CPU_ON ARM_PSCI_FN(3) +#define ARM_PSCI_FN_MIGRATE ARM_PSCI_FN(5)#define ARM_PSCI_RET_SUCCESS 0#define ARM_PSCI_RET_NI (-1)
PATCH v3 1/11 ARM: PSCI: change PSCI function IDs base and offsets
Quoted 5 lines · Andre Przywara
Hi,
Quoted 2 lines · macro.wave.z at gmail.com
From: Wang Dongsheng <[email protected]>
Quoted 9 lines
Quoted 3 lines
According to PSCI specification v1.0, the PSCI functions should start from
0x84000000for SMC32, this patch changes this base value as well as other function offset values.Out of curiosity: Do you plan to ever support ARMv8 boards with PSCI services in U-Boot as well?
Then we would need to think about adjusting the function IDs, because they use a "64-bit" flag for some functions.
My workmate Hongtao Jia <[email protected]> is working for ARMv8 PSCI. That should be in another separate file, so same or different function names can both be used freely I think.
Quoted 6 lines
Quoted 2 lines
Signed-off-by Wang Dongsheng <[email protected]>Signed-off-by Hongbo Zhang <[email protected]>Otherwise:
Reviewed-by Andre Przywara <[email protected]>
Thanks for review.
Quoted 28 lines
Quoted 28 lines
--- arch/arm/include/asm/psci.h | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-)arch/arm/include/asm/psci.h +5
-5@@ -19,13 +19,13 @@#define __ARM_PSCI_H__/* PSCI interface */ -#define ARM_PSCI_FN_BASE 0x95c1ba5e +#define ARM_PSCI_FN_BASE 0x84000000#define ARM_PSCI_FN (n) (ARM_PSCI_FN_BASE + (n)) -#define ARM_PSCI_FN_CPU_SUSPEND ARM_PSCI_FN(0) -#define ARM_PSCI_FN_CPU_OFF ARM_PSCI_FN(1) -#define ARM_PSCI_FN_CPU_ON ARM_PSCI_FN(2) -#define ARM_PSCI_FN_MIGRATE ARM_PSCI_FN(3) +#define ARM_PSCI_FN_CPU_SUSPEND ARM_PSCI_FN(1) +#define ARM_PSCI_FN_CPU_OFF ARM_PSCI_FN(2) +#define ARM_PSCI_FN_CPU_ON ARM_PSCI_FN(3) +#define ARM_PSCI_FN_MIGRATE ARM_PSCI_FN(5)#define ARM_PSCI_RET_SUCCESS 0#define ARM_PSCI_RET_NI (-1)
PATCH v3 1/11 ARM: PSCI: change PSCI function IDs base and offsets
Hi,
Quoted 10 lines · Hongbo Zhang
Quoted 9 lines · Andre Przywara
Hi,
Quoted 5 lines · macro.wave.z at gmail.com
From: Wang Dongsheng <[email protected]>
According to PSCI specification v1.0, the PSCI functions should start from
0x84000000for SMC32, this patch changes this base value as well as other function offset values.
Quoted 8 lines
Quoted 5 lines
Out of curiosity: Do you plan to ever support ARMv8 boards with PSCI services in U-Boot as well?
Then we would need to think about adjusting the function IDs, because they use a "64-bit" flag for some functions.My workmate Hongtao Jia <[email protected]> is working for ARMv8 PSCI. That should be in another separate file, so same or different function names can both be used freely I think.
OK, let's see how this looks like. The offsets are the same, the prefix is different, but not for every function - only for those that carry a register-sized argument (CPU_OFF uses the 32-bit prefix, CPU_ON the 64-bit one, for instance).
That's why I was asking how we address this without duplicating everything. But we can discuss this in the ARMv8 support thread.
Cheers,
Andre.
Quoted 38 lines
Quoted 7 lines
Quoted 3 lines
Signed-off-by Wang Dongsheng <[email protected]>Signed-off-by Hongbo Zhang <[email protected]>Otherwise:
Reviewed-by Andre Przywara <[email protected]>Thanks for review.
Quoted 28 lines
Quoted 28 lines
--- arch/arm/include/asm/psci.h | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-)arch/arm/include/asm/psci.h +5
-5@@ -19,13 +19,13 @@#define __ARM_PSCI_H__/* PSCI interface */ -#define ARM_PSCI_FN_BASE 0x95c1ba5e +#define ARM_PSCI_FN_BASE 0x84000000#define ARM_PSCI_FN (n) (ARM_PSCI_FN_BASE + (n)) -#define ARM_PSCI_FN_CPU_SUSPEND ARM_PSCI_FN(0) -#define ARM_PSCI_FN_CPU_OFF ARM_PSCI_FN(1) -#define ARM_PSCI_FN_CPU_ON ARM_PSCI_FN(2) -#define ARM_PSCI_FN_MIGRATE ARM_PSCI_FN(3) +#define ARM_PSCI_FN_CPU_SUSPEND ARM_PSCI_FN(1) +#define ARM_PSCI_FN_CPU_OFF ARM_PSCI_FN(2) +#define ARM_PSCI_FN_CPU_ON ARM_PSCI_FN(3) +#define ARM_PSCI_FN_MIGRATE ARM_PSCI_FN(5)#define ARM_PSCI_RET_SUCCESS 0#define ARM_PSCI_RET_NI (-1)
PATCH v3 1/11 ARM: PSCI: change PSCI function IDs base and offsets
Quoted 22 lines · Andre Przywara
Hi,
Quoted 10 lines · Hongbo Zhang
Quoted 9 lines · Andre Przywara
Hi,
Quoted 5 lines · macro.wave.z at gmail.com
From: Wang Dongsheng <[email protected]>
According to PSCI specification v1.0, the PSCI functions should start from
0x84000000for SMC32, this patch changes this base value as well as other function offset values.Quoted 8 lines
Quoted 5 lines
Out of curiosity: Do you plan to ever support ARMv8 boards with PSCI services in U-Boot as well?
Then we would need to think about adjusting the function IDs, because they use a "64-bit" flag for some functions.My workmate Hongtao Jia <[email protected]> is working for ARMv8 PSCI. That should be in another separate file, so same or different function names can both be used freely I think.
Quoted 7 lines
OK, let's see how this looks like. The offsets are the same, the prefix is different, but not for every function - only for those that carry a register-sized argument (
CPU_OFFuses the 32-bit prefix,CPU_ONthe 64-bit one, for instance).
That's why I was asking how we address this without duplicating everything. But we can discuss this in the ARMv8 support thread.
OK, I see, we can discuss that later for armv8.
And welcome to leave any comments for other patches in this serial.
Thanks.
Quoted 41 lines
Cheers,
Andre.Quoted 38 lines
Quoted 7 lines
Quoted 3 lines
Signed-off-by Wang Dongsheng <[email protected]>Signed-off-by Hongbo Zhang <[email protected]>Otherwise:
Reviewed-by Andre Przywara <[email protected]>Thanks for review.
Quoted 28 lines
Quoted 28 lines
--- arch/arm/include/asm/psci.h | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-)arch/arm/include/asm/psci.h +5
-5@@ -19,13 +19,13 @@#define __ARM_PSCI_H__/* PSCI interface */ -#define ARM_PSCI_FN_BASE 0x95c1ba5e +#define ARM_PSCI_FN_BASE 0x84000000#define ARM_PSCI_FN (n) (ARM_PSCI_FN_BASE + (n)) -#define ARM_PSCI_FN_CPU_SUSPEND ARM_PSCI_FN(0) -#define ARM_PSCI_FN_CPU_OFF ARM_PSCI_FN(1) -#define ARM_PSCI_FN_CPU_ON ARM_PSCI_FN(2) -#define ARM_PSCI_FN_MIGRATE ARM_PSCI_FN(3) +#define ARM_PSCI_FN_CPU_SUSPEND ARM_PSCI_FN(1) +#define ARM_PSCI_FN_CPU_OFF ARM_PSCI_FN(2) +#define ARM_PSCI_FN_CPU_ON ARM_PSCI_FN(3) +#define ARM_PSCI_FN_MIGRATE ARM_PSCI_FN(5)#define ARM_PSCI_RET_SUCCESS 0#define ARM_PSCI_RET_NI (-1)
PATCH v3 1/11 ARM: PSCI: change PSCI function IDs base and offsets
In reply to macro.wave.z at gmail.comQuoted 5 lines · macro.wave.z at gmail.com
From: Wang Dongsheng <[email protected]>
According to PSCI specification v1.0, the PSCI functions should start from
0x84000000for SMC32, this patch changes this base value as well as other function offset values.
I agree that these are the correct valeus for PSCI 0.2, and we must use those IDs for PSCI 0.2+.
However, this code is also used on platforms using PSCI 0.1, which did not have well-defined IDs, and relied on them being described in the DT. I fear that this may have the unintended sonequence of breaking those.
Does U-Boot patch the DT with the correct IDs per the PSCI 0.1 binding? If so, then things are fine.
Thanks,
Mark.
Quoted 32 lines
Signed-off-by Wang Dongsheng <[email protected]>Signed-off-by Hongbo Zhang <[email protected]>--- arch/arm/include/asm/psci.h | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-)arch/arm/include/asm/psci.h +5
-5@@ -19,13 +19,13 @@#define __ARM_PSCI_H__/* PSCI interface */ -#define ARM_PSCI_FN_BASE 0x95c1ba5e +#define ARM_PSCI_FN_BASE 0x84000000#define ARM_PSCI_FN (n) (ARM_PSCI_FN_BASE + (n)) -#define ARM_PSCI_FN_CPU_SUSPEND ARM_PSCI_FN(0) -#define ARM_PSCI_FN_CPU_OFF ARM_PSCI_FN(1) -#define ARM_PSCI_FN_CPU_ON ARM_PSCI_FN(2) -#define ARM_PSCI_FN_MIGRATE ARM_PSCI_FN(3) +#define ARM_PSCI_FN_CPU_SUSPEND ARM_PSCI_FN(1) +#define ARM_PSCI_FN_CPU_OFF ARM_PSCI_FN(2) +#define ARM_PSCI_FN_CPU_ON ARM_PSCI_FN(3) +#define ARM_PSCI_FN_MIGRATE ARM_PSCI_FN(5)#define ARM_PSCI_RET_SUCCESS 0#define ARM_PSCI_RET_NI (-1)Signature · 1 line
2.1.4
PATCH v3 1/11 ARM: PSCI: change PSCI function IDs base and offsets
Quoted 10 lines · Mark Rutland
Quoted 5 lines · macro.wave.z at gmail.com
From: Wang Dongsheng <[email protected]>
According to PSCI specification v1.0, the PSCI functions should start from
0x84000000for SMC32, this patch changes this base value as well as other function offset values.I agree that these are the correct valeus for PSCI 0.2, and we must use those IDs for PSCI 0.2+.
Quoted 7 lines
However, this code is also used on platforms using PSCI 0.1, which did not have well-defined IDs, and relied on them being described in the DT. I fear that this may have the unintended sonequence of breaking those.
Does U-Boot patch the DT with the correct IDs per the PSCI 0.1 binding? If so, then things are fine.
Hi Mark,
See such a piece of code from virt_dt.c:
ret = fdt_setprop_u32(fdt, nodeoff, "cpu_on", PSCI_FN_CPU_ON); The device tree nodes are created by u-boot, and the function IDs are just what I've edited, so when function IDs are updated, device tree nodes will be update simultaneously, so there should be no breaking you mentioned.
In my later 7/11 patch, Andre raised his comments about dt too, but that is another thing.
Quoted 35 lines
Thanks,
Mark.Quoted 32 lines
Signed-off-by Wang Dongsheng <[email protected]>Signed-off-by Hongbo Zhang <[email protected]>--- arch/arm/include/asm/psci.h | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-)arch/arm/include/asm/psci.h +5
-6@@ -19,13 +19,13 @@#define __ARM_PSCI_H__/* PSCI interface */ -#define ARM_PSCI_FN_BASE 0x95c1ba5e +#define ARM_PSCI_FN_BASE 0x84000000#define ARM_PSCI_FN (n) (ARM_PSCI_FN_BASE + (n)) -#define ARM_PSCI_FN_CPU_SUSPEND ARM_PSCI_FN(0) -#define ARM_PSCI_FN_CPU_OFF ARM_PSCI_FN(1) -#define ARM_PSCI_FN_CPU_ON ARM_PSCI_FN(2) -#define ARM_PSCI_FN_MIGRATE ARM_PSCI_FN(3) +#define ARM_PSCI_FN_CPU_SUSPEND ARM_PSCI_FN(1) +#define ARM_PSCI_FN_CPU_OFF ARM_PSCI_FN(2) +#define ARM_PSCI_FN_CPU_ON ARM_PSCI_FN(3) +#define ARM_PSCI_FN_MIGRATE ARM_PSCI_FN(5)#define ARM_PSCI_RET_SUCCESS 0#define ARM_PSCI_RET_NI (-1) --2.1.4
PATCH v3 2/11 ARM: PSCI: change PSCI related macros definition style
In reply to macro.wave.z at gmail.comFrom: Wang Dongsheng <[email protected]>
Since we are already under the directory of arch/arm/, the prefix ARM_ for macros isn't so necessary, and with more PSCI interfaces being added later, there will be much more redundant ARM_ prefixes, what's more, there are no ARM_/arm_ prefixes for other PSCI variables and functions either, so this patch updates these macro definitions to make them concise and consistent.
--- arch/arm/cpu/armv7/ls102xa/psci.S | 2 +- arch/arm/cpu/armv7/psci.S | 12 ++++++------ arch/arm/cpu/armv7/sunxi/psci_sun6i.S | 2 +- arch/arm/cpu/armv7/sunxi/psci_sun7i.S | 2 +- arch/arm/cpu/armv7/virt-dt.c | 8 ++++---- arch/arm/include/asm/psci.h | 24 +++++++++++++----------- arch/arm/mach-tegra/psci.S | 2 +- 7 files changed, 27 insertions(+), 25 deletions(-)
arch/arm/cpu/armv7/ls102xa/psci.S +1 -1
@@ -99,7 +99,7 @@ holdoff_release: dsb @ Return - mov r0, #ARM_PSCI_RET_SUCCESS + mov r0, #PSCI_RET_SUCCESS pop {lr} bx lr
arch/arm/cpu/armv7/psci.S +6 -6
@@ -50,7 +50,7 @@ ENTRY(psci_cpu_suspend) ENTRY(psci_cpu_off) ENTRY(psci_cpu_on) ENTRY(psci_migrate) - mov r0, #ARM_PSCI_RET_NI @ Return -1 (Not Implemented) + mov r0, #PSCI_RET_NOT_SUPPORTED @ Return -1 (Not Supported) mov pc, lr ENDPROC(psci_migrate) ENDPROC(psci_cpu_on)
@@ -62,13 +62,13 @@ ENDPROC(psci_cpu_suspend) .weak psci_migrate _psci_table: - .word ARM_PSCI_FN_CPU_SUSPEND + .word PSCI_FN_CPU_SUSPEND .word psci_cpu_suspend - .word ARM_PSCI_FN_CPU_OFF + .word PSCI_FN_CPU_OFF .word psci_cpu_off - .word ARM_PSCI_FN_CPU_ON + .word PSCI_FN_CPU_ON .word psci_cpu_on - .word ARM_PSCI_FN_MIGRATE + .word PSCI_FN_MIGRATE .word psci_migrate .word 0 .word 0
@@ -86,7 +86,7 @@ _smc_psci: 1: ldr r5, [r4] @ Load PSCI function ID ldr r6, [r4, #4] @ Load target PC cmp r5, #0 @ If reach the end, bail out - moveq r0, #ARM_PSCI_RET_INVAL @ Return -2 (Invalid) + moveq r0, #PSCI_RET_INVALID_PARAMS @ Return -2 (Invalid) beq 2f cmp r0, r5 @ If not matching, try next entry addne r4, r4, #8
arch/arm/cpu/armv7/sunxi/psci_sun6i.S +1 -1
@@ -204,7 +204,7 @@ psci_cpu_on: orr r6, r6, r4 str r6, [r0, #0x1e4] - mov r0, #ARM_PSCI_RET_SUCCESS @ Return PSCI_RET_SUCCESS + mov r0, #PSCI_RET_SUCCESS @ Return PSCI_RET_SUCCESS pop {pc} .globl psci_cpu_off
arch/arm/cpu/armv7/sunxi/psci_sun7i.S +1 -1
@@ -179,7 +179,7 @@ psci_cpu_on: orr r6, r6, r4 str r6, [r0, #0x1e4] - mov r0, #ARM_PSCI_RET_SUCCESS @ Return PSCI_RET_SUCCESS + mov r0, #PSCI_RET_SUCCESS @ Return PSCI_RET_SUCCESS pop {pc} .globl psci_cpu_off
arch/arm/cpu/armv7/virt-dt.c +4 -4
@@ -73,16 +73,16 @@ static int fdt_psci(void *fdt) tmp =fdt_setprop_string (fdt, nodeoff,"method" ,"smc" );if (tmp)return tmp; - tmp =fdt_setprop_u32 (fdt, nodeoff,"cpu_suspend" ,ARM_PSCI_FN_CPU_SUSPEND ); + tmp =fdt_setprop_u32 (fdt, nodeoff,"cpu_suspend" ,PSCI_FN_CPU_SUSPEND );if (tmp)return tmp; - tmp =fdt_setprop_u32 (fdt, nodeoff,"cpu_off" ,ARM_PSCI_FN_CPU_OFF ); + tmp =fdt_setprop_u32 (fdt, nodeoff,"cpu_off" ,PSCI_FN_CPU_OFF );if (tmp)return tmp; - tmp =fdt_setprop_u32 (fdt, nodeoff,"cpu_on" ,ARM_PSCI_FN_CPU_ON ); + tmp =fdt_setprop_u32 (fdt, nodeoff,"cpu_on" ,PSCI_FN_CPU_ON );if (tmp)return tmp; - tmp =fdt_setprop_u32 (fdt, nodeoff,"migrate" ,ARM_PSCI_FN_MIGRATE ); + tmp =fdt_setprop_u32 (fdt, nodeoff,"migrate" ,PSCI_FN_MIGRATE );if (tmp)return tmp;#endif
arch/arm/include/asm/psci.h +13 -11
@@ -18,19 +18,21 @@#ifndef __ARM_PSCI_H__#define __ARM_PSCI_H__ -/* PSCI interface */ -#define ARM_PSCI_FN_BASE 0x84000000 -#define ARM_PSCI_FN (n) (ARM_PSCI_FN_BASE + (n)) -#define ARM_PSCI_FN_CPU_SUSPEND ARM_PSCI_FN(1) -#define ARM_PSCI_FN_CPU_OFF ARM_PSCI_FN(2) -#define ARM_PSCI_FN_CPU_ON ARM_PSCI_FN(3) -#define ARM_PSCI_FN_MIGRATE ARM_PSCI_FN(5) +/* PSCI interfaces */ +#define PSCI_FN_BASE 0x84000000 +#define PSCI_FN_ID (n) (PSCI_FN_BASE + (n)) -#define ARM_PSCI_RET_SUCCESS 0 -#define ARM_PSCI_RET_NI (-1) -#define ARM_PSCI_RET_INVAL (-2) -#define ARM_PSCI_RET_DENIED (-3) +#define PSCI_FN_CPU_SUSPEND PSCI_FN_ID(1) +#define PSCI_FN_CPU_OFF PSCI_FN_ID(2) +#define PSCI_FN_CPU_ON PSCI_FN_ID(3) +#define PSCI_FN_MIGRATE PSCI_FN_ID(5) + +/* PSCI return values */ +#define PSCI_RET_SUCCESS 0 +#define PSCI_RET_NOT_SUPPORTED (-1) +#define PSCI_RET_INVALID_PARAMS (-2) +#define PSCI_RET_DENIED (-3)#ifndef __ASSEMBLY__int psci_update_dt (void *fdt);
arch/arm/mach-tegra/psci.S +1 -1
@@ -105,7 +105,7 @@ ENTRY(psci_cpu_on) mov r5, #(CSR_IMMEDIATE_WAKE | CSR_ENABLE) str r5, [r6, r2] - mov r0, #ARM_PSCI_RET_SUCCESS @ Return PSCI_RET_SUCCESS + mov r0, #PSCI_RET_SUCCESS @ Return PSCI_RET_SUCCESS pop {pc} ENDPROC(psci_cpu_on)
Signature · 1 line
2.1.4
PATCH v3 3/11 ARMv7: PSCI: update function psci_get_cpu_stack_top
In reply to macro.wave.z at gmail.comFrom: Hongbo Zhang <[email protected]>
There are issues of legacy fuction psci_get_cpu_stack_top:
First, the current algorithm arranges stacks from an fixed adress towards psci_text_end, if there are more CPUs, the stacks will overlap with psci text segment and even other segments.
This patch places stacks from psci text segment towards highter address, and all the stack space is reserved, so overlap can be avoided.
Second, even there is one word reserved in each stack for saving target PC, but this reserved space isn't used at all, the target PC is still saved to where the stack top pointer points.
This patch doesn't reserve this word as before, new way of saving target PC will be introduced in following patch.
--- arch/arm/cpu/armv7/psci.S | 10 +++++----- arch/arm/cpu/armv7/virt-dt.c | 9 +++++++-- arch/arm/include/asm/psci.h | 2 ++ 3 files changed, 14 insertions(+), 7 deletions(-)
arch/arm/cpu/armv7/psci.S +5 -5
@@ -196,16 +196,16 @@ ENDPROC(psci_cpu_off_common) @ expects CPU ID in r0 and returns stack top in r0 ENTRY(psci_get_cpu_stack_top) - mov r5, #0x400 @ 1kB of stack per CPU - mul r0, r0, r5 + mov r5, #PSCI_PERCPU_STACK_SIZE @ 1kB of stack per CPU + add r0, r0, #1 + mul r0, r0, r5 @ offset of each stack ldr r5, =psci_text_end @ end of monitor text - add r5, r5, #0x2000 @ Skip two pages + add r5, r5, #0x1000 @ Skip one page lsr r5, r5, #12 @ Align to start of page lsl r5, r5, #12 - sub r5, r5, #4 @ reserve 1 word for target PC - sub r0, r5, r0 @ here's our stack! + add r0, r5, r0 @ here's our stack! bx lr ENDPROC(psci_get_cpu_stack_top)
arch/arm/cpu/armv7/virt-dt.c +7 -2
@@ -124,9 +124,14 @@ int psci_update_dt(void *fdt)return 0 ;#endif #ifndef CONFIG_ARMV7_SECURE_BASE +size_t sz = __secure_end - __secure_start; +#ifdef CONFIG_ARMV7_PSCI + sz +=CONFIG_MAX_CPUS *PSCI_PERCPU_STACK_SIZE ; +/* margin to align psci_text_end to page end*/ + sz +=0x1000 ; +#endif /* secure code lives in RAM, keep it alive */ -fdt_add_mem_rsv (fdt, (unsigned long )__secure_start, - __secure_end - __secure_start); +fdt_add_mem_rsv (fdt, (unsigned long )__secure_start, sz);#endif return fdt_psci (fdt);
arch/arm/include/asm/psci.h +2 -0
@@ -18,6 +18,8 @@#ifndef __ARM_PSCI_H__#define __ARM_PSCI_H__ +/* size of percpu stack, 1kB */ +#define PSCI_PERCPU_STACK_SIZE 0x400/* PSCI interfaces */ #define PSCI_FN_BASE 0x84000000
Signature · 1 line
2.1.4
PATCH v3 4/11 ARMv7: PSCI: update the place of saving target PC
In reply to macro.wave.z at gmail.comFrom: Hongbo Zhang <[email protected]>
The legacy code reserves one word in each stack for saving target PC, but it isn't used, the target PC is still saved to where the stack top pointer points. This patch relocates the place for saving target PC to the lowest address of each stack, convinience is that we can save more contents if needed ilater next to saved target PC without re-adjust the stack top pointer.
--- arch/arm/cpu/armv7/ls102xa/psci.S | 1 + arch/arm/cpu/armv7/mx7/psci.S | 1 + arch/arm/cpu/armv7/psci.S | 3 ++- arch/arm/cpu/armv7/sunxi/psci_sun6i.S | 3 ++- arch/arm/cpu/armv7/sunxi/psci_sun7i.S | 3 ++- arch/arm/include/asm/psci.h | 1 + arch/arm/mach-tegra/psci.S | 3 ++- 7 files changed, 11 insertions(+), 4 deletions(-)
arch/arm/cpu/armv7/ls102xa/psci.S +1 -0
@@ -37,6 +37,7 @@ psci_cpu_on: mov r0, r1 bl psci_get_cpu_stack_top + sub r0, r0, #PSCI_TARGET_PC_OFFSET str r2, [r0] dsb
arch/arm/cpu/armv7/mx7/psci.S +1 -0
@@ -31,6 +31,7 @@ psci_cpu_on: mov r0, r1 bl psci_get_cpu_stack_top + sub r0, r0, #PSCI_TARGET_PC_OFFSET str r2, [r0] dsb
arch/arm/cpu/armv7/psci.S +2 -1
@@ -216,7 +216,8 @@ ENTRY(psci_cpu_entry) bl psci_get_cpu_id @ CPU ID => r0 bl psci_get_cpu_stack_top @ stack top => r0 - ldr r0, [r0] @ target PC at stack top + sub r0, r0, #PSCI_TARGET_PC_OFFSET + ldr r0, [r0] @ get target PC b _do_nonsec_entry ENDPROC(psci_cpu_entry)
arch/arm/cpu/armv7/sunxi/psci_sun6i.S +2 -1
@@ -136,7 +136,8 @@ psci_cpu_on: mov r0, r1 bl psci_get_cpu_stack_top @ get stack top of target CPU - str r2, [r0] @ store target PC at stack top + sub r0, r0, #PSCI_TARGET_PC_OFFSET + str r2, [r0] @ store target PC dsb movw r0, #(SUN6I_CPUCFG_BASE & 0xffff)
arch/arm/cpu/armv7/sunxi/psci_sun7i.S +2 -1
@@ -125,7 +125,8 @@ psci_cpu_on: mov r0, r1 bl psci_get_cpu_stack_top @ get stack top of target CPU - str r2, [r0] @ store target PC at stack top + sub r0, r0, #PSCI_TARGET_PC_OFFSET + str r2, [r0] @ store target PC dsb movw r0, #(SUN7I_CPUCFG_BASE & 0xffff)
arch/arm/include/asm/psci.h +1 -0
@@ -20,6 +20,7 @@/* size of percpu stack, 1kB */ #define PSCI_PERCPU_STACK_SIZE 0x400 +#define PSCI_TARGET_PC_OFFSET (PSCI_PERCPU_STACK_SIZE - 4)/* PSCI interfaces */ #define PSCI_FN_BASE 0x84000000
arch/arm/mach-tegra/psci.S +2 -1
@@ -92,7 +92,8 @@ ENTRY(psci_cpu_on) mov r0, r1 bl psci_get_cpu_stack_top @ get stack top of target CPU - str r2, [r0] @ store target PC at stack top + sub r0, r0, #PSCI_TARGET_PC_OFFSET + str r2, [r0] @ store target PC dsb ldr r6, =TEGRA_RESET_EXCEPTION_VECTOR
Signature · 1 line
2.1.4
PATCH v3 5/11 ARMv7: PSCI: add codes to save context ID for CPU_ON
In reply to macro.wave.z at gmail.comFrom: Hongbo Zhang <[email protected]>
According to latest PSCI specification, the context ID is needed by CPU_ON. This patch saves context ID to the second lowest address of the stack (next to where target PC is saved), and restores it to r0 when needed while target CPU booting up.
This patch in current format is for easier review, there are some lines duplication with previous saving target PC codes, e.g. codes of calling the psci_get_cpu_stack_top, this will be optimized by the following patch.
--- arch/arm/cpu/armv7/ls102xa/psci.S | 7 +++++++ arch/arm/cpu/armv7/mx7/psci.S | 8 +++++++- arch/arm/cpu/armv7/nonsec_virt.S | 7 +++++++ arch/arm/cpu/armv7/sunxi/psci_sun6i.S | 7 +++++++ arch/arm/cpu/armv7/sunxi/psci_sun7i.S | 8 ++++++++ arch/arm/include/asm/psci.h | 1 + arch/arm/mach-tegra/psci.S | 6 ++++++ 7 files changed, 43 insertions(+), 1 deletion(-)
arch/arm/cpu/armv7/ls102xa/psci.S +7 -0
@@ -27,6 +27,7 @@ @ r1 = target CPU @ r2 = target PC + @ r3 = target Conetxt ID .globl psci_cpu_on psci_cpu_on: push {lr}
@@ -41,6 +42,12 @@ psci_cpu_on: str r2, [r0] dsb + mov r0, r1 + bl psci_get_cpu_stack_top + sub r0, r0, #PSCI_CONTEXT_ID_OFFSET + str r3, [r0] + dsb + @ Get DCFG base address movw r4, #(CONFIG_SYS_FSL_GUTS_ADDR & 0xffff) movt r4, #(CONFIG_SYS_FSL_GUTS_ADDR >> 16)
arch/arm/cpu/armv7/mx7/psci.S +7 -1
@@ -24,7 +24,7 @@ psci_arch_init: @ r1 = target CPU @ r2 = target PC - + @ r3 = target Conetxt ID .globl psci_cpu_on psci_cpu_on: push {lr}
@@ -35,6 +35,12 @@ psci_cpu_on: str r2, [r0] dsb + mov r0, r1 + bl psci_get_cpu_stack_top + sub r0, r0, #PSCI_CONTEXT_ID_OFFSET + str r3, [r0] + dsb + ldr r2, =psci_cpu_entry bl imx_cpu_on
arch/arm/cpu/armv7/nonsec_virt.S +7 -0
@@ -11,6 +11,7 @@ #include <asm/gic.h> #include <asm/armv7.h> #include <asm/proc-armv/ptrace.h> +#include <asm/psci.h> .arch_extension sec .arch_extension virt
@@ -89,6 +90,12 @@ _secure_monitor: movne r4, #0 mcrrne p15, 4, r4, r4, c14 @ Reset CNTVOFF to zero 1: +#ifdef CONFIG_ARMV7_PSCI + bl psci_get_cpu_id + bl psci_get_cpu_stack_top + sub r0, r0, #PSCI_CONTEXT_ID_OFFSET + ldr r0, [r0] @ get Context ID in r0 +#endif mov lr, ip mov ip, #(F_BIT | I_BIT | A_BIT) @ Set A, I and F tst lr, #1 @ Check for Thumb PC
arch/arm/cpu/armv7/sunxi/psci_sun6i.S +7 -0
@@ -130,6 +130,7 @@ out: mcr p15, 0, r7, c1, c1, 0 @ r1 = target CPU @ r2 = target PC + @ r3 = target Conetxt ID .globl psci_cpu_on psci_cpu_on: push {lr}
@@ -140,6 +141,12 @@ psci_cpu_on: str r2, [r0] @ store target PC dsb + mov r0, r1 + bl psci_get_cpu_stack_top + sub r0, r0, #PSCI_CONTEXT_ID_OFFSET + str r3, [r0] + dsb + movw r0, #(SUN6I_CPUCFG_BASE & 0xffff) movt r0, #(SUN6I_CPUCFG_BASE >> 16)
arch/arm/cpu/armv7/sunxi/psci_sun7i.S +8 -0
@@ -119,6 +119,7 @@ out: mcr p15, 0, r7, c1, c1, 0 @ r1 = target CPU @ r2 = target PC + @ r3 = target Conetxt ID .globl psci_cpu_on psci_cpu_on: push {lr}
@@ -129,6 +130,13 @@ psci_cpu_on: str r2, [r0] @ store target PC dsb + + mov r0, r1 + bl psci_get_cpu_stack_top + sub r0, r0, #PSCI_CONTEXT_ID_OFFSET + str r3, [r0] + dsb + movw r0, #(SUN7I_CPUCFG_BASE & 0xffff) movt r0, #(SUN7I_CPUCFG_BASE >> 16)
arch/arm/include/asm/psci.h +1 -0
@@ -21,6 +21,7 @@/* size of percpu stack, 1kB */ #define PSCI_PERCPU_STACK_SIZE 0x400#define PSCI_TARGET_PC_OFFSET (PSCI_PERCPU_STACK_SIZE - 4) +#define PSCI_CONTEXT_ID_OFFSET (PSCI_PERCPU_STACK_SIZE - 8)/* PSCI interfaces */ #define PSCI_FN_BASE 0x84000000
arch/arm/mach-tegra/psci.S +6 -0
@@ -96,6 +96,12 @@ ENTRY(psci_cpu_on) str r2, [r0] @ store target PC dsb + mov r0, r1 + bl psci_get_cpu_stack_top + sub r0, r0, #PSCI_CONTEXT_ID_OFFSET + str r3, [r0] + dsb + ldr r6, =TEGRA_RESET_EXCEPTION_VECTOR ldr r5, =psci_cpu_entry str r5, [r6]
Signature · 1 line
2.1.4
PATCH v3 6/11 ARMv7: PSCI: factor out reusable psci_cpu_on_common
In reply to macro.wave.z at gmail.comFrom: Hongbo Zhang <[email protected]>
There are codes for saving target PC and target context ID in each platform psci_cpu_on routines, these can be factored out as psci_cpu_on_common.
--- arch/arm/cpu/armv7/ls102xa/psci.S | 12 +----------- arch/arm/cpu/armv7/mx7/psci.S | 12 +----------- arch/arm/cpu/armv7/psci.S | 15 +++++++++++++++ arch/arm/cpu/armv7/sunxi/psci_sun6i.S | 12 +----------- arch/arm/cpu/armv7/sunxi/psci_sun7i.S | 13 +------------ arch/arm/mach-tegra/psci.S | 12 +----------- 6 files changed, 20 insertions(+), 56 deletions(-)
arch/arm/cpu/armv7/ls102xa/psci.S +1 -11
@@ -36,17 +36,7 @@ psci_cpu_on: @ r1 = 0xf01 and r1, r1, #0xff - mov r0, r1 - bl psci_get_cpu_stack_top - sub r0, r0, #PSCI_TARGET_PC_OFFSET - str r2, [r0] - dsb - - mov r0, r1 - bl psci_get_cpu_stack_top - sub r0, r0, #PSCI_CONTEXT_ID_OFFSET - str r3, [r0] - dsb + bl psci_cpu_on_common @ Get DCFG base address movw r4, #(CONFIG_SYS_FSL_GUTS_ADDR & 0xffff)
arch/arm/cpu/armv7/mx7/psci.S +1 -11
@@ -29,17 +29,7 @@ psci_arch_init: psci_cpu_on: push {lr} - mov r0, r1 - bl psci_get_cpu_stack_top - sub r0, r0, #PSCI_TARGET_PC_OFFSET - str r2, [r0] - dsb - - mov r0, r1 - bl psci_get_cpu_stack_top - sub r0, r0, #PSCI_CONTEXT_ID_OFFSET - str r3, [r0] - dsb + bl psci_cpu_on_common ldr r2, =psci_cpu_entry bl imx_cpu_on
arch/arm/cpu/armv7/psci.S +15 -0
@@ -175,6 +175,21 @@ ENTRY(psci_enable_smp) ENDPROC(psci_enable_smp) .weak psci_enable_smp +/* expects target CPU in r1, target PC in r2, target conetxt ID in r3 */ +ENTRY(psci_cpu_on_common) + push {lr} + + mov r0, r1 + bl psci_get_cpu_stack_top @ get stack top of target CPU + sub r5, r0, #PSCI_TARGET_PC_OFFSET + str r2, [r5] @ save target PC + sub r5, r0, #PSCI_CONTEXT_ID_OFFSET + str r3, [r5] @ save target context ID + dsb + + pop {pc} +ENDPROC(psci_cpu_on_common) + ENTRY(psci_cpu_off_common) push {lr}
arch/arm/cpu/armv7/sunxi/psci_sun6i.S +1 -11
@@ -135,17 +135,7 @@ out: mcr p15, 0, r7, c1, c1, 0 psci_cpu_on: push {lr} - mov r0, r1 - bl psci_get_cpu_stack_top @ get stack top of target CPU - sub r0, r0, #PSCI_TARGET_PC_OFFSET - str r2, [r0] @ store target PC - dsb - - mov r0, r1 - bl psci_get_cpu_stack_top - sub r0, r0, #PSCI_CONTEXT_ID_OFFSET - str r3, [r0] - dsb + bl psci_cpu_on_common movw r0, #(SUN6I_CPUCFG_BASE & 0xffff) movt r0, #(SUN6I_CPUCFG_BASE >> 16)
arch/arm/cpu/armv7/sunxi/psci_sun7i.S +1 -12
@@ -124,18 +124,7 @@ out: mcr p15, 0, r7, c1, c1, 0 psci_cpu_on: push {lr} - mov r0, r1 - bl psci_get_cpu_stack_top @ get stack top of target CPU - sub r0, r0, #PSCI_TARGET_PC_OFFSET - str r2, [r0] @ store target PC - dsb - - - mov r0, r1 - bl psci_get_cpu_stack_top - sub r0, r0, #PSCI_CONTEXT_ID_OFFSET - str r3, [r0] - dsb + bl psci_cpu_on_common movw r0, #(SUN7I_CPUCFG_BASE & 0xffff) movt r0, #(SUN7I_CPUCFG_BASE >> 16)
arch/arm/mach-tegra/psci.S +1 -11
@@ -90,17 +90,7 @@ ENDPROC(psci_cpu_off) ENTRY(psci_cpu_on) push {lr} - mov r0, r1 - bl psci_get_cpu_stack_top @ get stack top of target CPU - sub r0, r0, #PSCI_TARGET_PC_OFFSET - str r2, [r0] @ store target PC - dsb - - mov r0, r1 - bl psci_get_cpu_stack_top - sub r0, r0, #PSCI_CONTEXT_ID_OFFSET - str r3, [r0] - dsb + bl psci_cpu_on_common ldr r6, =TEGRA_RESET_EXCEPTION_VECTOR ldr r5, =psci_cpu_entry
Signature · 1 line
2.1.4
PATCH v3 7/11 ARMv7: PSCI: add PSCI v1.0 functions skeleton
In reply to macro.wave.z at gmail.comFrom: Hongbo Zhang <[email protected]>
This patch adds all the PSCI v1.0 functions in to the common framework, with all the functions returning "not sopported" by default, as a common framework all the functions are added here, it is up to every platform developer to decide which version of PSCI and which functions in it to be implemented.
--- arch/arm/cpu/armv7/psci.S | 70 ++++++++++++++++++++++++++++++++++++++++++++ arch/arm/cpu/armv7/virt-dt.c | 45 +++++++++++++++++++++------- arch/arm/include/asm/psci.h | 21 +++++++++++++ 3 files changed, 125 insertions(+), 11 deletions(-)
arch/arm/cpu/armv7/psci.S +70 -0
@@ -46,30 +46,100 @@ ENTRY(default_psci_vector) ENDPROC(default_psci_vector) .weak default_psci_vector +ENTRY(psci_version) ENTRY(psci_cpu_suspend) ENTRY(psci_cpu_off) ENTRY(psci_cpu_on) +ENTRY(psci_affinity_info) ENTRY(psci_migrate) +ENTRY(psci_migrate_info_type) +ENTRY(psci_migrate_info_up_cpu) +ENTRY(psci_system_off) +ENTRY(psci_system_reset) +ENTRY(psci_features) +ENTRY(psci_cpu_freeze) +ENTRY(psci_cpu_default_suspend) +ENTRY(psci_node_hw_state) +ENTRY(psci_system_suspend) +ENTRY(psci_set_suspend_mode) +ENTRY(psi_stat_residency) +ENTRY(psci_stat_count) mov r0, #PSCI_RET_NOT_SUPPORTED @ Return -1 (Not Supported) mov pc, lr +ENDPROC(psci_stat_count) +ENDPROC(psi_stat_residency) +ENDPROC(psci_set_suspend_mode) +ENDPROC(psci_system_suspend) +ENDPROC(psci_node_hw_state) +ENDPROC(psci_cpu_default_suspend) +ENDPROC(psci_cpu_freeze) +ENDPROC(psci_features) +ENDPROC(psci_system_reset) +ENDPROC(psci_system_off) +ENDPROC(psci_migrate_info_up_cpu) +ENDPROC(psci_migrate_info_type) ENDPROC(psci_migrate) +ENDPROC(psci_affinity_info) ENDPROC(psci_cpu_on) ENDPROC(psci_cpu_off) ENDPROC(psci_cpu_suspend) +ENDPROC(psci_version) +.weak psci_version .weak psci_cpu_suspend .weak psci_cpu_off .weak psci_cpu_on +.weak psci_affinity_info .weak psci_migrate +.weak psci_migrate_info_type +.weak psci_migrate_info_up_cpu +.weak psci_system_off +.weak psci_system_reset +.weak psci_features +.weak psci_cpu_freeze +.weak psci_cpu_default_suspend +.weak psci_node_hw_state +.weak psci_system_suspend +.weak psci_set_suspend_mode +.weak psi_stat_residency +.weak psci_stat_count _psci_table: + .word PSCI_FN_PSCI_VERSION + .word psci_version .word PSCI_FN_CPU_SUSPEND .word psci_cpu_suspend .word PSCI_FN_CPU_OFF .word psci_cpu_off .word PSCI_FN_CPU_ON .word psci_cpu_on + .word PSCI_FN_AFFINITY_INFO + .word psci_affinity_info .word PSCI_FN_MIGRATE .word psci_migrate + .word PSCI_FN_MIGRATE_INFO_TYPE + .word psci_migrate_info_type + .word PSCI_FN_MIGRATE_INFO_UP_CPU + .word psci_migrate_info_up_cpu + .word PSCI_FN_SYSTEM_OFF + .word psci_system_off + .word PSCI_FN_SYSTEM_RESET + .word psci_system_reset + .word PSCI_FN_PSCI_FEATURES + .word psci_features + .word PSCI_FN_CPU_FREEZE + .word psci_cpu_freeze + .word PSCI_FN_CPU_DEFAULT_SUSPEND + .word psci_cpu_default_suspend + .word PSCI_FN_NODE_HW_STATE + .word psci_node_hw_state + .word PSCI_FN_SYSTEM_SUSPEND + .word psci_system_suspend + .word PSCI_FN_SET_SUSPEND_MODE + .word psci_set_suspend_mode + .word PSCI_FN_STAT_RESIDENCY + .word psi_stat_residency + .word PSCI_FN_STAT_COUNT + .word psci_stat_count .word 0 .word 0
arch/arm/cpu/armv7/virt-dt.c +34 -11
62 lines not on this page · raw message
arch/arm/include/asm/psci.h +21 -0
@@ -27,16 +27,37 @@#define PSCI_FN_BASE 0x84000000#define PSCI_FN_ID (n) (PSCI_FN_BASE + (n)) +#define PSCI_FN_PSCI_VERSION PSCI_FN_ID(0)#define PSCI_FN_CPU_SUSPEND PSCI_FN_ID(1)#define PSCI_FN_CPU_OFF PSCI_FN_ID(2)#define PSCI_FN_CPU_ON PSCI_FN_ID(3) +#define PSCI_FN_AFFINITY_INFO PSCI_FN_ID(4)#define PSCI_FN_MIGRATE PSCI_FN_ID(5) +#define PSCI_FN_MIGRATE_INFO_TYPE PSCI_FN_ID(6) +#define PSCI_FN_MIGRATE_INFO_UP_CPU PSCI_FN_ID(7) +#define PSCI_FN_SYSTEM_OFF PSCI_FN_ID(8) +#define PSCI_FN_SYSTEM_RESET PSCI_FN_ID(9) +#define PSCI_FN_PSCI_FEATURES PSCI_FN_ID(10) +#define PSCI_FN_CPU_FREEZE PSCI_FN_ID(11) +#define PSCI_FN_CPU_DEFAULT_SUSPEND PSCI_FN_ID(12) +#define PSCI_FN_NODE_HW_STATE PSCI_FN_ID(13) +#define PSCI_FN_SYSTEM_SUSPEND PSCI_FN_ID(14) +#define PSCI_FN_SET_SUSPEND_MODE PSCI_FN_ID(15) +#define PSCI_FN_STAT_RESIDENCY PSCI_FN_ID(16) +#define PSCI_FN_STAT_COUNT PSCI_FN_ID(17) +/* PSCI return values */ #define PSCI_RET_SUCCESS 0#define PSCI_RET_NOT_SUPPORTED (-1)#define PSCI_RET_INVALID_PARAMS (-2)#define PSCI_RET_DENIED (-3) +#define PSCI_RET_ALREADY_ON (-4) +#define PSCI_RET_ON_PENDING (-5) +#define PSCI_RET_INTERNAL_FAILURE (-6) +#define PSCI_RET_NOT_PRESENT (-7) +#define PSCI_RET_DISABLED (-8) +#define PSCI_RET_INVALID_ADDRESS (-9)#ifndef __ASSEMBLY__int psci_update_dt (void *fdt);
Signature · 1 line
2.1.4
PATCH v3 7/11 ARMv7: PSCI: add PSCI v1.0 functions skeleton
Hi,
Quoted 69 lines · macro.wave.z at gmail.com
From: Hongbo Zhang <[email protected]>
This patch adds all the PSCI v1.0 functions in to the common framework, with all the functions returning "not sopported" by default, as a common framework all the functions are added here, it is up to every platform developer to decide which version of PSCI and which functions in it to be implemented.
Signed-off-by Hongbo Zhang <[email protected]>Signed-off-by Wang Dongsheng <[email protected]>--- arch/arm/cpu/armv7/psci.S | 70 ++++++++++++++++++++++++++++++++++++++++++++ arch/arm/cpu/armv7/virt-dt.c | 45 +++++++++++++++++++++------- arch/arm/include/asm/psci.h | 21 +++++++++++++ 3 files changed, 125 insertions(+), 11 deletions(-)arch/arm/cpu/armv7/psci.S +32
-0@@ -46,30 +46,100 @@ ENTRY(default_psci_vector) ENDPROC(default_psci_vector) .weak default_psci_vector +ENTRY(psci_version) ENTRY(psci_cpu_suspend) ENTRY(psci_cpu_off) ENTRY(psci_cpu_on) +ENTRY(psci_affinity_info) ENTRY(psci_migrate) +ENTRY(psci_migrate_info_type) +ENTRY(psci_migrate_info_up_cpu) +ENTRY(psci_system_off) +ENTRY(psci_system_reset) +ENTRY(psci_features) +ENTRY(psci_cpu_freeze) +ENTRY(psci_cpu_default_suspend) +ENTRY(psci_node_hw_state) +ENTRY(psci_system_suspend) +ENTRY(psci_set_suspend_mode) +ENTRY(psi_stat_residency) +ENTRY(psci_stat_count) mov r0, #PSCI_RET_NOT_SUPPORTED @ Return -1 (Not Supported) mov pc, lr +ENDPROC(psci_stat_count) +ENDPROC(psi_stat_residency) +ENDPROC(psci_set_suspend_mode) +ENDPROC(psci_system_suspend) +ENDPROC(psci_node_hw_state) +ENDPROC(psci_cpu_default_suspend) +ENDPROC(psci_cpu_freeze) +ENDPROC(psci_features) +ENDPROC(psci_system_reset) +ENDPROC(psci_system_off) +ENDPROC(psci_migrate_info_up_cpu) +ENDPROC(psci_migrate_info_type) ENDPROC(psci_migrate) +ENDPROC(psci_affinity_info) ENDPROC(psci_cpu_on) ENDPROC(psci_cpu_off) ENDPROC(psci_cpu_suspend) +ENDPROC(psci_version) +.weak psci_version .weak psci_cpu_suspend .weak psci_cpu_off .weak psci_cpu_on +.weak psci_affinity_info .weak psci_migrate +.weak psci_migrate_info_type +.weak psci_migrate_info_up_cpu
arch/arm/cpu/armv7/psci.S ENTRY(default_psci_vector) · line 104
Quoted 10 lines
arch/arm/cpu/armv7/psci.S +10
-0+.weak psci_system_off +.weak psci_system_reset +.weak psci_features +.weak psci_cpu_freeze +.weak psci_cpu_default_suspend +.weak psci_node_hw_state +.weak psci_system_suspend +.weak psci_set_suspend_mode +.weak psi_stat_residency +.weak psci_stat_count
I wonder if we can have something more clever here to handle unimplemented functions. For the PSCI_FEATURES call we would need this very same list of functions again, so is it worthwhile to have some _code_ instead of a table which does the dispatching?
So this code could check against a list of unimplemented functions, returning #PSCI_RET_NOT_SUPPORTED if there is a hit.
Or we just have a list of _implemented_ functions and for every miss we return #PSCI_RET_NOT_SUPPORTED.
The PSCI_FEATURES call could then just use the very same list and this could be a generic implementation then.
Quoted 30 lines
arch/arm/cpu/armv7/psci.S +20
-0_psci_table: + .word PSCI_FN_PSCI_VERSION + .word psci_version .word PSCI_FN_CPU_SUSPEND .word psci_cpu_suspend .word PSCI_FN_CPU_OFF .word psci_cpu_off .word PSCI_FN_CPU_ON .word psci_cpu_on + .word PSCI_FN_AFFINITY_INFO + .word psci_affinity_info .word PSCI_FN_MIGRATE .word psci_migrate + .word PSCI_FN_MIGRATE_INFO_TYPE + .word psci_migrate_info_type + .word PSCI_FN_MIGRATE_INFO_UP_CPU + .word psci_migrate_info_up_cpu + .word PSCI_FN_SYSTEM_OFF + .word psci_system_off + .word PSCI_FN_SYSTEM_RESET + .word psci_system_reset + .word PSCI_FN_PSCI_FEATURES + .word psci_features + .word PSCI_FN_CPU_FREEZE + .word psci_cpu_freeze + .word PSCI_FN_CPU_DEFAULT_SUSPEND + .word psci_cpu_default_suspend + .word PSCI_FN_NODE_HW_STATE + .word psci_node_hw_state
arch/arm/cpu/armv7/psci.S ENTRY(default_psci_vector) · line 144
Quoted 10 lines
arch/arm/cpu/armv7/psci.S +8
-0+ .word PSCI_FN_SYSTEM_SUSPEND + .word psci_system_suspend + .word PSCI_FN_SET_SUSPEND_MODE + .word psci_set_suspend_mode + .word PSCI_FN_STAT_RESIDENCY + .word psi_stat_residency + .word PSCI_FN_STAT_COUNT + .word psci_stat_count .word 0 .word 0
So those function IDs are now contigious and also much more, can we just use the lower bits of the function ID as an index and get rid of the redundant pairing of (function ID, address) here?
Quoted 28 lines
arch/arm/cpu/armv7/virt-dt.c +19
-0@@ -26,6 +26,35 @@#include <asm/armv7.h> #include <asm/psci.h> +#ifdef CONFIG_ARMV7_PSCI +#ifdef CONFIG_ARMV7_PSCI_1_0 +static int fdt_psci_1_0_fixup (void *fdt,int nodeoff) +{ +return fdt_setprop_string (fdt, nodeoff,"compatible" ,"arm,psci-1.0" ); +} +#endif + +static int fdt_psci_0_1_fixup (void *fdt,int nodeoff) +{ +int ret; + + ret =fdt_appendprop_string (fdt, nodeoff,"compatible" ,"arm,psci" ); +if (ret) +return ret; + ret =fdt_setprop_u32 (fdt, nodeoff,"cpu_suspend" ,PSCI_FN_CPU_SUSPEND ); +if (ret) +return ret; + ret =fdt_setprop_u32 (fdt, nodeoff,"cpu_off" ,PSCI_FN_CPU_OFF );
arch/arm/cpu/armv7/virt-dt.c line 57
Quoted 10 lines
arch/arm/cpu/armv7/virt-dt.c +10
-0+if (ret) +return ret; + ret =fdt_setprop_u32 (fdt, nodeoff,"cpu_on" ,PSCI_FN_CPU_ON ); +if (ret) +return ret; + + return fdt_setprop_u32(fdt, nodeoff, "migrate", PSCI_FN_MIGRATE); +} +#endif +
I think it would be worth to use the compatibility features of the PSCI DT bindings here, that would allow to boot OSes which don't support PSCI 0.2 and help to ease migration of boards to v1.0 PSCI without regressions. So basically:
- The compatible string in the 1_0_fixup function becomes:
"arm,psci-1.0", "arm,psci-0,2", "arm,psci"
- This 0_1_fixup function above just sets the compatible string.
...
Quoted 10 lines
arch/arm/cpu/armv7/virt-dt.c +0
-3static int fdt_psci (void *fdt) {#ifdef CONFIG_ARMV7_PSCI @@ -67,22 +96,16 @@ static int fdt_psci(void *fdt)return nodeoff; } - tmp =fdt_setprop_string (fdt, nodeoff,"compatible" ,"arm,psci" ); -if (tmp) -return tmp;
arch/arm/cpu/armv7/virt-dt.c static int fdt_psci(void *fdt) · line 82
Quoted 10 lines
arch/arm/cpu/armv7/virt-dt.c +0
-7tmp =fdt_setprop_string (fdt, nodeoff,"method" ,"smc" );if (tmp)return tmp; - tmp =fdt_setprop_u32 (fdt, nodeoff,"cpu_suspend" ,PSCI_FN_CPU_SUSPEND ); -if (tmp) -return tmp; - tmp =fdt_setprop_u32 (fdt, nodeoff,"cpu_off" ,PSCI_FN_CPU_OFF ); -if (tmp) -return tmp; - tmp =fdt_setprop_u32 (fdt, nodeoff,"cpu_on" ,PSCI_FN_CPU_ON );
We keep those function ID specifiers in the node for compatibility reasons. For PSCI 0.2 and higher they are ignored, but older OSes can just use them as before.
arch/arm/cpu/armv7/virt-dt.c static int fdt_psci(void *fdt) · line 85
Quoted 6 lines
arch/arm/cpu/armv7/virt-dt.c +3
-1+ +#ifdef CONFIG_ARMV7_PSCI_1_0 + tmp =fdt_psci_1_0_fixup (fdt, nodeoff);if (tmp)return tmp; - tmp =fdt_setprop_u32 (fdt, nodeoff,"migrate" ,PSCI_FN_MIGRATE );
We keep this also.
So eventually the nodes look very similar, it's just the list of compatible strings that differs.
Quoted 34 lines
arch/arm/cpu/armv7/virt-dt.c +2
-0+#endif + tmp =fdt_psci_0_1_fixup (fdt, nodeoff);if (tmp)return tmp;#endif arch/arm/include/asm/psci.h +15
-0@@ -27,16 +27,37 @@#define PSCI_FN_BASE 0x84000000#define PSCI_FN_ID (n) (PSCI_FN_BASE + (n)) +#define PSCI_FN_PSCI_VERSION PSCI_FN_ID(0)#define PSCI_FN_CPU_SUSPEND PSCI_FN_ID(1)#define PSCI_FN_CPU_OFF PSCI_FN_ID(2)#define PSCI_FN_CPU_ON PSCI_FN_ID(3) +#define PSCI_FN_AFFINITY_INFO PSCI_FN_ID(4)#define PSCI_FN_MIGRATE PSCI_FN_ID(5) +#define PSCI_FN_MIGRATE_INFO_TYPE PSCI_FN_ID(6) +#define PSCI_FN_MIGRATE_INFO_UP_CPU PSCI_FN_ID(7) +#define PSCI_FN_SYSTEM_OFF PSCI_FN_ID(8) +#define PSCI_FN_SYSTEM_RESET PSCI_FN_ID(9) +#define PSCI_FN_PSCI_FEATURES PSCI_FN_ID(10) +#define PSCI_FN_CPU_FREEZE PSCI_FN_ID(11) +#define PSCI_FN_CPU_DEFAULT_SUSPEND PSCI_FN_ID(12) +#define PSCI_FN_NODE_HW_STATE PSCI_FN_ID(13) +#define PSCI_FN_SYSTEM_SUSPEND PSCI_FN_ID(14) +#define PSCI_FN_SET_SUSPEND_MODE PSCI_FN_ID(15) +#define PSCI_FN_STAT_RESIDENCY PSCI_FN_ID(16) +#define PSCI_FN_STAT_COUNT PSCI_FN_ID(17) +/* PSCI return values */
arch/arm/include/asm/psci.h line 60
Quoted 10 lines
arch/arm/include/asm/psci.h +6
-0#define PSCI_RET_SUCCESS 0#define PSCI_RET_NOT_SUPPORTED (-1)#define PSCI_RET_INVALID_PARAMS (-2)#define PSCI_RET_DENIED (-3) +#define PSCI_RET_ALREADY_ON (-4) +#define PSCI_RET_ON_PENDING (-5) +#define PSCI_RET_INTERNAL_FAILURE (-6) +#define PSCI_RET_NOT_PRESENT (-7) +#define PSCI_RET_DISABLED (-8) +#define PSCI_RET_INVALID_ADDRESS (-9)
I checked the function IDs and the return codes against the spec, they are correct.
Cheers,
Andre.
PATCH v3 7/11 ARMv7: PSCI: add PSCI v1.0 functions skeleton
Quoted 85 lines · Andre Przywara
Hi,
Quoted 69 lines · macro.wave.z at gmail.com
From: Hongbo Zhang <[email protected]>
This patch adds all the PSCI v1.0 functions in to the common framework, with all the functions returning "not sopported" by default, as a common framework all the functions are added here, it is up to every platform developer to decide which version of PSCI and which functions in it to be implemented.
Signed-off-by Hongbo Zhang <[email protected]>Signed-off-by Wang Dongsheng <[email protected]>--- arch/arm/cpu/armv7/psci.S | 70 ++++++++++++++++++++++++++++++++++++++++++++ arch/arm/cpu/armv7/virt-dt.c | 45 +++++++++++++++++++++------- arch/arm/include/asm/psci.h | 21 +++++++++++++ 3 files changed, 125 insertions(+), 11 deletions(-)arch/arm/cpu/armv7/psci.S +32
-0@@ -46,30 +46,100 @@ ENTRY(default_psci_vector) ENDPROC(default_psci_vector) .weak default_psci_vector +ENTRY(psci_version) ENTRY(psci_cpu_suspend) ENTRY(psci_cpu_off) ENTRY(psci_cpu_on) +ENTRY(psci_affinity_info) ENTRY(psci_migrate) +ENTRY(psci_migrate_info_type) +ENTRY(psci_migrate_info_up_cpu) +ENTRY(psci_system_off) +ENTRY(psci_system_reset) +ENTRY(psci_features) +ENTRY(psci_cpu_freeze) +ENTRY(psci_cpu_default_suspend) +ENTRY(psci_node_hw_state) +ENTRY(psci_system_suspend) +ENTRY(psci_set_suspend_mode) +ENTRY(psi_stat_residency) +ENTRY(psci_stat_count) mov r0, #PSCI_RET_NOT_SUPPORTED @ Return -1 (Not Supported) mov pc, lr +ENDPROC(psci_stat_count) +ENDPROC(psi_stat_residency) +ENDPROC(psci_set_suspend_mode) +ENDPROC(psci_system_suspend) +ENDPROC(psci_node_hw_state) +ENDPROC(psci_cpu_default_suspend) +ENDPROC(psci_cpu_freeze) +ENDPROC(psci_features) +ENDPROC(psci_system_reset) +ENDPROC(psci_system_off) +ENDPROC(psci_migrate_info_up_cpu) +ENDPROC(psci_migrate_info_type) ENDPROC(psci_migrate) +ENDPROC(psci_affinity_info) ENDPROC(psci_cpu_on) ENDPROC(psci_cpu_off) ENDPROC(psci_cpu_suspend) +ENDPROC(psci_version) +.weak psci_version .weak psci_cpu_suspend .weak psci_cpu_off .weak psci_cpu_on +.weak psci_affinity_info .weak psci_migrate +.weak psci_migrate_info_type +.weak psci_migrate_info_up_cpuarch/arm/cpu/armv7/psci.S ENTRY(default_psci_vector) · line 104
Quoted 10 lines
arch/arm/cpu/armv7/psci.S +10
-0+.weak psci_system_off +.weak psci_system_reset +.weak psci_features +.weak psci_cpu_freeze +.weak psci_cpu_default_suspend +.weak psci_node_hw_state +.weak psci_system_suspend +.weak psci_set_suspend_mode +.weak psi_stat_residency +.weak psci_stat_countI wonder if we can have something more clever here to handle unimplemented functions. For the
PSCI_FEATUREScall we would need this
Quoted 9 lines
very same list of functions again, so is it worthwhile to have some _code_ instead of a table which does the dispatching?
So this code could check against a list of unimplemented functions, returning #PSCI_RET_NOT_SUPPORTED if there is a hit.
Or we just have a list of _implemented_ functions and for every miss we return #PSCI_RET_NOT_SUPPORTED.
ThePSCI_FEATUREScall could then just use the very same list and this could be a generic implementation then.
I don't think so, because this is just a dummy and common framework, we cannot expect which functions will be implemented in each specific platforms, it is up to each platform's developer to decide which functions they need.
We offer default NOT_SUPPORTED implementation here, then each platform is only responsible to their own implementations, so when a non-implemented function is called, the PSCI code won't crush.
Quoted 41 lines
Quoted 30 lines
arch/arm/cpu/armv7/psci.S +20
-0_psci_table: + .word PSCI_FN_PSCI_VERSION + .word psci_version .word PSCI_FN_CPU_SUSPEND .word psci_cpu_suspend .word PSCI_FN_CPU_OFF .word psci_cpu_off .word PSCI_FN_CPU_ON .word psci_cpu_on + .word PSCI_FN_AFFINITY_INFO + .word psci_affinity_info .word PSCI_FN_MIGRATE .word psci_migrate + .word PSCI_FN_MIGRATE_INFO_TYPE + .word psci_migrate_info_type + .word PSCI_FN_MIGRATE_INFO_UP_CPU + .word psci_migrate_info_up_cpu + .word PSCI_FN_SYSTEM_OFF + .word psci_system_off + .word PSCI_FN_SYSTEM_RESET + .word psci_system_reset + .word PSCI_FN_PSCI_FEATURES + .word psci_features + .word PSCI_FN_CPU_FREEZE + .word psci_cpu_freeze + .word PSCI_FN_CPU_DEFAULT_SUSPEND + .word psci_cpu_default_suspend + .word PSCI_FN_NODE_HW_STATE + .word psci_node_hw_statearch/arm/cpu/armv7/psci.S ENTRY(default_psci_vector) · line 144
Quoted 10 lines
arch/arm/cpu/armv7/psci.S +8
-0+ .word PSCI_FN_SYSTEM_SUSPEND + .word psci_system_suspend + .word PSCI_FN_SET_SUSPEND_MODE + .word psci_set_suspend_mode + .word PSCI_FN_STAT_RESIDENCY + .word psi_stat_residency + .word PSCI_FN_STAT_COUNT + .word psci_stat_count .word 0 .word 0
Quoted 4 lines
So those function IDs are now contigious and also much more, can we just use the lower bits of the function ID as an index and get rid of the redundant pairing of (function ID, address) here?
This a for compatible of the v0.1, because in v0.1 the function IDs are implementation decided and may not be continuous.
Quoted 37 lines
Quoted 37 lines
arch/arm/cpu/armv7/virt-dt.c +28
-0@@ -26,6 +26,35 @@#include <asm/armv7.h> #include <asm/psci.h> +#ifdef CONFIG_ARMV7_PSCI +#ifdef CONFIG_ARMV7_PSCI_1_0 +static int fdt_psci_1_0_fixup (void *fdt,int nodeoff) +{ +return fdt_setprop_string (fdt, nodeoff,"compatible" ,"arm,psci-1.0" ); +} +#endif + +static int fdt_psci_0_1_fixup (void *fdt,int nodeoff) +{ +int ret; + + ret =fdt_appendprop_string (fdt, nodeoff,"compatible" ,"arm,psci" ); +if (ret) +return ret; + ret =fdt_setprop_u32 (fdt, nodeoff,"cpu_suspend" ,PSCI_FN_CPU_SUSPEND ); +if (ret) +return ret; + ret =fdt_setprop_u32 (fdt, nodeoff,"cpu_off" ,PSCI_FN_CPU_OFF ); +if (ret) +return ret; + ret =fdt_setprop_u32 (fdt, nodeoff,"cpu_on" ,PSCI_FN_CPU_ON ); +if (ret) +return ret; + +return fdt_setprop_u32 (fdt, nodeoff,"migrate" ,PSCI_FN_MIGRATE ); +} +#endif
Quoted 8 lines
arch/arm/cpu/armv7/virt-dt.c line 57
Quoted 1 line
arch/arm/cpu/armv7/virt-dt.c +1
-0+I think it would be worth to use the compatibility features of the PSCI DT bindings here, that would allow to boot OSes which don't support PSCI 0.2 and help to ease migration of boards to v1.0 PSCI without regressions. So basically:
- The compatible string in the 1_0_fixup function becomes:
"arm,psci-1.0", "arm,psci-0,2", "arm,psci"
I use fdt_appendprop_string, it *append* compatible string instead of *set*, so the final string would be:
"arm,psci-1.0", "arm,psci"
The "arm,psci-0,2", was missed, our internal opinion was that since we've had latest v1.0 and the v0.2 isn't implement at all, so we could skip v0.2 here.
But now your suggestion sounds reasonable, since v1.0 is compatible with v0.2, we can add these three strings in the 1_0_fixup.
Quoted 19 lines
- This 0_1_fixup function above just sets the compatible string.
...Quoted 16 lines
arch/arm/cpu/armv7/virt-dt.c +0
-6static int fdt_psci (void *fdt) {#ifdef CONFIG_ARMV7_PSCI @@ -67,22 +96,16 @@ static int fdt_psci(void *fdt)return nodeoff; } - tmp =fdt_setprop_string (fdt, nodeoff,"compatible" ,"arm,psci" ); -if (tmp) -return tmp; tmp =fdt_setprop_string (fdt, nodeoff,"method" ,"smc" );if (tmp)return tmp; - tmp =fdt_setprop_u32 (fdt, nodeoff,"cpu_suspend" ,PSCI_FN_CPU_SUSPEND ); -if (tmp) -return tmp;
Quoted 9 lines
arch/arm/cpu/armv7/virt-dt.c static int fdt_psci(void *fdt) · line 82
Quoted 4 lines
arch/arm/cpu/armv7/virt-dt.c +0
-4- tmp =fdt_setprop_u32 (fdt, nodeoff,"cpu_off" ,PSCI_FN_CPU_OFF ); -if (tmp) -return tmp; - tmp =fdt_setprop_u32 (fdt, nodeoff,"cpu_on" ,PSCI_FN_CPU_ON );We keep those function ID specifiers in the node for compatibility reasons. For PSCI 0.2 and higher they are ignored, but older OSes can just use them as before.
Yes, good suggestion, thanks.
Quoted 9 lines
arch/arm/cpu/armv7/virt-dt.c static int fdt_psci(void *fdt) · line 85
Quoted 6 lines
arch/arm/cpu/armv7/virt-dt.c +3
-1+ +#ifdef CONFIG_ARMV7_PSCI_1_0 + tmp =fdt_psci_1_0_fixup (fdt, nodeoff);if (tmp)return tmp; - tmp =fdt_setprop_u32 (fdt, nodeoff,"migrate" ,PSCI_FN_MIGRATE );We keep this also.
Quoted 3 lines
So eventually the nodes look very similar, it's just the list of compatible strings that differs.
Yes.
Quoted 33 lines
Quoted 33 lines
arch/arm/cpu/armv7/virt-dt.c +2
-0+#endif + tmp =fdt_psci_0_1_fixup (fdt, nodeoff);if (tmp)return tmp;#endif arch/arm/include/asm/psci.h +15
-0@@ -27,16 +27,37 @@#define PSCI_FN_BASE 0x84000000#define PSCI_FN_ID (n) (PSCI_FN_BASE + (n)) +#define PSCI_FN_PSCI_VERSION PSCI_FN_ID(0)#define PSCI_FN_CPU_SUSPEND PSCI_FN_ID(1)#define PSCI_FN_CPU_OFF PSCI_FN_ID(2)#define PSCI_FN_CPU_ON PSCI_FN_ID(3) +#define PSCI_FN_AFFINITY_INFO PSCI_FN_ID(4)#define PSCI_FN_MIGRATE PSCI_FN_ID(5) +#define PSCI_FN_MIGRATE_INFO_TYPE PSCI_FN_ID(6) +#define PSCI_FN_MIGRATE_INFO_UP_CPU PSCI_FN_ID(7) +#define PSCI_FN_SYSTEM_OFF PSCI_FN_ID(8) +#define PSCI_FN_SYSTEM_RESET PSCI_FN_ID(9) +#define PSCI_FN_PSCI_FEATURES PSCI_FN_ID(10) +#define PSCI_FN_CPU_FREEZE PSCI_FN_ID(11) +#define PSCI_FN_CPU_DEFAULT_SUSPEND PSCI_FN_ID(12) +#define PSCI_FN_NODE_HW_STATE PSCI_FN_ID(13) +#define PSCI_FN_SYSTEM_SUSPEND PSCI_FN_ID(14) +#define PSCI_FN_SET_SUSPEND_MODE PSCI_FN_ID(15) +#define PSCI_FN_STAT_RESIDENCY PSCI_FN_ID(16) +#define PSCI_FN_STAT_COUNT PSCI_FN_ID(17) +
Quoted 15 lines
arch/arm/include/asm/psci.h line 60
Quoted 11 lines
arch/arm/include/asm/psci.h +6
-0/* PSCI return values */ #define PSCI_RET_SUCCESS 0#define PSCI_RET_NOT_SUPPORTED (-1)#define PSCI_RET_INVALID_PARAMS (-2)#define PSCI_RET_DENIED (-3) +#define PSCI_RET_ALREADY_ON (-4) +#define PSCI_RET_ON_PENDING (-5) +#define PSCI_RET_INTERNAL_FAILURE (-6) +#define PSCI_RET_NOT_PRESENT (-7) +#define PSCI_RET_DISABLED (-8) +#define PSCI_RET_INVALID_ADDRESS (-9)I checked the function IDs and the return codes against the spec, they are correct.
Thanks for review.
Hongbo Zhang @ NXP/Freescale
Quoted 2 lines
Cheers,
Andre.
PATCH v3 7/11 ARMv7: PSCI: add PSCI v1.0 functions skeleton
Quoted 6 lines · Hongbo Zhang
Quoted 5 lines · Andre Przywara
Hi,
Quoted 2 lines · macro.wave.z at gmail.com
From: Hongbo Zhang <[email protected]>
<snip>
Quoted 28 lines
Quoted 18 lines
...
Quoted 16 lines
static int
fdt_psci(void *fdt)
{
#ifdefCONFIG_ARMV7_PSCIarch/arm/cpu/armv7/virt-dt.c +0
-6@@ -67,22 +96,16 @@ static int fdt_psci(void *fdt)return nodeoff; } - tmp =fdt_setprop_string (fdt, nodeoff,"compatible" ,"arm,psci" ); -if (tmp) -return tmp; tmp =fdt_setprop_string (fdt, nodeoff,"method" ,"smc" );if (tmp)return tmp; - tmp =fdt_setprop_u32 (fdt, nodeoff,"cpu_suspend" ,PSCI_FN_CPU_SUSPEND ); -if (tmp) -return tmp;Quoted 9 lines
arch/arm/cpu/armv7/virt-dt.c static int fdt_psci(void *fdt) · line 82
Quoted 4 lines
arch/arm/cpu/armv7/virt-dt.c +0
-4- tmp =fdt_setprop_u32 (fdt, nodeoff,"cpu_off" ,PSCI_FN_CPU_OFF ); -if (tmp) -return tmp; - tmp =fdt_setprop_u32 (fdt, nodeoff,"cpu_on" ,PSCI_FN_CPU_ON );We keep those function ID specifiers in the node for compatibility reasons. For PSCI 0.2 and higher they are ignored, but older OSes can just use them as before.
Quoted 1 line
Yes, good suggestion, thanks.
Hongbo,
I see you are in agreement. Are you going to respin this patch, or keep it as is?
York
PATCH v3 7/11 ARMv7: PSCI: add PSCI v1.0 functions skeleton
Quoted 38 lines · York Sun
Quoted 6 lines · Hongbo Zhang
Quoted 5 lines · Andre Przywara
Hi,
Quoted 2 lines · macro.wave.z at gmail.com
From: Hongbo Zhang <[email protected]>
<snip>
Quoted 28 lines
Quoted 27 lines
...
Quoted 10 lines
static int
fdt_psci(void *fdt)
{
#ifdefCONFIG_ARMV7_PSCIarch/arm/cpu/armv7/virt-dt.c +0
-3@@ -67,22 +96,16 @@ static int fdt_psci(void *fdt)return nodeoff; } - tmp =fdt_setprop_string (fdt, nodeoff,"compatible" ,"arm,psci" ); -if (tmp) -return tmp;arch/arm/cpu/armv7/virt-dt.c static int fdt_psci(void *fdt) · line 82
Quoted 10 lines
arch/arm/cpu/armv7/virt-dt.c +0
-7tmp =fdt_setprop_string (fdt, nodeoff,"method" ,"smc" );if (tmp)return tmp; - tmp =fdt_setprop_u32 (fdt, nodeoff,"cpu_suspend" ,PSCI_FN_CPU_SUSPEND ); -if (tmp) -return tmp; - tmp =fdt_setprop_u32 (fdt, nodeoff,"cpu_off" ,PSCI_FN_CPU_OFF ); -if (tmp) -return tmp; - tmp =fdt_setprop_u32 (fdt, nodeoff,"cpu_on" ,PSCI_FN_CPU_ON );We keep those function ID specifiers in the node for compatibility reasons. For PSCI 0.2 and higher they are ignored, but older OSes can just use them as before.
Quoted 7 lines
Quoted 1 line
Yes, good suggestion, thanks.
Hongbo,
I see you are in agreement. Are you going to respin this patch, or keep it as is?
York
Hi York,
I'll resend a new version soon, thanks.
PATCH v3 8/11 ARMv7: PSCI: ls102xa: check target CPU ID before further operations
In reply to macro.wave.z at gmail.comFrom: Hongbo Zhang <[email protected]>
The input parameter CPU ID needs to be validated before furher oprations such as CPU_ON, this patch introduces the function to do this.
--- arch/arm/cpu/armv7/ls102xa/psci.S | 34 +++++++++++++++++++++++++++++++++- 1 file changed, 33 insertions(+), 1 deletion(-)
arch/arm/cpu/armv7/ls102xa/psci.S +33 -1
@@ -25,6 +25,34 @@ #define ONE_MS (GENERIC_TIMER_CLK / 1000) #define RESET_WAIT (30 * ONE_MS) +.globl psci_check_target_cpu_id +psci_check_target_cpu_id: + @ Get the real CPU number + and r0, r1, #0xff + + @ Verify bit[31:24], bits must be zero. + tst r1, #0xff000000 + bne out_psci_invalid_target_cpu_id + + @ Verify Affinity level 2: Cluster, only one cluster in LS1021xa SoC. + tst r1, #0xff0000 + bne out_psci_invalid_target_cpu_id + + @ Verify Affinity level 1: Processors, should be in 0xf00 format. + lsr r1, r1, #8 + teq r1, #0xf + bne out_psci_invalid_target_cpu_id + + @ Verify Affinity level 0: CPU, only 0, 1 are valid values. + cmp r0, #2 + bge out_psci_invalid_target_cpu_id + + bx lr + +out_psci_invalid_target_cpu_id: + mov r0, #PSCI_RET_INVALID_PARAMS + bx lr + @ r1 = target CPU @ r2 = target PC @ r3 = target Conetxt ID
@@ -34,7 +62,10 @@ psci_cpu_on: @ Clear and Get the correct CPU number @ r1 = 0xf01 - and r1, r1, #0xff + bl psci_check_target_cpu_id + cmp r0, #PSCI_RET_INVALID_PARAMS + beq out_psci_cpu_on + mov r1, r0 bl psci_cpu_on_common
@@ -99,6 +130,7 @@ holdoff_release: @ Return mov r0, #PSCI_RET_SUCCESS +out_psci_cpu_on: pop {lr} bx lr
Signature · 1 line
2.1.4
PATCH v3 8/11 ARMv7: PSCI: ls102xa: check target CPU ID before further operations
Hi,
Quoted 4 lines · On Wed, May 18, 2016 at 5:10 PM, <[email protected]> wrote:
From: Hongbo Zhang <[email protected]>
The input parameter CPU ID needs to be validated before furher oprations such as
CPU_ON, this patch introduces the function to do this.
Could you generalize this patch for all platforms?
We already have the PSCI_NR_CPUS macro.
We could add PSCI_NR_CLUSTERS and PSCI_NR_CPUS_PER_CLUSTER or something? This doesn't account for asymmetric cluster designs though...
ChenYu
Quoted 68 lines
Signed-off-by Wang Dongsheng <[email protected]>Signed-off-by Hongbo Zhang <[email protected]>--- arch/arm/cpu/armv7/ls102xa/psci.S | 34 +++++++++++++++++++++++++++++++++- 1 file changed, 33 insertions(+), 1 deletion(-)arch/arm/cpu/armv7/ls102xa/psci.S +33
-2@@ -25,6 +25,34 @@ #define ONE_MS (GENERIC_TIMER_CLK / 1000) #define RESET_WAIT (30 * ONE_MS) +.globl psci_check_target_cpu_id +psci_check_target_cpu_id: + @ Get the real CPU number + and r0, r1, #0xff + + @ Verify bit[31:24], bits must be zero. + tst r1, #0xff000000 + bne out_psci_invalid_target_cpu_id + + @ Verify Affinity level 2: Cluster, only one cluster in LS1021xa SoC. + tst r1, #0xff0000 + bne out_psci_invalid_target_cpu_id + + @ Verify Affinity level 1: Processors, should be in 0xf00 format. + lsr r1, r1, #8 + teq r1, #0xf + bne out_psci_invalid_target_cpu_id + + @ Verify Affinity level 0: CPU, only 0, 1 are valid values. + cmp r0, #2 + bge out_psci_invalid_target_cpu_id + + bx lr + +out_psci_invalid_target_cpu_id: + mov r0, #PSCI_RET_INVALID_PARAMS + bx lr + @ r1 = target CPU @ r2 = target PC @ r3 = target Conetxt ID@@ -34,7 +62,10 @@ psci_cpu_on: @ Clear and Get the correct CPU number @ r1 = 0xf01 - and r1, r1, #0xff + bl psci_check_target_cpu_id + cmp r0, #PSCI_RET_INVALID_PARAMS + beq out_psci_cpu_on + mov r1, r0 bl psci_cpu_on_common@@ -99,6 +130,7 @@ holdoff_release: @ Return mov r0, #PSCI_RET_SUCCESS +out_psci_cpu_on: pop {lr} bx lr --2.1.4
PATCH v3 8/11 ARMv7: PSCI: ls102xa: check target CPU ID before further operations
Quoted 5 lines · Chen-Yu Tsai
Hi,
Quoted 2 lines · On Wed, May 18, 2016 at 5:10 PM, <[email protected]> wrote:
From: Hongbo Zhang <[email protected]>
Quoted 9 lines
Quoted 2 lines
The input parameter CPU ID needs to be validated before furher oprations such as
CPU_ON, this patch introduces the function to do this.Could you generalize this patch for all platforms?
We already have the
PSCI_NR_CPUSmacro.
We could addPSCI_NR_CLUSTERSandPSCI_NR_CPUS_PER_CLUSTERor something? This doesn't account for asymmetric cluster designs though...
Hi,
Thanks for review.
In this ducoment DDI0406C_C_arm_architecture_reference_manual, referring to:
Table B4-12 Possible implementations of the affinity levels
the MPIDR has more than one implementation formats, I cannot know which MPIDR format other platform implements, so I cannot make this a general function for all platforms.
And as you've mentioned, adding those macros doesn't apply for asymmetric system such as big.LITTLE, so currently introducing such a common validation function isn't feasible for me now.
In future if more and more platforms introduce their own validation codes, we could try to find if we can generalize such a common function for all platforms. But this should happen after this patch being merged at least..
Hongbo Zhang @ NXP/Freescale
Quoted 70 lines
ChenYu
Quoted 68 lines
Signed-off-by Wang Dongsheng <[email protected]>Signed-off-by Hongbo Zhang <[email protected]>--- arch/arm/cpu/armv7/ls102xa/psci.S | 34 +++++++++++++++++++++++++++++++++- 1 file changed, 33 insertions(+), 1 deletion(-)arch/arm/cpu/armv7/ls102xa/psci.S +33
-2@@ -25,6 +25,34 @@ #define ONE_MS (GENERIC_TIMER_CLK / 1000) #define RESET_WAIT (30 * ONE_MS) +.globl psci_check_target_cpu_id +psci_check_target_cpu_id: + @ Get the real CPU number + and r0, r1, #0xff + + @ Verify bit[31:24], bits must be zero. + tst r1, #0xff000000 + bne out_psci_invalid_target_cpu_id + + @ Verify Affinity level 2: Cluster, only one cluster in LS1021xa SoC. + tst r1, #0xff0000 + bne out_psci_invalid_target_cpu_id + + @ Verify Affinity level 1: Processors, should be in 0xf00 format. + lsr r1, r1, #8 + teq r1, #0xf + bne out_psci_invalid_target_cpu_id + + @ Verify Affinity level 0: CPU, only 0, 1 are valid values. + cmp r0, #2 + bge out_psci_invalid_target_cpu_id + + bx lr + +out_psci_invalid_target_cpu_id: + mov r0, #PSCI_RET_INVALID_PARAMS + bx lr + @ r1 = target CPU @ r2 = target PC @ r3 = target Conetxt ID@@ -34,7 +62,10 @@ psci_cpu_on: @ Clear and Get the correct CPU number @ r1 = 0xf01 - and r1, r1, #0xff + bl psci_check_target_cpu_id + cmp r0, #PSCI_RET_INVALID_PARAMS + beq out_psci_cpu_on + mov r1, r0 bl psci_cpu_on_common@@ -99,6 +130,7 @@ holdoff_release: @ Return mov r0, #PSCI_RET_SUCCESS +out_psci_cpu_on: pop {lr} bx lr --2.1.4
PATCH v3 9/11 ARMv7: PSCI: ls102xa: check ALREADY_ON or ON_PENDING for CPU_ON
In reply to macro.wave.z at gmail.comFrom: Hongbo Zhang <[email protected]>
For the robustness of codes, while powering on a CPU, it is better to check if the target CPU is already on or in the process of power on, if yes the power on routine shouldn't be executed further and should return with the corresponding status immediately.
--- arch/arm/cpu/armv7/ls102xa/psci.S | 29 +++++++++++++++++++++++++++++ arch/arm/include/asm/psci.h | 5 +++++ 2 files changed, 34 insertions(+)
arch/arm/cpu/armv7/ls102xa/psci.S +29 -0
@@ -67,6 +67,22 @@ psci_cpu_on: beq out_psci_cpu_on mov r1, r0 + bl psci_get_cpu_stack_top + sub r0, r0, #PSCI_CPU_STATUS_OFFSET + ldr r5, [r0] + + cmp r5, #PSCI_CPU_STATUS_ON + moveq r0, #PSCI_RET_ALREADY_ON + beq out_psci_cpu_on + + cmp r5, #PSCI_CPU_STATUS_ON_PENDING + moveq r0, #PSCI_RET_ON_PENDING + beq out_psci_cpu_on + + mov r5, #PSCI_CPU_STATUS_ON_PENDING + str r5, [r0] + dsb + bl psci_cpu_on_common @ Get DCFG base address
@@ -124,6 +140,12 @@ holdoff_release: rev r6, r6 str r6, [r4, #DCFG_CCSR_SCRATCHRW1] + mov r0, r1 + bl psci_get_cpu_stack_top + sub r0, r0, #PSCI_CPU_STATUS_OFFSET + mov r5, #PSCI_CPU_STATUS_ON + str r5, [r0] + isb dsb
@@ -138,6 +160,13 @@ out_psci_cpu_on: psci_cpu_off: bl psci_cpu_off_common + bl psci_get_cpu_id + bl psci_get_cpu_stack_top + sub r0, r0, #PSCI_CPU_STATUS_OFFSET + mov r5, #PSCI_CPU_STATUS_OFF + str r5, [r0] + dsb + 1: wfi b 1b
arch/arm/include/asm/psci.h +5 -0
@@ -22,6 +22,7 @@#define PSCI_PERCPU_STACK_SIZE 0x400#define PSCI_TARGET_PC_OFFSET (PSCI_PERCPU_STACK_SIZE - 4)#define PSCI_CONTEXT_ID_OFFSET (PSCI_PERCPU_STACK_SIZE - 8) +#define PSCI_CPU_STATUS_OFFSET (PSCI_PERCPU_STACK_SIZE - 12)/* PSCI interfaces */ #define PSCI_FN_BASE 0x84000000
@@ -47,6 +48,10 @@#define PSCI_FN_STAT_COUNT PSCI_FN_ID(17) +#define PSCI_CPU_STATUS_OFF 0 +#define PSCI_CPU_STATUS_ON 1 +#define PSCI_CPU_STATUS_ON_PENDING 2 +/* PSCI return values */ #define PSCI_RET_SUCCESS 0#define PSCI_RET_NOT_SUPPORTED (-1)
Signature · 1 line
2.1.4
PATCH v3 10/11 ARMv7: PSCI: ls102xa: add more PSCI v1.0 functions implemention
In reply to macro.wave.z at gmail.comFrom: Hongbo Zhang <[email protected]>
This patch implements PSCI functions for ls102xa SoC following PSCI v1.0, they are as the list:
psci_version,
psci_features,
psci_cpu_suspend,
psci_affinity_info,
psci_system_reset,
psci_system_off.
Tested on LS1021aQDS, LS1021aTWR.
--- arch/arm/cpu/armv7/ls102xa/psci.S | 105 +++++++++++++++++++++++++++-- arch/arm/include/asm/arch-ls102xa/config.h | 1 + arch/arm/include/asm/psci.h | 4 ++ board/freescale/ls1021aqds/Makefile | 1 + board/freescale/ls1021aqds/psci.S | 36 ++++++++++ board/freescale/ls1021atwr/Makefile | 1 + board/freescale/ls1021atwr/psci.S | 28 ++++++++ include/configs/ls1021aqds.h | 3 + include/configs/ls1021atwr.h | 1 + 9 files changed, 176 insertions(+), 4 deletions(-) create mode 100644 board/freescale/ls1021aqds/psci.S create mode 100644 board/freescale/ls1021atwr/psci.S
arch/arm/cpu/armv7/ls102xa/psci.S +101 -4
@@ -12,19 +12,72 @@ #include <asm/arch-armv7/generictimer.h> #include <asm/psci.h> +#define RCPM_TWAITSR 0x04C + #define SCFG_CORE0_SFT_RST 0x130 #define SCFG_CORESRENCR 0x204 -#define DCFG_CCSR_BRR 0x0E4 -#define DCFG_CCSR_SCRATCHRW1 0x200 +#define DCFG_CCSR_RSTCR 0x0B0 +#define DCFG_CCSR_RSTCR_RESET_REQ 0x2 +#define DCFG_CCSR_BRR 0x0E4 +#define DCFG_CCSR_SCRATCHRW1 0x200 + +#define PSCI_FN_PSCI_VERSION_FEATURE_MASK 0x0 +#define PSCI_FN_CPU_SUSPEND_FEATURE_MASK 0x0 +#define PSCI_FN_CPU_OFF_FEATURE_MASK 0x0 +#define PSCI_FN_CPU_ON_FEATURE_MASK 0x0 +#define PSCI_FN_AFFINITY_INFO_FEATURE_MASK 0x0 +#define PSCI_FN_SYSTEM_OFF_FEATURE_MASK 0x0 +#define PSCI_FN_SYSTEM_RESET_FEATURE_MASK 0x0 .pushsection ._secure.text, "ax" .arch_extension sec + .align 5 + #define ONE_MS (GENERIC_TIMER_CLK / 1000) #define RESET_WAIT (30 * ONE_MS) +.globl psci_version +psci_version: + movw r0, #0 + movt r0, #1 + + bx lr + +_ls102x_psci_supported_table: + .word PSCI_FN_PSCI_VERSION + .word PSCI_FN_PSCI_VERSION_FEATURE_MASK + .word PSCI_FN_CPU_SUSPEND + .word PSCI_FN_CPU_SUSPEND_FEATURE_MASK + .word PSCI_FN_CPU_OFF + .word PSCI_FN_CPU_OFF_FEATURE_MASK + .word PSCI_FN_CPU_ON + .word PSCI_FN_CPU_ON_FEATURE_MASK + .word PSCI_FN_AFFINITY_INFO + .word PSCI_FN_AFFINITY_INFO_FEATURE_MASK + .word PSCI_FN_SYSTEM_OFF + .word PSCI_FN_SYSTEM_OFF_FEATURE_MASK + .word PSCI_FN_SYSTEM_RESET + .word PSCI_FN_SYSTEM_RESET_FEATURE_MASK + .word 0 + .word PSCI_RET_NOT_SUPPORTED + +.globl psci_features +psci_features: + adr r2, _ls102x_psci_supported_table +1: ldr r3, [r2] + cmp r3, #0 + beq out_psci_features + cmp r1, r3 + addne r2, r2, #8 + bne 1b + +out_psci_features: + ldr r0, [r2, #4] + bx lr + .globl psci_check_target_cpu_id psci_check_target_cpu_id: @ Get the real CPU number
@@ -170,6 +223,52 @@ psci_cpu_off: 1: wfi b 1b +.globl psci_affinity_info +psci_affinity_info: + push {lr} + + mov r0, #PSCI_RET_INVALID_PARAMS + + @ Verify Affinity level + cmp r2, #0 + bne out_affinity_info + + bl psci_check_target_cpu_id + cmp r0, #PSCI_RET_INVALID_PARAMS + beq out_affinity_info + mov r1, r0 + + @ Get RCPM base address + movw r4, #(CONFIG_SYS_FSL_RCPM_ADDR & 0xffff) + movt r4, #(CONFIG_SYS_FSL_RCPM_ADDR >> 16) + + mov r0, #PSCI_AFFINITY_LEVEL_ON + + @ Detect target CPU state + ldr r2, [r4, #RCPM_TWAITSR] + rev r2, r2 + lsr r2, r2, r1 + ands r2, r2, #1 + beq out_affinity_info + + mov r0, #PSCI_AFFINITY_LEVEL_OFF + +out_affinity_info: + pop {pc} + +.globl psci_system_reset +psci_system_reset: + @ Get DCFG base address + movw r1, #(CONFIG_SYS_FSL_GUTS_ADDR & 0xffff) + movt r1, #(CONFIG_SYS_FSL_GUTS_ADDR >> 16) + + mov r2, #DCFG_CCSR_RSTCR_RESET_REQ + rev r2, r2 + str r2, [r1, #DCFG_CCSR_RSTCR] + +1: wfi + b 1b + .globl psci_arch_init psci_arch_init: mov r6, lr
@@ -180,6 +279,4 @@ psci_arch_init: bx r6 - .globl psci_text_end -psci_text_end: .popsection
arch/arm/include/asm/arch-ls102xa/config.h +1 -0
@@ -32,6 +32,7 @@#define CONFIG_SYS_FSL_SERDES_ADDR (CONFIG_SYS_IMMR + 0x00ea0000)#define CONFIG_SYS_FSL_GUTS_ADDR (CONFIG_SYS_IMMR + 0x00ee0000)#define CONFIG_SYS_FSL_LS1_CLK_ADDR (CONFIG_SYS_IMMR + 0x00ee1000) +#define CONFIG_SYS_FSL_RCPM_ADDR (CONFIG_SYS_IMMR + 0x00ee2000)#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x011c0500)#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x011d0500)#define CONFIG_SYS_DCU_ADDR (CONFIG_SYS_IMMR + 0x01ce0000)
arch/arm/include/asm/psci.h +4 -0
@@ -47,6 +47,10 @@#define PSCI_FN_STAT_RESIDENCY PSCI_FN_ID(16)#define PSCI_FN_STAT_COUNT PSCI_FN_ID(17) +/* PSCI affinity level state returned by AFFINITY_INFO */ +#define PSCI_AFFINITY_LEVEL_ON 0 +#define PSCI_AFFINITY_LEVEL_OFF 1 +#define PSCI_AFFINITY_LEVEL_ON_PENDING 2#define PSCI_CPU_STATUS_OFF 0#define PSCI_CPU_STATUS_ON 1
board/freescale/ls1021aqds/Makefile +1 -0
@@ -8,3 +8,4 @@ obj-y += ls1021aqds.o obj-y += ddr.o obj-y += eth.o obj-$(CONFIG_FSL_DCU_FB) += dcu.o +obj-$(CONFIG_ARMV7_PSCI) += psci.o
board/freescale/ls1021aqds/psci.S new file +36 -0
@@ -0,0 +1,36 @@ +/* + * Copyright 2016 NXP Semiconductor. + * Author: Wang Dongsheng <[email protected]> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <config.h> +#include <linux/linkage.h> + +#include <asm/armv7.h> +#include <asm/psci.h> + + .pushsection ._secure.text, "ax" + + .arch_extension sec + + .align 5 + +.globl psci_system_off +psci_system_off: + @ Get QIXIS base address + movw r1, #(QIXIS_BASE & 0xffff) + movt r1, #(QIXIS_BASE >> 16) + + ldrb r2, [r1, #QIXIS_PWR_CTL] + orr r2, r2, #QIXIS_PWR_CTL_POWEROFF + strb r2, [r1, #QIXIS_PWR_CTL] + +1: wfi + b 1b + +.globl psci_text_end +psci_text_end: + nop + .popsection
board/freescale/ls1021atwr/Makefile +1 -0
@@ -6,3 +6,4 @@ obj-y += ls1021atwr.o obj-$(CONFIG_FSL_DCU_FB) += dcu.o +obj-$(CONFIG_ARMV7_PSCI) += psci.o
board/freescale/ls1021atwr/psci.S new file +28 -0
@@ -0,0 +1,28 @@ +/* + * Copyright 2016 NXP Semiconductor. + * Author: Wang Dongsheng <[email protected]> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <config.h> +#include <linux/linkage.h> + +#include <asm/armv7.h> +#include <asm/psci.h> + + .pushsection ._secure.text, "ax" + + .arch_extension sec + + .align 5 + +.globl psci_system_off +psci_system_off: +1: wfi + b 1b + +.globl psci_text_end +psci_text_end: + nop + .popsection
include/configs/ls1021aqds.h +3 -0
@@ -10,6 +10,7 @@#define CONFIG_LS102XA #define CONFIG_ARMV7_PSCI +#define CONFIG_ARMV7_PSCI_1_0 #define CONFIG_SYS_FSL_CLK
@@ -279,6 +280,8 @@ unsigned long get_board_ddr_clk(void);#define QIXIS_LBMAP_SHIFT 0#define QIXIS_LBMAP_DFLTBANK 0x00#define QIXIS_LBMAP_ALTBANK 0x04 +#define QIXIS_PWR_CTL 0x21 +#define QIXIS_PWR_CTL_POWEROFF 0x80#define QIXIS_RST_CTL_RESET 0x44#define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20#define QIXIS_RCFG_CTL_RECONFIG_START 0x21
include/configs/ls1021atwr.h +1 -0
@@ -10,6 +10,7 @@#define CONFIG_LS102XA #define CONFIG_ARMV7_PSCI +#define CONFIG_ARMV7_PSCI_1_0 #define CONFIG_SYS_FSL_CLK
Signature · 1 line
2.1.4
PATCH v3 11/11 ARMv7: PSCI: ls102xa: move secure text section into OCRAM
In reply to macro.wave.z at gmail.comFrom: Hongbo Zhang <[email protected]>
LS1021 offers two secure OCRAM blocks for trustzone. This patch moves all the secure text sections into the OCRAM.
--- arch/arm/include/asm/arch-ls102xa/config.h | 2 +- include/configs/ls1021atwr.h | 2 ++ 2 files changed, 3 insertions(+), 1 deletion(-)
arch/arm/include/asm/arch-ls102xa/config.h +1 -1
@@ -10,7 +10,7 @@#define CONFIG_SYS_CACHELINE_SIZE 64#define OCRAM_BASE_ADDR 0x10000000 -#define OCRAM_SIZE 0x00020000 +#define OCRAM_SIZE 0x00010000#define OCRAM_BASE_S_ADDR 0x10010000#define OCRAM_S_SIZE 0x00010000
include/configs/ls1021atwr.h +2 -0
@@ -12,6 +12,8 @@#define CONFIG_ARMV7_PSCI #define CONFIG_ARMV7_PSCI_1_0 +#define CONFIG_ARMV7_SECURE_BASE OCRAM_BASE_S_ADDR +#define CONFIG_SYS_FSL_CLK #define CONFIG_DISPLAY_CPUINFO
Signature · 1 line
2.1.4