MIPS: Longson 3: Fix fast refill handler for 32 bit kernels
PATCH 1/1 MIPS: Longson 3: Fix fast refill handler for 32 bit kernels
A recent merge has broken the LLVMLinux build for 32-bit little endian. I've bisected it to 380cd58 and it looks like a bug in the kernel to me. Clang is rejecting the inline assembly in the expansion of 'write_c0_kpgd (swapper_pg_dir)' of tlbex.c. The relevant inline assembly can be found in __write_64bit_c0_split() and is attempting to use the 'L' and 'M' print modifiers on swapper_pg_dir which is a 32-bit unsigned long. These print modifiers only make sense for 64-bit values so I think the kernel source is incorrect.
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I don't have Loongson 3 hardware for testing, could somebody of the Loongson folks please review / test this? Thanks!
arch/mips/include/asm/mipsregs.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)
arch/mips/include/asm/mipsregs.h +2 -2
@@ -1652,8 +1652,8 @@ do { \#define read_c0_pgd () __read_64bit_c0_register($9, 7)#define write_c0_pgd (val) __write_64bit_c0_register($9, 7, val) -#define read_c0_kpgd () __read_64bit_c0_register($31, 7) -#define write_c0_kpgd (val) __write_64bit_c0_register($31, 7, val) +#define read_c0_kpgd () __read_ulong_c0_register($31, 7) +#define write_c0_kpgd (val) __write_ulong_c0_register($31, 7, val)/* Cavium OCTEON (cnMIPS) */ #define read_c0_cvmcount () __read_ulong_c0_register($9, 6)
Hi, Ralf,
Your change is correct, but I suggest modify
read_c0_pgd()/write_c0_pgd() as well.
Huacai
Quoted 38 lines · Ralf Baechle
A recent merge has broken the LLVMLinux build for 32-bit little endian. I've bisected it to 380cd58 and it looks like a bug in the kernel to me. Clang is rejecting the inline assembly in the expansion of '
write_c0_kpgd(swapper_pg_dir)' oftlbex.c. The relevant inline assembly can be found in__write_64bit_c0_split()and is attempting to use the 'L' and 'M' print modifiers onswapper_pg_dirwhich is a 32-bit unsigned long. These print modifiers only make sense for 64-bit values so I think the kernel source is incorrect.Signed-off-by Ralf Baechle <[email protected]>Reported-by Daniel Sanders <[email protected]>Cc Huacai Chen <[email protected]>Cc Aurelien Jarno <[email protected]>Cc Fuxin Zhang <[email protected]>Cc Zhangjin Wu <[email protected]>---
I don't have Loongson 3 hardware for testing, could somebody of the Loongson folks please review / test this? Thanks!arch/mips/include/asm/mipsregs.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)arch/mips/include/asm/mipsregs.h +2
-2@@ -1652,8 +1652,8 @@ do { \#define read_c0_pgd () __read_64bit_c0_register($9, 7)#define write_c0_pgd (val) __write_64bit_c0_register($9, 7, val) -#define read_c0_kpgd () __read_64bit_c0_register($31, 7) -#define write_c0_kpgd (val) __write_64bit_c0_register($31, 7, val) +#define read_c0_kpgd () __read_ulong_c0_register($31, 7) +#define write_c0_kpgd (val) __write_ulong_c0_register($31, 7, val)/* Cavium OCTEON (cnMIPS) */ #define read_c0_cvmcount () __read_ulong_c0_register($9, 6)