ARM: OMAP5: add support for fref-xtal-clk

Hi,

fref_xtal_clk is a clock going out from omap5 chip, sourced directly from the system oscillator. fref_xtal_clk can be used to provide a high frequency clock to some external component, in omap5 setups, typically twl6040 audio chip.

Testing done (number of boards on the test farm are currently out of order):

am335x-evm : BOOT FAIL!
am335x-evmsk : boot
am37x-evm : boot
am437x-sk : boot
am43x-epos-evm : boot
am437x-gp-evm : boot
am57xx-evm : boot
omap3-beagle-xm : boot
am335x-boneblack: boot
am335x-bone : boot
dra72x-evm : boot
dra7xx-evm : boot
omap5-uevm : boot

On omap5, also verified that the new clock node appears under debugfs.

am335x-evm failure is due to inability to mount NFS rootfs on the board in question the boot goes fine until that. There are some issues with the u-boot installed on this board currently.

-Tero

Control module can have multiple instances in a system, each with separate address space and features. Add base support for these auxiliary instances, with support for syscon and clock mappings under them.

---
 arch/arm/mach-omap2/control.c | 15 +++++++++++----
 include/linux/clk/ti.h        |  1 +
 2 files changed, 12 insertions(+), 4 deletions(-)

index 1662071..50875d0 100644
@@ -623,6 +623,7 @@ void __init omap3_ctrl_init(void)
 
 struct control_init_data {
 	int index;
+	void __iomem *mem;
 	s16 offset;
 };
 

@@ -660,15 +661,21 @@ int __init omap2_control_base_init(void)
 	struct device_node *np;
 	const struct of_device_id *match;
 	struct control_init_data *data;
+	void __iomem *mem;
 
 	for_each_matching_node_and_match(np, omap_scrm_dt_match_table, &match) {
 		data = (struct control_init_data *)match->data;
 
-		omap2_ctrl_base = of_iomap(np, 0);
-		if (!omap2_ctrl_base)
+		mem = of_iomap(np, 0);
+		if (!mem)
 			return -ENOMEM;
 
-		omap2_ctrl_offset = data->offset;
+		if (data->index == TI_CLKM_CTRL) {
+			omap2_ctrl_base = mem;
+			omap2_ctrl_offset = data->offset;
+		}
+
+		data->mem = mem;
 	}
 
 	return 0;

@@ -713,7 +720,7 @@ int __init omap_control_init(void)
 		} else {
 			/* No scm_conf found, direct access */
 			ret = omap2_clk_provider_init(np, data->index, NULL,
-						      omap2_ctrl_base);
+						      data->mem);
 			if (ret)
 				return ret;
 		}

index 6110fe0..5431f17 100644
@@ -197,6 +197,7 @@ enum {
 	TI_CLKM_PRM,
 	TI_CLKM_SCRM,
 	TI_CLKM_CTRL,
+	TI_CLKM_CTRL_AUX,
 	TI_CLKM_PLLSS,
 	CLK_MAX_MEMMAPS
 };

1.9.1

The pad configuration area under control module wkup has some miscellaneous config registers, that are not pinmux related. Add a separate area for these, and add support for syscon / clocks under this new area.

---
 .../devicetree/bindings/arm/omap/ctrl.txt          |  1 +
 arch/arm/boot/dts/omap5.dtsi                       | 22 ++++++++++++++++++++++
 2 files changed, 23 insertions(+)

index 3a4e590..33e459e 100644
@@ -23,6 +23,7 @@ Required properties:
 		"ti,omap4-scm-padconf-core"
 		"ti,omap5-scm-core"
 		"ti,omap5-scm-padconf-core"
+		"ti,omap5-scm-wkup-pad-conf"
 		"ti,dra7-scm-core"
 - reg:		Contains Control Module register address range
 		(base address and length)

index 84c1019..6fef4fa 100644
@@ -277,6 +277,28 @@
 				pinctrl-single,register-width = <16>;
 				pinctrl-single,function-mask = <0x7fff>;
 			};
+
+			omap5_scm_wkup_pad_conf: omap5_scm_wkup_pad_conf at cda0 {
+				compatible = "ti,omap5-scm-wkup-pad-conf",
+					     "simple-bus";
+				reg = <0xcda0 0x60>;
+				#address-cells = <1>;
+				#size-cells = <1>;
+				ranges = <0 0xcda0 0x60>;
+
+				scm_wkup_pad_conf: scm_conf at 0 {
+					compatible = "syscon", "simple-bus";
+					reg = <0x0 0x60>;
+					#address-cells = <1>;
+					#size-cells = <1>;
+					ranges = <0 0x0 0x60>;
+
+					scm_wkup_pad_conf_clocks: clocks at 0 {
+						#address-cells = <1>;
+						#size-cells = <0>;
+					};
+				};
+			};
 		};
 
 		ocmcram: ocmcram at 40300000 {

1.9.1

Match the new compatible string in the control module driver. The base infra maps the required syscon ranges and clock registers if available.

---
 arch/arm/mach-omap2/control.c | 5 +++++
 1 file changed, 5 insertions(+)

index 50875d0..5956641 100644
@@ -636,6 +636,10 @@ static const struct control_init_data omap2_ctrl_data = {
 	.offset = -OMAP2_CONTROL_GENERAL,
 };
 
+static const struct control_init_data ctrl_aux_data = {
+	.index = TI_CLKM_CTRL_AUX,
+};
+
 static const struct of_device_id omap_scrm_dt_match_table[] = {
 	{ .compatible = "ti,am3-scm", .data = &ctrl_data },
 	{ .compatible = "ti,am4-scm", .data = &ctrl_data },

@@ -645,6 +649,7 @@ static const struct of_device_id omap_scrm_dt_match_table[] = {
 	{ .compatible = "ti,dm816-scrm", .data = &ctrl_data },
 	{ .compatible = "ti,omap4-scm-core", .data = &ctrl_data },
 	{ .compatible = "ti,omap5-scm-core", .data = &ctrl_data },
+	{ .compatible = "ti,omap5-scm-wkup-pad-conf", .data = &ctrl_aux_data },
 	{ .compatible = "ti,dra7-scm-core", .data = &ctrl_data },
 	{ }
 };

1.9.1

The clock is directly sourced from sys_clkin, and provides an external output clock for (typically) TWL6040 chip.

---
 arch/arm/boot/dts/omap54xx-clocks.dtsi | 10 ++++++++++
 drivers/clk/ti/clk-54xx.c              |  1 +
 2 files changed, 11 insertions(+)

index 4899c23..a8153b4 100644
@@ -1388,3 +1388,13 @@
 		reg = <0x021c>;
 	};
 };
+
+&scm_wkup_pad_conf_clocks {
+	fref_xtal_ck: fref_xtal_ck {
+		#clock-cells = <0>;
+		compatible = "ti,gate-clock";
+		clocks = <&sys_clkin>;
+		ti,bit-shift = <28>;
+		reg = <0x14>;
+	};
+};

index 294bc03..20f6985 100644
@@ -222,6 +222,7 @@ static struct ti_dt_clk omap54xx_clks[] = {
 	DT_CLK("4013a000.timer", "timer_sys_ck", "dss_syc_gfclk_div"),
 	DT_CLK("4013c000.timer", "timer_sys_ck", "dss_syc_gfclk_div"),
 	DT_CLK("4013e000.timer", "timer_sys_ck", "dss_syc_gfclk_div"),
+	DT_CLK(NULL, "fref_xtal_ck", "fref_xtal_ck"),
 	{ .node_name = NULL },
 };
 

1.9.1

Can this patch be applied separately without issues?

Tony

From: Peter Ujfalusi <[email protected]>

The xref_xtal clock is used y twl6040 as mclk. It is needed for the HPPLL internally.

---
 arch/arm/boot/dts/omap5-board-common.dtsi | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

index dc759a3..bd0e315 100644
@@ -606,8 +606,8 @@
 		v2v1-supply = <&smps9_reg>;
 		enable-active-high;
 
-		clocks = <&clk32kgaudio>;
-		clock-names = "clk32k";
+		clocks = <&clk32kgaudio>, <&fref_xtal_ck>;
+		clock-names = "clk32k", "mclk";
 	};
 };
 

1.9.1

With the [1] patch applied to twl6040 I have verified that the HPPLL is working fine with this series on omap5-uevm. This is so great!

Thanks Tero,

[1] https://patchwork.kernel.org/patch/9067911/

P?ter