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mmc: sunxi: Changes in the host driver

PATCH Superseded Jean-Francois Moine 3 participants 17 messages Jul 20, 2016 – Aug 2, 2016

Subsystems (2)
MMC, SD and SDIO Arm/Allwinner sunXi SoC support
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Jean-Francois Moine

author
#0 lore raw

cover mmc: sunxi: Changes in the host driver

While testing the eMMC access in a Banana Pi M3, I found and fixed some problems:
- the driver was trying to set a strange rate when clk_round_rate() was returning an error
- the 'new timing mode' could not work because a register was not set
- with a parent clock at 1.2GHz, the output and sample phases were not correct for the A83T

Jean-Francois Moine (3):
mmc: sunxi: Check the value returned by clk_round_rate
mmc: sunxi: Set the 'New Timing' register for 8 bits DDR transfers
mmc: sunxi: Add support to the Allwinner A83T

 drivers/mmc/host/sunxi-mmc.c | 45 +++++++++++++++++++++++++++++++++++---------
 1 file changed, 38 insertions(+), 7 deletions(-)
Signature · 1 line
2.9.2
author
#1 lore raw

PATCH 1/3 mmc: sunxi: Check the value returned by clk_round_rate

clk_round_rate() may return an error. Check it.

Signed-off-by Jean-Francois Moine <[email protected]>
---
 drivers/mmc/host/sunxi-mmc.c | 12 +++++++++---
 1 file changed, 9 insertions(+), 3 deletions(-)
drivers/mmc/host/sunxi-mmc.c +9 -3
index 2ee4c21..ba647b7 100644
@@ -656,7 +656,8 @@ static int sunxi_mmc_oclk_onoff(struct sunxi_mmc_host *host, u32 oclk_en)
 static int sunxi_mmc_clk_set_rate(struct sunxi_mmc_host *host,
 				  struct mmc_ios *ios)
 {
-	u32 rate, oclk_dly, rval, sclk_dly;
+	long rate;
+	u32 oclk_dly, rval, sclk_dly;
 	u32 clock = ios->clock;
 	int ret;
 

@@ -666,13 +667,18 @@ static int sunxi_mmc_clk_set_rate(struct sunxi_mmc_host *host,
 		clock <<= 1;
 
 	rate = clk_round_rate(host->clk_mmc, clock);
-	dev_dbg(mmc_dev(host->mmc), "setting clk to %d, rounded %d\n",
+	if (rate < 0) {
+		dev_err(mmc_dev(host->mmc), "error rounding clk to %d: %ld\n",
+			clock, rate);
+		return rate;
+	}
+	dev_dbg(mmc_dev(host->mmc), "setting clk to %d, rounded %ld\n",
 		clock, rate);
 
 	/* setting clock rate */
 	ret = clk_set_rate(host->clk_mmc, rate);
 	if (ret) {
-		dev_err(mmc_dev(host->mmc), "error setting clk to %d: %d\n",
+		dev_err(mmc_dev(host->mmc), "error setting clk to %ld: %d\n",
 			rate, ret);
 		return ret;
 	}
Signature · 1 line
2.9.2
#2 lore raw

PATCH 1/3 mmc: sunxi: Check the value returned by clk_round_rate

Quoted 3 lines · Jean-Francois Moine

clk_round_rate() may return an error. Check it.

Signed-off-by Jean-Francois Moine <[email protected]>
Acked-by Maxime Ripard <[email protected]>

Thanks!
Maxime

Signature · 10 lines
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
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author
#3 lore raw

PATCH 2/3 mmc: sunxi: Set the 'New Timing' register for 8 bits DDR transfers

In reply to Jean-Francois Moine

The 'new timing mode' with 8 bits DDR works correctly when the NewTiming register is set.

Signed-off-by Jean-Francois Moine <[email protected]>

---
Note about the 'new timing mode'.

This patch assumes that, when the new mode is used, the clock driver sets the mode select in the MMC clock and multiplies the clock rate by 2:
- MMC side:
- with a timing 8 bits DDR at 50MHz, the MMC driver calls

    clk_set_rate() with a rate 50*2 = 100MHz,

- clock side:
- the clock driver sets the hardware MMC clock to 100*2 = 200MHz,
- setting the 'mode select' of the hardware MMC clock divides the rate by 2,
- MMC side:
- setting the MMC clock divider register to 1 divides the rate by 2.
So, the final rate is 50MHz.

For this to work, the clock driver must know when the 'mode select' is used.
Instead of using a new special clock function, in my driver, the 'mode select' capable clocks are declared as such with an associated rate (actually, mmc2 in A83T, and mmc{1,2} in H3).
When this rate is asked for (100MHz), the mode select is set. This works without change in the MMC driver. If a 100MHz rate would be used without 'mode select' for such clocks, an other mechanism should be found (information in the low bits of the rate?).

---
 drivers/mmc/host/sunxi-mmc.c | 22 ++++++++++++++++++----
 1 file changed, 18 insertions(+), 4 deletions(-)
drivers/mmc/host/sunxi-mmc.c +18 -4
index ba647b7..7f9c31a 100644
@@ -64,6 +64,7 @@
 #define SDXC_REG_CBCR	(0x48) /* SMC CIU Byte Count Register */
 #define SDXC_REG_BBCR	(0x4C) /* SMC BIU Byte Count Register */
 #define SDXC_REG_DBGC	(0x50) /* SMC Debug Enable Register */
+#define SDXC_REG_NTSR	(0x5c) /* SMC NewTiming Set Register */
 #define SDXC_REG_HWRST	(0x78) /* SMC Card Hardware Reset for Register */
 #define SDXC_REG_DMAC	(0x80) /* SMC IDMAC Control Register */
 #define SDXC_REG_DLBA	(0x84) /* SMC IDMAC Descriptor List Base Addre */

@@ -171,6 +172,9 @@
 #define SDXC_SEND_AUTO_STOPCCSD		BIT(9)
 #define SDXC_CEATA_DEV_IRQ_ENABLE	BIT(10)
 
+/* NewTiming Set Register */
+#define SDXC_NEWMODE_ENABLE		BIT(31)
+
 /* IDMA controller bus mod bit field */
 #define SDXC_IDMAC_SOFT_RESET		BIT(0)
 #define SDXC_IDMAC_FIX_BURST		BIT(1)

@@ -661,10 +665,20 @@ static int sunxi_mmc_clk_set_rate(struct sunxi_mmc_host *host,
 	u32 clock = ios->clock;
 	int ret;
 
-	/* 8 bit DDR requires a higher module clock */
-	if (ios->timing == MMC_TIMING_MMC_DDR52 &&
-	    ios->bus_width == MMC_BUS_WIDTH_8)
-		clock <<= 1;
+	/*
+	 * 8 bit DDR requires a higher module clock
+	 * and the 'new mode'
+	 */
+	if (ios->bus_width == MMC_BUS_WIDTH_8) {	/* eMMC */
+		rval = mmc_readl(host, REG_NTSR);
+		if (ios->timing == MMC_TIMING_MMC_DDR52) {
+			clock <<= 1;
+			rval |= SDXC_NEWMODE_ENABLE;
+		} else {
+			rval &= ~SDXC_NEWMODE_ENABLE;
+		}
+		mmc_writel(host, REG_NTSR, rval);
+	}
 
 	rate = clk_round_rate(host->clk_mmc, clock);
 	if (rate < 0) {
Signature · 1 line
2.9.2
#4 lore raw

PATCH 2/3 mmc: sunxi: Set the 'New Timing' register for 8 bits DDR transfers

Hi,

Quoted 2 lines · Jean-Francois Moine

The 'new timing mode' with 8 bits DDR works correctly when the NewTiming register is set.

What does that mode brings to the table?

Quoted 10 lines
Signed-off-by Jean-Francois Moine <[email protected]>

---
Note about the 'new timing mode'.

This patch assumes that, when the new mode is used, the clock driver sets the mode select in the MMC clock and multiplies the clock rate by 2:
- MMC side:
- with a timing 8 bits DDR at 50MHz, the MMC driver calls

Quoted 8 lines
    clk_set_rate() with a rate 50*2 = 100MHz,

- clock side:
- the clock driver sets the hardware MMC clock to 100*2 = 200MHz,
- setting the 'mode select' of the hardware MMC clock divides the rate by 2,
- MMC side:
- setting the MMC clock divider register to 1 divides the rate by 2.
So, the final rate is 50MHz.

What happens if you actually want to set it to 100MHz?

Maxime

Signature · 10 lines
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
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#5 lore raw

PATCH 2/3 mmc: sunxi: Set the 'New Timing' register for 8 bits DDR transfers

Quoted 7 lines · On Thu, 21 Jul 2016 10:56:15 +0200 Maxime Ripard…
Quoted 2 lines · Jean-Francois Moine

The 'new timing mode' with 8 bits DDR works correctly when the NewTiming register is set.

What does that mode brings to the table?

From my tests, the eMMC of the Banana Pi M3 (A83T) cannot work when the

new mode is not used.

Quoted 19 lines
Quoted 10 lines
Signed-off-by Jean-Francois Moine <[email protected]>

---
Note about the 'new timing mode'.

This patch assumes that, when the new mode is used, the clock driver sets the mode select in the MMC clock and multiplies the clock rate by 2:
- MMC side:
- with a timing 8 bits DDR at 50MHz, the MMC driver calls

Quoted 8 lines
    clk_set_rate() with a rate 50*2 = 100MHz,

- clock side:
- the clock driver sets the hardware MMC clock to 100*2 = 200MHz,
- setting the 'mode select' of the hardware MMC clock divides the rate by 2,
- MMC side:
- setting the MMC clock divider register to 1 divides the rate by 2.
So, the final rate is 50MHz.

Quoted 1 line

What happens if you actually want to set it to 100MHz?

There is no SDXC_CLK_100M in the mainline driver, and 100MHz is asked only for 8 bits DDR at 50MHz.

Signature · 2 lines
Ken ar c'henta?	|	      ** Breizh ha Linux atav! **
Jef		|		http://moinejf.free.fr/
#6 lore raw

PATCH 2/3 mmc: sunxi: Set the 'New Timing' register for 8 bits DDR transfers

Quoted 31 lines · Jean-Francois Moine
Quoted 5 lines · On Thu, 21 Jul 2016 10:56:15 +0200 Maxime Ripard…
Quoted 2 lines · Jean-Francois Moine

The 'new timing mode' with 8 bits DDR works correctly when the NewTiming register is set.

What does that mode brings to the table?

From my tests, the eMMC of the Banana Pi M3 (A83T) cannot work when the new mode is not used.

Quoted 19 lines
Quoted 18 lines
Signed-off-by Jean-Francois Moine <[email protected]>

---
Note about the 'new timing mode'.

This patch assumes that, when the new mode is used, the clock driver sets the mode select in the MMC clock and multiplies the clock rate by 2:
- MMC side:
- with a timing 8 bits DDR at 50MHz, the MMC driver calls

    clk_set_rate() with a rate 50*2 = 100MHz,

- clock side:
- the clock driver sets the hardware MMC clock to 100*2 = 200MHz,
- setting the 'mode select' of the hardware MMC clock divides the rate by 2,
- MMC side:
- setting the MMC clock divider register to 1 divides the rate by 2.
So, the final rate is 50MHz.

Quoted 4 lines
Quoted 1 line

What happens if you actually want to set it to 100MHz?

There is no SDXC_CLK_100M in the mainline driver, and 100MHz is asked only for 8 bits DDR at 50MHz.

You're missing the point.

clk_set_rate is supposed to apply a rate as close as possible as requested, there's no reason why you would request a rate twice as high as need.

You want to switch the clock from one mode to another, fine, create a new function for that. But don't hack an existing one.

Maxime

Signature · 10 lines
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
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author
#7 lore raw

PATCH 2/3 mmc: sunxi: Set the 'New Timing' register for 8 bits DDR transfers

Quoted 5 lines · On Fri, 29 Jul 2016 21:17:30 +0200 Maxime Ripard…
Quoted 4 lines
Quoted 1 line

What happens if you actually want to set it to 100MHz?

There is no SDXC_CLK_100M in the mainline driver, and 100MHz is asked only for 8 bits DDR at 50MHz.

Quoted 8 lines

You're missing the point.

clk_set_rate is supposed to apply a rate as close as possible as requested, there's no reason why you would request a rate twice as high as need.

You want to switch the clock from one mode to another, fine, create a new function for that. But don't hack an existing one.

I will not change the core clock stuff for this marginal case. Flagging the clock as 'new mode capable' is enough. Anyway, setting the 'new mode' bit to the clock divides the rate by two, so, there is no reason to not use it.

Signature · 2 lines
Ken ar c'henta?	|	      ** Breizh ha Linux atav! **
Jef		|		http://moinejf.free.fr/
#8 lore raw

[linux-sunxi] Re: [PATCH 2/3] mmc: sunxi: Set the 'New Timing' register for 8 bits DDR transfers

In reply to Maxime Ripard

Hi,

Quoted 34 lines · Maxime Ripard
Quoted 33 lines · Jean-Francois Moine
Quoted 5 lines · On Thu, 21 Jul 2016 10:56:15 +0200 Maxime Ripard…
Quoted 2 lines · Jean-Francois Moine

The 'new timing mode' with 8 bits DDR works correctly when the NewTiming register is set.

What does that mode brings to the table?

From my tests, the eMMC of the Banana Pi M3 (A83T) cannot work when the new mode is not used.

Quoted 20 lines
Quoted 10 lines
Signed-off-by Jean-Francois Moine <[email protected]>

---
Note about the 'new timing mode'.

This patch assumes that, when the new mode is used, the clock driver sets the mode select in the MMC clock and multiplies the clock rate by 2:
- MMC side:
- with a timing 8 bits DDR at 50MHz, the MMC driver calls

Quoted 8 lines
    clk_set_rate() with a rate 50*2 = 100MHz,

- clock side:
- the clock driver sets the hardware MMC clock to 100*2 = 200MHz,
- setting the 'mode select' of the hardware MMC clock divides the rate by 2,
- MMC side:
- setting the MMC clock divider register to 1 divides the rate by 2.
So, the final rate is 50MHz.

What happens if you actually want to set it to 100MHz?

Quoted 8 lines
Quoted 2 lines

There is no SDXC_CLK_100M in the mainline driver, and 100MHz is asked only for 8 bits DDR at 50MHz.

You're missing the point.

clk_set_rate is supposed to apply a rate as close as possible as requested, there's no reason why you would request a rate twice as high as need.

On all SoCs which support it, requesting DDR-8bit needs a twice as high clock as the mmc base clock (due to the DDR).

If you look at the current code you will see that what actually happens is that we pass twice as high clock as the mmc-subsys asks for to clk_set_rate and set the controllers *internal* divider to 2 (instead of the usual 1), this is not new and not introduced by Jean-Francois' patch.

All Jean-Francois' patch adds is the setting of the new SDXC_REG_NTSR reg msb bit when we do this. Note no changes to the clock rate calculations are made. If this fixes the eMMC on A83T boards this seems like a good patch to me, but IMHO we should only write the SDXC_REG_NTSR on the A83t and not everywhere as Jean-Francois' patch does.

Jean-Francois, can you submit a v2 of your patch and make the writing of SDXC_REG_NTSR depend on a new sun8i-a83t-mmc compatible ?

Also you should probably drop the bits about the clock stuff from the commit message as that just seems to confuse people.

Regards,

Hans

author
#9 lore raw

[linux-sunxi] Re: [PATCH 2/3] mmc: sunxi: Set the 'New Timing' register for 8 bits DDR transfers

Quoted 5 lines · On Sat, 30 Jul 2016 12:19:03 +0200 Hans de Goede <[email protected]> wrote:

Jean-Francois, can you submit a v2 of your patch and make the writing of SDXC_REG_NTSR depend on a new sun8i-a83t-mmc compatible ?

Also you should probably drop the bits about the clock stuff from the commit message as that just seems to confuse people.

Hi Hans,

I submitted a new patch (sorry, I forgot the history), but it asks for some explanation.

- in the old timings, the phase delays are set in the clock. That's why there is a function clk_set_phase() which is called from the MMC side.

- in the new timings, the delays are in the MMC register SDXC_REG_NTSR only.
In this case, the function clk_set_phase() is of no use (also, by test, it seems that the phase delays set by hardware
reset do work, so, there is no need to set them), but,

- there is a bit in the clock telling that the new timings are used, i.e. that the phase delays of the clock must be ignored.

Not setting this bit prevents the device to work (at least in the A83T, the H3 seems more helpful).

Signature · 2 lines
Ken ar c'henta?	|	      ** Breizh ha Linux atav! **
Jef		|		http://moinejf.free.fr/
#10 lore raw

[linux-sunxi] Re: [PATCH 2/3] mmc: sunxi: Set the 'New Timing' register for 8 bits DDR transfers

Hi,

Quoted 24 lines · Jean-Francois Moine
Quoted 5 lines · On Sat, 30 Jul 2016 12:19:03 +0200 Hans de Goede <[email protected]> wrote:

Jean-Francois, can you submit a v2 of your patch and make the writing of SDXC_REG_NTSR depend on a new sun8i-a83t-mmc compatible ?

Also you should probably drop the bits about the clock stuff from the commit message as that just seems to confuse people.

Hi Hans,

I submitted a new patch (sorry, I forgot the history), but it asks for some explanation.

- in the old timings, the phase delays are set in the clock. That's why there is a function clk_set_phase() which is called from the MMC side.

- in the new timings, the delays are in the MMC register SDXC_REG_NTSR only.
In this case, the function clk_set_phase() is of no use (also, by test, it seems that the phase delays set by hardware
reset do work, so, there is no need to set them), but,

Quoted 5 lines

- there is a bit in the clock telling that the new timings are used, i.e. that the phase delays of the clock must be ignored.

Not setting this bit prevents the device to work (at least in the A83T, the H3 seems more helpful).

Thanks for the explanation, it would be good to put this in the commit msg of v3 of the patch.

Regards,

Hans

#11 lore raw

PATCH 2/3 mmc: sunxi: Set the 'New Timing' register for 8 bits DDR transfers

In reply to Jean-Francois Moine
Quoted 11 lines · Jean-Francois Moine
Quoted 5 lines · On Thu, 21 Jul 2016 10:56:15 +0200 Maxime Ripard…
Quoted 2 lines · Jean-Francois Moine

The 'new timing mode' with 8 bits DDR works correctly when the NewTiming register is set.

What does that mode brings to the table?

From my tests, the eMMC of the Banana Pi M3 (A83T) cannot work when the new mode is not used.

That's odd. The one in the Pine64 seems to work just fine, and yet there's only the new mode on the A64.

Maxime

Signature · 10 lines
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
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#12 lore raw

PATCH 2/3 mmc: sunxi: Set the 'New Timing' register for 8 bits DDR transfers

Quoted 8 lines · On Fri, 29 Jul 2016 21:36:34 +0200 Maxime Ripard…
Quoted 7 lines · Jean-Francois Moine
Quoted 4 lines · On Thu, 21 Jul 2016 10:56:15 +0200 Maxime Ripard…
Quoted 2 lines · Jean-Francois Moine

The 'new timing mode' with 8 bits DDR works correctly when the NewTiming register is set.

Quoted 7 lines
Quoted 4 lines
Quoted 1 line

What does that mode brings to the table?

From my tests, the eMMC of the Banana Pi M3 (A83T) cannot work when the new mode is not used.

That's odd. The one in the Pine64 seems to work just fine, and yet there's only the new mode on the A64.

I spent 2 weeks on this problem. You may try it by yourself.

Signature · 2 lines
Ken ar c'henta?	|	      ** Breizh ha Linux atav! **
Jef		|		http://moinejf.free.fr/
author
#13 lore raw

PATCH 3/3 mmc: sunxi: Add support to the Allwinner A83T

In reply to Jean-Francois Moine

The rate of the PLL-PERIPH clock is usually set to 1.2GHz in the A83T. This patch sets the phase delays of the output and sample clocks accordingly.

Signed-off-by Jean-Francois Moine <[email protected]>

---
Note: The impacted phase delays are only for 50MHz.
The phase delays are not used in 50MHz 8 bits DDR (new timing mode).

---
 drivers/mmc/host/sunxi-mmc.c | 11 +++++++++++
 1 file changed, 11 insertions(+), 0 deletions(-)
drivers/mmc/host/sunxi-mmc.c +11 -0
index 7f9c31a..e161a64 100644
@@ -961,6 +961,7 @@ static int sunxi_mmc_card_busy(struct mmc_host *mmc)
 static const struct of_device_id sunxi_mmc_of_match[] = {
 	{ .compatible = "allwinner,sun4i-a10-mmc", },
 	{ .compatible = "allwinner,sun5i-a13-mmc", },
+	{ .compatible = "allwinner,sun8i-a83t-mmc", },
 	{ .compatible = "allwinner,sun9i-a80-mmc", },
 	{ /* sentinel */ }
 };

@@ -986,6 +987,14 @@ static const struct sunxi_mmc_clk_delay sunxi_mmc_clk_delays[] = {
 	[SDXC_CLK_50M_DDR_8BIT]	= { .output =  90, .sample = 180 },
 };
 
+static const struct sunxi_mmc_clk_delay sun8i_a83t_mmc_clk_delays[] = {
+	[SDXC_CLK_400K]		= { .output = 180, .sample = 180 },
+	[SDXC_CLK_25M]		= { .output = 180, .sample =  75 },
+	[SDXC_CLK_50M]		= { .output =  90, .sample = 105 },
+	[SDXC_CLK_50M_DDR]	= { .output =  60, .sample = 120 },
+	[SDXC_CLK_50M_DDR_8BIT]	= { .output =  180, .sample = 180 },
+};
+
 static const struct sunxi_mmc_clk_delay sun9i_mmc_clk_delays[] = {
 	[SDXC_CLK_400K]		= { .output = 180, .sample = 180 },
 	[SDXC_CLK_25M]		= { .output = 180, .sample =  75 },

@@ -1007,6 +1016,8 @@ static int sunxi_mmc_resource_request(struct sunxi_mmc_host *host,
 
 	if (of_device_is_compatible(np, "allwinner,sun9i-a80-mmc"))
 		host->clk_delays = sun9i_mmc_clk_delays;
+	else if (of_device_is_compatible(np, "allwinner,sun8i-a83t-mmc"))
+		host->clk_delays = sun8i_a83t_mmc_clk_delays;
 	else
 		host->clk_delays = sunxi_mmc_clk_delays;
Signature · 1 line
2.9.2
#14 lore raw

PATCH 3/3 mmc: sunxi: Add support to the Allwinner A83T

Maxime

Quoted 1 line · Jean-Francois Moine

The rate of the PLL-PERIPH clock is usually set to 1.2GHz in the A83T.

Uh? The datasheet says to set it to 600MHz.

Quoted 7 lines

This patch sets the phase delays of the output and sample clocks accordingly.

Signed-off-by Jean-Francois Moine <[email protected]>

---
Note: The impacted phase delays are only for 50MHz.
The phase delays are not used in 50MHz 8 bits DDR (new timing mode).

Actually, they seem to be, in the new timing mode register.

Maxime

Signature · 10 lines
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
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#15 lore raw

PATCH 3/3 mmc: sunxi: Add support to the Allwinner A83T

Quoted 4 lines · On Thu, 21 Jul 2016 10:58:38 +0200 Maxime Ripard…
Quoted 1 line · Jean-Francois Moine

The rate of the PLL-PERIPH clock is usually set to 1.2GHz in the A83T.

Uh? The datasheet says to set it to 600MHz.

Right. But the driver of the SDK for the Banana Pi M3 (A83T) sets it to 1.2GHz.

Quoted 9 lines
Quoted 7 lines

This patch sets the phase delays of the output and sample clocks accordingly.

Signed-off-by Jean-Francois Moine <[email protected]>

---
Note: The impacted phase delays are only for 50MHz.
The phase delays are not used in 50MHz 8 bits DDR (new timing mode).

Actually, they seem to be, in the new timing mode register.

In the SDK driver, nothing is set in the new timing mode register. Anyway, the eMMC works fine in both the Banana Pis M2+ and M3 with no delay.

Signature · 2 lines
Ken ar c'henta?	|	      ** Breizh ha Linux atav! **
Jef		|		http://moinejf.free.fr/
author
#16 lore raw

PATCH 3/3 mmc: sunxi: Add support to the Allwinner A83T

Quoted 7 lines · On Thu, 21 Jul 2016 11:18:51 +0200 Jean-Francois Moine <[email protected]> wrote:
Quoted 4 lines · Jean-Francois Moine
Quoted 1 line

The rate of the PLL-PERIPH clock is usually set to 1.2GHz in the A83T.

Uh? The datasheet says to set it to 600MHz.

Right. But the driver of the SDK for the Banana Pi M3 (A83T) sets it to 1.2GHz.

I tested again, and, with the pll-periph at 600MHz, both the SDcard and the eMMC are working fine.
So, you may forget about this patch, sorry for the noise.

Signature · 2 lines
Ken ar c'henta?	|	      ** Breizh ha Linux atav! **
Jef		|		http://moinejf.free.fr/