RAS changes for v4.8

GIT PULL Ingo Molnar 1 participant 1 message Jul 25, 2016 x86

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Ingo Molnar

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2016-07-25 08:34 UTC #0 lore raw

Linus,

Please pull the latest ras-core-for-linus git tree from:

git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip.git ras-core-for-linus

# HEAD: 38c54ccb2ded3e93d8a353baeb7b9e12e1b77e23 x86/mce: Fix mce_rdmsrl() warning message

The biggest change in this cycle was an enhancement by Yazen Ghannam to reduce the number of MCE error injection related IPIs. The rest are smaller fixes.

Thanks,

Ingo

------------------>
Aravind Gopalakrishnan (1):
x86/mce/AMD: Increase size of the bank_map type

Borislav Petkov (1):
x86/mce: Fix mce_rdmsrl() warning message

Tony Luck (1):
x86/mce: Do not use bank 1 for APEI generated error logs

Yazen Ghannam (1):
x86/RAS/AMD: Reduce the number of IPIs when prepping error injection

 arch/x86/kernel/cpu/mcheck/mce-apei.c |  2 +-
 arch/x86/kernel/cpu/mcheck/mce.c      |  2 +-
 arch/x86/kernel/cpu/mcheck/mce_amd.c  |  2 +-
 arch/x86/ras/mce_amd_inj.c            | 58 +++++++++++++++++------------------
 4 files changed, 31 insertions(+), 33 deletions(-)

arch/x86/kernel/cpu/mcheck/mce-apei.c +1 -1

index 34c89a3e8260..83f1a98d37db 100644
@@ -46,7 +46,7 @@ void apei_mce_report_mem_error(int severity, struct cper_sec_mem_err *mem_err)
 		return;
 
 	mce_setup(&m);
-	m.bank = 1;
+	m.bank = -1;
 	/* Fake a memory read error with unknown channel */
 	m.status = MCI_STATUS_VAL | MCI_STATUS_EN | MCI_STATUS_ADDRV | 0x9f;

arch/x86/kernel/cpu/mcheck/mce.c +1 -1

index 92e5e37d97bf..58af6300992d 100644
@@ -425,7 +425,7 @@ static u64 mce_rdmsrl(u32 msr)
 	}
 
 	if (rdmsrl_safe(msr, &v)) {
-		WARN_ONCE(1, "mce: Unable to read msr %d!\n", msr);
+		WARN_ONCE(1, "mce: Unable to read MSR 0x%x!\n", msr);
 		/*
 		 * Return zero in case the access faulted. This should
 		 * not happen normally but can happen if the CPU does

arch/x86/kernel/cpu/mcheck/mce_amd.c +1 -1

index 10b0661651e0..7b7f3be783d4 100644
@@ -93,7 +93,7 @@ const char * const amd_df_mcablock_names[] = {
 EXPORT_SYMBOL_GPL(amd_df_mcablock_names);
 
 static DEFINE_PER_CPU(struct threshold_bank **, threshold_banks);
-static DEFINE_PER_CPU(unsigned char, bank_map);	/* see which banks are on */
+static DEFINE_PER_CPU(unsigned int, bank_map);	/* see which banks are on */
 
 static void amd_threshold_interrupt(void);
 static void amd_deferred_error_interrupt(void);

arch/x86/ras/mce_amd_inj.c +28 ~~-30~~

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