Skip to contentSkip to conversation

ARM: dts: imx7s-warp: Add audio support

PATCH New Fabio Estevam 2 participants 4 messages Aug 15, 2016 – Aug 16, 2016

Subsystems (2)
Device tree bindings Arm i.MX and Layerscape
lore
Share & tools
lore

Fabio Estevam

author reviewer
#0 lore raw

PATCH 1/3 ARM: dts: imx7s-warp: Add audio support

From: Fabio Estevam <[email protected]>

warp7 has a sgtl5000 audio codec.

Add support for it.

Signed-off-by Fabio Estevam <[email protected]>
---
 arch/arm/boot/dts/imx7s-warp.dts | 51 ++++++++++++++++++++++++++++++++++++++++
 1 file changed, 51 insertions(+)
arch/arm/boot/dts/imx7s-warp.dts +51 -0
index ae23781..b9b45b1 100644
@@ -53,6 +53,27 @@
 	memory {
 		reg = <0x80000000 0x20000000>;
 	};
+
+	sound {
+		compatible = "simple-audio-card";
+		simple-audio-card,name = "imx7-sgtl5000";
+		simple-audio-card,format = "i2s";
+		simple-audio-card,bitclock-master = <&dailink_master>;
+		simple-audio-card,frame-master = <&dailink_master>;
+		simple-audio-card,cpu {
+			sound-dai = <&sai1>;
+		};
+
+		dailink_master: simple-audio-card,codec {
+			sound-dai = <&codec>;
+			clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_CLK>;
+		};
+	};
+};
+
+&clks {
+	assigned-clocks = <&clks IMX7D_PLL_AUDIO_POST_DIV>;
+	assigned-clock-rates = <884736000>;
 };
 
 &cpu0 {

@@ -161,12 +182,32 @@
 	pinctrl-0 = <&pinctrl_i2c4>;
 	status = "okay";
 
+	codec: sgtl5000 at 0a {
+		#sound-dai-cells = <0>;
+		reg = <0x0a>;
+		compatible = "fsl,sgtl5000";
+		clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_CLK>;
+		VDDA-supply = <&vgen4_reg>;
+		VDDIO-supply = <&vgen4_reg>;
+		VDDD-supply = <&vgen2_reg>;
+	};
+
 	mpl3115 at 60 {
 		compatible = "fsl,mpl3115";
 		reg = <0x60>;
 	};
 };
 
+&sai1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_sai1>;
+	assigned-clocks = <&clks IMX7D_SAI1_ROOT_SRC>,
+			  <&clks IMX7D_SAI1_ROOT_CLK>;
+	assigned-clock-parents = <&clks IMX7D_PLL_AUDIO_POST_DIV>;
+	assigned-clock-rates = <0>, <36864000>;
+	status = "okay";
+};
+
 &uart1 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_uart1>;

@@ -208,6 +249,16 @@
 		>;
 	};
 
+	pinctrl_sai1: sai1grp {
+		fsl,pins = <
+			MX7D_PAD_SAI1_RX_DATA__SAI1_RX_DATA0	0x1f
+			MX7D_PAD_SAI1_TX_BCLK__SAI1_TX_BCLK	0x1f
+			MX7D_PAD_SAI1_TX_SYNC__SAI1_TX_SYNC	0x1f
+			MX7D_PAD_SAI1_TX_DATA__SAI1_TX_DATA0	0x30
+			MX7D_PAD_SAI1_MCLK__SAI1_MCLK		0x1f
+		>;
+	};
+
 	pinctrl_uart1: uart1grp {
 		fsl,pins = <
 			MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX	0x79
Signature · 1 line
2.7.4
author reviewer
#1 lore raw

PATCH 2/3 ARM: dts: imx7s-warp: Add Wifi support

From: Fabio Estevam <[email protected]>

Warp7 has a BCM43430 Wifi chip connected to the USDHC1 port.

Add support for it.

Signed-off-by Fabio Estevam <[email protected]>
---
 arch/arm/boot/dts/imx7s-warp.dts | 41 ++++++++++++++++++++++++++++++++++++++++
 1 file changed, 41 insertions(+)
arch/arm/boot/dts/imx7s-warp.dts +41 -0
index b9b45b1..cf730c1 100644
@@ -54,6 +54,18 @@
 		reg = <0x80000000 0x20000000>;
 	};
 
+	reg_brcm: regulator-brcm {
+		compatible = "regulator-fixed";
+		enable-active-high;
+		gpio = <&gpio5 10 GPIO_ACTIVE_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_brcm_reg>;
+		regulator-name = "brcm_reg";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		startup-delay-us = <200000>;
+	};
+
 	sound {
 		compatible = "simple-audio-card";
 		simple-audio-card,name = "imx7-sgtl5000";

@@ -221,6 +233,17 @@
 	status = "okay";
 };
 
+&usdhc1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_usdhc1>;
+	bus-width = <4>;
+	keep-power-in-suspend;
+	no-1-8-v;
+	non-removable;
+	vmmc-supply = <&reg_brcm>;
+	status = "okay";
+};
+
 &usdhc3 {
 	pinctrl-names = "default", "state_100mhz", "state_200mhz";
 	pinctrl-0 = <&pinctrl_usdhc3>;

@@ -235,6 +258,12 @@
 };
 
 &iomuxc {
+	pinctrl_brcm_reg: brcmreggrp {
+		fsl,pins = <
+			MX7D_PAD_SD2_WP__GPIO5_IO10	0x14 /* WL_REG_ON */
+		>;
+	};
+
 	pinctrl_i2c1: i2c1grp {
 		fsl,pins = <
 			MX7D_PAD_I2C1_SDA__I2C1_SDA		0x4000007f

@@ -266,6 +295,18 @@
 		>;
 	};
 
+	pinctrl_usdhc1: usdhc1grp {
+		fsl,pins = <
+			MX7D_PAD_SD1_CMD__SD1_CMD	0x59
+			MX7D_PAD_SD1_CLK__SD1_CLK	0x19
+			MX7D_PAD_SD1_DATA0__SD1_DATA0	0x59
+			MX7D_PAD_SD1_DATA1__SD1_DATA1	0x59
+			MX7D_PAD_SD1_DATA2__SD1_DATA2	0x59
+			MX7D_PAD_SD1_DATA3__SD1_DATA3	0x59
+			MX7D_PAD_SD2_RESET_B__GPIO5_IO11 0x14 /* WL_HOST_WAKE */
+		>;
+	};
+
 	pinctrl_usdhc3: usdhc3grp {
 		fsl,pins = <
 			MX7D_PAD_SD3_CMD__SD3_CMD		0x59
Signature · 1 line
2.7.4
author reviewer
#2 lore raw

PATCH 3/3 ARM: dts: imx7s-warp: Use WDOG_B pin reset

In reply to Fabio Estevam

From: Fabio Estevam <[email protected]>

imx7s-warpd has WDOG1_B pin connected to the PMIC.

Pass the 'fsl,ext-reset-output' property so that the watchdog can trigger a system POR reset via the PMIC.

Signed-off-by Fabio Estevam <[email protected]>
---
 arch/arm/boot/dts/imx7s-warp.dts | 13 +++++++++++++
 1 file changed, 13 insertions(+)
arch/arm/boot/dts/imx7s-warp.dts +13 -0
index cf730c1..8ef1cdc 100644
@@ -257,6 +257,13 @@
 	status = "okay";
 };
 
+&wdog1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_wdog>;
+	fsl,ext-reset-output;
+	status = "okay";
+};
+
 &iomuxc {
 	pinctrl_brcm_reg: brcmreggrp {
 		fsl,pins = <

@@ -354,4 +361,10 @@
 			MX7D_PAD_SD3_RESET_B__SD3_RESET_B	0x1b
 		>;
 	};
+
+	pinctrl_wdog: wdoggrp {
+		fsl,pins = <
+			MX7D_PAD_GPIO1_IO00__WDOD1_WDOG_B	0x74
+		>;
+	};
 };
Signature · 1 line
2.7.4