ARM: Move SYS_CACHELINE_SIZE over to Kconfig

This series moves the CONFIG_SYS_CACHELINE_SIZE. First, in nearly all cases we are mirroring the values used by the Linux Kernel here. Also, so long as (and in this case, it is true) we implement flushes in hunks that are no larger than the smallest implementation (and given that we mirror the Linux Kernel, again we are fine) it is OK to align higher. The biggest changes here are that we always use 64 bytes for CPU_V7 even if for example the underlying core is only 32 bytes (this mirrors Linux). Second, we say ARM64 uses 64 bytes not 128 (as found in the Linux Kernel) as we do not need multi-platform support (to this degree) and only the Cavium ThunderX 88xx series has a use for such large alignment.

Cc Albert Aribaud <[email protected]>

Cc Marek Vasut <[email protected]>

Cc Stefano Babic <[email protected]>

Cc Prafulla Wadaskar <[email protected]>

Cc Luka Perkov <[email protected]>

Cc Stefan Roese <[email protected]>

Cc Nagendra T S <[email protected]>

Cc Vaibhav Hiremath <[email protected]>

Acked-by Lokesh Vutla <[email protected]>

Cc Steve Rae <[email protected]>

Cc Igor Grinberg <[email protected]>

Cc Nikita Kiryanov <[email protected]>

Cc Stefan Agner <[email protected]>

Acked-by Heiko Schocher <[email protected]>

Cc Mateusz Kulikowski <[email protected]>

Cc Peter Griffin <[email protected]>

Cc Paul Kocialkowski <[email protected]>

Cc Anatolij Gustschin <[email protected]>

Acked-by "Pali Roh?r" <[email protected]>

Cc Adam Ford <[email protected]>

Cc Steve Sakoman <[email protected]>

Cc Grazvydas Ignotas <[email protected]>

Cc Nishanth Menon <[email protected]>

Cc Stephen Warren <[email protected]>

Cc Robert Baldyga <[email protected]>

Cc Minkyu Kang <[email protected]>

Cc Thomas Weber <[email protected]>

Cc Masahiro Yamada <[email protected]>

Cc David Feng <[email protected]>

Cc Alison Wang <[email protected]>

Cc Michal Simek <[email protected]>

Cc Simon Glass <[email protected]>

Cc York Sun <[email protected]>

Cc Shengzhou Liu <[email protected]>

Cc Mingkai Hu <[email protected]>

Cc Prabhakar Kushwaha <[email protected]>

Cc Aneesh Bansal <[email protected]>

Cc Saksham Jain <[email protected]>

Cc Qianyu Gong <[email protected]>

Cc Wang Dongsheng <[email protected]>

Cc Alex Porosanu <[email protected]>

Cc Hongbo Zhang <[email protected]>

Cc tang yuantian <[email protected]>

Cc Rajesh Bhagat <[email protected]>

Cc Josh Wu <[email protected]>

Cc Bo Shen <[email protected]>

Cc Viresh Kumar <[email protected]>

Cc Hannes Schmelzer <[email protected]>

Cc Thomas Chou <[email protected]>

Cc Joe Hershberger <[email protected]>

Cc Sam Protsenko <[email protected]>

Cc Bin Meng <[email protected]>

Cc Christophe Ricard <[email protected]>

Cc Anand Moon <[email protected]>

Cc Beniamino Galvani <[email protected]>

Cc Carlo Caione <[email protected]>

Cc huang lin <[email protected]>

Cc Sjoerd Simons <[email protected]>

Cc Xu Ziyuan <[email protected]>

Cc "jk.kernel at gmail.com" <[email protected]>

Cc "Ariel D'Alessandro" <[email protected]>

Cc Kever Yang <[email protected]>

Cc Samuel Egli <[email protected]>

Cc Chin Liang See <[email protected]>

Cc Dinh Nguyen <[email protected]>

Cc Hans de Goede <[email protected]>

Cc Ian Campbell <[email protected]>

Cc Siarhei Siamashka <[email protected]>

Cc Boris Brezillon <[email protected]>

Cc Andre Przywara <[email protected]>

Cc Bernhard Nortmann <[email protected]>

Cc Wolfgang Denk <[email protected]>

Cc Ben Whitten <[email protected]>

Cc Tom Warren <[email protected]>

Cc Alexander Graf <[email protected]>

Cc Sekhar Nori <[email protected]>

Cc Vitaly Andrianov <[email protected]>

Cc "Andrew F. Davis" <[email protected]>

Cc Murali Karicheri <[email protected]>

Cc Carlos Hernandez <[email protected]>

Cc Ladislav Michl <[email protected]>

Cc Ash Charles <[email protected]>

Cc Mugunthan V N <[email protected]>

Cc Daniel Allred <[email protected]>

Cc Gong Qianyu <[email protected]>

Signed-off-by Tom Rini <[email protected]>

Acked-by Masahiro Yamada <[email protected]>

Acked-by Chin Liang See <[email protected]>

Tested-by Stephen Warren <[email protected]>

Acked-by Paul Kocialkowski <[email protected]>

This series moves the CONFIG_SYS_CACHELINE_SIZE. First, in nearly all cases we are mirroring the values used by the Linux Kernel here. Also, so long as (and in this case, it is true) we implement flushes in hunks that are no larger than the smallest implementation (and given that we mirror the Linux Kernel, again we are fine) it is OK to align higher. The biggest changes here are that we always use 64 bytes for CPU_V7 even if for example the underlying core is only 32 bytes (this mirrors Linux). Second, we say ARM64 uses 64 bytes not 128 (as found in the Linux Kernel) as we do not need multi-platform support (to this degree) and only the Cavium ThunderX 88xx series has a use for such large alignment.

 arch/arm/mach-uniphier/Kconfig                    |  1 +

This series moves the CONFIG_SYS_CACHELINE_SIZE. First, in nearly all
cases we are mirroring the values used by the Linux Kernel here.
Also,
so long as (and in this case, it is true) we implement flushes in hunks
that are no larger than the smallest implementation (and given that we
mirror the Linux Kernel, again we are fine) it is OK to align higher. The biggest changes here are that we always use 64 bytes for CPU_V7 even
if for example the underlying core is only 32 bytes (this mirrors Linux). Second, we say ARM64 uses 64 bytes not 128 (as found in the Linux Kernel) as we do not need multi-platform support (to this degree)
and only the Cavium ThunderX 88xx series has a use for such large alignment.

 arch/arm/Kconfig                                  | 27

...

arch/arm/Kconfig +0 -0

index aef901c3f448..e6d4a2043854 100644
@@ -7,6 +7,7 @@ config SYS_ARCH
 

arch/arm/Kconfig +6 -0

+config SYS_CACHELINE_SIZE
+	int
+	default 128 if SYS_CACHE_SHIFT_7
+	default 64 if SYS_CACHE_SHIFT_6
+	default 32 if SYS_CACHE_SHIFT_5
+

Hi Tom,

Quoted 19 lines · Tom Rini

This series moves the CONFIG_SYS_CACHELINE_SIZE. First, in nearly all
cases we are mirroring the values used by the Linux Kernel here.
Also,
so long as (and in this case, it is true) we implement flushes in hunks
that are no larger than the smallest implementation (and given that we
mirror the Linux Kernel, again we are fine) it is OK to align higher. The biggest changes here are that we always use 64 bytes for CPU_V7 even
if for example the underlying core is only 32 bytes (this mirrors Linux). Second, we say ARM64 uses 64 bytes not 128 (as found in the Linux Kernel) as we do not need multi-platform support (to this degree)
and only the Cavium ThunderX 88xx series has a use for such large alignment.

...

Quoted 11 lines

 arch/arm/Kconfig                                  | 27

...

arch/arm/Kconfig +0 -0

index aef901c3f448..e6d4a2043854 100644
@@ -7,6 +7,7 @@ config SYS_ARCH
 

...

Quoted 1 line

arch/arm/Kconfig

Quoted 6 lines

config CPU_V7
bool
select HAS_VBAR
select HAS_THUMB2

arch/arm/Kconfig +1 -0

+	select SYS_CACHE_SHIFT_6

CPU_V7 should use SYS_CACHE_SHIFT_5 which is 32 bytes cache lines.

Quoted 44 lines · Chin Liang See

Hi Tom,

Quoted 24 lines · Tom Rini

This series moves the CONFIG_SYS_CACHELINE_SIZE. First, in nearly
all
cases we are mirroring the values used by the Linux Kernel here.
Also,
so long as (and in this case, it is true) we implement flushes in hunks
that are no larger than the smallest implementation (and given that
we
mirror the Linux Kernel, again we are fine) it is OK to align higher.
The biggest changes here are that we always use 64 bytes for CPU_V7
even
if for example the underlying core is only 32 bytes (this mirrors Linux). Second, we say ARM64 uses 64 bytes not 128 (as found in the
Linux Kernel) as we do not need multi-platform support (to this degree)
and only the Cavium ThunderX 88xx series has a use for such large alignment.

...

Quoted 11 lines

 arch/arm/Kconfig                                  | 27

...

arch/arm/Kconfig +0 -0

index aef901c3f448..e6d4a2043854 100644
@@ -7,6 +7,7 @@ config SYS_ARCH
 

...

Quoted 1 line

Quoted 8 lines

arch/arm/Kconfig

Quoted 6 lines

config CPU_V7
bool
select HAS_VBAR
select HAS_THUMB2

arch/arm/Kconfig +1 -0

+	select SYS_CACHE_SHIFT_6

CPU_V7 should use SYS_CACHE_SHIFT_5 which is 32 bytes cache lines.

No, some V7 are 32 and some are 64, for example Cortex-A8.

include/configs/cm_t3517.h +0 -2

index ea9983bc7d43..a89ccb73b178 100644
@@ -10,8 +10,6 @@
 #ifndef __CONFIG_H
 #define __CONFIG_H
 
-#define CONFIG_SYS_CACHELINE_SIZE	64
-
 /*
  * High Level Configuration Options
  */

On Mon, Aug 22, 2016 at 08:22:17AM -0400, Tom Rini wrote:
[snip]

Quoted 8 lines

include/configs/cm_t3517.h +0 -0

index ea9983bc7d43..a89ccb73b178 100644
@@ -10,8 +10,6 @@
 #ifndef __CONFIG_H
 #define __CONFIG_H
 

include/configs/cm_t3517.h line 30

Quoted 9 lines

include/configs/cm_t3517.h +0 -2

-#define CONFIG_SYS_CACHELINE_SIZE	64
-
 /*
  * High Level Configuration Options
  */

@@ -30,7 +28,6 @@
  * Although the default iss 64, we still define it
  * to be on the safe side once the default is changed.
  */

That comment above probably looses sense with define removed...

include/configs/cm_t3517.h line 33

Quoted 4 lines

include/configs/cm_t3517.h +0 -1

-#define CONFIG_SYS_CACHELINE_SIZE	64
 
 #define CONFIG_EMIF4	/* The chip has EMIF4 controller */
 

regards,
ladis

PS. Tested on OMAP3 IGEPv2 and TAM-3517 boards

This series moves the CONFIG_SYS_CACHELINE_SIZE. First, in nearly all cases we are mirroring the values used by the Linux Kernel here. Also, so long as (and in this case, it is true) we implement flushes in hunks that are no larger than the smallest implementation (and given that we mirror the Linux Kernel, again we are fine) it is OK to align higher. The biggest changes here are that we always use 64 bytes for CPU_V7 even if for example the underlying core is only 32 bytes (this mirrors Linux). Second, we say ARM64 uses 64 bytes not 128 (as found in the Linux Kernel) as we do not need multi-platform support (to this degree) and only the Cavium ThunderX 88xx series has a use for such large alignment.

Quoted 11 lines · Tom Rini

This series moves the CONFIG_SYS_CACHELINE_SIZE. First, in nearly all cases we are mirroring the values used by the Linux Kernel here. Also, so long as (and in this case, it is true) we implement flushes in hunks that are no larger than the smallest implementation (and given that we mirror the Linux Kernel, again we are fine) it is OK to align higher. The biggest changes here are that we always use 64 bytes for CPU_V7 even if for example the underlying core is only 32 bytes (this mirrors Linux). Second, we say ARM64 uses 64 bytes not 128 (as found in the Linux Kernel) as we do not need multi-platform support (to this degree) and only the Cavium ThunderX 88xx series has a use for such large alignment.

Tested-by Stephen Warren <[email protected]>

This has the potential to cause a few more cache warnings due to the slightly stricter/larger alignment checking on older ARMv7s with smaller cache lines. However, it works fine on all the Tegra systems my automated tests run on right now, which does include one Cortex A9 with 32-byte cache line, and doesn't seem to actually trigger any additional unaligned buffer warnings.

This series moves the CONFIG_SYS_CACHELINE_SIZE.??First, in nearly all cases we are mirroring the values used by the Linux Kernel here.??Also, so long as (and in this case, it is true) we implement flushes in hunks that are no larger than the smallest implementation (and given that we mirror the Linux Kernel, again we are fine) it is OK to align higher. The biggest changes here are that we always use 64 bytes for CPU_V7 even if for example the underlying core is only 32 bytes (this mirrors Linux).??Second, we say ARM64 uses 64 bytes not 128 (as found in the Linux Kernel) as we do not need multi-platform support (to this degree) and only the Cavium ThunderX 88xx series has a use for such large alignment.

Cc Albert Aribaud <[email protected]>

Cc Marek Vasut <[email protected]>

Cc Stefano Babic <[email protected]>

Cc Prafulla Wadaskar <[email protected]>

Cc Luka Perkov <[email protected]>

Cc Stefan Roese <[email protected]>

Cc Nagendra T S <[email protected]>

Cc Vaibhav Hiremath <[email protected]>

Acked-by Lokesh Vutla <[email protected]>

Cc Steve Rae <[email protected]>

Cc Igor Grinberg <[email protected]>

Cc Nikita Kiryanov <[email protected]>

Cc Stefan Agner <[email protected]>

Acked-by Heiko Schocher <[email protected]>

Cc Mateusz Kulikowski <[email protected]>

Cc Peter Griffin <[email protected]>

Cc Paul Kocialkowski <[email protected]>

Cc Anatolij Gustschin <[email protected]>

Acked-by "Pali Roh?r" <[email protected]>

Cc Adam Ford <[email protected]>

Cc Steve Sakoman <[email protected]>

Cc Grazvydas Ignotas <[email protected]>

Cc Nishanth Menon <[email protected]>

Cc Stephen Warren <[email protected]>

Cc Robert Baldyga <[email protected]>

Cc Minkyu Kang <[email protected]>

Cc Thomas Weber <[email protected]>

Cc Masahiro Yamada <[email protected]>

Cc David Feng <[email protected]>

Cc Alison Wang <[email protected]>

Cc Michal Simek <[email protected]>

Cc Simon Glass <[email protected]>

Cc York Sun <[email protected]>

Cc Shengzhou Liu <[email protected]>

Cc Mingkai Hu <[email protected]>

Cc Prabhakar Kushwaha <[email protected]>

Cc Aneesh Bansal <[email protected]>

Cc Saksham Jain <[email protected]>

Cc Qianyu Gong <[email protected]>

Cc Wang Dongsheng <[email protected]>

Cc Alex Porosanu <[email protected]>

Cc Hongbo Zhang <[email protected]>

Cc tang yuantian <[email protected]>

Cc Rajesh Bhagat <[email protected]>

Cc Josh Wu <[email protected]>

Cc Bo Shen <[email protected]>

Cc Viresh Kumar <[email protected]>

Cc Hannes Schmelzer <[email protected]>

Cc Thomas Chou <[email protected]>

Cc Joe Hershberger <[email protected]>

Cc Sam Protsenko <[email protected]>

Cc Bin Meng <[email protected]>

Cc Christophe Ricard <[email protected]>

Cc Anand Moon <[email protected]>

Cc Beniamino Galvani <[email protected]>

Cc Carlo Caione <[email protected]>

Cc huang lin <[email protected]>

Cc Sjoerd Simons <[email protected]>

Cc Xu Ziyuan <[email protected]>

Cc "jk.kernel at gmail.com" <[email protected]>

Cc "Ariel D'Alessandro" <[email protected]>

Cc Kever Yang <[email protected]>

Cc Samuel Egli <[email protected]>

Cc Chin Liang See <[email protected]>

Cc Dinh Nguyen <[email protected]>

Cc Hans de Goede <[email protected]>

Cc Ian Campbell <[email protected]>

Cc Siarhei Siamashka <[email protected]>

Cc Boris Brezillon <[email protected]>

Cc Andre Przywara <[email protected]>

Cc Bernhard Nortmann <[email protected]>

Cc Wolfgang Denk <[email protected]>

Cc Ben Whitten <[email protected]>

Cc Tom Warren <[email protected]>

Cc Alexander Graf <[email protected]>

Cc Sekhar Nori <[email protected]>

Cc Vitaly Andrianov <[email protected]>

Cc "Andrew F. Davis" <[email protected]>

Cc Murali Karicheri <[email protected]>

Cc Carlos Hernandez <[email protected]>

Cc Ladislav Michl <[email protected]>

Cc Ash Charles <[email protected]>

Cc Mugunthan V N <[email protected]>

Cc Daniel Allred <[email protected]>

Cc Gong Qianyu <[email protected]>

Signed-off-by Tom Rini <[email protected]>

---
Changes in v2:
- Per Masahiro, add _SHIFT_x bools, select those. Also select _7 for ? CACHE_UNIPHIER as that is the case which needs 128 bytes.??Select _7 ? for Thunderx 88xx to mirror the Linux Kernel.??Note that I'm not using ? a default shift here as this needs to move to a higher level Kconfig ? file in time.
- Remove now useless comments from include/configs/
- Reword comment in arch/arm/include/asm/cache.h about what the value of ? CONFIG_SYS_CACHELINE_SIZE should be to not be L1 centric.
---
?arch/arm/Kconfig??????????????????????????????????| 27
+++++++++++++++++++++++

?arch/arm/cpu/arm11/cpu.c??????????????????????????|??5 -----
?arch/arm/cpu/arm926ejs/cache.c????????????????????|??5 -----
?arch/arm/cpu/pxa/cache.c??????????????????????????|??5 -----
?arch/arm/include/asm/arch-armada100/config.h??????|??2 --
?arch/arm/include/asm/arch-fsl-layerscape/config.h |??2 --
?arch/arm/include/asm/arch-ls102xa/config.h????????|??2 --
?arch/arm/include/asm/arch-mx5/imx-regs.h??????????|??2 --
?arch/arm/include/asm/arch-mx6/imx-regs.h??????????|??6 -----
?arch/arm/include/asm/arch-mx7/imx-regs.h??????????|??2 --
?arch/arm/include/asm/cache.h??????????????????????| 11 ++++-----
?arch/arm/lib/cache.c??????????????????????????????|??4 ----
?arch/arm/mach-kirkwood/include/mach/config.h??????|??2 --
?arch/arm/mach-mvebu/include/mach/config.h?????????|??2 --
?arch/arm/mach-uniphier/Kconfig????????????????????|??1 +
?include/configs/am3517_crane.h????????????????????|??2 --
?include/configs/am3517_evm.h??????????????????????|??2 --
?include/configs/am43xx_evm.h??????????????????????|??2 --
?include/configs/at91-sama5_common.h???????????????|??2 --
?include/configs/bcm23550_w1d.h????????????????????|??1 -
?include/configs/bcm28155_ap.h?????????????????????|??1 -
?include/configs/bcm_ep_board.h????????????????????|??2 --
?include/configs/bur_am335x_common.h???????????????|??1 -
?include/configs/cm_t3517.h????????????????????????|??3 ---
?include/configs/cm_t43.h??????????????????????????|??1 -
?include/configs/colibri_vf.h??????????????????????|??4 ----
?include/configs/corvus.h??????????????????????????|??1 -
?include/configs/dragonboard410c.h?????????????????|??2 --
?include/configs/exynos4-common.h??????????????????|??1 -
?include/configs/exynos5-common.h??????????????????|??1 -
?include/configs/flea3.h???????????????????????????|??1 -
?include/configs/hikey.h???????????????????????????|??3 ---
?include/configs/kc1.h?????????????????????????????|??1 -
?include/configs/kzm9g.h???????????????????????????|??2 --
?include/configs/mcx.h?????????????????????????????|??2 --
?include/configs/meson-gxbb-common.h???????????????|??1 -
?include/configs/nokia_rx51.h??????????????????????|??2 --
?include/configs/omap3_beagle.h????????????????????|??2 --
?include/configs/omap3_cairo.h?????????????????????|??2 --
?include/configs/omap3_evm.h???????????????????????|??2 --
?include/configs/omap3_logic.h?????????????????????|??1 -
?include/configs/omap3_overo.h?????????????????????|??1 -
?include/configs/omap3_pandora.h???????????????????|??2 --
?include/configs/omap3_zoom1.h?????????????????????|??2 --
?include/configs/pcm052.h??????????????????????????|??2 --
?include/configs/rcar-gen2-common.h????????????????|??2 --
?include/configs/rk3036_common.h???????????????????|??2 --
?include/configs/rk3288_common.h???????????????????|??2 --
?include/configs/rk3399_common.h???????????????????|??2 --
?include/configs/rpi.h?????????????????????????????|??6 -----
?include/configs/s5p_goni.h????????????????????????|??4 ----
?include/configs/siemens-am33x-common.h????????????|??2 --
?include/configs/smartweb.h????????????????????????|??2 --
?include/configs/smdkc100.h????????????????????????|??2 --
?include/configs/sniper.h??????????????????????????|??2 --
?include/configs/socfpga_common.h??????????????????|??1 -
?include/configs/sunxi-common.h????????????????????|??1 -
?include/configs/tam3517-common.h??????????????????|??2 --
?include/configs/tao3530.h?????????????????????????|??2 --
?include/configs/taurus.h??????????????????????????|??2 --
?include/configs/tegra114-common.h?????????????????|??3 ---
?include/configs/tegra124-common.h?????????????????|??3 ---
?include/configs/tegra186-common.h?????????????????|??3 ---
?include/configs/tegra20-common.h??????????????????|??3 ---
?include/configs/tegra210-common.h?????????????????|??3 ---
?include/configs/tegra30-common.h??????????????????|??3 ---
?include/configs/ti814x_evm.h??????????????????????|??2 --
?include/configs/ti816x_evm.h??????????????????????|??2 --
?include/configs/ti_am335x_common.h????????????????|??1 -
?include/configs/ti_armv7_keystone2.h??????????????|??1 -
?include/configs/ti_omap3_common.h?????????????????|??2 --
?include/configs/ti_omap4_common.h?????????????????|??1 -
?include/configs/ti_omap5_common.h?????????????????|??2 --
?include/configs/tricorder.h???????????????????????|??2 --
?include/configs/uniphier.h????????????????????????|??6 -----
?include/configs/vexpress_aemv8a.h?????????????????|??3 ---
?include/configs/vexpress_common.h?????????????????|??2 --
?include/configs/vf610twr.h????????????????????????|??2 --
?include/configs/woodburn_common.h?????????????????|??1 -
?include/configs/xilinx_zynqmp.h???????????????????|??3 ---
?include/configs/zynq-common.h?????????????????????|??2 --

?81 files changed, 32 insertions(+), 182 deletions(-)

arch/arm/Kconfig +0 -0

index aef901c3f448..e6d4a2043854 100644
@@ -7,6 +7,7 @@ config SYS_ARCH

?config ARM64
? bool
? select PHYS_64BIT

arch/arm/Kconfig +1 -0

+	select SYS_CACHE_SHIFT_6

?
?config DMA_ADDR_T_64BIT
? bool

arch/arm/Kconfig +0 -0

@@ -20,37 +21,47 @@ config HAS_THUMB2

?
?config CPU_ARM720T
?????????bool

arch/arm/Kconfig +1 -0

+	select SYS_CACHE_SHIFT_5

?
?config CPU_ARM920T
?????????bool

arch/arm/Kconfig +1 -0

+	select SYS_CACHE_SHIFT_5

?
?config CPU_ARM926EJS
?????????bool

arch/arm/Kconfig +1 -0

+	select SYS_CACHE_SHIFT_5

?
?config CPU_ARM946ES
?????????bool

arch/arm/Kconfig +1 -0

+	select SYS_CACHE_SHIFT_5

?
?config CPU_ARM1136
?????????bool

arch/arm/Kconfig +1 -0

+	select SYS_CACHE_SHIFT_5

?
?config CPU_ARM1176
?????????bool
?????????select HAS_VBAR

arch/arm/Kconfig +1 -0

+	select SYS_CACHE_SHIFT_5

?
?config CPU_V7
?????????bool
?????????select HAS_VBAR
?????????select HAS_THUMB2

arch/arm/Kconfig +1 -0

+	select SYS_CACHE_SHIFT_6

?
?config CPU_V7M
? bool
?????????select HAS_THUMB2

arch/arm/Kconfig +1 -0

+	select SYS_CACHE_SHIFT_5

?
?config CPU_PXA
?????????bool

arch/arm/Kconfig +1 -0

+	select SYS_CACHE_SHIFT_5

?
?config CPU_SA1100
?????????bool

arch/arm/Kconfig +1 -0

+	select SYS_CACHE_SHIFT_5

?
?config SYS_CPU
?????????default "arm720t" if CPU_ARM720T

arch/arm/Kconfig +0 -0

@@ -79,6 +90,21 @@ config SYS_ARM_ARCH

? default 4 if CPU_SA1100
? default 8 if ARM64
?

arch/arm/Kconfig +15 -0

+config SYS_CACHE_SHIFT_5
+	bool
+
+config SYS_CACHE_SHIFT_6
+	bool
+
+config SYS_CACHE_SHIFT_7
+	bool
+
+config SYS_CACHELINE_SIZE
+	int
+	default 128 if SYS_CACHE_SHIFT_7
+	default 64 if SYS_CACHE_SHIFT_6
+	default 32 if SYS_CACHE_SHIFT_5
+

?config SEMIHOSTING
? bool "support boot from semihosting"
? help

arch/arm/Kconfig +0 -0

@@ -867,6 +893,7 @@ config TARGET_THUNDERX_88XX

? bool "Support ThunderX 88xx"
? select ARM64
? select OF_CONTROL

arch/arm/Kconfig +1 -0

+	select SYS_CACHE_SHIFT_7

?
?endchoice
?

arch/arm/cpu/arm11/cpu.c +0 -0

index 7244c2e7d79e..ef32c3f0abd4 100644
@@ -53,11 +53,6 @@ static void cache_flush(void)
 ?}

?
?#ifndef CONFIG_SYS_DCACHE_OFF

arch/arm/cpu/arm11/cpu.c +0 -5

-
-#ifndef CONFIG_SYS_CACHELINE_SIZE
-#define CONFIG_SYS_CACHELINE_SIZE	32
-#endif
-

?void invalidate_dcache_all(void)
?{
? asm volatile("mcr p15, 0, %0, c7, c6, 0" : : "r" (0));

arch/arm/cpu/arm926ejs/cache.c +0 -0

index 2119382ab245..02cb24c24ffb 100644
@@ -8,11 +8,6 @@

?#include <common.h>
?
?#ifndef CONFIG_SYS_DCACHE_OFF

arch/arm/cpu/arm926ejs/cache.c +0 -5

-
-#ifndef CONFIG_SYS_CACHELINE_SIZE
-#define CONFIG_SYS_CACHELINE_SIZE	32
-#endif
-

?void invalidate_dcache_all(void)
?{
? asm volatile("mcr p15, 0, %0, c7, c6, 0\n" : : "r"(0));

arch/arm/cpu/pxa/cache.c +0 -0

index 7aba112c714b..d26354e1aadc 100644
@@ -8,11 +8,6 @@

?#include <common.h>
?
?#ifndef CONFIG_SYS_DCACHE_OFF

arch/arm/cpu/pxa/cache.c +0 -5

-
-#ifndef CONFIG_SYS_CACHELINE_SIZE
-#define CONFIG_SYS_CACHELINE_SIZE	32
-#endif
-

?void invalidate_dcache_all(void)
?{
? /* Flush/Invalidate I cache */

arch/arm/include/asm/arch-armada100/config.h +0 -0

index e062da18b113..6ebc759f4b96 100644
@@ -16,8 +16,6 @@

?#define _ARMD1_CONFIG_H
?
?#include <asm/arch/armada100.h>

arch/arm/include/asm/arch-armada100/config.h +0 -2

-/* default Dcache Line length for armada100 */
-#define CONFIG_SYS_CACHELINE_SIZE???????32

?
?#define CONFIG_SYS_TCLK (14745600) /* NS16550 clk
config */
?#define CONFIG_SYS_HZ_CLOCK (3250000) /* Timer Freq. 3.25MHZ */

arch/arm/include/asm/arch-fsl-layerscape/config.h +0 -0

index b0ad4b462689..527998111f31 100644
@@ -36,7 +36,6 @@

?#define CONFIG_SYS_FSL_SRDS_1
?#define CONFIG_SYS_FSL_SRDS_2
?#define CONFIG_SYS_PAGE_SIZE 0x10000
-#define CONFIG_SYS_CACHELINE_SIZE 64
?#ifndef L1_CACHE_BYTES
?#define L1_CACHE_SHIFT 6
?#define L1_CACHE_BYTES BIT(L1_CACHE_SHIFT)

arch/arm/include/asm/arch-fsl-layerscape/config.h +0 -0

@@ -150,7 +149,6 @@

?
?#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1
?#elif defined(CONFIG_FSL_LSCH2)
-#define CONFIG_SYS_CACHELINE_SIZE 64
?#define CONFIG_NUM_DDR_CONTROLLERS 1
?#define CONFIG_SYS_FSL_SEC_COMPAT 5
?#define CONFIG_SYS_FSL_OCRAM_BASE 0x10000000 /* initial RAM */

arch/arm/include/asm/arch-ls102xa/config.h +0 -0

index d408fe40561a..56d8f3247f54 100644
@@ -7,8 +7,6 @@

?#ifndef _ASM_ARMV7_LS102XA_CONFIG_
?#define _ASM_ARMV7_LS102XA_CONFIG_
?

arch/arm/include/asm/arch-ls102xa/config.h +0 -2

-#define CONFIG_SYS_CACHELINE_SIZE		64
-

?#define OCRAM_BASE_ADDR 0x10000000
?#define OCRAM_SIZE 0x00010000
?#define OCRAM_BASE_S_ADDR 0x10010000

arch/arm/include/asm/arch-mx5/imx-regs.h +0 -0

index e73cc0765326..3e79fa3224ec 100644
@@ -9,8 +9,6 @@

?
?#define ARCH_MXC
?

arch/arm/include/asm/arch-mx5/imx-regs.h +0 -2

-#define CONFIG_SYS_CACHELINE_SIZE 64
-

?#if defined(CONFIG_MX51)
?#define IRAM_BASE_ADDR 0x1FFE0000 /* internal ram */
?#define IPU_SOC_BASE_ADDR 0x40000000

arch/arm/include/asm/arch-mx6/imx-regs.h +0 -0

index ac37e4f8e689..53bf05439d91 100644
@@ -9,12 +9,6 @@

?
?#define ARCH_MXC
?

arch/arm/include/asm/arch-mx6/imx-regs.h +0 -6

-#ifdef CONFIG_MX6UL
-#define CONFIG_SYS_CACHELINE_SIZE	64
-#else
-#define CONFIG_SYS_CACHELINE_SIZE	32
-#endif
-

?#define ROMCP_ARB_BASE_ADDR?????????????0x00000000 ?#define ROMCP_ARB_END_ADDR??????????????0x000FFFFF ?

arch/arm/include/asm/arch-mx7/imx-regs.h +0 -0

index 74917f0e69d8..d33be313c6ee 100644
@@ -9,8 +9,6 @@

?
?#define ARCH_MXC
?

arch/arm/include/asm/arch-mx7/imx-regs.h +0 -2

-#define CONFIG_SYS_CACHELINE_SIZE	64
-

?#define ROM_SW_INFO_ADDR????????????????0x000001E8 ?#define ROMCP_ARB_BASE_ADDR?????????????0x00000000 ?#define ROMCP_ARB_END_ADDR??????????????0x00017FFF

arch/arm/include/asm/cache.h +0 -0

index 16e65c36a9a5..5400cbe18ff4 100644
@@ -43,14 +43,11 @@ void dram_bank_mmu_setup(int bank);

?#endif
?
?/*
- * The current upper bound for ARM L1 data cache line sizes is 64 bytes.??We
- * use that value for aligning DMA buffers unless the board config has specified
- * an alternate cache line size.
+ * The value of the largest data cache relevant to DMA operations shall be set
+ * for us in CONFIG_SYS_CACHELINE_SIZE.??In some cases this may be a larger
+ * value than found in the L1 cache but this is OK to use in terms of
+ * alignment.
? */
-#ifdef CONFIG_SYS_CACHELINE_SIZE
?#define ARCH_DMA_MINALIGN CONFIG_SYS_CACHELINE_SIZE

arch/arm/include/asm/cache.h +0 -3

-#else
-#define ARCH_DMA_MINALIGN	64
-#endif

?
?#endif /* _ASM_CACHE_H */

arch/arm/lib/cache.c +0 -0

index d330b09434a4..4f72f8914cc7 100644
@@ -10,10 +10,6 @@

?#include <common.h>
?#include <malloc.h>
?

arch/arm/lib/cache.c +0 -4

-#ifndef CONFIG_SYS_CACHELINE_SIZE
-#define CONFIG_SYS_CACHELINE_SIZE 32
-#endif
-

?/*
? * Flush range from all levels of d-cache/unified-cache. ? * Affects the range [start, start + size - 1].

arch/arm/mach- renamed from arch/arm/mach-kirkwood/include/mach/config.h +0 -0

kirkwood/include/mach/config.h
index 60b60aa6f6e6..446457fd812f 100644

arch/arm/mach-kirkwood/include/mach/config.h +0 -0

@@ -24,8 +24,6 @@

?#endif /* CONFIG_KW88F6281 */
?
?#include <asm/arch/soc.h>

arch/arm/mach-kirkwood/include/mach/config.h +0 -2

-#define CONFIG_SYS_CACHELINE_SIZE	32
-				/* default Dcache Line length for kirkwood */

?#define CONFIG_MD5 /* get_random_hex on krikwood needs MD5 support */
?#define CONFIG_KIRKWOOD_EGIGA_INIT /* Enable GbePort0/1 for kernel */
?#define CONFIG_KIRKWOOD_RGMII_PAD_1V8 /* Set RGMII Pad voltage to 1.8V
*/

arch/arm/mach- renamed from arch/arm/mach-mvebu/include/mach/config.h +0 -0

mvebu/include/mach/config.h
index 4df70d7d3f06..1b35e0802b24 100644

arch/arm/mach-mvebu/include/mach/config.h +0 -0

@@ -26,8 +26,6 @@

?#define MV88F78X60 /* for the DDR training bin_hdr code */ ?#endif
?

arch/arm/mach-mvebu/include/mach/config.h +0 -2

-#define CONFIG_SYS_CACHELINE_SIZE	32
-

?#define CONFIG_SYS_L2_PL310
?
?#ifdef CONFIG_SPL_BUILD

arch/arm/mach-uniphier/Kconfig +0 -0

index a8a0b90c39b2..89614581bb1f 100644
@@ -75,6 +75,7 @@ config ARCH_UNIPHIER_LD6B

?config CACHE_UNIPHIER
? bool "Enable the UniPhier L2 cache controller"
? depends on ARCH_UNIPHIER_32BIT

arch/arm/mach-uniphier/Kconfig +1 -0

+	select SYS_CACHE_SHIFT_7

? default y
? help
? ??This option allows to use the UniPhier System Cache as L2 cache.

include/configs/am3517_crane.h +0 -0

index a65d1a884b01..30c42781cafb 100644
@@ -13,8 +13,6 @@

?#ifndef __CONFIG_H
?#define __CONFIG_H
?

include/configs/am3517_crane.h +0 -2

-#define CONFIG_SYS_CACHELINE_SIZE	64
-

?/*
? * High Level Configuration Options
? */

include/configs/am3517_evm.h +0 -0

index 4d88aac63750..ef4a8baf43ce 100644
@@ -18,8 +18,6 @@

?#define CONFIG_OMAP
?#define CONFIG_OMAP_COMMON
?

include/configs/am3517_evm.h +0 -2

-#define CONFIG_SYS_CACHELINE_SIZE	64
-

?#define CONFIG_SYS_NO_FLASH
?
?#define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be
populated */

include/configs/am43xx_evm.h +0 -0

index 0467953566c6..518b904807be 100644
@@ -11,7 +11,6 @@

?
?#define CONFIG_BOARD_LATE_INIT
?#define CONFIG_ARCH_CPU_INIT
-#define CONFIG_SYS_CACHELINE_SIZE???????32
?#define CONFIG_MAX_RAM_BANK_SIZE (1024 << 21) /* 2GB */
?#define CONFIG_SYS_TIMERBASE 0x48040000 /* Use Timer2
*/
?

include/configs/am43xx_evm.h +0 -0

@@ -49,7 +48,6 @@

?/* Enabling L2 Cache */
?#define CONFIG_SYS_L2_PL310
?#define CONFIG_SYS_PL310_BASE 0x48242000
-#define CONFIG_SYS_CACHELINE_SIZE 32
?
?/*
? * Since SPL did pll and ddr initialization for us,

include/configs/at91- renamed from include/configs/at91-sama5_common.h +0 -0

sama5_common.h
index 9257c5f02923..051186d4bbb4 100644

include/configs/at91-sama5_common.h +0 -0

@@ -12,8 +12,6 @@

?
?#include <asm/hardware.h>
?

include/configs/at91-sama5_common.h +0 -2

-#define CONFIG_SYS_CACHELINE_SIZE	32
-

?#define CONFIG_SYS_TEXT_BASE 0x26f00000
?
?/* ARM asynchronous clock */

include/configs/bcm23550_w1d.h +0 -0

index 770dd872f977..b9688014cd2e 100644
@@ -127,7 +127,6 @@

?/* Commands */
?#define CONFIG_FAT_WRITE
?
-#define CONFIG_SYS_CACHELINE_SIZE 64
?#undef CONFIG_USB_GADGET_VBUS_DRAW
?#define CONFIG_USB_GADGET_VBUS_DRAW 0
?#define CONFIG_USBID_ADDR 0x34052c46

include/configs/bcm28155_ap.h +0 -0

index df0b2bac39d8..f38f08135569 100644
@@ -126,7 +126,6 @@

?/* Commands */
?#define CONFIG_FAT_WRITE
?
-#define CONFIG_SYS_CACHELINE_SIZE 64
?#define CONFIG_USBID_ADDR 0x34052c46
?
?#endif /* __BCM28155_AP_H */

include/configs/bcm_ep_board.h +0 -0

index 50cd7430b59b..b5e502921783 100644
@@ -11,8 +11,6 @@

?
?#define CONFIG_SKIP_LOWLEVEL_INIT
?

include/configs/bcm_ep_board.h +0 -2

-#define CONFIG_SYS_CACHELINE_SIZE	64
-

?/*
? * Memory configuration
? * (these must be defined elsewhere)

include/configs/bur_am335x_common.h +0 -0

index a94b1e271155..04da877db5f7 100644
@@ -15,7 +15,6 @@

?#define CONFIG_AM33XX
?#define CONFIG_OMAP
?#define CONFIG_OMAP_COMMON
-#define CONFIG_SYS_CACHELINE_SIZE 64
?#define CONFIG_MAX_RAM_BANK_SIZE (1024 << 20) /* 1GB */
?
?/* Timer information */

include/configs/cm_t3517.h +0 -0

index ea9983bc7d43..a89ccb73b178 100644
@@ -10,8 +10,6 @@

?#ifndef __CONFIG_H
?#define __CONFIG_H
?

include/configs/cm_t3517.h +0 -2

-#define CONFIG_SYS_CACHELINE_SIZE	64
-

?/*
? * High Level Configuration Options
? */

include/configs/cm_t3517.h +0 -0

@@ -30,7 +28,6 @@

? * Although the default iss 64, we still define it ? * to be on the safe side once the default is changed. ? */
-#define CONFIG_SYS_CACHELINE_SIZE 64
?
?#define CONFIG_EMIF4 /* The chip has EMIF4 controller */
?

include/configs/cm_t43.h +0 -0

index 5d94f133cba9..b896d4d79a4a 100644
@@ -79,7 +79,6 @@

?/* Enabling L2 Cache */
?#define CONFIG_SYS_L2_PL310
?#define CONFIG_SYS_PL310_BASE 0x48242000
-#define CONFIG_SYS_CACHELINE_SIZE 32
?
?/*
? * Since SPL did pll and ddr initialization for us,

include/configs/colibri_vf.h +0 -0

index 58925952dddf..fb68e598b233 100644
@@ -12,8 +12,6 @@

?#ifndef __CONFIG_H
?#define __CONFIG_H
?

include/configs/colibri_vf.h +0 -2

-#define CONFIG_SYS_CACHELINE_SIZE	32
-

?#include <asm/arch/imx-regs.h>
?
?#define CONFIG_VF610

include/configs/colibri_vf.h +0 -0

@@ -207,8 +205,6 @@

?
?#define CONFIG_SYS_NO_FLASH
?

include/configs/colibri_vf.h +0 -2

-#define CONFIG_SYS_CACHELINE_SIZE 32
-

?/* USB Host Support */
?#define CONFIG_USB_EHCI
?#define CONFIG_USB_EHCI_VF

include/configs/corvus.h +0 -0

index 28ea15b596ac..746475d45fec 100644
@@ -118,7 +118,6 @@
 ?#define CONFIG_SYS_DFU_DATA_BUF_SIZE	(SZ_1M)

?#define DFU_MANIFEST_POLL_TIMEOUT 25000
?
-#define CONFIG_SYS_CACHELINE_SIZE SZ_8K
?#define CONFIG_SYS_LOAD_ADDR ATMEL_BASE_CS6
?
?/* bootstrap + u-boot + env in nandflash */

include/configs/dragonboard410c.h +0 -0

index 1dbe2194f86c..cc7ab8365d1e 100644
@@ -27,8 +27,6 @@
 ?#define CONFIG_SYS_LOAD_ADDR		(CONFIG_SYS_SDRAM_BASE + 0x80000)

?#define CONFIG_SYS_BOOTM_LEN 0x1000000 /* 16MB max kernel size
*/
?

include/configs/dragonboard410c.h +0 -2

-#define CONFIG_SYS_CACHELINE_SIZE	64
-

?/* UART */
?#define CONFIG_BAUDRATE 115200
?

include/configs/exynos4- renamed from include/configs/exynos4-common.h +0 -0

common.h
index fbe0fa969d6e..fdbaf027ac47 100644

include/configs/exynos4-common.h +0 -0

@@ -15,7 +15,6 @@

?
?#define CONFIG_BOARD_COMMON
?
-#define CONFIG_SYS_CACHELINE_SIZE 32
?#define CONFIG_REVISION_TAG
?
?/* SD/MMC configuration */

include/configs/exynos5- renamed from include/configs/exynos5-common.h +0 -0

common.h
index f2ed7982b453..153878732b8e 100644

include/configs/exynos5-common.h +0 -0

@@ -13,7 +13,6 @@

?
?#include "exynos-common.h"
?
-#define CONFIG_SYS_CACHELINE_SIZE 64
?#define CONFIG_EXYNOS_SPL
?
?#ifdef FTRACE

include/configs/flea3.h +0 -0

index 824aca45b647..e84803dfb2b6 100644
@@ -19,7 +19,6 @@

?#define CONFIG_MX35
?
?#define CONFIG_SYS_DCACHE_OFF
-#define CONFIG_SYS_CACHELINE_SIZE 32
?
?#define CONFIG_DISPLAY_CPUINFO
?

include/configs/hikey.h +0 -0

index ffcc4d263070..9cbccd9dc9e9 100644
@@ -21,9 +21,6 @@

?
?#define CONFIG_SUPPORT_RAW_INITRD
?

include/configs/hikey.h +0 -3

-/* MMU Definitions */
-#define CONFIG_SYS_CACHELINE_SIZE	64
-

?#define CONFIG_IDENT_STRING "hikey"
?
?#define CONFIG_BOARD_EARLY_INIT_F

include/configs/kc1.h +0 -0

index b08cf2161db7..8b957996a7b2 100644
@@ -24,7 +24,6 @@

?
?#define CONFIG_SYS_L2_PL310 1
?#define CONFIG_SYS_PL310_BASE 0x48242000
-#define CONFIG_SYS_CACHELINE_SIZE 32
?
?/*
? * Platform

include/configs/kzm9g.h +0 -0

index 94f351615940..a4b296ab8ffa 100644
@@ -10,8 +10,6 @@

?
?#undef DEBUG
?

include/configs/kzm9g.h +0 -2

-#define CONFIG_SYS_CACHELINE_SIZE	32
-

?#define CONFIG_SH73A0
?#define CONFIG_KZM_A9_GT
?#define CONFIG_ARCH_RMOBILE_BOARD_STRING "KMC KZM-A9-GT"

include/configs/mcx.h +0 -0

index 0c6e1117d4fd..8387f1920d3a 100644
@@ -25,8 +25,6 @@

?#define CONFIG_MACH_TYPE MACH_TYPE_MCX
?#define CONFIG_BOARD_LATE_INIT
?

include/configs/mcx.h +0 -2

-#define CONFIG_SYS_CACHELINE_SIZE	64
-

?#define CONFIG_EMIF4 /* The chip has EMIF4 controller */
?
?#include <asm/arch/cpu.h> /* get chip and board defs */

include/configs/meson-gxbb- renamed from include/configs/meson-gxbb-common.h +0 -0

common.h
index eaf6a9c08a4c..3bba2e6658ca 100644

include/configs/meson-gxbb-common.h +0 -0

@@ -10,7 +10,6 @@

?
?#define CONFIG_CPU_ARMV8
?#define CONFIG_REMAKE_ELF
-#define CONFIG_SYS_CACHELINE_SIZE 64
?#define CONFIG_SYS_NO_FLASH
?#define CONFIG_NR_DRAM_BANKS 1
?#define CONFIG_ENV_IS_NOWHERE 1

include/configs/nokia_rx51.h +0 -0

index cd154a4bbb30..cdae54425341 100644
@@ -19,8 +19,6 @@

?#ifndef __CONFIG_H
?#define __CONFIG_H
?

include/configs/nokia_rx51.h +0 -2

-#define CONFIG_SYS_CACHELINE_SIZE 64
-

?/*
? * High Level Configuration Options
? */

include/configs/omap3_beagle.h +0 -0

index 4dbe2b62d14b..fc5de034fe34 100644
@@ -275,8 +275,6 @@

?
?#define CONFIG_OMAP3_SPI
?

include/configs/omap3_beagle.h +0 -2

-#define CONFIG_SYS_CACHELINE_SIZE	64
-

?/* Defines for SPL */
?#define CONFIG_SPL_OMAP3_ID_NAND
?

include/configs/omap3_cairo.h +0 -0

index 82e0d5000ca9..4310bada485a 100644
@@ -192,8 +192,6 @@

?
?#define CONFIG_OMAP3_SPI
?

include/configs/omap3_cairo.h +0 -2

-#define CONFIG_SYS_CACHELINE_SIZE	64
-

?/* Defines for SPL */
?#define CONFIG_SPL_OMAP3_ID_NAND
?

include/configs/omap3_evm.h +0 -0

index 52a24d37b882..e87b4c0118b7 100644
@@ -340,8 +340,6 @@

?/* Uncomment to define the board revision statically */
?/* #define CONFIG_STATIC_BOARD_REV OMAP3EVM_BOARD_GEN_2 */
?

include/configs/omap3_evm.h +0 -2

-#define CONFIG_SYS_CACHELINE_SIZE	64
-

?/* Defines for SPL */
?#define CONFIG_SPL_FRAMEWORK
?#define CONFIG_SPL_TEXT_BASE 0x40200800

include/configs/omap3_logic.h +0 -0

index 49a8b3f5ef43..05a43610e524 100644
@@ -82,7 +82,6 @@

?#define CONFIG_ANDROID_BOOT_IMAGE
?#define CONFIG_FASTBOOT_BUF_ADDR CONFIG_SYS_LOAD_ADDR
?#define CONFIG_FASTBOOT_BUF_SIZE 0x07000000
-#define CONFIG_SYS_CACHELINE_SIZE 64
?
?/* TWL4030 */
?#define CONFIG_TWL4030_PWM

include/configs/omap3_overo.h +0 -0

index fbd0c2a07085..618a546dedbe 100644
@@ -215,7 +215,6 @@

?/* Initial RAM setup */
?#define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800
?#define CONFIG_SYS_INIT_RAM_SIZE 0x800
-#define CONFIG_SYS_CACHELINE_SIZE 64
?
?/* NAND boot config */
?#define CONFIG_SYS_NAND_BUSWIDTH_16BIT

include/configs/omap3_pandora.h +0 -0

index 380ec129cda2..9e7bd88adb00 100644
@@ -119,6 +119,4 @@

?#define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET
?#define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET
?

include/configs/omap3_pandora.h +0 -2

-#define CONFIG_SYS_CACHELINE_SIZE	64
-

?#endif /* __CONFIG_H */

include/configs/omap3_zoom1.h +0 -0

index 99d9fc3b2569..639705194813 100644
@@ -176,8 +176,6 @@

?#define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET
?#define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET
?

include/configs/omap3_zoom1.h +0 -2

-#define CONFIG_SYS_CACHELINE_SIZE	64
-

?#ifdef CONFIG_CMD_NET
?/* Ethernet (LAN9211 from SMSC9118 family) */
?#define CONFIG_SMC911X

include/configs/pcm052.h +0 -0

index 74e22db15121..57a76306e248 100644
@@ -9,8 +9,6 @@

?#ifndef __CONFIG_H
?#define __CONFIG_H
?

include/configs/pcm052.h +0 -2

-#define CONFIG_SYS_CACHELINE_SIZE	32
-

?#include <asm/arch/imx-regs.h>
?
?#define CONFIG_VF610

include/configs/rcar-gen2- renamed from include/configs/rcar-gen2-common.h +0 -0

common.h
index 80313fc8c571..8f91e8e00129 100644

include/configs/rcar-gen2-common.h +0 -0

@@ -9,8 +9,6 @@

?#ifndef __RCAR_GEN2_COMMON_H
?#define __RCAR_GEN2_COMMON_H
?

include/configs/rcar-gen2-common.h +0 -2

-#define CONFIG_SYS_CACHELINE_SIZE 64
-

?#include <asm/arch/rmobile.h>
?
?#define CONFIG_CMD_DFL

include/configs/rk3036_common.h +0 -0

index 21d468354bec..101a3ed5bd73 100644
@@ -6,8 +6,6 @@

?#ifndef __CONFIG_RK3036_COMMON_H
?#define __CONFIG_RK3036_COMMON_H
?

include/configs/rk3036_common.h +0 -2

-#define CONFIG_SYS_CACHELINE_SIZE	64
-

?#include <asm/arch/hardware.h>
?
?#define CONFIG_SYS_NO_FLASH

include/configs/rk3288_common.h +0 -0

index d3d4c680e99c..601186c5c1e9 100644
@@ -7,8 +7,6 @@

?#ifndef __CONFIG_RK3288_COMMON_H
?#define __CONFIG_RK3288_COMMON_H
?

include/configs/rk3288_common.h +0 -2

-#define CONFIG_SYS_CACHELINE_SIZE	64
-

?#include <asm/arch/hardware.h>
?
?#define CONFIG_SYS_NO_FLASH

include/configs/rk3399_common.h +0 -0

index 6875308e11b2..e9626a5e398b 100644
@@ -7,8 +7,6 @@

?#ifndef __CONFIG_RK3399_COMMON_H
?#define __CONFIG_RK3399_COMMON_H
?

include/configs/rk3399_common.h +0 -2

-#define CONFIG_SYS_CACHELINE_SIZE	64
-

?#define CONFIG_SYS_NO_FLASH
?#define CONFIG_NR_DRAM_BANKS 1
?#define CONFIG_ENV_SIZE 0x2000

include/configs/rpi.h +0 -0

index dbbb81efa99f..752cc319fceb 100644
@@ -14,12 +14,6 @@

?#define CONFIG_SKIP_LOWLEVEL_INIT
?#endif
?

include/configs/rpi.h +0 -6

-#ifdef CONFIG_BCM2835
-#define CONFIG_SYS_CACHELINE_SIZE		32
-#else
-#define CONFIG_SYS_CACHELINE_SIZE		64
-#endif
-

?/* Architecture, CPU, etc.*/
?#define CONFIG_ARCH_CPU_INIT
?

include/configs/s5p_goni.h +0 -0

index 87e51d0aa9a2..61c5663c4082 100644
@@ -17,8 +17,6 @@

?#define CONFIG_S5PC110 1 /* which is in a S5PC110 */
?#define CONFIG_MACH_GONI 1 /* working with Goni */
?

include/configs/s5p_goni.h +0 -2

-#define CONFIG_SYS_CACHELINE_SIZE	64
-

?#include <linux/sizes.h>
?#include <asm/arch/cpu.h> /* get chip and board defs */
?

include/configs/s5p_goni.h +0 -0

@@ -236,8 +234,6 @@

?
?#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_LOAD_ADDR - 0x1000000)
?

include/configs/s5p_goni.h +0 -2

-#define CONFIG_SYS_CACHELINE_SIZE???????64
-

?#define CONFIG_POWER
?#define CONFIG_POWER_I2C
?#define CONFIG_POWER_MAX8998

include/configs/siemens- renamed from include/configs/siemens-am33x-common.h +0 -0

am33x-common.h
index eab665c2866b..3d25e3db3e6b 100644

include/configs/siemens-am33x-common.h +0 -0

@@ -36,8 +36,6 @@

?#define CONFIG_SETUP_MEMORY_TAGS
?#define CONFIG_INITRD_TAG
?

include/configs/siemens-am33x-common.h +0 -2

-#define CONFIG_SYS_CACHELINE_SIZE???????64
-

?/* commands to include */
?
?#define CONFIG_ENV_VARS_UBOOT_CONFIG

include/configs/smartweb.h +0 -0

index 076a5ce2992f..8ad8f24cc91e 100644
@@ -170,8 +170,6 @@

?#define CONFIG_DFU_NAND
?#define CONFIG_SYS_DFU_DATA_BUF_SIZE SZ_1M
?#define DFU_MANIFEST_POLL_TIMEOUT 25000

include/configs/smartweb.h +0 -2

-
-#define CONFIG_SYS_CACHELINE_SIZE	0x2000

?#endif
?
?/* General Boot Parameter */

include/configs/smdkc100.h +0 -0

index 84a188af3a6e..9d52689b80fd 100644
@@ -12,8 +12,6 @@

?#ifndef __CONFIG_H
?#define __CONFIG_H
?

include/configs/smdkc100.h +0 -2

-#define CONFIG_SYS_CACHELINE_SIZE	64
-

?/*
? * High Level Configuration Options
? * (easy to change)

include/configs/sniper.h +0 -0

index fb348a5cd26e..e2f5e60b2aa5 100644
@@ -16,8 +16,6 @@

? * CPU
? */
?

include/configs/sniper.h +0 -2

-#define CONFIG_SYS_CACHELINE_SIZE	64
-

?#define CONFIG_ARM_ARCH_CP15_ERRATA
?#define CONFIG_ARM_ERRATA_454179
?#define CONFIG_ARM_ERRATA_430973

include/configs/socfpga_common.h +0 -0

index f654f945bc11..ce5781b80652 100644
@@ -75,7 +75,6 @@

?/*
? * Cache
? */
-#define CONFIG_SYS_CACHELINE_SIZE 32
?#define CONFIG_SYS_L2_PL310
?#define CONFIG_SYS_PL310_BASE SOCFPGA_MPUL2_ADDRESS
?

include/configs/sunxi-common.h +0 -0

index b9aa62b2af68..f64edd4b0fe0 100644
@@ -55,7 +55,6 @@

?
?/* CPU */
?#define CONFIG_DISPLAY_CPUINFO
-#define CONFIG_SYS_CACHELINE_SIZE 64
?#define CONFIG_TIMER_CLK_FREQ 24000000
?
?/*

include/configs/tam3517- renamed from include/configs/tam3517-common.h +0 -0

common.h
index 73ff416aed2a..521306509599 100644

include/configs/tam3517-common.h +0 -0

@@ -23,8 +23,6 @@

?
?#define CONFIG_SYS_TEXT_BASE 0x80008000
?

include/configs/tam3517-common.h +0 -2

-#define CONFIG_SYS_CACHELINE_SIZE	64
-

?#define CONFIG_EMIF4 /* The chip has EMIF4 controller */
?
?#include <asm/arch/cpu.h> /* get chip and board defs */

include/configs/tao3530.h +0 -0

index 6616d7396e74..52bd8370a032 100644
@@ -13,8 +13,6 @@

?#ifndef __CONFIG_H
?#define __CONFIG_H
?

include/configs/tao3530.h +0 -2

-#define CONFIG_SYS_CACHELINE_SIZE	64
-

?/*
? * High Level Configuration Options
? */

include/configs/taurus.h +0 -0

index 2d091db07d97..513e6552548a 100644
@@ -133,8 +133,6 @@

?#define CONFIG_DFU_NAND
?#define CONFIG_SYS_DFU_DATA_BUF_SIZE (SZ_1M)
?#define DFU_MANIFEST_POLL_TIMEOUT 25000

include/configs/taurus.h +0 -2

-
-#define CONFIG_SYS_CACHELINE_SIZE	SZ_8K

?#endif
?
?/* SPI EEPROM */

include/configs/tegra114- renamed from include/configs/tegra114-common.h +0 -0

common.h
index 21454d47cb5f..107a0f880331 100644

include/configs/tegra114-common.h +0 -0

@@ -8,9 +8,6 @@

?#define _TEGRA114_COMMON_H_
?#include "tegra-common.h"
?

include/configs/tegra114-common.h +0 -3

-/* Cortex-A15 uses a cache line size of 64 bytes */
-#define CONFIG_SYS_CACHELINE_SIZE	64
-

?/*
? * NS16550 Configuration
? */

include/configs/tegra124- renamed from include/configs/tegra124-common.h +0 -0

common.h
index 39e74f023fda..8cf9bac15680 100644

include/configs/tegra124-common.h +0 -0

@@ -10,9 +10,6 @@

?
?#include "tegra-common.h"
?

include/configs/tegra124-common.h +0 -3

-/* Cortex-A15 uses a cache line size of 64 bytes */
-#define CONFIG_SYS_CACHELINE_SIZE	64
-

?/*
? * NS16550 Configuration
? */

include/configs/tegra186- renamed from include/configs/tegra186-common.h +0 -0

common.h
index aa7b9d038a7e..98e4fc2d252b 100644

include/configs/tegra186-common.h +0 -0

@@ -9,9 +9,6 @@

?
?#include "tegra-common.h"
?

include/configs/tegra186-common.h +0 -3

-/* Cortex-A57 uses a cache line size of 64 bytes */
-#define CONFIG_SYS_CACHELINE_SIZE	64
-

?/*
? * NS16550 Configuration
? */

include/configs/tegra20- renamed from include/configs/tegra20-common.h +0 -0

common.h
index 00e85c48c41b..793310ff473d 100644

include/configs/tegra20-common.h +0 -0

@@ -9,9 +9,6 @@

?#define _TEGRA20_COMMON_H_
?#include "tegra-common.h"
?

include/configs/tegra20-common.h +0 -3

-/* Cortex-A9 uses a cache line size of 32 bytes */
-#define CONFIG_SYS_CACHELINE_SIZE	32
-

?/*
? * Errata configuration
? */

include/configs/tegra210- renamed from include/configs/tegra210-common.h +0 -0

common.h
index 8f35a7bf3dc6..874fe34d4f4d 100644

include/configs/tegra210-common.h +0 -0

@@ -10,9 +10,6 @@

?
?#include "tegra-common.h"
?

include/configs/tegra210-common.h +0 -3

-/* Cortex-A57 uses a cache line size of 64 bytes */
-#define CONFIG_SYS_CACHELINE_SIZE	64
-

?/*
? * NS16550 Configuration
? */

include/configs/tegra30- renamed from include/configs/tegra30-common.h +0 -0

common.h
index 9afd86484bb2..baf3d00f34ba 100644

include/configs/tegra30-common.h +0 -0

@@ -9,9 +9,6 @@

?#define _TEGRA30_COMMON_H_
?#include "tegra-common.h"
?

include/configs/tegra30-common.h +0 -3

-/* Cortex-A9 uses a cache line size of 32 bytes */
-#define CONFIG_SYS_CACHELINE_SIZE	32
-

?/*
? * Errata configuration
? */

include/configs/ti814x_evm.h +0 -0

index 3c058832e176..732854eb306e 100644
@@ -16,8 +16,6 @@

?#ifndef __CONFIG_TI814X_EVM_H
?#define __CONFIG_TI814X_EVM_H
?

include/configs/ti814x_evm.h +0 -2

-#define CONFIG_SYS_CACHELINE_SIZE	64
-

?#define CONFIG_TI81XX
?#define CONFIG_TI814X
?#define CONFIG_SYS_NO_FLASH

include/configs/ti816x_evm.h +0 -0

index 05fd00fd5d27..17f12a898a8d 100644
@@ -10,8 +10,6 @@

?#ifndef __CONFIG_TI816X_EVM_H
?#define __CONFIG_TI816X_EVM_H
?

include/configs/ti816x_evm.h +0 -2

-#define CONFIG_SYS_CACHELINE_SIZE	64
-

?#define CONFIG_TI81XX
?#define CONFIG_TI816X
?#define CONFIG_SYS_NO_FLASH

include/configs/ti_am335x_common.h +0 -0

index bcd56fc08dc1..a9b10d053297 100644
@@ -14,7 +14,6 @@

?
?#define CONFIG_AM33XX
?#define CONFIG_ARCH_CPU_INIT
-#define CONFIG_SYS_CACHELINE_SIZE???????64
?#define CONFIG_MAX_RAM_BANK_SIZE (1024 << 20) /* 1GB */
?#define CONFIG_SYS_TIMERBASE 0x48040000 /* Use Timer2
*/
?#define CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC

include/configs/ti_armv7_keystone2.h +0 -0

index 4aa262e1a871..c830c0c0bf68 100644
@@ -200,7 +200,6 @@

?#define CONFIG_USB_STORAGE
?#define CONFIG_EFI_PARTITION
?#define CONFIG_FS_FAT
-#define CONFIG_SYS_CACHELINE_SIZE 64
?#define CONFIG_USB_SS_BASE KS2_USB_SS_BASE
?#define CONFIG_USB_HOST_XHCI_BASE KS2_USB_HOST_XHCI_BASE
?#define CONFIG_DEV_USB_PHY_BASE KS2_DEV_USB_PHY_BASE

include/configs/ti_omap3_common.h +0 -0

index 32877d1964de..c54b7b55c4f4 100644
@@ -18,8 +18,6 @@

? * High Level Configuration Options
? */
?

include/configs/ti_omap3_common.h +0 -2

-#define CONFIG_SYS_CACHELINE_SIZE	64
-

?#include <asm/arch/cpu.h>
?#include <asm/arch/omap.h>
?

include/configs/ti_omap4_common.h +0 -0

index 5fad3c1242c5..e6e88c528252 100644
@@ -26,7 +26,6 @@

?#define CONFIG_SYS_L2_PL310 1
?#define CONFIG_SYS_PL310_BASE 0x48242000
?#endif
-#define CONFIG_SYS_CACHELINE_SIZE 32
?
?/* Get CPU defs */
?#include <asm/arch/cpu.h>

include/configs/ti_omap5_common.h +0 -0

index 3589cdc3a88e..e42c88e3b928 100644
@@ -23,8 +23,6 @@

?/* Common ARM Erratas */
?#define CONFIG_ARM_ERRATA_798870
?

include/configs/ti_omap5_common.h +0 -2

-#define CONFIG_SYS_CACHELINE_SIZE	64
-

?/* Use General purpose timer 1 */
?#define CONFIG_SYS_TIMERBASE GPT2_BASE
?

include/configs/tricorder.h +0 -0

index 127a9689482f..ae0e89c59456 100644
@@ -16,8 +16,6 @@

?#ifndef __CONFIG_H
?#define __CONFIG_H
?

include/configs/tricorder.h +0 -2

-#define CONFIG_SYS_CACHELINE_SIZE	64
-

?/* High Level Configuration Options */
?#define CONFIG_SYS_THUMB_BUILD
?#define CONFIG_OMAP /* in a TI OMAP core */

include/configs/uniphier.h +0 -0

index 0f5b20ff48c4..f41a0b1cad6a 100644
@@ -30,12 +30,6 @@

?/* #define CONFIG_SYS_ICACHE_OFF */
?/* #define CONFIG_SYS_DCACHE_OFF */
?

include/configs/uniphier.h +0 -6

-#ifdef CONFIG_CACHE_UNIPHIER
-#define CONFIG_SYS_CACHELINE_SIZE	128
-#else
-#define CONFIG_SYS_CACHELINE_SIZE	32
-#endif
-

?#define CONFIG_DISPLAY_CPUINFO
?#define CONFIG_DISPLAY_BOARDINFO
?#define CONFIG_MISC_INIT_F

include/configs/vexpress_aemv8a.h +0 -0

index 9aca3936fb13..71c4a1f08d62 100644
@@ -19,9 +19,6 @@

?
?#define CONFIG_SUPPORT_RAW_INITRD
?

include/configs/vexpress_aemv8a.h +0 -3

-/* MMU Definitions */
-#define CONFIG_SYS_CACHELINE_SIZE	64
-

?#define CONFIG_IDENT_STRING " vexpress_aemv8a"
?
?/* Link Definitions */

include/configs/vexpress_common.h +0 -0

index 51898e623cbf..a8eba314e30d 100644
@@ -118,8 +118,6 @@

?#define CONFIG_SYS_MEMTEST_START V2M_BASE
?#define CONFIG_SYS_MEMTEST_END 0x20000000
?

include/configs/vexpress_common.h +0 -2

-#define CONFIG_SYS_CACHELINE_SIZE	64
-

?#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs
*/
?#define CONFIG_SETUP_MEMORY_TAGS 1
?#define CONFIG_SYS_L2CACHE_OFF 1

include/configs/vf610twr.h +0 -0

index c4a1fd091ab6..33f966ac6e47 100644
@@ -9,8 +9,6 @@

?#ifndef __CONFIG_H
?#define __CONFIG_H
?

include/configs/vf610twr.h +0 -2

-#define CONFIG_SYS_CACHELINE_SIZE	32
-

?#include <asm/arch/imx-regs.h>
?
?#define CONFIG_VF610

include/configs/woodburn_common.h +0 -0

index 153466a623ff..de6b1838d765 100644
@@ -19,7 +19,6 @@

?#define CONFIG_SYS_FSL_CLK
?
?#define CONFIG_SYS_DCACHE_OFF
-#define CONFIG_SYS_CACHELINE_SIZE 32
?
?#define CONFIG_DISPLAY_CPUINFO
?

include/configs/xilinx_zynqmp.h +0 -0

index ca60e5d3d9cd..02f0e4c9a9a8 100644
@@ -34,9 +34,6 @@

?/* Have release address at the end of 256MB for now */
?#define CPU_RELEASE_ADDR 0xFFFFFF0
?

include/configs/xilinx_zynqmp.h +0 -3

-/* Cache Definitions */
-#define CONFIG_SYS_CACHELINE_SIZE	64
-

?#if !defined(CONFIG_IDENT_STRING)
?# define CONFIG_IDENT_STRING " Xilinx ZynqMP"
?#endif

include/configs/zynq-common.h +0 -0

index e59e412d58a6..5f7fefde3d56 100644
@@ -16,8 +16,6 @@

?#endif
?
?/* Cache options */

include/configs/zynq-common.h +0 -2

-#define CONFIG_SYS_CACHELINE_SIZE	32
-

?#define CONFIG_SYS_L2CACHE_OFF
?#ifndef CONFIG_SYS_L2CACHE_OFF
?# define CONFIG_SYS_L2_PL310

Use a tab not 8 spaces.

Signed-off-by Tom Rini <[email protected]>