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arm: mvebu: theadorable: Configure board for PCIe 2.0 capability

PATCH New Stefan Roese 2 participants 2 messages Aug 25, 2016 – Sep 24, 2016

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Stefan Roese

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PATCH 1/1 arm: mvebu: theadorable: Configure board for PCIe 2.0 capability

Use a board-specific board_sat_r_get() function to configure the board for PCIe 2.0 capability (e.g. 5GB/s link speed). Otherwise the default of 2.5GB/s will be established.

Signed-off-by Stefan Roese <[email protected]>
---
 board/theadorable/theadorable.c | 6 ++++++
 1 file changed, 6 insertions(+)
board/theadorable/theadorable.c +6 -0
index 9c0f120..4be7b61 100644
@@ -126,6 +126,12 @@ MV_BIN_SERDES_CFG *board_serdes_cfg_get(u8 pex_mode)
 	return &theadorable_serdes_cfg[0];
 }
 
+u8 board_sat_r_get(u8 dev_num, u8 reg)
+{
+	/* Bit 0 enables PCI 2.0 link capabilities instead of PCI 1.x */
+	return 0x01;
+}
+
 int board_early_init_f(void)
 {
 	/* Configure MPP */
Signature · 1 line
2.9.3
#1 lore raw

PATCH 1/1 arm: mvebu: theadorable: Configure board for PCIe 2.0 capability

Quoted 5 lines · Stefan Roese

Use a board-specific board_sat_r_get() function to configure the board for PCIe 2.0 capability (e.g. 5GB/s link speed). Otherwise the default of 2.5GB/s will be established.

Signed-off-by Stefan Roese <[email protected]>

Applied to u-boot-marvell/master

Thanks,
Stefan