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arm: l2x0: add PMU support

PATCH Superseded Mark Rutland 3 participants 4 messages Aug 31, 2016 – Sep 2, 2016

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Arm (32-bit) CPU hotplug
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Mark Rutland

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PATCH v4 1/1 arm: l2x0: add PMU support

The L2C-220 (AKA L220) and L2C-310 (AKA PL310) cache controllers feature a Performance Monitoring Unit (PMU), which can be useful for tuning and/or debugging. This hardware is always present and the relevant registers are accessible to non-secure accesses. Thus, no special firmware interface is necessary.

This patch adds support for the PMU, plugging into the usual perf infrastructure. The overflow interrupt is not always available (e.g. on RealView PBX A9 it is not wired up at all), and the hardware counters saturate, so the driver does not make use of this. Instead, the driver periodically polls and reset counters as required to avoid losing events due to saturation.

Signed-off-by Mark Rutland <[email protected]>
Acked-by Pawel Moll <[email protected]>
Cc Kim Phillips <[email protected]>
Cc Russell King <[email protected]>
Cc Will Deacon <[email protected]>
---
 arch/arm/include/asm/hardware/cache-l2x0.h |  19 +
 arch/arm/mm/Kconfig                        |   7 +
 arch/arm/mm/Makefile                       |   1 +
 arch/arm/mm/cache-l2x0-pmu.c               | 584 +++++++++++++++++++++++++++++
 arch/arm/mm/cache-l2x0.c                   |   6 +
 include/linux/cpuhotplug.h                 |   1 +
 6 files changed, 618 insertions(+)
 create mode 100644 arch/arm/mm/cache-l2x0-pmu.c

Since v1 [1]:
* Use relaxed IO accessors, per Russell's comment. From testing, this can save 3% overhead in an extreme case (idle system and trivial workload).
* Add Kim's Tested-by.

Since v2 [2]:
* Trivial rebase to v4.8-rc4.
* Add Pawel's Acked-by.
* Fix l2x0_pmu_num_active_counters return type, per Will's comment.
* Update comment regarding L210 support, per Will's comment.

Since v3 [3]:
* Split PMU driver into separate file, per Russell's comments.
* Dropped Kim's Tested-by, due to changes in structure and probing.

[1] http://lists.infradead.org/pipermail/linux-arm-kernel/2016-August/449622.html
[2] http://lists.infradead.org/pipermail/linux-arm-kernel/2016-August/450024.html
[3] http://lists.infradead.org/pipermail/linux-arm-kernel/2016-August/452432.html

arch/arm/include/asm/hardware/cache-l2x0.h +19 -0
index 3a5ec1c..736292b 100644
@@ -87,6 +87,15 @@
 #define L310_CACHE_ID_RTL_R3P2		0x08
 #define L310_CACHE_ID_RTL_R3P3		0x09
 
+#define L2X0_EVENT_CNT_CTRL_ENABLE	BIT(0)
+
+#define L2X0_EVENT_CNT_CFG_SRC_SHIFT	2
+#define L2X0_EVENT_CNT_CFG_SRC_MASK	0xf
+#define L2X0_EVENT_CNT_CFG_SRC_DISABLED	0
+#define L2X0_EVENT_CNT_CFG_INT_DISABLED	0
+#define L2X0_EVENT_CNT_CFG_INT_INCR	1
+#define L2X0_EVENT_CNT_CFG_INT_OVERFLOW	2
+
 /* L2C auxiliary control register - bits common to L2C-210/220/310 */
 #define L2C_AUX_CTRL_WAY_SIZE_SHIFT		17
 #define L2C_AUX_CTRL_WAY_SIZE_MASK		(7 << 17)

@@ -157,6 +166,16 @@ static inline int l2x0_of_init(u32 aux_val, u32 aux_mask)
 }
 #endif
 
+#ifdef CONFIG_CACHE_L2X0_PMU
+void l2x0_pmu_register(void __iomem *base, u32 part);
+void l2x0_pmu_suspend(void);
+void l2x0_pmu_resume(void);
+#else
+static inline void l2x0_pmu_register(void __iomem *base, u32 part) {}
+static inline void l2x0_pmu_suspend(void) {}
+static inline void l2x0_pmu_resume(void) {}
+#endif
+
 struct l2x0_regs {
 	unsigned long phy_base;
 	unsigned long aux_ctrl;
arch/arm/mm/Kconfig +7 -0
index d15a7fe..0e8cbac 100644
@@ -916,6 +916,13 @@ config CACHE_L2X0
 	help
 	  This option enables the L2x0 PrimeCell.
 
+config CACHE_L2X0_PMU
+	bool "L2x0 performance monitor support" if CACHE_L2X0
+	depends on PERF_EVENTS
+	help
+	  This option enables support for the performance monitoring features
+	  of the L220 and PL310 outer cache controllers.
+
 if CACHE_L2X0
 
 config PL310_ERRATA_588369
arch/arm/mm/Makefile +1 -0
index 7f76d96..8fb95e4 100644
@@ -101,6 +101,7 @@ AFLAGS_proc-v7.o	:=-Wa,-march=armv7-a
 obj-$(CONFIG_OUTER_CACHE)	+= l2c-common.o
 obj-$(CONFIG_CACHE_FEROCEON_L2)	+= cache-feroceon-l2.o
 obj-$(CONFIG_CACHE_L2X0)	+= cache-l2x0.o l2c-l2x0-resume.o
+obj-$(CONFIG_CACHE_L2X0_PMU)	+= cache-l2x0-pmu.o
 obj-$(CONFIG_CACHE_XSC3L2)	+= cache-xsc3l2.o
 obj-$(CONFIG_CACHE_TAUROS2)	+= cache-tauros2.o
 obj-$(CONFIG_CACHE_UNIPHIER)	+= cache-uniphier.o
arch/arm/mm/cache-l2x0-pmu.c new file +584 -0

584 lines not on this page · raw message

arch/arm/mm/cache-l2x0.c +6 -0
index cc12905..a555ac6 100644
@@ -142,6 +142,8 @@ static void l2c_disable(void)
 {
 	void __iomem *base = l2x0_base;
 
+	l2x0_pmu_suspend();
+
 	outer_cache.flush_all();
 	l2c_write_sec(0, base, L2X0_CTRL);
 	dsb(st);

@@ -159,6 +161,8 @@ static void l2c_resume(void)
 	/* Do not touch the controller if already enabled. */
 	if (!(readl_relaxed(base + L2X0_CTRL) & L2X0_CTRL_EN))
 		l2c_enable(base, l2x0_data->num_lock);
+
+	l2x0_pmu_resume();
 }
 
 /*

@@ -892,6 +896,8 @@ static int __init __l2c_init(const struct l2c_init_data *data,
 	pr_info("%s: CACHE_ID 0x%08x, AUX_CTRL 0x%08x\n",
 		data->type, cache_id, aux);
 
+	l2x0_pmu_register(l2x0_base, cache_id);
+
 	return 0;
 }
include/linux/cpuhotplug.h +1 -0
index 242bf53..7e1ba14 100644
@@ -86,6 +86,7 @@ enum cpuhp_state {
 	CPUHP_AP_PERF_S390_SF_ONLINE,
 	CPUHP_AP_PERF_ARM_CCI_ONLINE,
 	CPUHP_AP_PERF_ARM_CCN_ONLINE,
+	CPUHP_AP_PERF_ARM_L2X0_ONLINE,
 	CPUHP_AP_WORKQUEUE_ONLINE,
 	CPUHP_AP_RCUTREE_ONLINE,
 	CPUHP_AP_NOTIFY_ONLINE,
Signature · 1 line
1.9.1
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#1 lore raw

PATCH v4 1/1 arm: l2x0: add PMU support

Quoted 13 lines · Mark Rutland

The L2C-220 (AKA L220) and L2C-310 (AKA PL310) cache controllers feature a Performance Monitoring Unit (PMU), which can be useful for tuning and/or debugging. This hardware is always present and the relevant registers are accessible to non-secure accesses. Thus, no special firmware interface is necessary.

This patch adds support for the PMU, plugging into the usual perf infrastructure. The overflow interrupt is not always available (e.g. on RealView PBX A9 it is not wired up at all), and the hardware counters saturate, so the driver does not make use of this. Instead, the driver periodically polls and reset counters as required to avoid losing events due to saturation.

Quoted 5 lines
Signed-off-by Mark Rutland <[email protected]>
Acked-by Pawel Moll <[email protected]>
Cc Kim Phillips <[email protected]>
Cc Russell King <[email protected]>
Cc Will Deacon <[email protected]>

Much better, thanks. When you're happy, please put it in the patch system, thanks.

Signature · 3 lines
RMK's Patch system: http://www.armlinux.org.uk/developer/patches/
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#2 lore raw

PATCH v4 1/1 arm: l2x0: add PMU support

Quoted 14 lines · On Thu, 1 Sep 2016 16:37:07 +0100 Russell King - ARM Linux…
Quoted 13 lines · Mark Rutland

The L2C-220 (AKA L220) and L2C-310 (AKA PL310) cache controllers feature a Performance Monitoring Unit (PMU), which can be useful for tuning and/or debugging. This hardware is always present and the relevant registers are accessible to non-secure accesses. Thus, no special firmware interface is necessary.

This patch adds support for the PMU, plugging into the usual perf infrastructure. The overflow interrupt is not always available (e.g. on RealView PBX A9 it is not wired up at all), and the hardware counters saturate, so the driver does not make use of this. Instead, the driver periodically polls and reset counters as required to avoid losing events due to saturation.

Quoted 8 lines
Quoted 5 lines
Signed-off-by Mark Rutland <[email protected]>
Acked-by Pawel Moll <[email protected]>
Cc Kim Phillips <[email protected]>
Cc Russell King <[email protected]>
Cc Will Deacon <[email protected]>

Much better, thanks. When you're happy, please put it in the patch system, thanks.

feel free to tack on my:

Tested-by Kim Phillips <[email protected]>

Thanks,

Kim

author
#3 lore raw

PATCH v4 1/1 arm: l2x0: add PMU support

Quoted 23 lines · Kim Phillips
Quoted 20 lines · On Thu, 1 Sep 2016 16:37:07 +0100 Russell King - ARM Linux…
Quoted 18 lines · Mark Rutland

The L2C-220 (AKA L220) and L2C-310 (AKA PL310) cache controllers feature a Performance Monitoring Unit (PMU), which can be useful for tuning and/or debugging. This hardware is always present and the relevant registers are accessible to non-secure accesses. Thus, no special firmware interface is necessary.

This patch adds support for the PMU, plugging into the usual perf infrastructure. The overflow interrupt is not always available (e.g. on RealView PBX A9 it is not wired up at all), and the hardware counters saturate, so the driver does not make use of this. Instead, the driver periodically polls and reset counters as required to avoid losing events due to saturation.

Signed-off-by Mark Rutland <[email protected]>
Acked-by Pawel Moll <[email protected]>
Cc Kim Phillips <[email protected]>
Cc Russell King <[email protected]>
Cc Will Deacon <[email protected]>
Quoted 6 lines
Quoted 2 lines

Much better, thanks. When you're happy, please put it in the patch system, thanks.

feel free to tack on my:

Tested-by Kim Phillips <[email protected]>

Cheers!

I've folded that in, and dropped this in the patch system as 8611/1.

Thanks,
Mark.