Add SDHI to r8a7796/salvator-x
Subsystems (7)
v2 cover Add SDHI to r8a7796/salvator-x
Hi,
this patch set updates drivers, documentation and DT to enable SDHI0 & 3 on the r8a7796/salvator-x. This includes defining nodes for all available SDHI and GPIO devices.
I have boot-tested this which seems successful.
However, I do not have physical access to an r8a7796/salvator-x board and the one that I have remote access to does not appear to have any SD cards present. I would be grateful of any testing anyone can provide.
Based on renesas-drivers-2016-08-09-v4.8-rc1
Provided for testing as the topic/r8a7796-sdhi-v2 branch in my renesas tree on kernel.org.
Changes since v1 noted in individual changelogs.
Acks from v1 also added.
Ai Kyuse (1):
mmc: sh_mobile_sdhi: Add r8a7796 support
Simon Horman (4):
clk: renesas: r8a7796: Add SDIF clocks
gpio: rcar: Add r8a7796 (R-Car M3-W) support
arm64: dts: r8a7796: add SDHI nodes
arm64: dts: r8a7796: salvator-x: enable SDHI0 & 3
Takeshi Kihara (3):
clk: renesas: r8a7796: Add GPIO clocks
pinctrl: sh-pfc: r8a7796: Add SDHI pins, groups and functions
arm64: dts: r8a7796: Add GPIO device nodes
.../devicetree/bindings/gpio/renesas,gpio-rcar.txt | 1 + Documentation/devicetree/bindings/mmc/tmio_mmc.txt | 1 + arch/arm64/boot/dts/renesas/r8a7796-salvator-x.dts | 84 +++++++ arch/arm64/boot/dts/renesas/r8a7796.dtsi | 154 ++++++++++++ drivers/clk/renesas/r8a7796-cpg-mssr.c | 18 ++ drivers/gpio/gpio-rcar.c | 4 + drivers/mmc/host/sh_mobile_sdhi.c | 1 + drivers/pinctrl/sh-pfc/pfc-r8a7796.c | 275 +++++++++++++++++++++ 8 files changed, 538 insertions(+)
Signature · 1 line
2.7.0.rc3.207.g0ac5344
PATCH v2 1/8 clk: renesas: r8a7796: Add GPIO clocks
From: Takeshi Kihara <[email protected]>
Add GPIO clocks for the R8A7796 SoC.
--- drivers/clk/renesas/r8a7796-cpg-mssr.c | 8 ++++++++ 1 file changed, 8 insertions(+)
drivers/clk/renesas/r8a7796-cpg-mssr.c +8 -0
@@ -106,6 +106,14 @@ static const struct mssr_mod_clk r8a7796_mod_clks[] __initconst = {DEF_MOD ("scif2" ,310 ,R8A7796_CLK_S3D4 ),DEF_MOD ("rwdt0" ,402 ,R8A7796_CLK_R ),DEF_MOD ("intc-ap" ,408 ,R8A7796_CLK_S3D1 ), +DEF_MOD ("gpio7" ,905 ,R8A7796_CLK_S3D4 ), +DEF_MOD ("gpio6" ,906 ,R8A7796_CLK_S3D4 ), +DEF_MOD ("gpio5" ,907 ,R8A7796_CLK_S3D4 ), +DEF_MOD ("gpio4" ,908 ,R8A7796_CLK_S3D4 ), +DEF_MOD ("gpio3" ,909 ,R8A7796_CLK_S3D4 ), +DEF_MOD ("gpio2" ,910 ,R8A7796_CLK_S3D4 ), +DEF_MOD ("gpio1" ,911 ,R8A7796_CLK_S3D4 ), + DEF_MOD("gpio0", 912, R8A7796_CLK_S3D4), }; static const unsigned int r8a7796_crit_mod_clks[] __initconst = {
Signature · 1 line
2.7.0.rc3.207.g0ac5344
PATCH v2 2/8 clk: renesas: r8a7796: Add SDIF clocks
In reply to Simon HormanThis patch adds SDIF clocks for R8A7796 SoC.
Based on work by Ai Kyuse and Yoshihiro Shimoda for the r8a7795 SoC.
---
v2
* Add and use SDSRC
--- drivers/clk/renesas/r8a7796-cpg-mssr.c | 10 ++++++++++ 1 file changed, 10 insertions(+)
drivers/clk/renesas/r8a7796-cpg-mssr.c +10 -0
@@ -70,6 +70,7 @@ static const struct cpg_core_clk r8a7796_core_clks[] __initconst = {DEF_FIXED (".s1" ,CLK_S1 ,CLK_PLL1_DIV2 ,3 ,1 ),DEF_FIXED (".s2" ,CLK_S2 ,CLK_PLL1_DIV2 ,4 ,1 ),DEF_FIXED (".s3" ,CLK_S3 ,CLK_PLL1_DIV2 ,6 ,1 ), +DEF_FIXED (".sdsrc" ,CLK_SDSRC ,CLK_PLL1_DIV2 ,2 ,1 ),/* Core Clock Outputs */ DEF_FIXED("ztr", R8A7796_CLK_ZTR, CLK_PLL1_DIV2, 6, 1),
@@ -93,6 +94,11 @@ static const struct cpg_core_clk r8a7796_core_clks[] __initconst = {DEF_FIXED ("s3d2" ,R8A7796_CLK_S3D2 ,CLK_S3 ,2 ,1 ),DEF_FIXED ("s3d4" ,R8A7796_CLK_S3D4 ,CLK_S3 ,4 ,1 ), +DEF_GEN3_SD ("sd0" ,R8A7796_CLK_SD0 ,CLK_SDSRC ,0x0074 ), +DEF_GEN3_SD ("sd1" ,R8A7796_CLK_SD1 ,CLK_SDSRC ,0x0078 ), +DEF_GEN3_SD ("sd2" ,R8A7796_CLK_SD2 ,CLK_SDSRC ,0x0268 ), +DEF_GEN3_SD ("sd3" ,R8A7796_CLK_SD3 ,CLK_SDSRC ,0x026c ), +DEF_FIXED ("cl" ,R8A7796_CLK_CL ,CLK_PLL1_DIV2 ,48 ,1 ), DEF_FIXED("cp", R8A7796_CLK_CP, CLK_EXTAL, 2, 1),
@@ -104,6 +110,10 @@ static const struct cpg_core_clk r8a7796_core_clks[] __initconst = {static const struct mssr_mod_clk r8a7796_mod_clks[]__initconst = {DEF_MOD ("scif2" ,310 ,R8A7796_CLK_S3D4 ), +DEF_MOD ("sdif3" ,311 ,R8A7796_CLK_SD3 ), +DEF_MOD ("sdif2" ,312 ,R8A7796_CLK_SD2 ), +DEF_MOD ("sdif1" ,313 ,R8A7796_CLK_SD1 ), +DEF_MOD ("sdif0" ,314 ,R8A7796_CLK_SD0 ),DEF_MOD ("rwdt0" ,402 ,R8A7796_CLK_R ),DEF_MOD ("intc-ap" ,408 ,R8A7796_CLK_S3D1 ),DEF_MOD ("gpio7" ,905 ,R8A7796_CLK_S3D4 ),
Signature · 1 line
2.7.0.rc3.207.g0ac5344
PATCH v2 3/8 pinctrl: sh-pfc: r8a7796: Add SDHI pins, groups and functions
In reply to Simon HormanFrom: Takeshi Kihara <[email protected]>
This patch adds SDHI pins, groups and functions to R8A7796 SoC.
--- drivers/pinctrl/sh-pfc/pfc-r8a7796.c | 275 +++++++++++++++++++++++++++++++++++ 1 file changed, 275 insertions(+)
drivers/pinctrl/sh-pfc/pfc-r8a7796.c +275 -0
@@ -1684,6 +1684,213 @@ static const unsigned int scif5_clk_b_mux[] = { SCK5_B_MARK, }; +/* - SDHI0 ------------------------------------------------------------------ */ +static const unsigned int sdhi0_data1_pins[] = { +/* D0 */ +RCAR_GP_PIN (3 ,2 ), +}; +static const unsigned int sdhi0_data1_mux[] = { +SD0_DAT0_MARK , +}; +static const unsigned int sdhi0_data4_pins[] = { +/* D[0:3] */ +RCAR_GP_PIN (3 ,2 ),RCAR_GP_PIN (3 ,3 ), +RCAR_GP_PIN (3 ,4 ),RCAR_GP_PIN (3 ,5 ), +}; +static const unsigned int sdhi0_data4_mux[] = { +SD0_DAT0_MARK ,SD0_DAT1_MARK , +SD0_DAT2_MARK ,SD0_DAT3_MARK , +}; +static const unsigned int sdhi0_ctrl_pins[] = { +/* CLK, CMD */ +RCAR_GP_PIN (3 ,0 ),RCAR_GP_PIN (3 ,1 ), +}; +static const unsigned int sdhi0_ctrl_mux[] = { +SD0_CLK_MARK ,SD0_CMD_MARK , +}; +static const unsigned int sdhi0_cd_pins[] = { +/* CD */ +RCAR_GP_PIN (3 ,12 ), +}; +static const unsigned int sdhi0_cd_mux[] = { +SD0_CD_MARK , +}; +static const unsigned int sdhi0_wp_pins[] = { +/* WP */ +RCAR_GP_PIN (3 ,13 ), +}; +static const unsigned int sdhi0_wp_mux[] = { +SD0_WP_MARK , +}; +/* - SDHI1 ------------------------------------------------------------------ */ +static const unsigned int sdhi1_data1_pins[] = { +/* D0 */ +RCAR_GP_PIN (3 ,8 ), +}; +static const unsigned int sdhi1_data1_mux[] = { +SD1_DAT0_MARK , +}; +static const unsigned int sdhi1_data4_pins[] = { +/* D[0:3] */ +RCAR_GP_PIN (3 ,8 ),RCAR_GP_PIN (3 ,9 ), +RCAR_GP_PIN (3 ,10 ),RCAR_GP_PIN (3 ,11 ), +}; +static const unsigned int sdhi1_data4_mux[] = { +SD1_DAT0_MARK ,SD1_DAT1_MARK , +SD1_DAT2_MARK ,SD1_DAT3_MARK , +}; +static const unsigned int sdhi1_ctrl_pins[] = { +/* CLK, CMD */ +RCAR_GP_PIN (3 ,6 ),RCAR_GP_PIN (3 ,7 ), +}; +static const unsigned int sdhi1_ctrl_mux[] = { +SD1_CLK_MARK ,SD1_CMD_MARK , +}; +static const unsigned int sdhi1_cd_pins[] = { +/* CD */ +RCAR_GP_PIN (3 ,14 ), +}; +static const unsigned int sdhi1_cd_mux[] = { +SD1_CD_MARK , +}; +static const unsigned int sdhi1_wp_pins[] = { +/* WP */ +RCAR_GP_PIN (3 ,15 ), +}; +static const unsigned int sdhi1_wp_mux[] = { +SD1_WP_MARK , +}; +/* - SDHI2 ------------------------------------------------------------------ */ +static const unsigned int sdhi2_data1_pins[] = { +/* D0 */ +RCAR_GP_PIN (4 ,2 ), +}; +static const unsigned int sdhi2_data1_mux[] = { +SD2_DAT0_MARK , +}; +static const unsigned int sdhi2_data4_pins[] = { +/* D[0:3] */ +RCAR_GP_PIN (4 ,2 ),RCAR_GP_PIN (4 ,3 ), +RCAR_GP_PIN (4 ,4 ),RCAR_GP_PIN (4 ,5 ), +}; +static const unsigned int sdhi2_data4_mux[] = { +SD2_DAT0_MARK ,SD2_DAT1_MARK , +SD2_DAT2_MARK ,SD2_DAT3_MARK , +}; +static const unsigned int sdhi2_data8_pins[] = { +/* D[0:7] */ +RCAR_GP_PIN (4 ,2 ),RCAR_GP_PIN (4 ,3 ), +RCAR_GP_PIN (4 ,4 ),RCAR_GP_PIN (4 ,5 ), +RCAR_GP_PIN (3 ,8 ),RCAR_GP_PIN (3 ,9 ), +RCAR_GP_PIN (3 ,10 ),RCAR_GP_PIN (3 ,11 ), +}; +static const unsigned int sdhi2_data8_mux[] = { +SD2_DAT0_MARK ,SD2_DAT1_MARK , +SD2_DAT2_MARK ,SD2_DAT3_MARK , +SD2_DAT4_MARK ,SD2_DAT5_MARK , +SD2_DAT6_MARK ,SD2_DAT7_MARK , +}; +static const unsigned int sdhi2_ctrl_pins[] = { +/* CLK, CMD */ +RCAR_GP_PIN (4 ,0 ),RCAR_GP_PIN (4 ,1 ), +}; +static const unsigned int sdhi2_ctrl_mux[] = { +SD2_CLK_MARK ,SD2_CMD_MARK , +}; +static const unsigned int sdhi2_cd_a_pins[] = { +/* CD */ +RCAR_GP_PIN (4 ,13 ), +}; +static const unsigned int sdhi2_cd_a_mux[] = { +SD2_CD_A_MARK , +}; +static const unsigned int sdhi2_cd_b_pins[] = { +/* CD */ +RCAR_GP_PIN (5 ,10 ), +}; +static const unsigned int sdhi2_cd_b_mux[] = { +SD2_CD_B_MARK , +}; +static const unsigned int sdhi2_wp_a_pins[] = { +/* WP */ +RCAR_GP_PIN (4 ,14 ), +}; +static const unsigned int sdhi2_wp_a_mux[] = { +SD2_WP_A_MARK , +}; +static const unsigned int sdhi2_wp_b_pins[] = { +/* WP */ +RCAR_GP_PIN (5 ,11 ), +}; +static const unsigned int sdhi2_wp_b_mux[] = { +SD2_WP_B_MARK , +}; +static const unsigned int sdhi2_ds_pins[] = { +/* DS */ +RCAR_GP_PIN (4 ,6 ), +}; +static const unsigned int sdhi2_ds_mux[] = { +SD2_DS_MARK , +}; +/* - SDHI3 ------------------------------------------------------------------ */ +static const unsigned int sdhi3_data1_pins[] = { +/* D0 */ +RCAR_GP_PIN (4 ,9 ), +}; +static const unsigned int sdhi3_data1_mux[] = { +SD3_DAT0_MARK , +}; +static const unsigned int sdhi3_data4_pins[] = { +/* D[0:3] */ +RCAR_GP_PIN (4 ,9 ),RCAR_GP_PIN (4 ,10 ), +RCAR_GP_PIN (4 ,11 ),RCAR_GP_PIN (4 ,12 ), +}; +static const unsigned int sdhi3_data4_mux[] = { +SD3_DAT0_MARK ,SD3_DAT1_MARK , +SD3_DAT2_MARK ,SD3_DAT3_MARK , +}; +static const unsigned int sdhi3_data8_pins[] = { +/* D[0:7] */ +RCAR_GP_PIN (4 ,9 ),RCAR_GP_PIN (4 ,10 ), +RCAR_GP_PIN (4 ,11 ),RCAR_GP_PIN (4 ,12 ), +RCAR_GP_PIN (4 ,13 ),RCAR_GP_PIN (4 ,14 ), +RCAR_GP_PIN (4 ,15 ),RCAR_GP_PIN (4 ,16 ), +}; +static const unsigned int sdhi3_data8_mux[] = { +SD3_DAT0_MARK ,SD3_DAT1_MARK , +SD3_DAT2_MARK ,SD3_DAT3_MARK , +SD3_DAT4_MARK ,SD3_DAT5_MARK , +SD3_DAT6_MARK ,SD3_DAT7_MARK , +}; +static const unsigned int sdhi3_ctrl_pins[] = { +/* CLK, CMD */ +RCAR_GP_PIN (4 ,7 ),RCAR_GP_PIN (4 ,8 ), +}; +static const unsigned int sdhi3_ctrl_mux[] = { +SD3_CLK_MARK ,SD3_CMD_MARK , +}; +static const unsigned int sdhi3_cd_pins[] = { +/* CD */ +RCAR_GP_PIN (4 ,15 ), +}; +static const unsigned int sdhi3_cd_mux[] = { +SD3_CD_MARK , +}; +static const unsigned int sdhi3_wp_pins[] = { +/* WP */ +RCAR_GP_PIN (4 ,16 ), +}; +static const unsigned int sdhi3_wp_mux[] = { +SD3_WP_MARK , +}; +static const unsigned int sdhi3_ds_pins[] = { +/* DS */ +RCAR_GP_PIN (4 ,17 ), +}; +static const unsigned int sdhi3_ds_mux[] = { +SD3_DS_MARK , +}; +static const struct sh_pfc_pin_group pinmux_groups[] = {SH_PFC_PIN_GROUP (scif0_data),SH_PFC_PIN_GROUP (scif0_clk),
@@ -1712,6 +1919,32 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {SH_PFC_PIN_GROUP (scif5_clk_a),SH_PFC_PIN_GROUP (scif5_data_b ),SH_PFC_PIN_GROUP (scif5_clk_b ), +SH_PFC_PIN_GROUP (sdhi0_data1 ), +SH_PFC_PIN_GROUP (sdhi0_data4 ), +SH_PFC_PIN_GROUP (sdhi0_ctrl ), +SH_PFC_PIN_GROUP (sdhi0_cd ), +SH_PFC_PIN_GROUP (sdhi0_wp ), +SH_PFC_PIN_GROUP (sdhi1_data1 ), +SH_PFC_PIN_GROUP (sdhi1_data4 ), +SH_PFC_PIN_GROUP (sdhi1_ctrl ), +SH_PFC_PIN_GROUP (sdhi1_cd ), +SH_PFC_PIN_GROUP (sdhi1_wp ), +SH_PFC_PIN_GROUP (sdhi2_data1 ), +SH_PFC_PIN_GROUP (sdhi2_data4 ), +SH_PFC_PIN_GROUP (sdhi2_data8 ), +SH_PFC_PIN_GROUP (sdhi2_ctrl ), +SH_PFC_PIN_GROUP (sdhi2_cd_a ), +SH_PFC_PIN_GROUP (sdhi2_wp_a ), +SH_PFC_PIN_GROUP (sdhi2_cd_b ), +SH_PFC_PIN_GROUP (sdhi2_wp_b ), +SH_PFC_PIN_GROUP (sdhi2_ds ), +SH_PFC_PIN_GROUP (sdhi3_data1 ), +SH_PFC_PIN_GROUP (sdhi3_data4 ), +SH_PFC_PIN_GROUP (sdhi3_data8 ), +SH_PFC_PIN_GROUP (sdhi3_ctrl ), +SH_PFC_PIN_GROUP (sdhi3_cd ), +SH_PFC_PIN_GROUP (sdhi3_wp ), + SH_PFC_PIN_GROUP(sdhi3_ds), };static const char *const scif0_groups[] = {
@@ -1759,6 +1992,44 @@ static const char * const scif5_groups[] = { "scif5_clk_b", }; +static const char *const sdhi0_groups[] = { +"sdhi0_data1" , +"sdhi0_data4" , +"sdhi0_ctrl" , +"sdhi0_cd" , +"sdhi0_wp" , +}; + +static const char *const sdhi1_groups[] = { +"sdhi1_data1" , +"sdhi1_data4" , +"sdhi1_ctrl" , +"sdhi1_cd" , +"sdhi1_wp" , +}; + +static const char *const sdhi2_groups[] = { +"sdhi2_data1" , +"sdhi2_data4" , +"sdhi2_data8" , +"sdhi2_ctrl" , +"sdhi2_cd_a" , +"sdhi2_wp_a" , +"sdhi2_cd_b" , +"sdhi2_wp_b" , +"sdhi2_ds" , +}; + +static const char *const sdhi3_groups[] = { +"sdhi3_data1" , +"sdhi3_data4" , +"sdhi3_data8" , +"sdhi3_ctrl" , +"sdhi3_cd" , +"sdhi3_wp" , +"sdhi3_ds" , +}; +static const struct sh_pfc_function pinmux_functions[] = {SH_PFC_FUNCTION (scif0),SH_PFC_FUNCTION (scif1),
@@ -1766,6 +2037,10 @@ static const struct sh_pfc_function pinmux_functions[] = {SH_PFC_FUNCTION (scif3),SH_PFC_FUNCTION (scif4 ),SH_PFC_FUNCTION (scif5 ), +SH_PFC_FUNCTION (sdhi0 ), +SH_PFC_FUNCTION (sdhi1 ), +SH_PFC_FUNCTION (sdhi2 ), + SH_PFC_FUNCTION(sdhi3), };static const struct pinmux_cfg_reg pinmux_config_regs[] = {
Signature · 1 line
2.7.0.rc3.207.g0ac5344
PATCH v2 4/8 gpio: rcar: Add r8a7796 (R-Car M3-W) support
In reply to Simon HormanR-Car Gen3's GPIO blocks are identical to Gen2's in every respect.
Based on work for the r8a7795 (R-Car H3) by Ulrich Hecht.
---
v2
* New patch
--- Documentation/devicetree/bindings/gpio/renesas,gpio-rcar.txt | 1 + drivers/gpio/gpio-rcar.c | 4 ++++ 2 files changed, 5 insertions(+)
Documentation/devicetree/bindings/gpio/renesas,gpio-rcar.txt +1 -0
@@ -11,6 +11,7 @@ Required Properties: - "renesas,gpio-r8a7793": for R8A7793 (R-Car M2-N) compatible GPIO controller. - "renesas,gpio-r8a7794": for R8A7794 (R-Car E2) compatible GPIO controller. - "renesas,gpio-r8a7795": for R8A7795 (R-Car H3) compatible GPIO controller. + - "renesas,gpio-r8a7796": for R8A7796 (R-Car M3-W) compatible GPIO controller. - "renesas,gpio-rcar": for generic R-Car GPIO controller. - reg: Base address and length of each memory resource used by the GPIO
drivers/gpio/gpio-rcar.c +4 -0
@@ -348,6 +348,10 @@ static const struct of_device_id gpio_rcar_of_table[] = {/* Gen3 GPIO is identical to Gen2. */ .data = &gpio_rcar_info_gen2, }, { + .compatible = "renesas,gpio-r8a7796", + /* Gen3 GPIO is identical to Gen2. */ + .data = &gpio_rcar_info_gen2, + }, { .compatible = "renesas,gpio-rcar", .data = &gpio_rcar_info_gen1, }, {
Signature · 1 line
2.7.0.rc3.207.g0ac5344
PATCH v2 4/8 gpio: rcar: Add r8a7796 (R-Car M3-W) support
Quoted 6 lines · Simon Horman
R-Car Gen3's GPIO blocks are identical to Gen2's in every respect.
Based on work for the r8a7795 (R-Car H3) by Ulrich Hecht.
Cc Ulrich Hecht <[email protected]>Signed-off-by Simon Horman <[email protected]>
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert at linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
PATCH v2 5/8 mmc: sh_mobile_sdhi: Add r8a7796 support
In reply to Simon HormanFrom: Ai Kyuse <[email protected]>
Add support for r8a7796 SoC.
--- Documentation/devicetree/bindings/mmc/tmio_mmc.txt | 1 + drivers/mmc/host/sh_mobile_sdhi.c | 1 + 2 files changed, 2 insertions(+)
Documentation/devicetree/bindings/mmc/tmio_mmc.txt +1 -0
@@ -23,6 +23,7 @@ Required properties: "renesas,sdhi-r8a7793" - SDHI IP on R8A7793 SoC "renesas,sdhi-r8a7794" - SDHI IP on R8A7794 SoC "renesas,sdhi-r8a7795" - SDHI IP on R8A7795 SoC + "renesas,sdhi-r8a7796" - SDHI IP on R8A7796 SoC Optional properties: - toshiba,mmc-wrprotect-disable: write-protect detection is unavailable
drivers/mmc/host/sh_mobile_sdhi.c +1 -0
@@ -129,6 +129,7 @@ static const struct of_device_id sh_mobile_sdhi_of_match[] = { { .compatible = "renesas,sdhi-r8a7793", .data = &of_rcar_gen2_compatible, }, { .compatible = "renesas,sdhi-r8a7794", .data = &of_rcar_gen2_compatible, }, { .compatible = "renesas,sdhi-r8a7795", .data = &of_rcar_gen3_compatible, }, + { .compatible = "renesas,sdhi-r8a7796", .data = &of_rcar_gen3_compatible, }, {}, }; MODULE_DEVICE_TABLE(of, sh_mobile_sdhi_of_match);
Signature · 1 line
2.7.0.rc3.207.g0ac5344
PATCH v2 6/8 arm64: dts: r8a7796: Add GPIO device nodes
In reply to Simon HormanFrom: Takeshi Kihara <[email protected]>
Add GPIO device nodes to the DT of the r8a7796 SoC.
--- arch/arm64/boot/dts/renesas/r8a7796.dtsi | 112 +++++++++++++++++++++++++++++++ 1 file changed, 112 insertions(+)
arch/arm64/boot/dts/renesas/r8a7796.dtsi +112 -0
@@ -107,6 +107,118 @@ status = "disabled"; }; + gpio0: gpio at e6050000 { + compatible = "renesas,gpio-r8a7796", + "renesas,gpio-rcar"; + reg = <0 0xe6050000 0 0x50>; + interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 0 16>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 912>; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + }; + + gpio1: gpio at e6051000 { + compatible = "renesas,gpio-r8a7796", + "renesas,gpio-rcar"; + reg = <0 0xe6051000 0 0x50>; + interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 32 29>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 911>; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + }; + + gpio2: gpio at e6052000 { + compatible = "renesas,gpio-r8a7796", + "renesas,gpio-rcar"; + reg = <0 0xe6052000 0 0x50>; + interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 64 15>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 910>; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + }; + + gpio3: gpio at e6053000 { + compatible = "renesas,gpio-r8a7796", + "renesas,gpio-rcar"; + reg = <0 0xe6053000 0 0x50>; + interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 96 16>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 909>; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + }; + + gpio4: gpio at e6054000 { + compatible = "renesas,gpio-r8a7796", + "renesas,gpio-rcar"; + reg = <0 0xe6054000 0 0x50>; + interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 128 18>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 908>; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + }; + + gpio5: gpio at e6055000 { + compatible = "renesas,gpio-r8a7796", + "renesas,gpio-rcar"; + reg = <0 0xe6055000 0 0x50>; + interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 160 26>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 907>; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + }; + + gpio6: gpio at e6055400 { + compatible = "renesas,gpio-r8a7796", + "renesas,gpio-rcar"; + reg = <0 0xe6055400 0 0x50>; + interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 192 32>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 906>; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + }; + + gpio7: gpio at e6055800 { + compatible = "renesas,gpio-r8a7796", + "renesas,gpio-rcar"; + reg = <0 0xe6055800 0 0x50>; + interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 224 4>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 905>; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + }; + pfc: pfc at e6060000 { compatible = "renesas,pfc-r8a7796"; reg = <0 0xe6060000 0 0x50c>;
Signature · 1 line
2.7.0.rc3.207.g0ac5344
PATCH v2 7/8 arm64: dts: r8a7796: add SDHI nodes
In reply to Simon HormanAdd SDHI nodes to the DT of the r8a7796 SoC.
Based on the DT of the r8a7795 SoC.
--- arch/arm64/boot/dts/renesas/r8a7796.dtsi | 42 ++++++++++++++++++++++++++++++++ 1 file changed, 42 insertions(+)
arch/arm64/boot/dts/renesas/r8a7796.dtsi +42 -0
@@ -251,5 +251,47 @@ power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; status = "disabled"; }; + + sdhi0: sd at ee100000 { + compatible = "renesas,sdhi-r8a7796"; + reg = <0 0xee100000 0 0x2000>; + interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 314>; + max-frequency = <200000000>; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + status = "disabled"; + }; + + sdhi1: sd at ee120000 { + compatible = "renesas,sdhi-r8a7796"; + reg = <0 0xee120000 0 0x2000>; + interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 313>; + max-frequency = <200000000>; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + status = "disabled"; + }; + + sdhi2: sd at ee140000 { + compatible = "renesas,sdhi-r8a7796"; + reg = <0 0xee140000 0 0x2000>; + interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 312>; + max-frequency = <200000000>; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + cap-mmc-highspeed; + status = "disabled"; + }; + + sdhi3: sd at ee160000 { + compatible = "renesas,sdhi-r8a7796"; + reg = <0 0xee160000 0 0x2000>; + interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 311>; + max-frequency = <200000000>; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + cap-mmc-highspeed; + status = "disabled"; + }; }; };
Signature · 1 line
2.7.0.rc3.207.g0ac5344
PATCH v2 8/8 arm64: dts: r8a7796: salvator-x: enable SDHI0 & 3
In reply to Simon HormanEnable the exposed SD card slots in the DT of the r8a7796/salvator-x.
Based on work for the r8a7795/salvator-x by Ai Kyuse.
--- arch/arm64/boot/dts/renesas/r8a7796-salvator-x.dts | 84 ++++++++++++++++++++++ 1 file changed, 84 insertions(+)
arch/arm64/boot/dts/renesas/r8a7796-salvator-x.dts +84 -0
@@ -10,6 +10,7 @@ /dts-v1/; #include "r8a7796.dtsi" +#include <dt-bindings/gpio/gpio.h> / { model = "Renesas Salvator-X board based on r8a7796";
@@ -29,6 +30,55 @@ /* first 128MB is reserved for secure area. */ reg = <0x0 0x48000000 0x0 0x78000000>; }; + + vcc_sdhi0: regulator-vcc-sdhi0 { + compatible = "regulator-fixed"; + + regulator-name = "SDHI0 Vcc"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&gpio5 2 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + vccq_sdhi0: regulator-vccq-sdhi0 { + compatible = "regulator-gpio"; + + regulator-name = "SDHI0 VccQ"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + + gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>; + gpios-states = <1>; + states = <3300000 1 + 1800000 0>; + }; + + vcc_sdhi3: regulator-vcc-sdhi3 { + compatible = "regulator-fixed"; + + regulator-name = "SDHI3 Vcc"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&gpio3 15 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + vccq_sdhi3: regulator-vccq-sdhi3 { + compatible = "regulator-gpio"; + + regulator-name = "SDHI3 VccQ"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + + gpios = <&gpio3 14 GPIO_ACTIVE_HIGH>; + gpios-states = <1>; + states = <3300000 1 + 1800000 0>; + }; + }; &pfc {
@@ -36,12 +86,46 @@ groups = "scif2_data_a"; function = "scif2"; }; + + sdhi0_pins: sd0 { + groups = "sdhi0_data4", "sdhi0_ctrl"; + function = "sdhi0"; + }; + + sdhi3_pins: sd3 { + groups = "sdhi3_data4", "sdhi3_ctrl"; + function = "sdhi3"; + }; }; &extal_clk { clock-frequency = <16666666>; }; +&sdhi0 { + pinctrl-0 = <&sdhi0_pins>; + pinctrl-names = "default"; + + vmmc-supply = <&vcc_sdhi0>; + vqmmc-supply = <&vccq_sdhi0>; + cd-gpios = <&gpio3 12 GPIO_ACTIVE_LOW>; + wp-gpios = <&gpio3 13 GPIO_ACTIVE_HIGH>; + bus-width = <4>; + status = "okay"; +}; + +&sdhi3 { + pinctrl-0 = <&sdhi3_pins>; + pinctrl-names = "default"; + + vmmc-supply = <&vcc_sdhi3>; + vqmmc-supply = <&vccq_sdhi3>; + cd-gpios = <&gpio4 15 GPIO_ACTIVE_LOW>; + wp-gpios = <&gpio4 16 GPIO_ACTIVE_HIGH>; + bus-width = <4>; + status = "okay"; +}; + &scif2 { pinctrl-0 = <&scif2_pins>; pinctrl-names = "default";
Signature · 1 line
2.7.0.rc3.207.g0ac5344
v2 cover Add SDHI to r8a7796/salvator-x
In reply to Simon HormanQuoted 11 lines · Simon Horman
Hi,
this patch set updates drivers, documentation and DT to enable SDHI0 & 3 on the r8a7796/salvator-x. This includes defining nodes for all available SDHI and GPIO devices.
I have boot-tested this which seems successful.
However, I do not have physical access to an r8a7796/salvator-x board and the one that I have remote access to does not appear to have any SD cards present. I would be grateful of any testing anyone can provide.
The board I have access to now has SD cards present and I have been able to lightly test this patchset. Access to both SD card slogs seems to work.
Quoted 7 lines
Based on renesas-drivers-2016-08-09-v4.8-rc1
Provided for testing as the topic/r8a7796-sdhi-v2 branch in my renesas tree on kernel.org.
Changes since v1 noted in individual changelogs.
Acks from v1 also added.
v2 cover Add SDHI to r8a7796/salvator-x
In reply to Simon HormanHi Simon,
Thank you for the patches.
Quoted 6 lines · On Tuesday 23 Aug 2016 09:49:42 Simon Horman wrote:
Hi,
this patch set updates drivers, documentation and DT to enable SDHI0 & 3 on the r8a7796/salvator-x. This includes defining nodes for all available SDHI and GPIO devices.
Quoted 7 lines
I have boot-tested this which seems successful.
However, I do not have physical access to an r8a7796/salvator-x board and the one that I have remote access to does not appear to have any SD cards present. I would be grateful of any testing anyone can provide.Based on renesas-drivers-2016-08-09-v4.8-rc1
For patches 1/8, 4/8 and 6/8, applied on top of your devel branch (with the gpio-ranges property removed from 6/8 due to the lack of PFC support),
I've tested the patches with ethernet support that uses GPIO-2-11 as an interrupt pin (I'll post the ethernet patches for r8a7796 soon).
Quoted 29 lines
Provided for testing as the topic/r8a7796-sdhi-v2 branch in my renesas tree on kernel.org.
Changes since v1 noted in individual changelogs.
Acks from v1 also added.Ai Kyuse (1):
mmc:sh_mobile_sdhi: Add r8a7796 supportSimon Horman (4):
clk: renesas: r8a7796: Add SDIF clocks
gpio: rcar: Add r8a7796 (R-Car M3-W) support
arm64: dts: r8a7796: add SDHI nodes
arm64: dts: r8a7796: salvator-x: enable SDHI0 & 3Takeshi Kihara (3):
clk: renesas: r8a7796: Add GPIO clocks
pinctrl: sh-pfc: r8a7796: Add SDHI pins, groups and functions
arm64: dts: r8a7796: Add GPIO device nodes.../devicetree/bindings/gpio/renesas,gpio-rcar.txt | 1 + Documentation/devicetree/bindings/mmc/tmio_mmc.txt | 1 + arch/arm64/boot/dts/renesas/r8a7796-salvator-x.dts | 84 +++++++ arch/arm64/boot/dts/renesas/r8a7796.dtsi | 154 ++++++++++++ drivers/clk/renesas/r8a7796-cpg-mssr.c | 18 ++ drivers/gpio/gpio-rcar.c | 4 + drivers/mmc/host/sh_mobile_sdhi.c | 1 + drivers/pinctrl/sh-pfc/pfc-r8a7796.c | 275 ++++++++++++++++++ 8 files changed, 538 insertions(+)
Signature · 3 lines
Regards, Laurent Pinchart
v2 cover Add SDHI to r8a7796/salvator-x
Quoted 17 lines · Laurent Pinchart
Hi Simon,
Thank you for the patches.
Quoted 12 lines · On Tuesday 23 Aug 2016 09:49:42 Simon Horman wrote:
Hi,
this patch set updates drivers, documentation and DT to enable SDHI0 & 3 on the r8a7796/salvator-x. This includes defining nodes for all available SDHI and GPIO devices.
I have boot-tested this which seems successful.
However, I do not have physical access to an r8a7796/salvator-x board and the one that I have remote access to does not appear to have any SD cards present. I would be grateful of any testing anyone can provide.
Quoted 7 lines
Quoted 1 line
Based on renesas-drivers-2016-08-09-v4.8-rc1
For patches 1/8, 4/8 and 6/8, applied on top of your devel branch (with the gpio-ranges property removed from 6/8 due to the lack of PFC support),
Reviewed-by Laurent Pinchart <[email protected]>Tested-by Laurent Pinchart <[email protected]>
Thanks.
Quoted 2 lines
I've tested the patches with ethernet support that uses GPIO-2-11 as an interrupt pin (I'll post the ethernet patches for r8a7796 soon).
Great! I have a use for them and was planing to make some myself.
Quoted 35 lines
Quoted 29 lines
Provided for testing as the topic/r8a7796-sdhi-v2 branch in my renesas tree on kernel.org.
Changes since v1 noted in individual changelogs.
Acks from v1 also added.Ai Kyuse (1):
mmc:sh_mobile_sdhi: Add r8a7796 supportSimon Horman (4):
clk: renesas: r8a7796: Add SDIF clocks
gpio: rcar: Add r8a7796 (R-Car M3-W) support
arm64: dts: r8a7796: add SDHI nodes
arm64: dts: r8a7796: salvator-x: enable SDHI0 & 3Takeshi Kihara (3):
clk: renesas: r8a7796: Add GPIO clocks
pinctrl: sh-pfc: r8a7796: Add SDHI pins, groups and functions
arm64: dts: r8a7796: Add GPIO device nodes.../devicetree/bindings/gpio/renesas,gpio-rcar.txt | 1 + Documentation/devicetree/bindings/mmc/tmio_mmc.txt | 1 + arch/arm64/boot/dts/renesas/r8a7796-salvator-x.dts | 84 +++++++ arch/arm64/boot/dts/renesas/r8a7796.dtsi | 154 ++++++++++++ drivers/clk/renesas/r8a7796-cpg-mssr.c | 18 ++ drivers/gpio/gpio-rcar.c | 4 + drivers/mmc/host/sh_mobile_sdhi.c | 1 + drivers/pinctrl/sh-pfc/pfc-r8a7796.c | 275 ++++++++++++++++++ 8 files changed, 538 insertions(+)Signature · 3 lines
Regards, Laurent Pinchart
v2 cover Add SDHI to r8a7796/salvator-x
Quoted 20 lines · Simon Horman
Quoted 19 lines · Laurent Pinchart
Hi Simon,
Thank you for the patches.
Quoted 13 lines · On Tuesday 23 Aug 2016 09:49:42 Simon Horman wrote:
Hi,
this patch set updates drivers, documentation and DT to enable SDHI0 & 3 on the r8a7796/salvator-x. This includes defining nodes for all available SDHI and GPIO devices.
I have boot-tested this which seems successful.
However, I do not have physical access to an r8a7796/salvator-x board and the one that I have remote access to does not appear to have any SD cards present. I would be grateful of any testing anyone can provide.Based on renesas-drivers-2016-08-09-v4.8-rc1
Quoted 7 lines
Quoted 5 lines
For patches 1/8, 4/8 and 6/8, applied on top of your devel branch (with the gpio-ranges property removed from 6/8 due to the lack of PFC support),
Reviewed-by Laurent Pinchart <[email protected]>Tested-by Laurent Pinchart <[email protected]>Thanks.
I have queued up 6/8 and 7/8 in a branch based on
sh-pfc-for-v4.9-tag2.
v2 cover Add SDHI to r8a7796/salvator-x
Quoted 24 lines · Simon Horman
Quoted 23 lines · Simon Horman
Quoted 22 lines · Laurent Pinchart
Hi Simon,
Thank you for the patches.
Quoted 6 lines · On Tuesday 23 Aug 2016 09:49:42 Simon Horman wrote:
Hi,
this patch set updates drivers, documentation and DT to enable SDHI0 & 3 on the r8a7796/salvator-x. This includes defining nodes for all available SDHI and GPIO devices.
Quoted 7 lines
I have boot-tested this which seems successful.
However, I do not have physical access to an r8a7796/salvator-x board and the one that I have remote access to does not appear to have any SD cards present. I would be grateful of any testing anyone can provide.Based on renesas-drivers-2016-08-09-v4.8-rc1
For patches 1/8, 4/8 and 6/8, applied on top of your devel branch (with the gpio-ranges property removed from 6/8 due to the lack of PFC support),
Quoted 7 lines
Quoted 4 lines
Quoted 2 lines
Reviewed-by Laurent Pinchart <[email protected]>Tested-by Laurent Pinchart <[email protected]>Thanks.
I have queued up 6/8 and 7/8 in a branch based on
sh-pfc-for-v4.9-tag2.
I was a little hasty there. I have queued up 6/8 (GPIO) only.