ARM: move ARMV7_PSCI and ARMV7_PSCI_NR_CPUS to Kconfig

PATCH New Masahiro Yamada 4 participants 16 messages Aug 30, 2016 – Sep 26, 2016

Subsystems (6)

Arm (32-bit) Arm sub-architectures Tegra architecture support Arm/Allwinner sunXi SoC support +2 more subsystems

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Masahiro Yamada

author

2016-08-30 07:22 UTC #0 lore raw

v2 cover ARM: move ARMV7_PSCI and ARMV7_PSCI_NR_CPUS to Kconfig

Masahiro Yamada (4):
ARM: tegra: remove wrong dependency on SPL_BUILD
ARM: armv7: guard memory reserve for PSCI with #ifdef
CONFIG_ARMV7_PSCI
ARM: armv7: move CONFIG_ARMV7_PSCI to Kconfig
ARM: armv7: move ARMV7_PSCI_NR_CPUS to Kconfig

 arch/arm/Kconfig                     |  3 +++
 arch/arm/cpu/armv7/Kconfig           | 19 +++++++++++++++++++
 arch/arm/cpu/armv7/mx7/Kconfig       |  1 +
 arch/arm/cpu/u-boot.lds              |  4 ++--
 arch/arm/mach-tegra/tegra124/Kconfig |  5 +++--
 arch/arm/mach-uniphier/Kconfig       |  1 +
 board/sunxi/Kconfig                  |  5 +++++
 include/configs/arndale.h            |  1 -
 include/configs/bcm_ep_board.h       |  1 -
 include/configs/jetson-tk1.h         |  2 --
 include/configs/ls1021aqds.h         |  2 --
 include/configs/ls1021atwr.h         |  2 --
 include/configs/mx7_common.h         |  2 --
 include/configs/sun6i.h              |  2 --
 include/configs/sun7i.h              |  2 --
 include/configs/sun8i.h              | 13 -------------
 include/configs/uniphier.h           |  2 --
 include/configs/vexpress_ca15_tc2.h  |  1 -
 18 files changed, 34 insertions(+), 34 deletions(-)

Signature · 1 line

1.9.1

Masahiro Yamada

author

2016-08-30 07:22 UTC #1 lore raw

PATCH v2 1/4 ARM: tegra: remove wrong dependency on SPL_BUILD

SPL_BUILD is not a CONFIG in Kconfig, so !SPL_BUILD is always true.

Signed-off-by Masahiro Yamada <[email protected]>

---

Changes in v2: None

 arch/arm/mach-tegra/tegra124/Kconfig | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

arch/arm/mach-tegra/tegra124/Kconfig +2 -2

index f3324ff..44f63f7 100644
@@ -6,8 +6,8 @@ choice
 
 config TARGET_JETSON_TK1
 	bool "NVIDIA Tegra124 Jetson TK1 board"
-	select CPU_V7_HAS_NONSEC if !SPL_BUILD
-	select CPU_V7_HAS_VIRT if !SPL_BUILD
+	select CPU_V7_HAS_NONSEC
+	select CPU_V7_HAS_VIRT
 
 config TARGET_NYAN_BIG
 	bool "Google/NVIDIA Nyan-big Chromebook"

Signature · 1 line

1.9.1

Tom Rini

2016-09-07 17:59 UTC #2 lore raw

PATCH v2 1/4 ARM: tegra: remove wrong dependency on SPL_BUILD

Quoted 3 lines · Masahiro Yamada

SPL_BUILD is not a CONFIG in Kconfig, so !SPL_BUILD is always true.
Signed-off-by Masahiro Yamada <[email protected]>

Applied to u-boot/master, thanks!

Signature · 8 lines

Tom
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Masahiro Yamada

author

2016-08-30 07:22 UTC #3 lore raw

PATCH v2 2/4 ARM: armv7: guard memory reserve for PSCI with #ifdef CONFIG_ARMV7_PSCI

In reply to Masahiro Yamada

If CONFIG_ARMV7_NONSEC is enabled, the linker script requires CONFIG_ARMV7_PSCI_NR_CPUS regardless of CONFIG_ARMV7_PSCI.

Signed-off-by Masahiro Yamada <[email protected]>

---

Changes in v2: None

 arch/arm/cpu/u-boot.lds | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

arch/arm/cpu/u-boot.lds +2 -2

index 36c9fd0..0a5fae6 100644
@@ -83,10 +83,10 @@ SECTIONS
 #endif
 	{
 		KEEP(*(.__secure_stack_start))
-
+#ifdef CONFIG_ARMV7_PSCI
 		/* Skip addreses for stack */
 		. = . + CONFIG_ARMV7_PSCI_NR_CPUS * ARM_PSCI_STACK_SIZE;
-
+#endif
 		/* Align end of stack section to page boundary */
 		. = ALIGN(CONSTANT(COMMONPAGESIZE));

Signature · 1 line

1.9.1

Tom Rini

2016-09-07 17:59 UTC #4 lore raw

PATCH v2 2/4 ARM: armv7: guard memory reserve for PSCI with #ifdef CONFIG_ARMV7_PSCI

Quoted 4 lines · Masahiro Yamada

If CONFIG_ARMV7_NONSEC is enabled, the linker script requires CONFIG_ARMV7_PSCI_NR_CPUS regardless of CONFIG_ARMV7_PSCI.
Signed-off-by Masahiro Yamada <[email protected]>

Applied to u-boot/master, thanks!

Signature · 8 lines

Tom
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Jon Masters

2016-09-23 05:09 UTC #5 lore raw

PATCH v2 2/4 ARM: armv7: guard memory reserve for PSCI with #ifdef CONFIG_ARMV7_PSCI

In reply to Masahiro Yamada

Quoted 19 lines · Masahiro Yamada

If CONFIG_ARMV7_NONSEC is enabled, the linker script requires CONFIG_ARMV7_PSCI_NR_CPUS regardless of CONFIG_ARMV7_PSCI.
Signed-off-by Masahiro Yamada <[email protected]>
---
Changes in v2: None
 arch/arm/cpu/u-boot.lds | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)
arch/arm/cpu/u-boot.lds +0 -0
index 36c9fd0..0a5fae6 100644
@@ -83,10 +83,10 @@ SECTIONS
 #endif
 	{

arch/arm/cpu/u-boot.lds SECTIONS · line 92

Quoted 10 lines

arch/arm/cpu/u-boot.lds +2 -2

 		KEEP(*(.__secure_stack_start))
-
+#ifdef CONFIG_ARMV7_PSCI
 		/* Skip addreses for stack */
 		. = . + CONFIG_ARMV7_PSCI_NR_CPUS * ARM_PSCI_STACK_SIZE;
-
+#endif
 		/* Align end of stack section to page boundary */
 		. = ALIGN(CONSTANT(COMMONPAGESIZE));

In the Fedora U-Boot ELF builds being tested for 32-bit U-Boot on KVM (AArch32 on ARMv8 hardware, as a means of decommissioning older v7 builders and replacing them with VMs on v8 hosts) this results in the following for a vexpress_ca15_tc2 U-Boot build target:

2 .secure_text 00000130 8082d000 8082d000 0003d000 2**5
CONTENTS, ALLOC, LOAD, READONLY, CODE
3 .secure_stack 00000000 8082e000 8082e000 0004e000 2**0
ALLOC
4 .__secure_end 00000004 8082e000 8082e000 0003e000 2**0
CONTENTS, ALLOC, LOAD, DATA

Which QEMU then refuses to load because there's no space allocated for the secure_stack. What do you think we should do about this? I haven't been tracking the PSCI implementation (which is pretty cool btw, woot!) work you've been doing and we don't really need it for the VM case anyway, just need the resulting build to link correctly. So sure, probably I/we need to understand the status of the PSCI work too.

Jon.

Signature · 1 line

Computer Architect | Sent from my Fedora powered laptop

Jon Masters

2016-09-23 05:34 UTC #6 lore raw

PATCH v2 2/4 ARM: armv7: guard memory reserve for PSCI with #ifdef CONFIG_ARMV7_PSCI

Quoted 43 lines · Jon Masters

Quoted 19 lines · Masahiro Yamada
If CONFIG_ARMV7_NONSEC is enabled, the linker script requires CONFIG_ARMV7_PSCI_NR_CPUS regardless of CONFIG_ARMV7_PSCI.
Signed-off-by Masahiro Yamada <[email protected]>
---
Changes in v2: None
 arch/arm/cpu/u-boot.lds | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)
arch/arm/cpu/u-boot.lds +0 -0
index 36c9fd0..0a5fae6 100644
@@ -83,10 +83,10 @@ SECTIONS
 #endif
 	{
arch/arm/cpu/u-boot.lds SECTIONS · line 92
Quoted 10 lines
arch/arm/cpu/u-boot.lds +2 -2
 		KEEP(*(.__secure_stack_start))
-
+#ifdef CONFIG_ARMV7_PSCI
 		/* Skip addreses for stack */
 		. = . + CONFIG_ARMV7_PSCI_NR_CPUS * ARM_PSCI_STACK_SIZE;
-
+#endif
 		/* Align end of stack section to page boundary */
 		. = ALIGN(CONSTANT(COMMONPAGESIZE));
 
In the Fedora U-Boot ELF builds being tested for 32-bit U-Boot on KVM (AArch32 on ARMv8 hardware, as a means of decommissioning older v7 builders and replacing them with VMs on v8 hosts) this results in the following for a vexpress_ca15_tc2 U-Boot build target:
2 .secure_text 00000130 8082d000 8082d000 0003d000 2**5
CONTENTS, ALLOC, LOAD, READONLY, CODE
3 .secure_stack 00000000 8082e000 8082e000 0004e000 2**0
ALLOC
4 .__secure_end 00000004 8082e000 8082e000 0003e000 2**0
CONTENTS, ALLOC, LOAD, DATA

Quoted 6 lines

Which QEMU then refuses to load because there's no space allocated for the secure_stack. What do you think we should do about this? I haven't been tracking the PSCI implementation (which is pretty cool btw, woot!) work you've been doing and we don't really need it for the VM case anyway, just need the resulting build to link correctly. So sure, probably I/we need to understand the status of the PSCI work too.

Ok, so the specific problem seems to be:

commit 5a3aae68c74e029ed29d22999ab6f22687382f2d

Author: Masahiro Yamada <[email protected]>
Date:   Tue Aug 30 16:22:21 2016 +0900

ARM: armv7: guard memory reserve for PSCI with #ifdef CONFIG_ARMV7_PSCI

If CONFIG_ARMV7_NONSEC is enabled, the linker script requires CONFIG_ARMV7_PSCI_NR_CPUS regardless of CONFIG_ARMV7_PSCI.

Reviewed-by Alexander Graf <[email protected]>

Signed-off-by Masahiro Yamada <[email protected]>

This introduced the change that results in no secure stack space being allocated in the ELF image. The vexpress_ca15_tc2 target doesn't claim to support PSCI /however/ the default includes say that we are ARMV7_NONSEC and CONFIG_ARMV7_PSCI_NR_CPUS will default to 4 in that case regardless, so this is why we were previously allocating space for the (presumably unused) secure_stack (prior to the above commit). That commit changed things by wrapping it in a conditional on ARMV7_PSCI.

Can someone who is actually a U-Boot person tell us what the intention is in this case, and what should actually happen to the linker script?

Jon.

Signature · 1 line

Computer Architect | Sent from my Fedora powered laptop

Masahiro Yamada

author

2016-09-26 05:25 UTC #7 lore raw

PATCH v2 2/4 ARM: armv7: guard memory reserve for PSCI with #ifdef CONFIG_ARMV7_PSCI

Hi Jon,

2016-09-23 14:34 GMT+09:00 Jon Masters <[email protected]>:

Quoted 73 lines · Jon Masters

Quoted 43 lines · Masahiro Yamada
Quoted 19 lines
If CONFIG_ARMV7_NONSEC is enabled, the linker script requires CONFIG_ARMV7_PSCI_NR_CPUS regardless of CONFIG_ARMV7_PSCI.
Signed-off-by Masahiro Yamada <[email protected]>
---
Changes in v2: None
 arch/arm/cpu/u-boot.lds | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)
arch/arm/cpu/u-boot.lds +0 -0
index 36c9fd0..0a5fae6 100644
@@ -83,10 +83,10 @@ SECTIONS
 #endif
     {
arch/arm/cpu/u-boot.lds SECTIONS · line 92
Quoted 10 lines
arch/arm/cpu/u-boot.lds +2 -2
             KEEP(*(.__secure_stack_start))
-
+#ifdef CONFIG_ARMV7_PSCI
             /* Skip addreses for stack */
             . = . + CONFIG_ARMV7_PSCI_NR_CPUS * ARM_PSCI_STACK_SIZE;
-
+#endif
             /* Align end of stack section to page boundary */
             . = ALIGN(CONSTANT(COMMONPAGESIZE));
 
In the Fedora U-Boot ELF builds being tested for 32-bit U-Boot on KVM (AArch32 on ARMv8 hardware, as a means of decommissioning older v7 builders and replacing them with VMs on v8 hosts) this results in the following for a vexpress_ca15_tc2 U-Boot build target:
2 .secure_text 00000130 8082d000 8082d000 0003d000 2**5
CONTENTS, ALLOC, LOAD, READONLY, CODE
3 .secure_stack 00000000 8082e000 8082e000 0004e000 2**0
ALLOC
4 .__secure_end 00000004 8082e000 8082e000 0003e000 2**0
CONTENTS, ALLOC, LOAD, DATA
Quoted 6 lines
Which QEMU then refuses to load because there's no space allocated for the secure_stack. What do you think we should do about this? I haven't been tracking the PSCI implementation (which is pretty cool btw, woot!) work you've been doing and we don't really need it for the VM case anyway, just need the resulting build to link correctly. So sure, probably I/we need to understand the status of the PSCI work too.
Ok, so the specific problem seems to be:
commit 5a3aae68c74e029ed29d22999ab6f22687382f2d
Author: Masahiro Yamada <[email protected]>
Date:   Tue Aug 30 16:22:21 2016 +0900
ARM: armv7: guard memory reserve for PSCI with #ifdef CONFIG_ARMV7_PSCI
If CONFIG_ARMV7_NONSEC is enabled, the linker script requires CONFIG_ARMV7_PSCI_NR_CPUS regardless of CONFIG_ARMV7_PSCI.
Reviewed-by Alexander Graf <[email protected]>
Signed-off-by Masahiro Yamada <[email protected]>
This introduced the change that results in no secure stack space being allocated in the ELF image. The vexpress_ca15_tc2 target doesn't claim to support PSCI /however/ the default includes say that we are ARMV7_NONSEC and CONFIG_ARMV7_PSCI_NR_CPUS will default to 4 in that case regardless, so this is why we were previously allocating space for the (presumably unused) secure_stack (prior to the above commit). That commit changed things by wrapping it in a conditional on ARMV7_PSCI.

Quoted 5 lines

Can someone who is actually a U-Boot person tell us what the intention is in this case, and what should actually happen to the linker script?
Jon.

My motivation for that commit was just
to move some PSCI related options to Kconfig.

If the empty section is the cause of your problem, I think
http://patchwork.ozlabs.org/patch/674962/
will work.
But, it will break CONFIG_ARMV7_SECURE_MAX_SIZE checking, instead.

The PSCI work for ARMv7 is mostly from Chen-Yu. So, I am hoping he will help us.

Signature · 2 lines

Best Regards
Masahiro Yamada

Masahiro Yamada

author

2016-08-30 07:22 UTC #8 lore raw

PATCH v2 3/4 ARM: armv7: move CONFIG_ARMV7_PSCI to Kconfig

In reply to Masahiro Yamada

Add ARCH_SUPPORT_PSCI as a non-configurable option that platforms can select. Then, move CONFIG_ARMV7_PSCI, which is automatically enabled if both ARMV7_NONSEC and ARCH_SUPPORT_PSCI are enabled.

Signed-off-by Masahiro Yamada <[email protected]>

---

Changes in v2: None

 arch/arm/Kconfig                     |  3 +++
 arch/arm/cpu/armv7/Kconfig           | 10 ++++++++++
 arch/arm/cpu/armv7/mx7/Kconfig       |  1 +
 arch/arm/mach-tegra/tegra124/Kconfig |  1 +
 arch/arm/mach-uniphier/Kconfig       |  1 +
 board/sunxi/Kconfig                  |  5 +++++
 include/configs/jetson-tk1.h         |  1 -
 include/configs/ls1021aqds.h         |  1 -
 include/configs/ls1021atwr.h         |  1 -
 include/configs/mx7_common.h         |  1 -
 include/configs/sun6i.h              |  1 -
 include/configs/sun7i.h              |  1 -
 include/configs/sun8i.h              |  1 -
 include/configs/uniphier.h           |  1 -
 14 files changed, 21 insertions(+), 8 deletions(-)

arch/arm/Kconfig +3 -0

index c871eaf..37fee43 100644
@@ -816,10 +816,13 @@ config TARGET_LS1021AQDS
 	bool "Support ls1021aqds"
 	select CPU_V7
 	select SUPPORT_SPL
+	select ARCH_SUPPORT_PSCI
+
 config TARGET_LS1021ATWR
 	bool "Support ls1021atwr"
 	select CPU_V7
 	select SUPPORT_SPL
+	select ARCH_SUPPORT_PSCI
 
 config TARGET_LS1043AQDS
 	bool "Support ls1043aqds"

arch/arm/cpu/armv7/Kconfig +10 -0

index 41c6639..4390f59 100644
@@ -6,6 +6,9 @@ config CPU_V7_HAS_NONSEC
 config CPU_V7_HAS_VIRT
         bool
 
+config ARCH_SUPPORT_PSCI
+        bool
+
 config ARMV7_NONSEC
 	bool "Enable support for booting in non-secure mode" if EXPERT
 	depends on CPU_V7_HAS_NONSEC

@@ -31,6 +34,13 @@ config ARMV7_VIRT
 	---help---
 	Say Y here to boot in hypervisor (HYP) mode when booting non-secure.
 
+config ARMV7_PSCI
+	bool "Enable PSCI support" if EXPERT
+	depends on ARMV7_NONSEC && ARCH_SUPPORT_PSCI
+	default y
+	help
+	  Say Y here to enable PSCI support.
+
 config ARMV7_LPAE
 	bool "Use LPAE page table format" if EXPERT
 	depends on CPU_V7

arch/arm/cpu/armv7/mx7/Kconfig +1 -0

index 5fdc8dd..fb00b8c 100644
@@ -5,6 +5,7 @@ config MX7
 	select ROM_UNIFIED_SECTIONS
 	select CPU_V7_HAS_VIRT
 	select CPU_V7_HAS_NONSEC
+	select ARCH_SUPPORT_PSCI
 	default y
 
 config MX7D

arch/arm/mach-tegra/tegra124/Kconfig +1 -0

index 44f63f7..f97eb85 100644
@@ -8,6 +8,7 @@ config TARGET_JETSON_TK1
 	bool "NVIDIA Tegra124 Jetson TK1 board"
 	select CPU_V7_HAS_NONSEC
 	select CPU_V7_HAS_VIRT
+	select ARCH_SUPPORT_PSCI
 
 config TARGET_NYAN_BIG
 	bool "Google/NVIDIA Nyan-big Chromebook"

arch/arm/mach-uniphier/Kconfig +1 -0

index 8961458..7bee6c7 100644
@@ -8,6 +8,7 @@ config ARCH_UNIPHIER_32BIT
 	select CPU_V7
 	select CPU_V7_HAS_NONSEC
 	select ARMV7_NONSEC
+	select ARCH_SUPPORT_PSCI
 
 config ARCH_UNIPHIER_64BIT
 	bool

board/sunxi/Kconfig +5 -0

index 1b30669..4e91f49 100644
@@ -37,6 +37,7 @@ config MACH_SUN6I
 	select CPU_V7
 	select CPU_V7_HAS_NONSEC
 	select CPU_V7_HAS_VIRT
+	select ARCH_SUPPORT_PSCI
 	select SUNXI_GEN_SUN6I
 	select SUPPORT_SPL
 	select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT

@@ -46,6 +47,7 @@ config MACH_SUN7I
 	select CPU_V7
 	select CPU_V7_HAS_NONSEC
 	select CPU_V7_HAS_VIRT
+	select ARCH_SUPPORT_PSCI
 	select SUNXI_GEN_SUN4I
 	select SUPPORT_SPL
 	select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT

@@ -55,6 +57,7 @@ config MACH_SUN8I_A23
 	select CPU_V7
 	select CPU_V7_HAS_NONSEC
 	select CPU_V7_HAS_VIRT
+	select ARCH_SUPPORT_PSCI
 	select SUNXI_GEN_SUN6I
 	select SUPPORT_SPL
 	select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT

@@ -64,6 +67,7 @@ config MACH_SUN8I_A33
 	select CPU_V7
 	select CPU_V7_HAS_NONSEC
 	select CPU_V7_HAS_VIRT
+	select ARCH_SUPPORT_PSCI
 	select SUNXI_GEN_SUN6I
 	select SUPPORT_SPL
 	select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT

@@ -79,6 +83,7 @@ config MACH_SUN8I_H3
 	select CPU_V7
 	select CPU_V7_HAS_NONSEC
 	select CPU_V7_HAS_VIRT
+	select ARCH_SUPPORT_PSCI
 	select SUNXI_GEN_SUN6I
 	select SUPPORT_SPL
 	select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT

include/configs/jetson-tk1.h +0 -1

index 2b172a5..1eba74a 100644
@@ -60,7 +60,6 @@
 #include "tegra-common-usb-gadget.h"
 #include "tegra-common-post.h"
 
-#define CONFIG_ARMV7_PSCI			1
 #define CONFIG_ARMV7_PSCI_NR_CPUS		4
 /* Reserve top 1M for secure RAM */
 #define CONFIG_ARMV7_SECURE_BASE		0xfff00000

include/configs/ls1021aqds.h +0 -1

index 47180f9..86969a1 100644
@@ -9,7 +9,6 @@
 
 #define CONFIG_LS102XA
 
-#define CONFIG_ARMV7_PSCI
 #define CONFIG_ARMV7_PSCI_1_0
 #define CONFIG_ARMV7_PSCI_NR_CPUS	CONFIG_MAX_CPUS

include/configs/ls1021atwr.h +0 -1

index 2f19950..d0fc7ff 100644
@@ -9,7 +9,6 @@
 
 #define CONFIG_LS102XA
 
-#define CONFIG_ARMV7_PSCI
 #define CONFIG_ARMV7_PSCI_1_0
 #define CONFIG_ARMV7_PSCI_NR_CPUS	CONFIG_MAX_CPUS

include/configs/mx7_common.h +0 -1

index 7295fa6..52c0d0f 100644
@@ -72,7 +72,6 @@
 #define CONFIG_CMD_FUSE
 #define CONFIG_MXC_OCOTP
 
-#define CONFIG_ARMV7_PSCI
 #define CONFIG_ARMV7_PSCI_NR_CPUS	2
 #define CONFIG_ARMV7_SECURE_BASE	0x00900000

include/configs/sun6i.h +0 -1

index 0625502..41552c4 100644
@@ -22,7 +22,6 @@
 
 #define CONFIG_SUNXI_USB_PHYS	3
 
-#define CONFIG_ARMV7_PSCI		1
 #define CONFIG_ARMV7_PSCI_NR_CPUS	4
 #define CONFIG_ARMV7_SECURE_BASE	SUNXI_SRAM_B_BASE
 #define CONFIG_ARMV7_SECURE_MAX_SIZE    (64 * 1024) /* 64 KB */

include/configs/sun7i.h +0 -1

index e9074d5..63760c5 100644
@@ -20,7 +20,6 @@
 
 #define CONFIG_SUNXI_USB_PHYS	3
 
-#define CONFIG_ARMV7_PSCI		1
 #define CONFIG_ARMV7_PSCI_NR_CPUS	2
 #define CONFIG_ARMV7_SECURE_BASE	SUNXI_SRAM_B_BASE
 #define CONFIG_ARMV7_SECURE_MAX_SIZE	(64 * 1024) /* 64 KB */

include/configs/sun8i.h +0 -1

index b9a8731..151ffdc 100644
@@ -27,7 +27,6 @@
 #endif
 
 #ifndef CONFIG_MACH_SUN8I_A83T
-#define CONFIG_ARMV7_PSCI		1
 #if defined(CONFIG_MACH_SUN8I_A23)
 #define CONFIG_ARMV7_PSCI_NR_CPUS	2
 #elif defined(CONFIG_MACH_SUN8I_A33)

include/configs/uniphier.h +0 -1

index 55ba99c..66696c2 100644
@@ -11,7 +11,6 @@
 #ifndef __CONFIG_UNIPHIER_COMMON_H__
 #define __CONFIG_UNIPHIER_COMMON_H__
 
-#define CONFIG_ARMV7_PSCI
 #define CONFIG_ARMV7_PSCI_1_0
 #define CONFIG_ARMV7_PSCI_NR_CPUS   4

Signature · 1 line

1.9.1

Masahiro Yamada

author

2016-09-07 00:53 UTC #9 lore raw

PATCH v2 3/4 ARM: armv7: move CONFIG_ARMV7_PSCI to Kconfig

Tom,

2016-08-30 16:22 GMT+09:00 Masahiro Yamada <[email protected]>:

Quoted 6 lines

Add ARCH_SUPPORT_PSCI as a non-configurable option that platforms can select. Then, move CONFIG_ARMV7_PSCI, which is automatically enabled if both ARMV7_NONSEC and ARCH_SUPPORT_PSCI are enabled.
Signed-off-by Masahiro Yamada <[email protected]>
---

If possible,
please add Alex's Reviewed-by to each patch of this series when applied.

Alex issued his tag in the cover letter, but I assume Patchwork cannot handle this automatically.
http://lists.denx.de/pipermail/u-boot/2016-September/265486.html

Signature · 2 lines

Best Regards
Masahiro Yamada

Tom Rini

2016-09-07 12:49 UTC #10 lore raw

PATCH v2 3/4 ARM: armv7: move CONFIG_ARMV7_PSCI to Kconfig

Quoted 11 lines · Masahiro Yamada

Tom,
2016-08-30 16:22 GMT+09:00 Masahiro Yamada <[email protected]>:
Quoted 6 lines
Add ARCH_SUPPORT_PSCI as a non-configurable option that platforms can select. Then, move CONFIG_ARMV7_PSCI, which is automatically enabled if both ARMV7_NONSEC and ARCH_SUPPORT_PSCI are enabled.
Signed-off-by Masahiro Yamada <[email protected]>
---

Quoted 8 lines

If possible,
please add Alex's Reviewed-by to each patch of this series when applied.
Alex issued his tag in the cover letter, but I assume Patchwork cannot handle this automatically.
http://lists.denx.de/pipermail/u-boot/2016-September/265486.html

Yes, stuff like that is still a work in progress, added, thanks!

Signature · 8 lines

Tom
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Tom Rini

2016-09-07 17:59 UTC #11 lore raw

PATCH v2 3/4 ARM: armv7: move CONFIG_ARMV7_PSCI to Kconfig

In reply to Masahiro Yamada

Quoted 5 lines · Masahiro Yamada

Add ARCH_SUPPORT_PSCI as a non-configurable option that platforms can select. Then, move CONFIG_ARMV7_PSCI, which is automatically enabled if both ARMV7_NONSEC and ARCH_SUPPORT_PSCI are enabled.
Signed-off-by Masahiro Yamada <[email protected]>

Applied to u-boot/master, thanks!

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Tom
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Tom Rini

2016-09-07 17:59 UTC #12 lore raw

PATCH v2 3/4 ARM: armv7: move CONFIG_ARMV7_PSCI to Kconfig

In reply to Masahiro Yamada

Quoted 5 lines · Masahiro Yamada

Add ARCH_SUPPORT_PSCI as a non-configurable option that platforms can select. Then, move CONFIG_ARMV7_PSCI, which is automatically enabled if both ARMV7_NONSEC and ARCH_SUPPORT_PSCI are enabled.
Signed-off-by Masahiro Yamada <[email protected]>

Applied to u-boot/master, thanks!

Signature · 8 lines

Tom
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Masahiro Yamada

author

2016-08-30 07:22 UTC #13 lore raw

PATCH v2 4/4 ARM: armv7: move ARMV7_PSCI_NR_CPUS to Kconfig

In reply to Masahiro Yamada

Move this option to Kconfig and set its default value to 4; this increases the number of supported CPUs for some boards.

It consumes 1KB memory per CPU for PSCI stack, but it should not be a big deal, given the amount of memory used for the modern OSes.

Signed-off-by Masahiro Yamada <[email protected]>

---

Changes in v2:
- Add help to the Kconfig entry

 arch/arm/cpu/armv7/Kconfig          |  9 +++++++++
 include/configs/arndale.h           |  1 -
 include/configs/bcm_ep_board.h      |  1 -
 include/configs/jetson-tk1.h        |  1 -
 include/configs/ls1021aqds.h        |  1 -
 include/configs/ls1021atwr.h        |  1 -
 include/configs/mx7_common.h        |  1 -
 include/configs/sun6i.h             |  1 -
 include/configs/sun7i.h             |  1 -
 include/configs/sun8i.h             | 12 ------------
 include/configs/uniphier.h          |  1 -
 include/configs/vexpress_ca15_tc2.h |  1 -
 12 files changed, 9 insertions(+), 22 deletions(-)

arch/arm/cpu/armv7/Kconfig +9 -0

index 4390f59..b9c4f4e 100644
@@ -41,6 +41,15 @@ config ARMV7_PSCI
 	help
 	  Say Y here to enable PSCI support.
 
+config ARMV7_PSCI_NR_CPUS
+	int "Maximum supported CPUs for PSCI"
+	depends on ARMV7_NONSEC
+	default 4
+	help
+	  The maximum number of CPUs supported in the PSCI firmware.
+	  It is no problem to set a larger value than the number of
+	  CPUs in the actual hardware implementation.
+
 config ARMV7_LPAE
 	bool "Use LPAE page table format" if EXPERT
 	depends on CPU_V7

include/configs/arndale.h +0 -1

index 18e59fc..b08f341 100644
@@ -45,7 +45,6 @@
 
 #define CONFIG_S5P_PA_SYSRAM	0x02020000
 #define CONFIG_SMP_PEN_ADDR	CONFIG_S5P_PA_SYSRAM
-#define CONFIG_ARMV7_PSCI_NR_CPUS	4
 
 /* The PERIPHBASE in the CBAR register is wrong on the Arndale, so override it */
 #define CONFIG_ARM_GIC_BASE_ADDRESS	0x10480000

include/configs/bcm_ep_board.h +0 -1

index b5e5029..4b255d8 100644
@@ -91,6 +91,5 @@
 /* Misc utility code */
 #define CONFIG_BOUNCE_BUFFER
 #define CONFIG_CRC32_VERIFY
-#define CONFIG_ARMV7_PSCI_NR_CPUS	4
 
 #endif /* __BCM_EP_BOARD_H */

include/configs/jetson-tk1.h +0 -1

index 1eba74a..7c59790 100644
@@ -60,7 +60,6 @@
 #include "tegra-common-usb-gadget.h"
 #include "tegra-common-post.h"
 
-#define CONFIG_ARMV7_PSCI_NR_CPUS		4
 /* Reserve top 1M for secure RAM */
 #define CONFIG_ARMV7_SECURE_BASE		0xfff00000
 #define CONFIG_ARMV7_SECURE_RESERVE_SIZE	0x00100000

include/configs/ls1021aqds.h +0 -1

index 86969a1..abbd1c4 100644
@@ -10,7 +10,6 @@
 #define CONFIG_LS102XA
 
 #define CONFIG_ARMV7_PSCI_1_0
-#define CONFIG_ARMV7_PSCI_NR_CPUS	CONFIG_MAX_CPUS
 
 #define CONFIG_ARMV7_SECURE_BASE	OCRAM_BASE_S_ADDR

include/configs/ls1021atwr.h +0 -1

index d0fc7ff..511b0b3 100644
@@ -10,7 +10,6 @@
 #define CONFIG_LS102XA
 
 #define CONFIG_ARMV7_PSCI_1_0
-#define CONFIG_ARMV7_PSCI_NR_CPUS	CONFIG_MAX_CPUS
 
 #define CONFIG_ARMV7_SECURE_BASE	OCRAM_BASE_S_ADDR

include/configs/mx7_common.h +0 -1

index 52c0d0f..4b1077c 100644
@@ -72,7 +72,6 @@
 #define CONFIG_CMD_FUSE
 #define CONFIG_MXC_OCOTP
 
-#define CONFIG_ARMV7_PSCI_NR_CPUS	2
 #define CONFIG_ARMV7_SECURE_BASE	0x00900000
 
 #endif

include/configs/sun6i.h +0 -1

index 41552c4..67a26c2 100644
@@ -22,7 +22,6 @@
 
 #define CONFIG_SUNXI_USB_PHYS	3
 
-#define CONFIG_ARMV7_PSCI_NR_CPUS	4
 #define CONFIG_ARMV7_SECURE_BASE	SUNXI_SRAM_B_BASE
 #define CONFIG_ARMV7_SECURE_MAX_SIZE    (64 * 1024) /* 64 KB */

include/configs/sun7i.h +0 -1

index 63760c5..d8e6e20 100644
@@ -20,7 +20,6 @@
 
 #define CONFIG_SUNXI_USB_PHYS	3
 
-#define CONFIG_ARMV7_PSCI_NR_CPUS	2
 #define CONFIG_ARMV7_SECURE_BASE	SUNXI_SRAM_B_BASE
 #define CONFIG_ARMV7_SECURE_MAX_SIZE	(64 * 1024) /* 64 KB */

include/configs/sun8i.h +0 ~~-12~~

index 151ffdc..011d70f 100644
@@ -26,18 +26,6 @@
 	#define CONFIG_SUNXI_USB_PHYS	2
 #endif
 
-#ifndef CONFIG_MACH_SUN8I_A83T
-#if defined(CONFIG_MACH_SUN8I_A23)
-#define CONFIG_ARMV7_PSCI_NR_CPUS	2
-#elif defined(CONFIG_MACH_SUN8I_A33)
-#define CONFIG_ARMV7_PSCI_NR_CPUS	4
-#elif defined(CONFIG_MACH_SUN8I_H3)
-#define CONFIG_ARMV7_PSCI_NR_CPUS	4
-#else
-#error Unsupported sun8i variant
-#endif
-#endif
-
 /*
  * Include common sunxi configuration where most the settings are
  */

include/configs/uniphier.h +0 -1

index 66696c2..b3ca46b 100644
@@ -12,7 +12,6 @@
 #define __CONFIG_UNIPHIER_COMMON_H__
 
 #define CONFIG_ARMV7_PSCI_1_0
-#define CONFIG_ARMV7_PSCI_NR_CPUS   4
 
 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS  10

include/configs/vexpress_ca15_tc2.h +0 -1

index 9583e8c..b509a9c 100644
@@ -16,6 +16,5 @@
 
 #define CONFIG_SYSFLAGS_ADDR	0x1c010030
 #define CONFIG_SMP_PEN_ADDR	CONFIG_SYSFLAGS_ADDR
-#define CONFIG_ARMV7_PSCI_NR_CPUS	4
 
 #endif

Signature · 1 line

1.9.1

Tom Rini

2016-09-07 17:59 UTC #14 lore raw

PATCH v2 4/4 ARM: armv7: move ARMV7_PSCI_NR_CPUS to Kconfig

Quoted 7 lines · Masahiro Yamada

Move this option to Kconfig and set its default value to 4; this increases the number of supported CPUs for some boards.
It consumes 1KB memory per CPU for PSCI stack, but it should not be a big deal, given the amount of memory used for the modern OSes.
Signed-off-by Masahiro Yamada <[email protected]>

Applied to u-boot/master, thanks!

Signature · 8 lines

Tom
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Alexander Graf

2016-09-01 13:45 UTC #15 lore raw

v2 cover ARM: move ARMV7_PSCI and ARMV7_PSCI_NR_CPUS to Kconfig

In reply to Masahiro Yamada

Quoted 6 lines · Masahiro Yamada

Masahiro Yamada (4):
ARM: tegra: remove wrong dependency on SPL_BUILD
ARM: armv7: guard memory reserve for PSCI with #ifdef
CONFIG_ARMV7_PSCI
ARM: armv7: move CONFIG_ARMV7_PSCI to Kconfig
ARM: armv7: move ARMV7_PSCI_NR_CPUS to Kconfig

Reviewed-by Alexander Graf <[email protected]>

If you want to make me happier next time, write up a description on what the patch set is about in the cover letter :)

Alex