Add ZTE ZX296718 support

Add device tree support for ZX296718 SoC and evaluation board based on it.

Also document new values.

Signed-off-by Jun Nie <[email protected]>

---
 Documentation/devicetree/bindings/arm/zte.txt |  24 +++
 arch/arm64/boot/dts/Makefile                  |   1 +
 arch/arm64/boot/dts/zte/Makefile              |   5 +
 arch/arm64/boot/dts/zte/zx296718-evb.dts      |  25 +++
 arch/arm64/boot/dts/zte/zx296718.dtsi         | 254 ++++++++++++++++++++++++++
 5 files changed, 309 insertions(+)
 create mode 100644 arch/arm64/boot/dts/zte/Makefile
 create mode 100644 arch/arm64/boot/dts/zte/zx296718-evb.dts
 create mode 100644 arch/arm64/boot/dts/zte/zx296718.dtsi

arch/arm64/boot/dts/zte/Makefile new file +5 -0

new file mode 100644
index 0000000..6678066
@@ -0,0 +1,5 @@
+dtb-$(CONFIG_ARCH_ZX) += zx296718-evb.dtb
+
+always		:= $(dtb-y)
+subdir-y	:= $(dts-dirs)
+clean-files	:= *.dtb

arch/arm64/boot/dts/zte/zx296718-evb.dts new file +0 -0

new file mode 100644
index 0000000..d7cefb4

arch/arm64/boot/dts/zte/zx296718-evb.dts new file +21 -0

+/dts-v1/;
+#include "zx296718.dtsi"
+
+/ {
+	model = "ZTE zx296718 evaluation board";
+	compatible = "zte,zx296718-evb", "zte,zx296718";
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+
+	memory at 40000000 {
+		device_type = "memory";
+		reg = <0x40000000 0x40000000>;
+	};
+
+};
+
+&uart0 {
+	status = "okay";
+};

arch/arm64/boot/dts/zte/zx296718.dtsi new file +0 -0

new file mode 100644
index 0000000..c75a819

arch/arm64/boot/dts/zte/zx296718.dtsi new file +75 -0

+#include <dt-bindings/input/input.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+	compatible = "zte,zx296718";
+	#address-cells = <1>;
+	#size-cells = <1>;
+
+	aliases {
+		serial0 = &uart0;
+	};
+
+	cpus {
+		#address-cells = <2>;
+		#size-cells = <0>;
+
+		cpu-map {
+			cluster0 {
+				core0 {
+					cpu = <&cpu0>;
+				};
+				core1 {
+					cpu = <&cpu1>;
+				};
+				core2 {
+					cpu = <&cpu2>;
+				};
+				core3 {
+					cpu = <&cpu3>;
+				};
+			};
+		};
+
+		cpu0: cpu at 0 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a53","arm,armv8";
+			reg = <0x0 0x0>;
+			enable-method = "psci";
+		};
+
+		cpu1: cpu at 1 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a53","arm,armv8";
+			reg = <0x0 0x1>;
+			enable-method = "psci";
+		};
+
+		cpu2: cpu at 2 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a53","arm,armv8";
+			reg = <0x0 0x2>;
+			enable-method = "psci";
+		};
+
+		cpu3: cpu at 3 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a53","arm,armv8";
+			reg = <0x0 0x3>;
+			enable-method = "psci";
+		};
+	};
+
+	osc12m: osc12m-clk {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <12000000>;
+		clock-output-names = "osc12m";
+	};
+
+	osc24m: osc24m-clk {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <24000000>;
+		clock-output-names = "osc24m";

arch/arm64/boot/dts/zte/zx296718.dtsi new file +79 -0

+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <24000>;
+		clock-output-names = "rtcclk";
+	};
+
+	osc32k: osc32k-clk {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <32000>;
+		clock-output-names = "osc32k";
+	};
+
+	osc60m: osc60m-clk {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <60000000>;
+		clock-output-names = "osc60m";
+	};
+
+	osc99m: osc99m-clk {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <99000000>;
+		clock-output-names = "osc99m";
+	};
+
+	osc125m: osc125m-clk {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <125000000>;
+		clock-output-names = "osc125m";
+	};
+
+	osc198m: osc198m-clk {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <198000000>;
+		clock-output-names = "osc198m";
+	};
+
+	pll_vga: pll-1073m-clk {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <1073000000>;
+		clock-output-names = "pll_vga";
+	};
+
+	pll_ddr: pll-932m-clk {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <932000000>;
+		clock-output-names = "pll_ddr";
+	};
+
+	pll_mac: pll-1000m-clk {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <1000000000>;
+		clock-output-names = "pll_mac";
+	};
+
+	pll_mm0: pll-1188m-clk {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <1188000000>;
+		clock-output-names = "pll_mm0";
+	};
+
+	pll_mm1: pll-1296m-clk {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <1296000000>;
+		clock-output-names = "pll_mm1";
+	};
+
+	pll_audio: pll-884m-clk {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;

This version looks pretty good to me. Some nit-picks below though ...

Quoted 1 line · Jun Nie

Add device tree support for ZX296718 SoC and evaluation board based on it.

Please wrap the commit log around column 70.

Quoted 13 lines

Also document new values.

Signed-off-by Jun Nie <[email protected]>

---
 Documentation/devicetree/bindings/arm/zte.txt |  24 +++
 arch/arm64/boot/dts/Makefile                  |   1 +
 arch/arm64/boot/dts/zte/Makefile              |   5 +
 arch/arm64/boot/dts/zte/zx296718-evb.dts      |  25 +++
 arch/arm64/boot/dts/zte/zx296718.dtsi         | 254 ++++++++++++++++++++++++++
 5 files changed, 309 insertions(+)
 create mode 100644 arch/arm64/boot/dts/zte/Makefile
 create mode 100644 arch/arm64/boot/dts/zte/zx296718-evb.dts
 create mode 100644 arch/arm64/boot/dts/zte/zx296718.dtsi

<snip>

Quoted 17 lines

arch/arm64/boot/dts/zte/Makefile new file +5 -0

new file mode 100644
index 0000000..6678066
@@ -0,0 +1,5 @@
+dtb-$(CONFIG_ARCH_ZX) += zx296718-evb.dtb
+
+always               := $(dtb-y)
+subdir-y     := $(dts-dirs)
+clean-files  := *.dtb

arch/arm64/boot/dts/zte/zx296718-evb.dts new file +0 -0

new file mode 100644
index 0000000..d7cefb4
@@ -0,0 +1,25 @@

arch/arm64/boot/dts/zte/zx296718-evb.dts line 4

Quoted 4 lines

arch/arm64/boot/dts/zte/zx296718-evb.dts new file +4 -0

+/*
+ * ZTE Ltd. zx296718 Plaform
+ *
+ */

We should probably consider to add a proper licence. GPL/X11 dual is mostly used and recommended, and there are quite a lot examples in the DTS folder.

Quoted 26 lines

arch/arm64/boot/dts/zte/zx296718-evb.dts new file +21 -0

+/dts-v1/;
+#include "zx296718.dtsi"
+
+/ {
+     model = "ZTE zx296718 evaluation board";
+     compatible = "zte,zx296718-evb", "zte,zx296718";
+
+     chosen {
+             stdout-path = "serial0:115200n8";
+     };
+
+     memory at 40000000 {
+             device_type = "memory";
+             reg = <0x40000000 0x40000000>;
+     };
+
+};
+
+&uart0 {
+     status = "okay";
+};

arch/arm64/boot/dts/zte/zx296718.dtsi new file +0 -0

new file mode 100644
index 0000000..c75a819

arch/arm64/boot/dts/zte/zx296718.dtsi line 5

Quoted 6 lines

arch/arm64/boot/dts/zte/zx296718.dtsi new file +5 -0

@@ -0,0 +1,254 @@
+/*
+ * DTS File for ZTE ZX296718 Plaform
+ *
+ * Copyright (c) 2016 ZTE Semiconductor Co., Ltd.
+ */

Ditto

Quoted 81 lines

arch/arm64/boot/dts/zte/zx296718.dtsi new file +80 -0

+#include <dt-bindings/input/input.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+     compatible = "zte,zx296718";
+     #address-cells = <1>;
+     #size-cells = <1>;
+
+     aliases {
+             serial0 = &uart0;
+     };
+
+     cpus {
+             #address-cells = <2>;
+             #size-cells = <0>;
+
+             cpu-map {
+                     cluster0 {
+                             core0 {
+                                     cpu = <&cpu0>;
+                             };
+                             core1 {
+                                     cpu = <&cpu1>;
+                             };
+                             core2 {
+                                     cpu = <&cpu2>;
+                             };
+                             core3 {
+                                     cpu = <&cpu3>;
+                             };
+                     };
+             };
+
+             cpu0: cpu at 0 {
+                     device_type = "cpu";
+                     compatible = "arm,cortex-a53","arm,armv8";
+                     reg = <0x0 0x0>;
+                     enable-method = "psci";
+             };
+
+             cpu1: cpu at 1 {
+                     device_type = "cpu";
+                     compatible = "arm,cortex-a53","arm,armv8";
+                     reg = <0x0 0x1>;
+                     enable-method = "psci";
+             };
+
+             cpu2: cpu at 2 {
+                     device_type = "cpu";
+                     compatible = "arm,cortex-a53","arm,armv8";
+                     reg = <0x0 0x2>;
+                     enable-method = "psci";
+             };
+
+             cpu3: cpu at 3 {
+                     device_type = "cpu";
+                     compatible = "arm,cortex-a53","arm,armv8";
+                     reg = <0x0 0x3>;
+                     enable-method = "psci";
+             };
+     };
+
+     osc12m: osc12m-clk {
+             compatible = "fixed-clock";
+             #clock-cells = <0>;
+             clock-frequency = <12000000>;
+             clock-output-names = "osc12m";
+     };
+
+     osc24m: osc24m-clk {
+             compatible = "fixed-clock";
+             #clock-cells = <0>;
+             clock-frequency = <24000000>;
+             clock-output-names = "osc24m";
+     };
+
+     osc25m: osc25m-clk {
+             compatible = "fixed-clock";
+             #clock-cells = <0>;

arch/arm64/boot/dts/zte/zx296718.dtsi line 90

Quoted 5 lines

arch/arm64/boot/dts/zte/zx296718.dtsi new file +5 -0

+             clock-frequency = <25000000>;
+             clock-output-names = "osc25m";
+     };
+
+     clk24k: clk-24k {

I would suggest we name node of fixed rate clock in an unified way like clock-xxx.

Quoted 84 lines

arch/arm64/boot/dts/zte/zx296718.dtsi new file +84 -0

+             compatible = "fixed-clock";
+             #clock-cells = <0>;
+             clock-frequency = <24000>;
+             clock-output-names = "rtcclk";
+     };
+
+     osc32k: osc32k-clk {
+             compatible = "fixed-clock";
+             #clock-cells = <0>;
+             clock-frequency = <32000>;
+             clock-output-names = "osc32k";
+     };
+
+     osc60m: osc60m-clk {
+             compatible = "fixed-clock";
+             #clock-cells = <0>;
+             clock-frequency = <60000000>;
+             clock-output-names = "osc60m";
+     };
+
+     osc99m: osc99m-clk {
+             compatible = "fixed-clock";
+             #clock-cells = <0>;
+             clock-frequency = <99000000>;
+             clock-output-names = "osc99m";
+     };
+
+     osc125m: osc125m-clk {
+             compatible = "fixed-clock";
+             #clock-cells = <0>;
+             clock-frequency = <125000000>;
+             clock-output-names = "osc125m";
+     };
+
+     osc198m: osc198m-clk {
+             compatible = "fixed-clock";
+             #clock-cells = <0>;
+             clock-frequency = <198000000>;
+             clock-output-names = "osc198m";
+     };
+
+     pll_vga: pll-1073m-clk {
+             compatible = "fixed-clock";
+             #clock-cells = <0>;
+             clock-frequency = <1073000000>;
+             clock-output-names = "pll_vga";
+     };
+
+     pll_ddr: pll-932m-clk {
+             compatible = "fixed-clock";
+             #clock-cells = <0>;
+             clock-frequency = <932000000>;
+             clock-output-names = "pll_ddr";
+     };
+
+     pll_mac: pll-1000m-clk {
+             compatible = "fixed-clock";
+             #clock-cells = <0>;
+             clock-frequency = <1000000000>;
+             clock-output-names = "pll_mac";
+     };
+
+     pll_mm0: pll-1188m-clk {
+             compatible = "fixed-clock";
+             #clock-cells = <0>;
+             clock-frequency = <1188000000>;
+             clock-output-names = "pll_mm0";
+     };
+
+     pll_mm1: pll-1296m-clk {
+             compatible = "fixed-clock";
+             #clock-cells = <0>;
+             clock-frequency = <1296000000>;
+             clock-output-names = "pll_mm1";
+     };
+
+     pll_audio: pll-884m-clk {
+             compatible = "fixed-clock";
+             #clock-cells = <0>;
+             clock-frequency = <884000000>;
+             clock-output-names = "pll_audio";
+     };
+
+     pll_hsic: pll-960m-clk {

arch/arm64/boot/dts/zte/zx296718.dtsi line 179

Quoted 5 lines

arch/arm64/boot/dts/zte/zx296718.dtsi new file +5 -0

+             compatible = "fixed-clock";
+             #clock-cells = <0>;
+             clock-frequency = <960000000>;
+             clock-output-names = "pll_hsic";
+     };

Do we really have so many uncontrolled clocks with fixed rate in the SoC?

Shawn

PLL clocks can be configured actually according to register. But I prefer to keep them as fixed clocks due to two reasons:
1. ZTE do not want to expose too much information of PLL.
2. All clients blocks, such as MMC and video codec, assume the
related input clock's frequency as a derivation from PLL default frequency value in block clock control register description.

arch/arm64/boot/dts/zte/zx296718.dtsi new file +37 -0

+
+		aon_sysctrl: aon-sysctrl at 116000 {
+			compatible = "zte,zx296718-aon-sysctrl", "syscon";
+			reg = <0x116000 0x1000>;
+		};
+
+		uart0: uart at 11f000 {
+			compatible = "arm,pl011", "arm,primecell";
+			arm,primecell-periphid = <0x001feffe>;
+			reg = <0x11f000 0x1000>;
+			interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&osc24m>;
+			clock-names = "apb_pclk";
+			status = "disabled";
+		};
+
+		dma: dma-controller at 1460000 {
+			compatible = "zte,zx296702-dma";
+			reg = <0x01460000 0x1000>;
+			interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&osc24m>;
+			clock-names = "dmaclk";
+			#dma-cells = <1>;
+			dma-channels = <32>;
+			dma-requests = <32>;
+		};
+
+		sysctrl: sysctrl at 1463000 {
+			compatible = "zte,zx296718-sysctrl", "syscon";
+			reg = <0x1463000 0x1000>;
+		};
+
+		gic: interrupt-controller at 2a00000 {
+			compatible = "arm,gic-v3";
+			#interrupt-cells = <3>;
+			#address-cells = <0>;
+			#redistributor-regions = <6>;

arch/arm64/boot/dts/zte/zx296718-evb.dts new file +3 -0

+		};
+	};
+};

Signature · 7 lines

1.9.1


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A bit more comments as below ...

arch/arm64/boot/dts/zte/zx296718.dtsi line 198

Quoted 13 lines · Jun Nie

arch/arm64/boot/dts/zte/zx296718.dtsi new file +13 -0

+	soc {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "simple-bus";
+		interrupt-parent = <&gic>;
+		ranges;
+
+		timer {
+			compatible = "arm,armv8-timer";
+			interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
+				     <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
+				     <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
+				     <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;

Affinity bits are missing for PPI interrupt. You can use a bit help from defines in include/dt-bindings/interrupt-controller/arm-gic.h.