firmware: add driver for lpc18xx boot ROM

PATCH New Joachim Eastwood 3 participants 10 messages Sep 13, 2016 – Oct 8, 2016

Subsystems (3)

Device tree bindings Arm i.MX and Layerscape Arm/LPC18XX architecture

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Joachim Eastwood

author

2016-09-13 19:51 UTC #0 lore raw

cover firmware: add driver for lpc18xx boot ROM

This patch set adds a firmware driver for the boot ROM found on all NXP LPC18xx/43xx devices. The boot ROM contains serveral APIs that is used to retrive device specific information and program the internal Flash and OTP memories.

For now this driver only uses the API in the boot ROM to expose device information via a 'SoC device'. Support for Flash and OTP programming will be added later.

Also note that not all APIs are avaliable on all devices. The IAP API that is used to retrive device information is only avaliable on devices with Flash. Flashless devices retrive information from OTP memory. To determin if IAP is avaliable one must check a specific register in the CREG (syscon) block.

I intend to take this patch set via arm-soc/drivers through my lpc18xx tree for 4.10.

Joachim Eastwood (3):
firmware: add lpc18xx boot rom driver
firmware: dt: document lpc1850 boot ROM bindings
ARM: dts: lpc18xx: add boot rom node

 .../devicetree/bindings/firmware/nxp,boot-rom.txt  |  21 ++
 arch/arm/boot/dts/lpc18xx.dtsi                     |   8 +
 drivers/firmware/Kconfig                           |  12 +
 drivers/firmware/Makefile                          |   1 +
 drivers/firmware/nxp_lpc_boot_rom.c                | 411 +++++++++++++++++++++
 5 files changed, 453 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/firmware/nxp,boot-rom.txt
 create mode 100644 drivers/firmware/nxp_lpc_boot_rom.c

Signature · 1 line

2.9.3

Joachim Eastwood

author

2016-09-13 19:51 UTC #1 lore raw

PATCH 1/3 firmware: add lpc18xx boot rom driver

Firmware driver for the boot ROM found on all NXP LPC18xx/43xx devices. This driver makes it possible to retrieve device specific information from either the ROM via API calls or from OTP memory.

The boot ROM contains several APIs for on-chip devices. Note that not all APIs are available on all devices. The API to retrieve device information and internal Flash programming (IAP) is only available on devices with Flash. Flashless devices retrieve device information from OTP memory. The CHIPID register in CREG (syscon) is used to check if IAP is available.

For now this driver is only used to expose device information via a 'SoC device'. Linux API for the IAP and OTP will be added later. These two APIs will be used by a Flash MTD driver and a OTP NVMEM driver to program the memory.

Signed-off-by Joachim Eastwood <[email protected]>

---
 drivers/firmware/Kconfig            |  12 ++
 drivers/firmware/Makefile           |   1 +
 drivers/firmware/nxp_lpc_boot_rom.c | 411 ++++++++++++++++++++++++++++++++++++
 3 files changed, 424 insertions(+)
 create mode 100644 drivers/firmware/nxp_lpc_boot_rom.c

drivers/firmware/Kconfig +12 -0

index 0e22f24..904f727 100644
@@ -163,6 +163,18 @@ config ISCSI_IBFT
 	  detect iSCSI boot parameters dynamically during system boot, say Y.
 	  Otherwise, say N.
 
+config NXP_LPC_BOOT_ROM
+	tristate "NXP LPC boot ROM API"
+	depends on ARCH_LPC18XX || COMPILE_TEST
+	depends on OF && HAS_IOMEM && NVMEM
+	select MFD_SYSCON
+	select SOC_BUS
+	help
+	  This option enables support for using the API in the boot ROM
+	  present on NXP LPC18xx and LPC43xx devices. This is required
+	  to retrieve part specific information and for writing to the
+	  internal Flash and OTP memories.
+
 config RASPBERRYPI_FIRMWARE
 	tristate "Raspberry Pi Firmware Driver"
 	depends on BCM2835_MBOX

drivers/firmware/Makefile +1 -0

index 44a59dc..0060afd 100644
@@ -14,6 +14,7 @@ obj-$(CONFIG_DMIID)		+= dmi-id.o
 obj-$(CONFIG_ISCSI_IBFT_FIND)	+= iscsi_ibft_find.o
 obj-$(CONFIG_ISCSI_IBFT)	+= iscsi_ibft.o
 obj-$(CONFIG_FIRMWARE_MEMMAP)	+= memmap.o
+obj-$(CONFIG_NXP_LPC_BOOT_ROM)	+= nxp_lpc_boot_rom.o
 obj-$(CONFIG_RASPBERRYPI_FIRMWARE) += raspberrypi.o
 obj-$(CONFIG_FW_CFG_SYSFS)	+= qemu_fw_cfg.o
 obj-$(CONFIG_QCOM_SCM)		+= qcom_scm.o

drivers/firmware/nxp_lpc_boot_rom.c new file +411 -0

411 lines not on this page · raw message

Signature · 1 line

2.9.3

Vladimir Zapolskiy

maintainer

2016-10-07 01:42 UTC #2 lore raw

PATCH 1/3 firmware: add lpc18xx boot rom driver

Hi Joachim,

Quoted 11 lines · Joachim Eastwood

Firmware driver for the boot ROM found on all NXP LPC18xx/43xx devices. This driver makes it possible to retrieve device specific information from either the ROM via API calls or from OTP memory.
The boot ROM contains several APIs for on-chip devices. Note that not all APIs are available on all devices. The API to retrieve device information and internal Flash programming (IAP) is only available on devices with Flash. Flashless devices retrieve device information from OTP memory. The CHIPID register in CREG (syscon) is used to check if IAP is available.

Quoted 6 lines

For now this driver is only used to expose device information via a 'SoC device'. Linux API for the IAP and OTP will be added later. These two APIs will be used by a Flash MTD driver and a OTP NVMEM driver to program the memory.
Signed-off-by Joachim Eastwood <[email protected]>

please feel free to add to the series my

Tested-by Vladimir Zapolskiy <[email protected]>

Reviewed-by Vladimir Zapolskiy <[email protected]>

I tested the change on a board powered by LPC4357.

Nevertheless I have some nitpicks for your consideration.

And the first one is that I'm not totally convinced that drivers/firmware is the proper place for the driver, I tend to think that it might be a good time to create drivers/soc/nxp/

Quoted 7 lines

---
 drivers/firmware/Kconfig            |  12 ++
 drivers/firmware/Makefile           |   1 +
 drivers/firmware/nxp_lpc_boot_rom.c | 411 ++++++++++++++++++++++++++++++++++++
 3 files changed, 424 insertions(+)
 create mode 100644 drivers/firmware/nxp_lpc_boot_rom.c

[snip]

Quoted 10 lines

drivers/firmware/nxp_lpc_boot_rom.c new file +10 -0

+/* LPC18xx/43xx CREG (syscon) defines */
+#define LPC18XX_CREG_CHIPID		0x200
+#define LPC18XX_FLASH_CHIPID0		0x4284e02b
+#define LPC18XX_FLASH_CHIPID1		0x7284e02b
+#define LPC18XX_FLASHLESS_CHIPID0	0x5284e02b
+#define LPC18XX_FLASHLESS_CHIPID1	0x6284e02b
+#define LPC43XX_FLASH_CHIPID0		0x4906002b
+#define LPC43XX_FLASH_CHIPID1		0x7906002b
+#define LPC43XX_FLASHLESS_CHIPID0	0x5906002b
+#define LPC43XX_FLASHLESS_CHIPID1	0x6906002b

drivers/firmware/nxp_lpc_boot_rom.c line 75

Quoted 10 lines

drivers/firmware/nxp_lpc_boot_rom.c new file +10 -0

+
+#define NXP_PART_LPC(_num, _id0, _id1, _sz0, _sz1)	\
+	{						\
+		.name = "LPC"#_num,			\
+		.id[0] = _id0, .id[1] = _id1,		\
+		.flash_size[0] = _sz0 * 1024,		\
+		.flash_size[1] = _sz1 * 1024,		\
+	}
+
+

checkpatch complains:

CHECK: Please don't use multiple blank lines #145: FILE: drivers/firmware/nxp_lpc_boot_rom.c:75:
+
+

drivers/firmware/nxp_lpc_boot_rom.c line 78

Quoted 3 lines

drivers/firmware/nxp_lpc_boot_rom.c new file +3 -0
+struct nxp_lpc_part {
+	const char *name;
+	u16 flash_size[2];

flash_size[2] is set by NXP_PART_LPC() macro but unused, however in my build environment (W=1 and sparse checks) I get tons of legitimate compile time warnings:

drivers/firmware/nxp_lpc_boot_rom.c:93:9: warning: cast truncates bits from constant value (80000 becomes 0) drivers/firmware/nxp_lpc_boot_rom.c:93:9: warning: cast truncates bits from constant value (80000 becomes 0) drivers/firmware/nxp_lpc_boot_rom.c:94:9: warning: cast truncates bits from constant value (80000 becomes 0) drivers/firmware/nxp_lpc_boot_rom.c:94:9: warning: cast truncates bits from constant value (80000 becomes 0)
....

drivers/firmware/nxp_lpc_boot_rom.c:93:2: warning: large integer implicitly truncated to unsigned type [-Woverflow]
NXP_PART_LPC(1857, 0xf001d830, 0x00, 512, 512),
^
drivers/firmware/nxp_lpc_boot_rom.c:93:2: warning: large integer implicitly truncated to unsigned type [-Woverflow] drivers/firmware/nxp_lpc_boot_rom.c:94:2: warning: large integer implicitly truncated to unsigned type [-Woverflow]
NXP_PART_LPC(18S57, 0xf001d860, 0x00, 512, 512),
^
....

and so on.

Please consider either to store flash size in kB or change storage type to u32.

Quoted 52 lines

drivers/firmware/nxp_lpc_boot_rom.c new file +52 -0

+	u32 id[2];
+};
+
+static const struct nxp_lpc_part nxp_lpc_parts[] = {
+	/* LPC18xx Flashless parts */
+	NXP_PART_LPC(1850,  0xf000d830, 0x00,   0,   0),
+	NXP_PART_LPC(18S50, 0xf000d860, 0x00,   0,   0),
+	NXP_PART_LPC(1830,  0xf000da30, 0x00,   0,   0),
+	NXP_PART_LPC(18S30, 0xf000da60, 0x00,   0,   0),
+	NXP_PART_LPC(1820,  0xf00adb3c, 0x00,   0,   0),
+	NXP_PART_LPC(18S20, 0xf00adb6c, 0x00,   0,   0),
+	NXP_PART_LPC(1810,  0xf00b5b3f, 0x00,   0,   0),
+	NXP_PART_LPC(18S10, 0xf00b5b6f, 0x00,   0,   0),
+	/* LPC18xx Flash parts */
+	NXP_PART_LPC(1857,  0xf001d830, 0x00, 512, 512),
+	NXP_PART_LPC(18S57, 0xf001d860, 0x00, 512, 512),
+	NXP_PART_LPC(1853,  0xf001d830, 0x44, 256, 256),
+	NXP_PART_LPC(1837,  0xf001da30, 0x00, 512, 512),
+	NXP_PART_LPC(18S37, 0xf001d860, 0x00, 512, 512),
+	NXP_PART_LPC(1833,  0xf001da30, 0x44, 256, 256),
+	NXP_PART_LPC(1827,  0xf001db3c, 0x00, 512, 512),
+	NXP_PART_LPC(1825,  0xf001db3c, 0x22, 384, 384),
+	NXP_PART_LPC(1823,  0xf00bdb3c, 0x44, 256, 256),
+	NXP_PART_LPC(1822,  0xf00bdb3c, 0x80, 512,   0),
+	NXP_PART_LPC(1817,  0xf001db3f, 0x00, 512, 512),
+	NXP_PART_LPC(1815,  0xf001db3f, 0x22, 384, 384),
+	NXP_PART_LPC(1813,  0xf00bdb3f, 0x44, 256, 256),
+	NXP_PART_LPC(1812,  0xf00bdb3f, 0x80, 512,   0),
+	/* LPC43xx Flashless parts */
+	NXP_PART_LPC(4370,  0x00000030, 0x00,   0,   0), /* LBGA256 */
+	NXP_PART_LPC(4370,  0x00000230, 0x00,   0,   0), /* TFBGA100 */
+	NXP_PART_LPC(43S70, 0x00000060, 0x00,   0,   0),
+	NXP_PART_LPC(4350,  0xa0000830, 0x00,   0,   0),
+	NXP_PART_LPC(43S50, 0xa0000860, 0x00,   0,   0),
+	NXP_PART_LPC(4330,  0xa0000a30, 0x00,   0,   0),
+	NXP_PART_LPC(43S30, 0xa0000a60, 0x00,   0,   0),
+	NXP_PART_LPC(4320,  0xa000cb3c, 0x00,   0,   0),
+	NXP_PART_LPC(43S20, 0xa000cb6c, 0x00,   0,   0),
+	NXP_PART_LPC(4310,  0xa00acb3f, 0x00,   0,   0),
+	/* LPC43xx parts with Flash */
+	NXP_PART_LPC(4367,  0x8001c030, 0x00, 512, 512),
+	NXP_PART_LPC(43S67, 0x8001c060, 0x00, 512, 512),
+	NXP_PART_LPC(4357,  0xa001c830, 0x00, 512, 512),
+	NXP_PART_LPC(43S57, 0xa001c860, 0x00, 512, 512), /* LBGA256 */
+	NXP_PART_LPC(43S57, 0xa001ca60, 0x00, 512, 512), /* LQFP208 */
+	NXP_PART_LPC(4353,  0xa001c830, 0x44, 256, 256),
+	NXP_PART_LPC(4337,  0xa001ca30, 0x00, 512, 512),
+	NXP_PART_LPC(43S37, 0xa001ca60, 0x00, 512, 512),
+	NXP_PART_LPC(4333,  0xa001ca30, 0x44, 256, 256),
+	NXP_PART_LPC(4327,  0xa001cb3c, 0x00, 512, 512),
+	NXP_PART_LPC(4325,  0xa001cb3c, 0x22, 384, 384),
+	NXP_PART_LPC(4323,  0xa00bcb3c, 0x44, 256, 256),

drivers/firmware/nxp_lpc_boot_rom.c line 140

Quoted 10 lines

drivers/firmware/nxp_lpc_boot_rom.c new file +10 -0

+	NXP_PART_LPC(4322,  0xa00bcb3c, 0x80, 512,   0),
+	NXP_PART_LPC(4317,  0xa001cb3f, 0x00, 512, 512),
+	NXP_PART_LPC(4315,  0xa001cb3f, 0x22, 384, 384),
+	NXP_PART_LPC(4313,  0xa00bcb3f, 0x44, 256, 256),
+	NXP_PART_LPC(4312,  0xa00bcb3f, 0x80, 512,   0),
+};
+
+struct iap_rom {
+	void (*entry)(u32 *, u32 *);
+};

Here it might be simpler to declare a typedef instead of a struct.

Quoted 6 lines

drivers/firmware/nxp_lpc_boot_rom.c new file +6 -0

+struct nxp_rom_api {
+	struct device *dev;
+	void __iomem *rom;
+
+	bool has_iap;
+	struct iap_rom iap;

drivers/firmware/nxp_lpc_boot_rom.c line 157

Quoted 10 lines

drivers/firmware/nxp_lpc_boot_rom.c new file +10 -0

+	spinlock_t lock;
+
+	const struct nxp_lpc_part *part;
+	const char *partname;
+	u32 boot_version;
+
+	struct soc_device *soc_dev;
+	struct soc_device_attribute soc_dev_attr;
+};
+

--
With best wishes,
Vladimir

Joachim Eastwood

author

2016-10-08 10:49 UTC #3 lore raw

PATCH 1/3 firmware: add lpc18xx boot rom driver

Hi Vladimir,

Quoted 19 lines · Vladimir Zapolskiy

Hi Joachim,
Quoted 16 lines · Joachim Eastwood
Firmware driver for the boot ROM found on all NXP LPC18xx/43xx devices. This driver makes it possible to retrieve device specific information from either the ROM via API calls or from OTP memory.
The boot ROM contains several APIs for on-chip devices. Note that not all APIs are available on all devices. The API to retrieve device information and internal Flash programming (IAP) is only available on devices with Flash. Flashless devices retrieve device information from OTP memory. The CHIPID register in CREG (syscon) is used to check if IAP is available.
For now this driver is only used to expose device information via a 'SoC device'. Linux API for the IAP and OTP will be added later. These two APIs will be used by a Flash MTD driver and a OTP NVMEM driver to program the memory.

Quoted 8 lines

Quoted 1 line
Signed-off-by Joachim Eastwood <[email protected]>
please feel free to add to the series my
Tested-by Vladimir Zapolskiy <[email protected]>
Reviewed-by Vladimir Zapolskiy <[email protected]>
I tested the change on a board powered by LPC4357.

Thanks!

Quoted 5 lines

Nevertheless I have some nitpicks for your consideration.
And the first one is that I'm not totally convinced that drivers/firmware is the proper place for the driver, I tend to think that it might be a good time to create drivers/soc/nxp/

As the driver stand now, I agree with you. But I do plan to add firmware functionally later for Flash programming which will be used for a MTD driver and OTP programming for the OTP nvmem driver. This is also stated in the cover letter.

See this patch for the Flash ROM API:
https://github.com/manabian/linux-lpc/commit/f33b03e7b47515a1d48b42f8bb1476ad5c67025b

The reason why I want to merge a simple driver now is:
i) The driver useful for SoC identification
ii ) It's easier to review and the Flash API is really a separate thing iii ) The Flash API can be reviewed/merged together with its user (MTD-driver)

Quoted 33 lines

Quoted 7 lines

---
 drivers/firmware/Kconfig            |  12 ++
 drivers/firmware/Makefile           |   1 +
 drivers/firmware/nxp_lpc_boot_rom.c | 411 ++++++++++++++++++++++++++++++++++++
 3 files changed, 424 insertions(+)
 create mode 100644 drivers/firmware/nxp_lpc_boot_rom.c

[snip]

Quoted 10 lines

drivers/firmware/nxp_lpc_boot_rom.c new file +10 -0

+/* LPC18xx/43xx CREG (syscon) defines */
+#define LPC18XX_CREG_CHIPID          0x200
+#define LPC18XX_FLASH_CHIPID0                0x4284e02b
+#define LPC18XX_FLASH_CHIPID1                0x7284e02b
+#define LPC18XX_FLASHLESS_CHIPID0    0x5284e02b
+#define LPC18XX_FLASHLESS_CHIPID1    0x6284e02b
+#define LPC43XX_FLASH_CHIPID0                0x4906002b
+#define LPC43XX_FLASH_CHIPID1                0x7906002b
+#define LPC43XX_FLASHLESS_CHIPID0    0x5906002b
+#define LPC43XX_FLASHLESS_CHIPID1    0x6906002b

drivers/firmware/nxp_lpc_boot_rom.c line 75

Quoted 10 lines

drivers/firmware/nxp_lpc_boot_rom.c new file +10 -0

+
+#define NXP_PART_LPC(_num, _id0, _id1, _sz0, _sz1)   \
+     {                                               \
+             .name = "LPC"#_num,                     \
+             .id[0] = _id0, .id[1] = _id1,           \
+             .flash_size[0] = _sz0 * 1024,           \
+             .flash_size[1] = _sz1 * 1024,           \
+     }
+
+

checkpatch complains:

Quoted 2 lines

CHECK: Please don't use multiple blank lines #145: FILE: drivers/firmware/nxp_lpc_boot_rom.c:75:

I'll fix up.

Quoted 8 lines

drivers/firmware/nxp_lpc_boot_rom.c line 78
Quoted 4 lines
drivers/firmware/nxp_lpc_boot_rom.c new file +3 -0
+struct nxp_lpc_part {
+     const char *name;
+     u16 flash_size[2];
flash_size[2] is set by NXP_PART_LPC() macro but unused, however in my build environment (W=1 and sparse checks) I get tons of legitimate compile time warnings:

flash_size is currently unused, but will be used by the MTD via the Flash ROM API. I only kept in this patch to avoid the churn later, but if it causes warnings I'll remove it.

Quoted 15 lines

drivers/firmware/nxp_lpc_boot_rom.c:93:9: warning: cast truncates bits from constant value (80000 becomes 0) drivers/firmware/nxp_lpc_boot_rom.c:93:9: warning: cast truncates bits from constant value (80000 becomes 0) drivers/firmware/nxp_lpc_boot_rom.c:94:9: warning: cast truncates bits from constant value (80000 becomes 0) drivers/firmware/nxp_lpc_boot_rom.c:94:9: warning: cast truncates bits from constant value (80000 becomes 0)
....
drivers/firmware/nxp_lpc_boot_rom.c:93:2: warning: large integer implicitly truncated to unsigned type [-Woverflow]
NXP_PART_LPC(1857, 0xf001d830, 0x00, 512, 512),
^
drivers/firmware/nxp_lpc_boot_rom.c:93:2: warning: large integer implicitly truncated to unsigned type [-Woverflow] drivers/firmware/nxp_lpc_boot_rom.c:94:2: warning: large integer implicitly truncated to unsigned type [-Woverflow]
NXP_PART_LPC(18S57, 0xf001d860, 0x00, 512, 512),
^
....

Quoted 3 lines

and so on.
Please consider either to store flash size in kB or change storage type to u32.

This was a last minute change and I didn't notice before sending it. I have already fixed this up in my tree.

Quoted 56 lines

drivers/firmware/nxp_lpc_boot_rom.c new file +56 -0

+     u32 id[2];
+};
+
+static const struct nxp_lpc_part nxp_lpc_parts[] = {
+     /* LPC18xx Flashless parts */
+     NXP_PART_LPC(1850,  0xf000d830, 0x00,   0,   0),
+     NXP_PART_LPC(18S50, 0xf000d860, 0x00,   0,   0),
+     NXP_PART_LPC(1830,  0xf000da30, 0x00,   0,   0),
+     NXP_PART_LPC(18S30, 0xf000da60, 0x00,   0,   0),
+     NXP_PART_LPC(1820,  0xf00adb3c, 0x00,   0,   0),
+     NXP_PART_LPC(18S20, 0xf00adb6c, 0x00,   0,   0),
+     NXP_PART_LPC(1810,  0xf00b5b3f, 0x00,   0,   0),
+     NXP_PART_LPC(18S10, 0xf00b5b6f, 0x00,   0,   0),
+     /* LPC18xx Flash parts */
+     NXP_PART_LPC(1857,  0xf001d830, 0x00, 512, 512),
+     NXP_PART_LPC(18S57, 0xf001d860, 0x00, 512, 512),
+     NXP_PART_LPC(1853,  0xf001d830, 0x44, 256, 256),
+     NXP_PART_LPC(1837,  0xf001da30, 0x00, 512, 512),
+     NXP_PART_LPC(18S37, 0xf001d860, 0x00, 512, 512),
+     NXP_PART_LPC(1833,  0xf001da30, 0x44, 256, 256),
+     NXP_PART_LPC(1827,  0xf001db3c, 0x00, 512, 512),
+     NXP_PART_LPC(1825,  0xf001db3c, 0x22, 384, 384),
+     NXP_PART_LPC(1823,  0xf00bdb3c, 0x44, 256, 256),
+     NXP_PART_LPC(1822,  0xf00bdb3c, 0x80, 512,   0),
+     NXP_PART_LPC(1817,  0xf001db3f, 0x00, 512, 512),
+     NXP_PART_LPC(1815,  0xf001db3f, 0x22, 384, 384),
+     NXP_PART_LPC(1813,  0xf00bdb3f, 0x44, 256, 256),
+     NXP_PART_LPC(1812,  0xf00bdb3f, 0x80, 512,   0),
+     /* LPC43xx Flashless parts */
+     NXP_PART_LPC(4370,  0x00000030, 0x00,   0,   0), /* LBGA256 */
+     NXP_PART_LPC(4370,  0x00000230, 0x00,   0,   0), /* TFBGA100 */
+     NXP_PART_LPC(43S70, 0x00000060, 0x00,   0,   0),
+     NXP_PART_LPC(4350,  0xa0000830, 0x00,   0,   0),
+     NXP_PART_LPC(43S50, 0xa0000860, 0x00,   0,   0),
+     NXP_PART_LPC(4330,  0xa0000a30, 0x00,   0,   0),
+     NXP_PART_LPC(43S30, 0xa0000a60, 0x00,   0,   0),
+     NXP_PART_LPC(4320,  0xa000cb3c, 0x00,   0,   0),
+     NXP_PART_LPC(43S20, 0xa000cb6c, 0x00,   0,   0),
+     NXP_PART_LPC(4310,  0xa00acb3f, 0x00,   0,   0),
+     /* LPC43xx parts with Flash */
+     NXP_PART_LPC(4367,  0x8001c030, 0x00, 512, 512),
+     NXP_PART_LPC(43S67, 0x8001c060, 0x00, 512, 512),
+     NXP_PART_LPC(4357,  0xa001c830, 0x00, 512, 512),
+     NXP_PART_LPC(43S57, 0xa001c860, 0x00, 512, 512), /* LBGA256 */
+     NXP_PART_LPC(43S57, 0xa001ca60, 0x00, 512, 512), /* LQFP208 */
+     NXP_PART_LPC(4353,  0xa001c830, 0x44, 256, 256),
+     NXP_PART_LPC(4337,  0xa001ca30, 0x00, 512, 512),
+     NXP_PART_LPC(43S37, 0xa001ca60, 0x00, 512, 512),
+     NXP_PART_LPC(4333,  0xa001ca30, 0x44, 256, 256),
+     NXP_PART_LPC(4327,  0xa001cb3c, 0x00, 512, 512),
+     NXP_PART_LPC(4325,  0xa001cb3c, 0x22, 384, 384),
+     NXP_PART_LPC(4323,  0xa00bcb3c, 0x44, 256, 256),
+     NXP_PART_LPC(4322,  0xa00bcb3c, 0x80, 512,   0),
+     NXP_PART_LPC(4317,  0xa001cb3f, 0x00, 512, 512),
+     NXP_PART_LPC(4315,  0xa001cb3f, 0x22, 384, 384),
+     NXP_PART_LPC(4313,  0xa00bcb3f, 0x44, 256, 256),

Quoted 8 lines

drivers/firmware/nxp_lpc_boot_rom.c line 140
Quoted 6 lines
drivers/firmware/nxp_lpc_boot_rom.c new file +6 -0
+     NXP_PART_LPC(4312,  0xa00bcb3f, 0x80, 512,   0),
+};
+
+struct iap_rom {
+     void (*entry)(u32 *, u32 *);
+};
Here it might be simpler to declare a typedef instead of a struct.

This is done using a struct to keep it consistent with the other ROM APIs that will be added later. The IAP is kinda special since it only has one function while most other APIs have several functions.

regards,
Joachim Eastwood

Joachim Eastwood

author

2016-09-13 19:51 UTC #4 lore raw

PATCH 2/3 firmware: dt: document lpc1850 boot ROM bindings

In reply to Joachim Eastwood

Binding documentation for the NXP LPC boot ROM.

Signed-off-by Joachim Eastwood <[email protected]>

---
 .../devicetree/bindings/firmware/nxp,boot-rom.txt   | 21 +++++++++++++++++++++
 1 file changed, 21 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/firmware/nxp,boot-rom.txt

Documentation/devicetree/bindings/firmware/nxp,boot-rom.txt new file +21 -0

new file mode 100644
index 0000000..5f3a044
@@ -0,0 +1,21 @@
+* NXP LPC boot ROM
+
+NXP LPC microcontrollers contains a boot ROM used to retrieve part information
+and access internal Flash memory and OTP memory. Note that the Flash API is
+not available on Flashless devices.
+
+Required properties:
+- compatible: must contain the following: "nxp,lpc1850-boot-rom".
+- reg: physical base address of the ROM and length of memory mapped region.
+- syscon: handle to NXP CREG (Configuration Registers) syscon block.
+- nvmem-cells: = handle to OTP memory cell which contain the part ID.
+- nvmem-cell-names: must contain "PartID".
+
+Example:
+boot_rom: firmware at 10400000 {
+	compatible = "nxp,lpc1850-boot-rom";
+	reg = <0x10400000 0x10000>;
+	syscon = <&creg>;
+	nvmem-cells = <&part_id>;
+	nvmem-cell-names = "PartID";
+};

Signature · 1 line

2.9.3

Rob Herring

maintainer

2016-09-23 13:39 UTC #5 lore raw

PATCH 2/3 firmware: dt: document lpc1850 boot ROM bindings

Quoted 14 lines · Joachim Eastwood

Binding documentation for the NXP LPC boot ROM.
Signed-off-by Joachim Eastwood <[email protected]>
---
 .../devicetree/bindings/firmware/nxp,boot-rom.txt   | 21 +++++++++++++++++++++
 1 file changed, 21 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/firmware/nxp,boot-rom.txt
Documentation/devicetree/bindings/firmware/nxp,boot-rom.txt new file +0 -0
new file mode 100644
index 0000000..5f3a044

Documentation/devicetree/bindings/firmware/nxp,boot-rom.txt line 5

Quoted 5 lines

Documentation/devicetree/bindings/firmware/nxp,boot-rom.txt new file +5 -0

@@ -0,0 +1,21 @@
+* NXP LPC boot ROM
+
+NXP LPC microcontrollers contains a boot ROM used to retrieve part information
+and access internal Flash memory and OTP memory. Note that the Flash API is
+not available on Flashless devices.

Is this determined at run-time? If not flashless devices should have a different compatible string to determine this then.

Quoted 19 lines

Documentation/devicetree/bindings/firmware/nxp,boot-rom.txt new file +16 -0

+
+Required properties:
+- compatible: must contain the following: "nxp,lpc1850-boot-rom".
+- reg: physical base address of the ROM and length of memory mapped region.
+- syscon: handle to NXP CREG (Configuration Registers) syscon block.
+- nvmem-cells: = handle to OTP memory cell which contain the part ID.
+- nvmem-cell-names: must contain "PartID".
+
+Example:
+boot_rom: firmware at 10400000 {
+	compatible = "nxp,lpc1850-boot-rom";
+	reg = <0x10400000 0x10000>;
+	syscon = <&creg>;
+	nvmem-cells = <&part_id>;
+	nvmem-cell-names = "PartID";
+};

Signature · 1 line

2.9.3

Joachim Eastwood

author

2016-09-23 20:01 UTC #6 lore raw

PATCH 2/3 firmware: dt: document lpc1850 boot ROM bindings

Quoted 9 lines · Rob Herring

Quoted 8 lines · Joachim Eastwood
Binding documentation for the NXP LPC boot ROM.
Signed-off-by Joachim Eastwood <[email protected]>
---
 .../devicetree/bindings/firmware/nxp,boot-rom.txt   | 21 +++++++++++++++++++++
 1 file changed, 21 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/firmware/nxp,boot-rom.txt

Quoted 14 lines

Documentation/devicetree/bindings/firmware/nxp,boot-rom.txt line 5
Quoted 11 lines
Documentation/devicetree/bindings/firmware/nxp,boot-rom.txt new file +5 -0
new file mode 100644
index 0000000..5f3a044
@@ -0,0 +1,21 @@
+* NXP LPC boot ROM
+
+NXP LPC microcontrollers contains a boot ROM used to retrieve part information
+and access internal Flash memory and OTP memory. Note that the Flash API is
+not available on Flashless devices.
Is this determined at run-time? If not flashless devices should have a different compatible string to determine this then.

It is determined at run time by reading a 'CHIP ID' register in CREG (syscon) that is present on both Flash and Flashless devices.

regards,
Joachim Eastwood

Joachim Eastwood

author

2016-09-13 19:51 UTC #7 lore raw

PATCH 3/3 ARM: dts: lpc18xx: add boot rom node

In reply to Joachim Eastwood

Add node for the boot ROM found on all NXP LPC18xx/43xx devices.

Signed-off-by Joachim Eastwood <[email protected]>

---
 arch/arm/boot/dts/lpc18xx.dtsi | 8 ++++++++
 1 file changed, 8 insertions(+)

arch/arm/boot/dts/lpc18xx.dtsi +8 -0

index 631e6f6c..9f94f3e 100644
@@ -81,6 +81,14 @@
 			status = "disabled";
 		};
 
+		boot_rom: firmware at 10400000 {
+			compatible = "nxp,lpc1850-boot-rom";
+			reg = <0x10400000 0x10000>;
+			syscon = <&creg>;
+			nvmem-cells = <&part_id>;
+			nvmem-cell-names = "PartID";
+		};
+
 		dmac: dma-controller at 40002000 {
 			compatible = "arm,pl080", "arm,primecell";
 			arm,primecell-periphid = <0x00041080>;

Signature · 1 line

2.9.3

Vladimir Zapolskiy

maintainer

2016-10-07 01:50 UTC #8 lore raw

PATCH 3/3 ARM: dts: lpc18xx: add boot rom node

Hi Joachim,

Quoted 12 lines · Joachim Eastwood

Add node for the boot ROM found on all NXP LPC18xx/43xx devices.
Signed-off-by Joachim Eastwood <[email protected]>
---
 arch/arm/boot/dts/lpc18xx.dtsi | 8 ++++++++
 1 file changed, 8 insertions(+)
arch/arm/boot/dts/lpc18xx.dtsi +0 -0
index 631e6f6c..9f94f3e 100644

arch/arm/boot/dts/lpc18xx.dtsi line 88

Quoted 8 lines

arch/arm/boot/dts/lpc18xx.dtsi +5 -0

@@ -81,6 +81,14 @@
 			status = "disabled";
 		};
 
+		boot_rom: firmware at 10400000 {
+			compatible = "nxp,lpc1850-boot-rom";
+			reg = <0x10400000 0x10000>;
+			syscon = <&creg>;
+			nvmem-cells = <&part_id>;

nitpicking, this change has a compile time dependency on yours "nvmem: add lpc18xx OTP memory driver" series, I haven't noticed this info stated, but it may be an overlook on my part.

arch/arm/boot/dts/lpc18xx.dtsi line 94

Quoted 7 lines

arch/arm/boot/dts/lpc18xx.dtsi +3 -0

+			nvmem-cell-names = "PartID";
+		};
+
 		dmac: dma-controller at 40002000 {
 			compatible = "arm,pl080", "arm,primecell";
 			arm,primecell-periphid = <0x00041080>;

Tested-by Vladimir Zapolskiy <[email protected]>

Reviewed-by Vladimir Zapolskiy <[email protected]>

--
With best wishes,
Vladimir

Joachim Eastwood

author

2016-10-08 10:28 UTC #9 lore raw

PATCH 3/3 ARM: dts: lpc18xx: add boot rom node

Hi Vladimir,

Quoted 18 lines · Vladimir Zapolskiy

Hi Joachim,
Quoted 15 lines · Joachim Eastwood
Add node for the boot ROM found on all NXP LPC18xx/43xx devices.
Signed-off-by Joachim Eastwood <[email protected]>
---
 arch/arm/boot/dts/lpc18xx.dtsi | 8 ++++++++
 1 file changed, 8 insertions(+)
arch/arm/boot/dts/lpc18xx.dtsi +0 -0
index 631e6f6c..9f94f3e 100644
@@ -81,6 +81,14 @@
                      status = "disabled";
              };
 

Quoted 9 lines

arch/arm/boot/dts/lpc18xx.dtsi line 88
Quoted 5 lines
arch/arm/boot/dts/lpc18xx.dtsi +5 -0
+             boot_rom: firmware at 10400000 {
+                     compatible = "nxp,lpc1850-boot-rom";
+                     reg = <0x10400000 0x10000>;
+                     syscon = <&creg>;
+                     nvmem-cells = <&part_id>;
nitpicking, this change has a compile time dependency on yours "nvmem: add lpc18xx OTP memory driver" series, I haven't noticed this info stated, but it may be an overlook on my part.

It's not really a hard dependency and I will ensure that the DTS changes comes in the correct order.

Quoted 10 lines

arch/arm/boot/dts/lpc18xx.dtsi line 94
Quoted 7 lines
arch/arm/boot/dts/lpc18xx.dtsi +3 -0
+                     nvmem-cell-names = "PartID";
+             };
+
              dmac: dma-controller at 40002000 {
                      compatible = "arm,pl080", "arm,primecell";
                      arm,primecell-periphid = <0x00041080>;
Tested-by Vladimir Zapolskiy <[email protected]>
Reviewed-by Vladimir Zapolskiy <[email protected]>

Thanks for testing and going through the changes.

regards,
Joachim Eastwood