serial: Add serial_mvebu_a3700 for Armada 3700 SoC
Subsystems (10)
PATCH 1/15 serial: Add serial_mvebu_a3700 for Armada 3700 SoC
The Armada 3700's UART is a simple serial port. It has a 32 bytes Tx FIFO and a 64 bytes Rx FIFO integrated. This patch adds support for this UART including the DEBUG UART functions for very early debug output.
Signed-off-by Stefan Roese <[email protected]>
Cc Nadav Haklai <[email protected]>
Cc Kostya Porotchkin <[email protected]>
Cc Wilson Ding <[email protected]>
Cc Victor Gu <[email protected]>
Cc Hua Jing <[email protected]>
Cc Terry Zhou <[email protected]>
Cc Hanna Hawa <[email protected]>
Cc Haim Boot <[email protected]>
--- drivers/serial/Kconfig | 15 ++++ drivers/serial/Makefile | 1 + drivers/serial/serial_mvebu_a3700.c | 173 ++++++++++++++++++++++++++++++++++++ 3 files changed, 189 insertions(+) create mode 100644 drivers/serial/serial_mvebu_a3700.c
drivers/serial/Kconfig +15 -0
@@ -147,6 +147,13 @@ config DEBUG_UART_ARM_DCC This port is available at least on ARMv6, ARMv7, ARMv8 and XScale architectures. +config DEBUG_MVEBU_A3700_UART + bool "Marvell Armada 3700" + help + Select this to enable a debug UART using the serial_mvebu driver. You + will need to provide parameters to make this work. The driver will + be available until the real driver-model serial is running. + config DEBUG_UART_ZYNQ bool "Xilinx Zynq" help
@@ -295,6 +302,13 @@ config FSL_LPUART Select this to enable a Low Power UART for Freescale VF610 and QorIQ Layerscape devices. +config MVEBU_A3700_UART + bool "UART support for Armada 3700" + default n + help + Choose this option to add support for UART driver on the Marvell + Armada 3700 SoC. The base address is configured via DT. + config PIC32_SERIAL bool "Support for Microchip PIC32 on-chip UART" depends on DM_SERIAL && MACH_PIC32
@@ -371,4 +385,5 @@ config MSM_SERIAL It should support all Qualcomm devices with UARTDM version 1.4, for example APQ8016 and MSM8916. Single baudrate is supported in current implementation (115200). + endmenu
drivers/serial/Makefile +1 -0
@@ -46,6 +46,7 @@ obj-$(CONFIG_PIC32_SERIAL) += serial_pic32.o obj-$(CONFIG_STM32X7_SERIAL) += serial_stm32x7.o obj-$(CONFIG_BCM283X_MU_SERIAL) += serial_bcm283x_mu.o obj-$(CONFIG_MSM_SERIAL) += serial_msm.o +obj-$(CONFIG_MVEBU_A3700_UART) += serial_mvebu_a3700.o ifndef CONFIG_SPL_BUILD obj-$(CONFIG_USB_TTY) += usbtty.o
drivers/serial/serial_mvebu_a3700.c new file +173 -0
173 lines not on this page · raw message
Signature · 1 line
2.9.3
PATCH 2/15 spi: Add driver for Marvell Armada 3700 SoC
The SPI IP core in the Marvell Armada 3700 is similar to the one in the other Armada SoCs. But the differences are big enough that it makes sense to introduce a new driver instead of cluttering the old kirkwood driver with #ifdef's.
Signed-off-by Stefan Roese <[email protected]>
Cc Nadav Haklai <[email protected]>
Cc Kostya Porotchkin <[email protected]>
Cc Wilson Ding <[email protected]>
Cc Victor Gu <[email protected]>
Cc Hua Jing <[email protected]>
Cc Terry Zhou <[email protected]>
Cc Hanna Hawa <[email protected]>
Cc Haim Boot <[email protected]>
Cc Jagan Teki <[email protected]>
--- drivers/spi/Kconfig | 7 ++ drivers/spi/Makefile | 1 + drivers/spi/mvebu_a3700_spi.c | 281 ++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 289 insertions(+) create mode 100644 drivers/spi/mvebu_a3700_spi.c
drivers/spi/Kconfig +7 -0
@@ -75,6 +75,13 @@ config ICH_SPI access the SPI NOR flash on platforms embedding this Intel ICH IP core. +config MVEBU_A3700_SPI + bool "Marvell Armada 3700 SPI driver" + help + Enable the Marvell Armada 3700 SPI driver. This driver can be + used to access the SPI NOR flash on platforms embedding this + Marvell IP core. + config PIC32_SPI bool "Microchip PIC32 SPI driver" depends on MACH_PIC32
drivers/spi/Makefile +1 -0
@@ -37,6 +37,7 @@ obj-$(CONFIG_KIRKWOOD_SPI) += kirkwood_spi.o obj-$(CONFIG_LPC32XX_SSP) += lpc32xx_ssp.o obj-$(CONFIG_MPC52XX_SPI) += mpc52xx_spi.o obj-$(CONFIG_MPC8XXX_SPI) += mpc8xxx_spi.o +obj-$(CONFIG_MVEBU_A3700_SPI) += mvebu_a3700_spi.o obj-$(CONFIG_MXC_SPI) += mxc_spi.o obj-$(CONFIG_MXS_SPI) += mxs_spi.o obj-$(CONFIG_OMAP3_SPI) += omap3_spi.o
drivers/spi/mvebu_a3700_spi.c new file +281 -0
281 lines not on this page · raw message
Signature · 1 line
2.9.3
PATCH 2/15 spi: Add driver for Marvell Armada 3700 SoC
Quoted 147 lines · Stefan Roese
The SPI IP core in the Marvell Armada 3700 is similar to the one in the other Armada SoCs. But the differences are big enough that it makes sense to introduce a new driver instead of cluttering the old kirkwood driver with #ifdef's.
Signed-off-by Stefan Roese <[email protected]>Cc Nadav Haklai <[email protected]>Cc Kostya Porotchkin <[email protected]>Cc Wilson Ding <[email protected]>Cc Victor Gu <[email protected]>Cc Hua Jing <[email protected]>Cc Terry Zhou <[email protected]>Cc Hanna Hawa <[email protected]>Cc Haim Boot <[email protected]>Cc Jagan Teki <[email protected]>--- drivers/spi/Kconfig | 7 ++ drivers/spi/Makefile | 1 + drivers/spi/mvebu_a3700_spi.c | 281 ++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 289 insertions(+) create mode 100644 drivers/spi/mvebu_a3700_spi.cdrivers/spi/Kconfig +7
-0@@ -75,6 +75,13 @@ config ICH_SPI access the SPI NOR flash on platforms embedding this Intel ICH IP core. +config MVEBU_A3700_SPI + bool "Marvell Armada 3700 SPI driver" + help + Enable the Marvell Armada 3700 SPI driver. This driver can be + used to access the SPI NOR flash on platforms embedding this + Marvell IP core. + config PIC32_SPI bool "Microchip PIC32 SPI driver" depends on MACH_PIC32drivers/spi/Makefile +1
-0@@ -37,6 +37,7 @@ obj-$(CONFIG_KIRKWOOD_SPI) += kirkwood_spi.o obj-$(CONFIG_LPC32XX_SSP) += lpc32xx_ssp.o obj-$(CONFIG_MPC52XX_SPI) += mpc52xx_spi.o obj-$(CONFIG_MPC8XXX_SPI) += mpc8xxx_spi.o +obj-$(CONFIG_MVEBU_A3700_SPI) += mvebu_a3700_spi.o obj-$(CONFIG_MXC_SPI) += mxc_spi.o obj-$(CONFIG_MXS_SPI) += mxs_spi.o obj-$(CONFIG_OMAP3_SPI) += omap3_spi.odrivers/spi/mvebu_a3700_spi.c new file +89
-0@@ -0,0 +1,281 @@ +/* +* Copyright (C) 2015 Marvell International Ltd. +* +* Copyright (C) 2016 Stefan Roese <[email protected]> +* +* SPDX-License-Identifier: GPL-2.0+ +*/ + +#include <common.h> +#include <dm.h> +#include <malloc.h> +#include <spi.h> +#include <wait_bit.h> +#include <asm/io.h> + +DECLARE_GLOBAL_DATA_PTR ; + +#define SPI_TIMEOUT 10000 + +#define MVEBU_SPI_A3700_XFER_RDY BIT(1) +#define MVEBU_SPI_A3700_FIFO_FLUSH BIT(9) +#define MVEBU_SPI_A3700_BYTE_LEN BIT(5) +#define MVEBU_SPI_A3700_CLK_PHA BIT(6) +#define MVEBU_SPI_A3700_CLK_POL BIT(7) +#define MVEBU_SPI_A3700_FIFO_EN BIT(17) +#define MVEBU_SPI_A3700_SPI_EN_0 BIT(16) +#define MVEBU_SPI_A3700_CLK_PRESCALE_BIT 0 +#define MVEBU_SPI_A3700_CLK_PRESCALE_MASK \ + (0x1f << MVEBU_SPI_A3700_CLK_PRESCALE_BIT) + +/* SPI registers */ +struct spi_reg { +u32 ctrl;/* 0x10600 */ +u32 cfg;/* 0x10604 */ +u32 dout;/* 0x10608 */ +u32 din;/* 0x1060c */ +}; + +struct mvebu_spi_platdata { +struct spi_reg *spireg; +}; + +static void spi_cs_activate (struct spi_reg *reg,int cs) +{ +setbits_le32 (®->ctrl,MVEBU_SPI_A3700_SPI_EN_0 << cs); +} + +static void spi_cs_deactivate (struct spi_reg *reg,int cs) +{ +clrbits_le32 (®->ctrl,MVEBU_SPI_A3700_SPI_EN_0 << cs); +} + +/** +* spi_legacy_shift_byte() - triggers the real SPI transfer +* @bytelen: Indicate how many bytes to transfer. +* @dout: Buffer address of what to send. +* @din: Buffer address of where to receive. +* +* This function triggers the real SPI transfer in legacy mode. It +* will shift out char buffer from @dout, and shift in char buffer to +* @din, if necessary. +* +* This function assumes that only one byte is shifted at one time. +* However, it is not its responisbility to set the transfer type to +* one-byte. Also, it does not guarantee that it will work if transfer +* type becomes two-byte. See spi_set_legacy() for details. +* +* In legacy mode, simply write to the SPI_DOUT register will trigger +* the transfer. +* +* If @dout == NULL, which means no actual data needs to be sent out, +* then the function will shift out 0x00 in order to shift in data. +* The XFER_RDY flag is checked every time before accessing SPI_DOUT +* and SPI_DIN register. +* +* The number of transfers to be triggerred is decided by @bytelen. +* +* Return: 0 - cool +* -ETIMEDOUT - XFER_RDY flag timeout +*/ +static int spi_legacy_shift_byte (struct spi_reg *reg,unsigned int bytelen, +const void *dout,void *din) +{ +const u8 *dout_8; +u8 *din_8; +int ret; + +/* Use 0x00 as dummy dout */ +const u8 dummy_dout =0x0 ;
drivers/spi/mvebu_a3700_spi.c line 99
Quoted 10 lines
drivers/spi/mvebu_a3700_spi.c new file +10
-0+u32 pending_dout =0x0 ; + +/* dout_8: pointer of current dout */ + dout_8 = dout; +/* din_8: pointer of current din */ + din_8 = din; + +while (bytelen) { + ret =wait_for_bit (__func__, ®->ctrl, +MVEBU_SPI_A3700_XFER_RDY , true,100 , false);
Do we have any documentation in data sheet or something for this 100 ms?
Quoted 79 lines
drivers/spi/mvebu_a3700_spi.c new file +79
-0+if (ret) +return ret; + +if (dout) + pending_dout = (u32)*dout_8; +else + pending_dout = (u32 )dummy_dout; + +/* Trigger the xfer */ +writel (pending_dout, ®->dout); + +if (din) { + ret =wait_for_bit (__func__, ®->ctrl, +MVEBU_SPI_A3700_XFER_RDY , + true,100 , false); +if (ret) +return ret; + +/* Read what is transferred in */ + *din_8 = (u8 )readl (®->din); + } + +/* Don't increment the current pointer if NULL */ +if (dout) + dout_8++; +if (din) + din_8++; + + bytelen--; + } + +return 0 ; +} + +static int mvebu_spi_xfer (struct udevice *dev,unsigned int bitlen, +const void *dout,void *din,unsigned long flags) +{ +struct udevice *bus = dev->parent; +struct mvebu_spi_platdata *plat =dev_get_platdata (bus); +struct spi_reg *reg = plat->spireg; +unsigned int bytelen; +int ret; + + bytelen = bitlen /8 ; + +if (dout && din) +debug ("This is a duplex transfer.\n" ); + +/* Activate CS */ +if (flags &SPI_XFER_BEGIN ) { +debug ("SPI: activate cs.\n" ); +spi_cs_activate (reg,spi_chip_select (dev)); + } + +/* Send and/or receive */ +if (dout || din) { + ret =spi_legacy_shift_byte (reg, bytelen, dout, din); +if (ret) +return ret; + } + +/* Deactivate CS */ +if (flags &SPI_XFER_END ) { + ret =wait_for_bit (__func__, ®->ctrl, +MVEBU_SPI_A3700_XFER_RDY , true,100 , false); +if (ret) +return ret; + +debug ("SPI: deactivate cs.\n" ); +spi_cs_deactivate (reg,spi_chip_select (dev)); + } + +return 0 ; +} + +static int mvebu_spi_set_speed (struct udevice *bus,uint hz) +{ +struct mvebu_spi_platdata *plat =dev_get_platdata (bus); +struct spi_reg *reg = plat->spireg;
drivers/spi/mvebu_a3700_spi.c line 188
Quoted 10 lines
drivers/spi/mvebu_a3700_spi.c new file +10
-0+u32 data; + + data =readl (®->cfg); + +/* Set Prescaler */ + data &= ~MVEBU_SPI_A3700_CLK_PRESCALE_MASK ; + +/* Calculate Prescaler = (spi_input_freq / spi_max_freq) */ +/* ToDo: get real values for clock and frequency */ + data |=160000 /40000 ;
Better to get these from dt atleast for now and also please set the freq/baud value by evaluating using input 'hz'
thanks!
Signature · 4 lines
Jagan Teki Free Software Engineer | www.openedev.com U-Boot, Linux | Upstream Maintainer Hyderabad, India.
PATCH 2/15 spi: Add driver for Marvell Armada 3700 SoC
Quoted 152 lines · Jagan Teki
Quoted 151 lines · Stefan Roese
The SPI IP core in the Marvell Armada 3700 is similar to the one in the other Armada SoCs. But the differences are big enough that it makes sense to introduce a new driver instead of cluttering the old kirkwood driver with #ifdef's.
Signed-off-by Stefan Roese <[email protected]>Cc Nadav Haklai <[email protected]>Cc Kostya Porotchkin <[email protected]>Cc Wilson Ding <[email protected]>Cc Victor Gu <[email protected]>Cc Hua Jing <[email protected]>Cc Terry Zhou <[email protected]>Cc Hanna Hawa <[email protected]>Cc Haim Boot <[email protected]>Cc Jagan Teki <[email protected]>--- drivers/spi/Kconfig | 7 ++ drivers/spi/Makefile | 1 + drivers/spi/mvebu_a3700_spi.c | 281 ++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 289 insertions(+) create mode 100644 drivers/spi/mvebu_a3700_spi.cdrivers/spi/Kconfig +7
-0@@ -75,6 +75,13 @@ config ICH_SPI access the SPI NOR flash on platforms embedding this Intel ICH IP core. +config MVEBU_A3700_SPI + bool "Marvell Armada 3700 SPI driver" + help + Enable the Marvell Armada 3700 SPI driver. This driver can be + used to access the SPI NOR flash on platforms embedding this + Marvell IP core. + config PIC32_SPI bool "Microchip PIC32 SPI driver" depends on MACH_PIC32drivers/spi/Makefile +1
-0@@ -37,6 +37,7 @@ obj-$(CONFIG_KIRKWOOD_SPI) += kirkwood_spi.o obj-$(CONFIG_LPC32XX_SSP) += lpc32xx_ssp.o obj-$(CONFIG_MPC52XX_SPI) += mpc52xx_spi.o obj-$(CONFIG_MPC8XXX_SPI) += mpc8xxx_spi.o +obj-$(CONFIG_MVEBU_A3700_SPI) += mvebu_a3700_spi.o obj-$(CONFIG_MXC_SPI) += mxc_spi.o obj-$(CONFIG_MXS_SPI) += mxs_spi.o obj-$(CONFIG_OMAP3_SPI) += omap3_spi.odrivers/spi/mvebu_a3700_spi.c new file +93
-0@@ -0,0 +1,281 @@ +/* +* Copyright (C) 2015 Marvell International Ltd. +* +* Copyright (C) 2016 Stefan Roese <[email protected]> +* +* SPDX-License-Identifier: GPL-2.0+ +*/ + +#include <common.h> +#include <dm.h> +#include <malloc.h> +#include <spi.h> +#include <wait_bit.h> +#include <asm/io.h> + +DECLARE_GLOBAL_DATA_PTR ; + +#define SPI_TIMEOUT 10000 + +#define MVEBU_SPI_A3700_XFER_RDY BIT(1) +#define MVEBU_SPI_A3700_FIFO_FLUSH BIT(9) +#define MVEBU_SPI_A3700_BYTE_LEN BIT(5) +#define MVEBU_SPI_A3700_CLK_PHA BIT(6) +#define MVEBU_SPI_A3700_CLK_POL BIT(7) +#define MVEBU_SPI_A3700_FIFO_EN BIT(17) +#define MVEBU_SPI_A3700_SPI_EN_0 BIT(16) +#define MVEBU_SPI_A3700_CLK_PRESCALE_BIT 0 +#define MVEBU_SPI_A3700_CLK_PRESCALE_MASK \ + (0x1f << MVEBU_SPI_A3700_CLK_PRESCALE_BIT) + +/* SPI registers */ +struct spi_reg { +u32 ctrl;/* 0x10600 */ +u32 cfg;/* 0x10604 */ +u32 dout;/* 0x10608 */ +u32 din;/* 0x1060c */ +}; + +struct mvebu_spi_platdata { +struct spi_reg *spireg; +}; + +static void spi_cs_activate (struct spi_reg *reg,int cs) +{ +setbits_le32 (®->ctrl,MVEBU_SPI_A3700_SPI_EN_0 << cs); +} + +static void spi_cs_deactivate (struct spi_reg *reg,int cs) +{ +clrbits_le32 (®->ctrl,MVEBU_SPI_A3700_SPI_EN_0 << cs); +} + +/** +* spi_legacy_shift_byte() - triggers the real SPI transfer +* @bytelen: Indicate how many bytes to transfer. +* @dout: Buffer address of what to send. +* @din: Buffer address of where to receive. +* +* This function triggers the real SPI transfer in legacy mode. It +* will shift out char buffer from @dout, and shift in char buffer to +* @din, if necessary. +* +* This function assumes that only one byte is shifted at one time. +* However, it is not its responisbility to set the transfer type to +* one-byte. Also, it does not guarantee that it will work if transfer +* type becomes two-byte. See spi_set_legacy() for details. +* +* In legacy mode, simply write to the SPI_DOUT register will trigger +* the transfer. +* +* If @dout == NULL, which means no actual data needs to be sent out, +* then the function will shift out 0x00 in order to shift in data. +* The XFER_RDY flag is checked every time before accessing SPI_DOUT +* and SPI_DIN register. +* +* The number of transfers to be triggerred is decided by @bytelen. +* +* Return: 0 - cool +* -ETIMEDOUT - XFER_RDY flag timeout +*/ +static int spi_legacy_shift_byte (struct spi_reg *reg,unsigned int bytelen, +const void *dout,void *din) +{ +const u8 *dout_8; +u8 *din_8; +int ret; + +/* Use 0x00 as dummy dout */ +const u8 dummy_dout =0x0 ; +u32 pending_dout =0x0 ; + +/* dout_8: pointer of current dout */ + dout_8 = dout;
Quoted 8 lines
drivers/spi/mvebu_a3700_spi.c line 99
Quoted 6 lines
drivers/spi/mvebu_a3700_spi.c new file +6
-0+/* din_8: pointer of current din */ + din_8 = din; + +while (bytelen) { + ret =wait_for_bit (__func__, ®->ctrl, +MVEBU_SPI_A3700_XFER_RDY , true,100 , false);Do we have any documentation in data sheet or something for this 100 ms?
No, not really.
Quoted 84 lines
Quoted 84 lines
drivers/spi/mvebu_a3700_spi.c new file +84
-0+if (ret) +return ret; + +if (dout) + pending_dout = (u32)*dout_8; +else + pending_dout = (u32 )dummy_dout; + +/* Trigger the xfer */ +writel (pending_dout, ®->dout); + +if (din) { + ret =wait_for_bit (__func__, ®->ctrl, +MVEBU_SPI_A3700_XFER_RDY , + true,100 , false); +if (ret) +return ret; + +/* Read what is transferred in */ + *din_8 = (u8 )readl (®->din); + } + +/* Don't increment the current pointer if NULL */ +if (dout) + dout_8++; +if (din) + din_8++; + + bytelen--; + } + +return 0 ; +} + +static int mvebu_spi_xfer (struct udevice *dev,unsigned int bitlen, +const void *dout,void *din,unsigned long flags) +{ +struct udevice *bus = dev->parent; +struct mvebu_spi_platdata *plat =dev_get_platdata (bus); +struct spi_reg *reg = plat->spireg; +unsigned int bytelen; +int ret; + + bytelen = bitlen /8 ; + +if (dout && din) +debug ("This is a duplex transfer.\n" ); + +/* Activate CS */ +if (flags &SPI_XFER_BEGIN ) { +debug ("SPI: activate cs.\n" ); +spi_cs_activate (reg,spi_chip_select (dev)); + } + +/* Send and/or receive */ +if (dout || din) { + ret =spi_legacy_shift_byte (reg, bytelen, dout, din); +if (ret) +return ret; + } + +/* Deactivate CS */ +if (flags &SPI_XFER_END ) { + ret =wait_for_bit (__func__, ®->ctrl, +MVEBU_SPI_A3700_XFER_RDY , true,100 , false); +if (ret) +return ret; + +debug ("SPI: deactivate cs.\n" ); +spi_cs_deactivate (reg,spi_chip_select (dev)); + } + +return 0 ; +} + +static int mvebu_spi_set_speed (struct udevice *bus,uint hz) +{ +struct mvebu_spi_platdata *plat =dev_get_platdata (bus); +struct spi_reg *reg = plat->spireg; +u32 data; + + data =readl (®->cfg); + +/* Set Prescaler */
Quoted 8 lines
drivers/spi/mvebu_a3700_spi.c line 188
Quoted 5 lines
drivers/spi/mvebu_a3700_spi.c new file +5
-0+ data &= ~MVEBU_SPI_A3700_CLK_PRESCALE_MASK ; + +/* Calculate Prescaler = (spi_input_freq / spi_max_freq) */ +/* ToDo: get real values for clock and frequency */ + data |=160000 /40000 ;Better to get these from dt atleast for now and also please set the freq/baud value by evaluating using input 'hz'
Okay. Updated for v2 - coming soon...
Thanks,
Stefan
PATCH v2 2/15 spi: Add driver for Marvell Armada 3700 SoC
In reply to Stefan RoeseThe SPI IP core in the Marvell Armada 3700 is similar to the one in the other Armada SoCs. But the differences are big enough that it makes sense to introduce a new driver instead of cluttering the old kirkwood driver with #ifdef's.
Signed-off-by Stefan Roese <[email protected]>
Cc Nadav Haklai <[email protected]>
Cc Kostya Porotchkin <[email protected]>
Cc Wilson Ding <[email protected]>
Cc Victor Gu <[email protected]>
Cc Hua Jing <[email protected]>
Cc Terry Zhou <[email protected]>
Cc Hanna Hawa <[email protected]>
Cc Haim Boot <[email protected]>
Cc Jagan Teki <[email protected]>
---
v2:
- Evaluated hz and used values provided by the DT in mvebu_spi_set_speed() as suggested by Jagan
drivers/spi/Kconfig | 7 + drivers/spi/Makefile | 1 + drivers/spi/mvebu_a3700_spi.c | 289 ++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 297 insertions(+) create mode 100644 drivers/spi/mvebu_a3700_spi.c
drivers/spi/Kconfig +7 -0
@@ -68,6 +68,13 @@ config ICH_SPI access the SPI NOR flash on platforms embedding this Intel ICH IP core. +config MVEBU_A3700_SPI + bool "Marvell Armada 3700 SPI driver" + help + Enable the Marvell Armada 3700 SPI driver. This driver can be + used to access the SPI NOR flash on platforms embedding this + Marvell IP core. + config PIC32_SPI bool "Microchip PIC32 SPI driver" depends on MACH_PIC32
drivers/spi/Makefile +1 -0
@@ -37,6 +37,7 @@ obj-$(CONFIG_KIRKWOOD_SPI) += kirkwood_spi.o obj-$(CONFIG_LPC32XX_SSP) += lpc32xx_ssp.o obj-$(CONFIG_MPC52XX_SPI) += mpc52xx_spi.o obj-$(CONFIG_MPC8XXX_SPI) += mpc8xxx_spi.o +obj-$(CONFIG_MVEBU_A3700_SPI) += mvebu_a3700_spi.o obj-$(CONFIG_MXC_SPI) += mxc_spi.o obj-$(CONFIG_MXS_SPI) += mxs_spi.o obj-$(CONFIG_OMAP3_SPI) += omap3_spi.o
drivers/spi/mvebu_a3700_spi.c new file +289 -0
289 lines not on this page · raw message
Signature · 1 line
2.9.3
PATCH v2 2/15 spi: Add driver for Marvell Armada 3700 SoC
Quoted 243 lines · Stefan Roese
The SPI IP core in the Marvell Armada 3700 is similar to the one in the other Armada SoCs. But the differences are big enough that it makes sense to introduce a new driver instead of cluttering the old kirkwood driver with #ifdef's.
Signed-off-by Stefan Roese <[email protected]>Cc Nadav Haklai <[email protected]>Cc Kostya Porotchkin <[email protected]>Cc Wilson Ding <[email protected]>Cc Victor Gu <[email protected]>Cc Hua Jing <[email protected]>Cc Terry Zhou <[email protected]>Cc Hanna Hawa <[email protected]>Cc Haim Boot <[email protected]>Cc Jagan Teki <[email protected]>---
v2:
- Evaluated hz and used values provided by the DT inmvebu_spi_set_speed()as suggested by Jagandrivers/spi/Kconfig | 7 + drivers/spi/Makefile | 1 + drivers/spi/mvebu_a3700_spi.c | 289 ++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 297 insertions(+) create mode 100644 drivers/spi/mvebu_a3700_spi.cdrivers/spi/Kconfig +7
-0@@ -68,6 +68,13 @@ config ICH_SPI access the SPI NOR flash on platforms embedding this Intel ICH IP core. +config MVEBU_A3700_SPI + bool "Marvell Armada 3700 SPI driver" + help + Enable the Marvell Armada 3700 SPI driver. This driver can be + used to access the SPI NOR flash on platforms embedding this + Marvell IP core. + config PIC32_SPI bool "Microchip PIC32 SPI driver" depends on MACH_PIC32drivers/spi/Makefile +1
-0@@ -37,6 +37,7 @@ obj-$(CONFIG_KIRKWOOD_SPI) += kirkwood_spi.o obj-$(CONFIG_LPC32XX_SSP) += lpc32xx_ssp.o obj-$(CONFIG_MPC52XX_SPI) += mpc52xx_spi.o obj-$(CONFIG_MPC8XXX_SPI) += mpc8xxx_spi.o +obj-$(CONFIG_MVEBU_A3700_SPI) += mvebu_a3700_spi.o obj-$(CONFIG_MXC_SPI) += mxc_spi.o obj-$(CONFIG_MXS_SPI) += mxs_spi.o obj-$(CONFIG_OMAP3_SPI) += omap3_spi.odrivers/spi/mvebu_a3700_spi.c new file +181
-0@@ -0,0 +1,289 @@ +/* +* Copyright (C) 2015 Marvell International Ltd. +* +* Copyright (C) 2016 Stefan Roese <[email protected]> +* +* SPDX-License-Identifier: GPL-2.0+ +*/ + +#include <common.h> +#include <dm.h> +#include <malloc.h> +#include <spi.h> +#include <wait_bit.h> +#include <asm/io.h> + +DECLARE_GLOBAL_DATA_PTR ; + +#define SPI_TIMEOUT 10000 + +#define MVEBU_SPI_A3700_XFER_RDY BIT(1) +#define MVEBU_SPI_A3700_FIFO_FLUSH BIT(9) +#define MVEBU_SPI_A3700_BYTE_LEN BIT(5) +#define MVEBU_SPI_A3700_CLK_PHA BIT(6) +#define MVEBU_SPI_A3700_CLK_POL BIT(7) +#define MVEBU_SPI_A3700_FIFO_EN BIT(17) +#define MVEBU_SPI_A3700_SPI_EN_0 BIT(16) +#define MVEBU_SPI_A3700_CLK_PRESCALE_BIT 0 +#define MVEBU_SPI_A3700_CLK_PRESCALE_MASK \ + (0x1f << MVEBU_SPI_A3700_CLK_PRESCALE_BIT) + +/* SPI registers */ +struct spi_reg { +u32 ctrl;/* 0x10600 */ +u32 cfg;/* 0x10604 */ +u32 dout;/* 0x10608 */ +u32 din;/* 0x1060c */ +}; + +struct mvebu_spi_platdata { +struct spi_reg *spireg; +unsigned int frequency; +unsigned int clock; +}; + +static void spi_cs_activate (struct spi_reg *reg,int cs) +{ +setbits_le32 (®->ctrl,MVEBU_SPI_A3700_SPI_EN_0 << cs); +} + +static void spi_cs_deactivate (struct spi_reg *reg,int cs) +{ +clrbits_le32 (®->ctrl,MVEBU_SPI_A3700_SPI_EN_0 << cs); +} + +/** +* spi_legacy_shift_byte() - triggers the real SPI transfer +* @bytelen: Indicate how many bytes to transfer. +* @dout: Buffer address of what to send. +* @din: Buffer address of where to receive. +* +* This function triggers the real SPI transfer in legacy mode. It +* will shift out char buffer from @dout, and shift in char buffer to +* @din, if necessary. +* +* This function assumes that only one byte is shifted at one time. +* However, it is not its responisbility to set the transfer type to +* one-byte. Also, it does not guarantee that it will work if transfer +* type becomes two-byte. See spi_set_legacy() for details. +* +* In legacy mode, simply write to the SPI_DOUT register will trigger +* the transfer. +* +* If @dout == NULL, which means no actual data needs to be sent out, +* then the function will shift out 0x00 in order to shift in data. +* The XFER_RDY flag is checked every time before accessing SPI_DOUT +* and SPI_DIN register. +* +* The number of transfers to be triggerred is decided by @bytelen. +* +* Return: 0 - cool +* -ETIMEDOUT - XFER_RDY flag timeout +*/ +static int spi_legacy_shift_byte (struct spi_reg *reg,unsigned int bytelen, +const void *dout,void *din) +{ +const u8 *dout_8; +u8 *din_8; +int ret; + +/* Use 0x00 as dummy dout */ +const u8 dummy_dout =0x0 ; +u32 pending_dout =0x0 ; + +/* dout_8: pointer of current dout */ + dout_8 = dout; +/* din_8: pointer of current din */ + din_8 = din; + +while (bytelen) { + ret =wait_for_bit (__func__, ®->ctrl, +MVEBU_SPI_A3700_XFER_RDY , true,100 , false); +if (ret) +return ret; + +if (dout) + pending_dout = (u32)*dout_8; +else + pending_dout = (u32 )dummy_dout; + +/* Trigger the xfer */ +writel (pending_dout, ®->dout); + +if (din) { + ret =wait_for_bit (__func__, ®->ctrl, +MVEBU_SPI_A3700_XFER_RDY , + true,100 , false); +if (ret) +return ret; + +/* Read what is transferred in */ + *din_8 = (u8 )readl (®->din); + } + +/* Don't increment the current pointer if NULL */ +if (dout) + dout_8++; +if (din) + din_8++; + + bytelen--; + } + +return 0 ; +} + +static int mvebu_spi_xfer (struct udevice *dev,unsigned int bitlen, +const void *dout,void *din,unsigned long flags) +{ +struct udevice *bus = dev->parent; +struct mvebu_spi_platdata *plat =dev_get_platdata (bus); +struct spi_reg *reg = plat->spireg; +unsigned int bytelen; +int ret; + + bytelen = bitlen /8 ; + +if (dout && din) +debug ("This is a duplex transfer.\n" ); + +/* Activate CS */ +if (flags &SPI_XFER_BEGIN ) { +debug ("SPI: activate cs.\n" ); +spi_cs_activate (reg,spi_chip_select (dev)); + } + +/* Send and/or receive */ +if (dout || din) { + ret =spi_legacy_shift_byte (reg, bytelen, dout, din); +if (ret) +return ret; + } + +/* Deactivate CS */ +if (flags &SPI_XFER_END ) { + ret =wait_for_bit (__func__, ®->ctrl, +MVEBU_SPI_A3700_XFER_RDY , true,100 , false); +if (ret) +return ret; + +debug ("SPI: deactivate cs.\n" ); +spi_cs_deactivate (reg,spi_chip_select (dev)); + } + +return 0 ; +} + +static int mvebu_spi_set_speed (struct udevice *bus,uint hz) +{ +struct mvebu_spi_platdata *plat =dev_get_platdata (bus); +struct spi_reg *reg = plat->spireg; +u32 data;
drivers/spi/mvebu_a3700_spi.c line 191
Quoted 10 lines
drivers/spi/mvebu_a3700_spi.c new file +10
-0+ + data =readl (®->cfg); + +/* Set Prescaler */ + data &= ~MVEBU_SPI_A3700_CLK_PRESCALE_MASK ; + +/* Calculate Prescaler = (spi_input_freq / spi_max_freq) */ +if (hz > plat->frequency) + hz = plat->frequency; + data |= plat->clock / plat->frequency;
Need to use the hz to compute here.
Quoted 58 lines
drivers/spi/mvebu_a3700_spi.c new file +58
-0+ +writel (data, ®->cfg); + +return 0 ; +} + +static int mvebu_spi_set_mode (struct udevice *bus,uint mode) +{ +struct mvebu_spi_platdata *plat =dev_get_platdata (bus); +struct spi_reg *reg = plat->spireg; + +/* +* Set SPI polarity +* 0: Serial interface clock is low when inactive +* 1: Serial interface clock is high when inactive +*/ +if (mode &SPI_CPOL ) +setbits_le32 (®->cfg,MVEBU_SPI_A3700_CLK_POL ); +else +clrbits_le32 (®->cfg,MVEBU_SPI_A3700_CLK_POL ); +if (mode &SPI_CPHA ) +setbits_le32 (®->cfg,MVEBU_SPI_A3700_CLK_PHA ); +else +clrbits_le32 (®->cfg,MVEBU_SPI_A3700_CLK_PHA ); + +return 0 ; +} + +static int mvebu_spi_probe (struct udevice *bus) +{ +struct mvebu_spi_platdata *plat =dev_get_platdata (bus); +struct spi_reg *reg = plat->spireg; +u32 data; +int ret; + +/* +* Settings SPI controller to be working in legacy mode, which +* means use only DO pin (I/O 1) for Data Out, and DI pin (I/O 0) +* for Data In. +*/ + +/* Flush read/write FIFO */ + data =readl (®->cfg); +writel (data |MVEBU_SPI_A3700_FIFO_FLUSH , ®->cfg); + ret =wait_for_bit (__func__, ®->cfg,MVEBU_SPI_A3700_FIFO_FLUSH , + false,1000 , false); +if (ret) +return ret; + +/* Disable FIFO mode */ + data &= ~MVEBU_SPI_A3700_FIFO_EN ; + +/* Always shift 1 byte at a time */ + data &= ~MVEBU_SPI_A3700_BYTE_LEN ; + +writel (data, ®->cfg); + +return 0 ;
drivers/spi/mvebu_a3700_spi.c line 259
Quoted 10 lines
drivers/spi/mvebu_a3700_spi.c new file +10
-0+} + +static int mvebu_spi_ofdata_to_platdata (struct udevice *bus) +{ +struct mvebu_spi_platdata *plat =dev_get_platdata (bus); + + plat->spireg = (struct spi_reg *)dev_get_addr (bus); + + plat->clock =fdtdec_get_int (gd->fdt_blob, bus->of_offset, +"clock-frequency" ,160000 );
I think this is not related to spi, global clock is it? usually we can't use clock-frequency we set the clock with the help of spi-max-frequency.
thanks!
Signature · 4 lines
Jagan Teki Free Software Engineer | www.openedev.com U-Boot, Linux | Upstream Maintainer Hyderabad, India.
PATCH v2 2/15 spi: Add driver for Marvell Armada 3700 SoC
Quoted 248 lines · Jagan Teki
Quoted 247 lines · Stefan Roese
The SPI IP core in the Marvell Armada 3700 is similar to the one in the other Armada SoCs. But the differences are big enough that it makes sense to introduce a new driver instead of cluttering the old kirkwood driver with #ifdef's.
Signed-off-by Stefan Roese <[email protected]>Cc Nadav Haklai <[email protected]>Cc Kostya Porotchkin <[email protected]>Cc Wilson Ding <[email protected]>Cc Victor Gu <[email protected]>Cc Hua Jing <[email protected]>Cc Terry Zhou <[email protected]>Cc Hanna Hawa <[email protected]>Cc Haim Boot <[email protected]>Cc Jagan Teki <[email protected]>---
v2:
- Evaluated hz and used values provided by the DT inmvebu_spi_set_speed()as suggested by Jagandrivers/spi/Kconfig | 7 + drivers/spi/Makefile | 1 + drivers/spi/mvebu_a3700_spi.c | 289 ++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 297 insertions(+) create mode 100644 drivers/spi/mvebu_a3700_spi.cdrivers/spi/Kconfig +7
-0@@ -68,6 +68,13 @@ config ICH_SPI access the SPI NOR flash on platforms embedding this Intel ICH IP core. +config MVEBU_A3700_SPI + bool "Marvell Armada 3700 SPI driver" + help + Enable the Marvell Armada 3700 SPI driver. This driver can be + used to access the SPI NOR flash on platforms embedding this + Marvell IP core. + config PIC32_SPI bool "Microchip PIC32 SPI driver" depends on MACH_PIC32drivers/spi/Makefile +1
-0@@ -37,6 +37,7 @@ obj-$(CONFIG_KIRKWOOD_SPI) += kirkwood_spi.o obj-$(CONFIG_LPC32XX_SSP) += lpc32xx_ssp.o obj-$(CONFIG_MPC52XX_SPI) += mpc52xx_spi.o obj-$(CONFIG_MPC8XXX_SPI) += mpc8xxx_spi.o +obj-$(CONFIG_MVEBU_A3700_SPI) += mvebu_a3700_spi.o obj-$(CONFIG_MXC_SPI) += mxc_spi.o obj-$(CONFIG_MXS_SPI) += mxs_spi.o obj-$(CONFIG_OMAP3_SPI) += omap3_spi.odrivers/spi/mvebu_a3700_spi.c new file +185
-0@@ -0,0 +1,289 @@ +/* +* Copyright (C) 2015 Marvell International Ltd. +* +* Copyright (C) 2016 Stefan Roese <[email protected]> +* +* SPDX-License-Identifier: GPL-2.0+ +*/ + +#include <common.h> +#include <dm.h> +#include <malloc.h> +#include <spi.h> +#include <wait_bit.h> +#include <asm/io.h> + +DECLARE_GLOBAL_DATA_PTR ; + +#define SPI_TIMEOUT 10000 + +#define MVEBU_SPI_A3700_XFER_RDY BIT(1) +#define MVEBU_SPI_A3700_FIFO_FLUSH BIT(9) +#define MVEBU_SPI_A3700_BYTE_LEN BIT(5) +#define MVEBU_SPI_A3700_CLK_PHA BIT(6) +#define MVEBU_SPI_A3700_CLK_POL BIT(7) +#define MVEBU_SPI_A3700_FIFO_EN BIT(17) +#define MVEBU_SPI_A3700_SPI_EN_0 BIT(16) +#define MVEBU_SPI_A3700_CLK_PRESCALE_BIT 0 +#define MVEBU_SPI_A3700_CLK_PRESCALE_MASK \ + (0x1f << MVEBU_SPI_A3700_CLK_PRESCALE_BIT) + +/* SPI registers */ +struct spi_reg { +u32 ctrl;/* 0x10600 */ +u32 cfg;/* 0x10604 */ +u32 dout;/* 0x10608 */ +u32 din;/* 0x1060c */ +}; + +struct mvebu_spi_platdata { +struct spi_reg *spireg; +unsigned int frequency; +unsigned int clock; +}; + +static void spi_cs_activate (struct spi_reg *reg,int cs) +{ +setbits_le32 (®->ctrl,MVEBU_SPI_A3700_SPI_EN_0 << cs); +} + +static void spi_cs_deactivate (struct spi_reg *reg,int cs) +{ +clrbits_le32 (®->ctrl,MVEBU_SPI_A3700_SPI_EN_0 << cs); +} + +/** +* spi_legacy_shift_byte() - triggers the real SPI transfer +* @bytelen: Indicate how many bytes to transfer. +* @dout: Buffer address of what to send. +* @din: Buffer address of where to receive. +* +* This function triggers the real SPI transfer in legacy mode. It +* will shift out char buffer from @dout, and shift in char buffer to +* @din, if necessary. +* +* This function assumes that only one byte is shifted at one time. +* However, it is not its responisbility to set the transfer type to +* one-byte. Also, it does not guarantee that it will work if transfer +* type becomes two-byte. See spi_set_legacy() for details. +* +* In legacy mode, simply write to the SPI_DOUT register will trigger +* the transfer. +* +* If @dout == NULL, which means no actual data needs to be sent out, +* then the function will shift out 0x00 in order to shift in data. +* The XFER_RDY flag is checked every time before accessing SPI_DOUT +* and SPI_DIN register. +* +* The number of transfers to be triggerred is decided by @bytelen. +* +* Return: 0 - cool +* -ETIMEDOUT - XFER_RDY flag timeout +*/ +static int spi_legacy_shift_byte (struct spi_reg *reg,unsigned int bytelen, +const void *dout,void *din) +{ +const u8 *dout_8; +u8 *din_8; +int ret; + +/* Use 0x00 as dummy dout */ +const u8 dummy_dout =0x0 ; +u32 pending_dout =0x0 ; + +/* dout_8: pointer of current dout */ + dout_8 = dout; +/* din_8: pointer of current din */ + din_8 = din; + +while (bytelen) { + ret =wait_for_bit (__func__, ®->ctrl, +MVEBU_SPI_A3700_XFER_RDY , true,100 , false); +if (ret) +return ret; + +if (dout) + pending_dout = (u32)*dout_8; +else + pending_dout = (u32 )dummy_dout; + +/* Trigger the xfer */ +writel (pending_dout, ®->dout); + +if (din) { + ret =wait_for_bit (__func__, ®->ctrl, +MVEBU_SPI_A3700_XFER_RDY , + true,100 , false); +if (ret) +return ret; + +/* Read what is transferred in */ + *din_8 = (u8 )readl (®->din); + } + +/* Don't increment the current pointer if NULL */ +if (dout) + dout_8++; +if (din) + din_8++; + + bytelen--; + } + +return 0 ; +} + +static int mvebu_spi_xfer (struct udevice *dev,unsigned int bitlen, +const void *dout,void *din,unsigned long flags) +{ +struct udevice *bus = dev->parent; +struct mvebu_spi_platdata *plat =dev_get_platdata (bus); +struct spi_reg *reg = plat->spireg; +unsigned int bytelen; +int ret; + + bytelen = bitlen /8 ; + +if (dout && din) +debug ("This is a duplex transfer.\n" ); + +/* Activate CS */ +if (flags &SPI_XFER_BEGIN ) { +debug ("SPI: activate cs.\n" ); +spi_cs_activate (reg,spi_chip_select (dev)); + } + +/* Send and/or receive */ +if (dout || din) { + ret =spi_legacy_shift_byte (reg, bytelen, dout, din); +if (ret) +return ret; + } + +/* Deactivate CS */ +if (flags &SPI_XFER_END ) { + ret =wait_for_bit (__func__, ®->ctrl, +MVEBU_SPI_A3700_XFER_RDY , true,100 , false); +if (ret) +return ret; + +debug ("SPI: deactivate cs.\n" ); +spi_cs_deactivate (reg,spi_chip_select (dev)); + } + +return 0 ; +} + +static int mvebu_spi_set_speed (struct udevice *bus,uint hz) +{ +struct mvebu_spi_platdata *plat =dev_get_platdata (bus); +struct spi_reg *reg = plat->spireg; +u32 data; + + data =readl (®->cfg); + +/* Set Prescaler */
Quoted 8 lines
drivers/spi/mvebu_a3700_spi.c line 191
Quoted 6 lines
drivers/spi/mvebu_a3700_spi.c new file +6
-0+ data &= ~MVEBU_SPI_A3700_CLK_PRESCALE_MASK ; + +/* Calculate Prescaler = (spi_input_freq / spi_max_freq) */ +if (hz > plat->frequency) + hz = plat->frequency; + data |= plat->clock / plat->frequency;Need to use the hz to compute here.
Yes, hz should be used instead of plat->frequency here. Will fix in v3. Thanks for noticing.
Quoted 64 lines
Quoted 64 lines
drivers/spi/mvebu_a3700_spi.c new file +64
-0+ +writel (data, ®->cfg); + +return 0 ; +} + +static int mvebu_spi_set_mode (struct udevice *bus,uint mode) +{ +struct mvebu_spi_platdata *plat =dev_get_platdata (bus); +struct spi_reg *reg = plat->spireg; + +/* +* Set SPI polarity +* 0: Serial interface clock is low when inactive +* 1: Serial interface clock is high when inactive +*/ +if (mode &SPI_CPOL ) +setbits_le32 (®->cfg,MVEBU_SPI_A3700_CLK_POL ); +else +clrbits_le32 (®->cfg,MVEBU_SPI_A3700_CLK_POL ); +if (mode &SPI_CPHA ) +setbits_le32 (®->cfg,MVEBU_SPI_A3700_CLK_PHA ); +else +clrbits_le32 (®->cfg,MVEBU_SPI_A3700_CLK_PHA ); + +return 0 ; +} + +static int mvebu_spi_probe (struct udevice *bus) +{ +struct mvebu_spi_platdata *plat =dev_get_platdata (bus); +struct spi_reg *reg = plat->spireg; +u32 data; +int ret; + +/* +* Settings SPI controller to be working in legacy mode, which +* means use only DO pin (I/O 1) for Data Out, and DI pin (I/O 0) +* for Data In. +*/ + +/* Flush read/write FIFO */ + data =readl (®->cfg); +writel (data |MVEBU_SPI_A3700_FIFO_FLUSH , ®->cfg); + ret =wait_for_bit (__func__, ®->cfg,MVEBU_SPI_A3700_FIFO_FLUSH , + false,1000 , false); +if (ret) +return ret; + +/* Disable FIFO mode */ + data &= ~MVEBU_SPI_A3700_FIFO_EN ; + +/* Always shift 1 byte at a time */ + data &= ~MVEBU_SPI_A3700_BYTE_LEN ; + +writel (data, ®->cfg); + +return 0 ; +} + +static int mvebu_spi_ofdata_to_platdata (struct udevice *bus) +{ +struct mvebu_spi_platdata *plat =dev_get_platdata (bus); +
Quoted 8 lines
drivers/spi/mvebu_a3700_spi.c line 259
Quoted 4 lines
drivers/spi/mvebu_a3700_spi.c new file +4
-0+ plat->spireg = (struct spi_reg *)dev_get_addr (bus); + + plat->clock =fdtdec_get_int (gd->fdt_blob, bus->of_offset, +"clock-frequency" ,160000 );I think this is not related to spi, global clock is it? usually we can't use clock-frequency we set the clock with the help of spi-max-frequency.
This is the input clock to the SPI IP core in the SoC. And in most drivers I've seen so far, this frequency is configured via some macros / defines. E.g.:
CONFIG_SYS_TCLKCONFIG_CQSPI_REF_CLK
...
Best would be if this SPI input clock could be read via some clock driver infrastructure. But this is something that we don't have for MVEBU in U-Boot yet. So I can either switch back to some define for this value here or leave it as the DT property for now.
Thanks,
Stefan
PATCH v2 2/15 spi: Add driver for Marvell Armada 3700 SoC
Quoted 357 lines · Stefan Roese
Quoted 258 lines · Jagan Teki
Quoted 256 lines · Stefan Roese
The SPI IP core in the Marvell Armada 3700 is similar to the one in the other Armada SoCs. But the differences are big enough that it makes sense to introduce a new driver instead of cluttering the old kirkwood driver with #ifdef's.
Signed-off-by Stefan Roese <[email protected]>Cc Nadav Haklai <[email protected]>Cc Kostya Porotchkin <[email protected]>Cc Wilson Ding <[email protected]>Cc Victor Gu <[email protected]>Cc Hua Jing <[email protected]>Cc Terry Zhou <[email protected]>Cc Hanna Hawa <[email protected]>Cc Haim Boot <[email protected]>Cc Jagan Teki <[email protected]>---
v2:
- Evaluated hz and used values provided by the DT inmvebu_spi_set_speed()
as suggested by Jagandrivers/spi/Kconfig | 7 + drivers/spi/Makefile | 1 + drivers/spi/mvebu_a3700_spi.c | 289 ++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 297 insertions(+) create mode 100644 drivers/spi/mvebu_a3700_spi.cdrivers/spi/Kconfig +7
-0@@ -68,6 +68,13 @@ config ICH_SPI access the SPI NOR flash on platforms embedding this Intel ICH IP core. +config MVEBU_A3700_SPI + bool "Marvell Armada 3700 SPI driver" + help + Enable the Marvell Armada 3700 SPI driver. This driver can be + used to access the SPI NOR flash on platforms embedding this + Marvell IP core. + config PIC32_SPI bool "Microchip PIC32 SPI driver" depends on MACH_PIC32drivers/spi/Makefile +1
-0@@ -37,6 +37,7 @@ obj-$(CONFIG_KIRKWOOD_SPI) += kirkwood_spi.o obj-$(CONFIG_LPC32XX_SSP) += lpc32xx_ssp.o obj-$(CONFIG_MPC52XX_SPI) += mpc52xx_spi.o obj-$(CONFIG_MPC8XXX_SPI) += mpc8xxx_spi.o +obj-$(CONFIG_MVEBU_A3700_SPI) += mvebu_a3700_spi.o obj-$(CONFIG_MXC_SPI) += mxc_spi.o obj-$(CONFIG_MXS_SPI) += mxs_spi.o obj-$(CONFIG_OMAP3_SPI) += omap3_spi.odrivers/spi/mvebu_a3700_spi.c new file +83
-0@@ -0,0 +1,289 @@ +/* +* Copyright (C) 2015 Marvell International Ltd. +* +* Copyright (C) 2016 Stefan Roese <[email protected]> +* +* SPDX-License-Identifier: GPL-2.0+ +*/ + +#include <common.h> +#include <dm.h> +#include <malloc.h> +#include <spi.h> +#include <wait_bit.h> +#include <asm/io.h> + +DECLARE_GLOBAL_DATA_PTR ; + +#define SPI_TIMEOUT 10000 + +#define MVEBU_SPI_A3700_XFER_RDY BIT(1) +#define MVEBU_SPI_A3700_FIFO_FLUSH BIT(9) +#define MVEBU_SPI_A3700_BYTE_LEN BIT(5) +#define MVEBU_SPI_A3700_CLK_PHA BIT(6) +#define MVEBU_SPI_A3700_CLK_POL BIT(7) +#define MVEBU_SPI_A3700_FIFO_EN BIT(17) +#define MVEBU_SPI_A3700_SPI_EN_0 BIT(16) +#define MVEBU_SPI_A3700_CLK_PRESCALE_BIT 0 +#define MVEBU_SPI_A3700_CLK_PRESCALE_MASK \ + (0x1f << MVEBU_SPI_A3700_CLK_PRESCALE_BIT) + +/* SPI registers */ +struct spi_reg { +u32 ctrl;/* 0x10600 */ +u32 cfg;/* 0x10604 */ +u32 dout;/* 0x10608 */ +u32 din;/* 0x1060c */ +}; + +struct mvebu_spi_platdata { +struct spi_reg *spireg; +unsigned int frequency; +unsigned int clock; +}; + +static void spi_cs_activate (struct spi_reg *reg,int cs) +{ +setbits_le32 (®->ctrl,MVEBU_SPI_A3700_SPI_EN_0 << cs); +} + +static void spi_cs_deactivate (struct spi_reg *reg,int cs) +{ +clrbits_le32 (®->ctrl,MVEBU_SPI_A3700_SPI_EN_0 << cs); +} + +/** +* spi_legacy_shift_byte() - triggers the real SPI transfer +* @bytelen: Indicate how many bytes to transfer. +* @dout: Buffer address of what to send. +* @din: Buffer address of where to receive. +* +* This function triggers the real SPI transfer in legacy mode. It +* will shift out char buffer from @dout, and shift in char buffer to +* @din, if necessary. +* +* This function assumes that only one byte is shifted at one time. +* However, it is not its responisbility to set the transfer type to +* one-byte. Also, it does not guarantee that it will work if transfer +* type becomes two-byte. See spi_set_legacy() for details. +* +* In legacy mode, simply write to the SPI_DOUT register will trigger +* the transfer. +* +* If @dout == NULL, which means no actual data needs to be sent out, +* then the function will shift out 0x00 in order to shift in data. +* The XFER_RDY flag is checked every time before accessing SPI_DOUT +* and SPI_DIN register. +* +* The number of transfers to be triggerred is decided by @bytelen. +* +* Return: 0 - cool +* -ETIMEDOUT - XFER_RDY flag timeout +*/ +static int spi_legacy_shift_byte(struct spi_reg *reg, unsigned intbytelen,
drivers/spi/mvebu_a3700_spi.c new file +18
-0+ const void *dout, void *din) +{ + const u8 *dout_8; +u8 *din_8; +int ret; + +/* Use 0x00 as dummy dout */ +const u8 dummy_dout =0x0 ; +u32 pending_dout =0x0 ; + +/* dout_8: pointer of current dout */ + dout_8 = dout; +/* din_8: pointer of current din */ + din_8 = din; + + while (bytelen) { + ret = wait_for_bit(__func__, ®->ctrl, + MVEBU_SPI_A3700_XFER_RDY, true, 100,false);
drivers/spi/mvebu_a3700_spi.c new file +36
-0+if (ret) +return ret; + +if (dout) + pending_dout = (u32)*dout_8; +else + pending_dout = (u32 )dummy_dout; + +/* Trigger the xfer */ +writel (pending_dout, ®->dout); + +if (din) { + ret =wait_for_bit (__func__, ®->ctrl, +MVEBU_SPI_A3700_XFER_RDY , + true,100 , false); +if (ret) +return ret; + +/* Read what is transferred in */ + *din_8 = (u8 )readl (®->din); + } + +/* Don't increment the current pointer if NULL */ +if (dout) + dout_8++; +if (din) + din_8++; + + bytelen--; + } + +return 0 ; +} + +static int mvebu_spi_xfer (struct udevice *dev,unsigned int bitlen, + const void *dout, void *din, unsigned longflags)
drivers/spi/mvebu_a3700_spi.c new file +29
-0+{ +struct udevice *bus = dev->parent; +struct mvebu_spi_platdata *plat =dev_get_platdata (bus); +struct spi_reg *reg = plat->spireg; +unsigned int bytelen; +int ret; + + bytelen = bitlen /8 ; + +if (dout && din) +debug ("This is a duplex transfer.\n" ); + +/* Activate CS */ +if (flags &SPI_XFER_BEGIN ) { +debug ("SPI: activate cs.\n" ); +spi_cs_activate (reg,spi_chip_select (dev)); + } + +/* Send and/or receive */ +if (dout || din) { + ret =spi_legacy_shift_byte (reg, bytelen, dout, din); +if (ret) +return ret; + } + +/* Deactivate CS */ +if (flags &SPI_XFER_END ) { + ret = wait_for_bit(__func__, ®->ctrl, + MVEBU_SPI_A3700_XFER_RDY, true, 100,false);
drivers/spi/mvebu_a3700_spi.c new file +20
-0+if (ret) +return ret; + +debug ("SPI: deactivate cs.\n" ); +spi_cs_deactivate (reg,spi_chip_select (dev)); + } + +return 0 ; +} + +static int mvebu_spi_set_speed (struct udevice *bus,uint hz) +{ +struct mvebu_spi_platdata *plat =dev_get_platdata (bus); +struct spi_reg *reg = plat->spireg; +u32 data; + + data =readl (®->cfg); + +/* Set Prescaler */ + data &= ~MVEBU_SPI_A3700_CLK_PRESCALE_MASK ;Quoted 8 lines
drivers/spi/mvebu_a3700_spi.c line 191
Quoted 5 lines
drivers/spi/mvebu_a3700_spi.c new file +5
-0+ +/* Calculate Prescaler = (spi_input_freq / spi_max_freq) */ +if (hz > plat->frequency) + hz = plat->frequency; + data |= plat->clock / plat->frequency;Need to use the hz to compute here.
Yes, hz should be used instead of
plat->frequencyhere. Will fix in v3. Thanks for noticing.Quoted 66 lines
Quoted 66 lines
drivers/spi/mvebu_a3700_spi.c new file +45
-0+ +writel (data, ®->cfg); + +return 0 ; +} + +static int mvebu_spi_set_mode (struct udevice *bus,uint mode) +{ +struct mvebu_spi_platdata *plat =dev_get_platdata (bus); +struct spi_reg *reg = plat->spireg; + +/* +* Set SPI polarity +* 0: Serial interface clock is low when inactive +* 1: Serial interface clock is high when inactive +*/ +if (mode &SPI_CPOL ) +setbits_le32 (®->cfg,MVEBU_SPI_A3700_CLK_POL ); +else +clrbits_le32 (®->cfg,MVEBU_SPI_A3700_CLK_POL ); +if (mode &SPI_CPHA ) +setbits_le32 (®->cfg,MVEBU_SPI_A3700_CLK_PHA ); +else +clrbits_le32 (®->cfg,MVEBU_SPI_A3700_CLK_PHA ); + +return 0 ; +} + +static int mvebu_spi_probe (struct udevice *bus) +{ +struct mvebu_spi_platdata *plat =dev_get_platdata (bus); +struct spi_reg *reg = plat->spireg; +u32 data; +int ret; + +/* +* Settings SPI controller to be working in legacy mode, which +* means use only DO pin (I/O 1) for Data Out, and DI pin (I/O 0) +* for Data In. +*/ + +/* Flush read/write FIFO */ + data =readl (®->cfg); +writel (data |MVEBU_SPI_A3700_FIFO_FLUSH , ®->cfg); + ret = wait_for_bit(__func__, ®->cfg,
MVEBU_SPI_A3700_FIFO_FLUSH,drivers/spi/mvebu_a3700_spi.c new file +20
-0+ false, 1000, false); +if (ret) +return ret; + +/* Disable FIFO mode */ + data &= ~MVEBU_SPI_A3700_FIFO_EN ; + +/* Always shift 1 byte at a time */ + data &= ~MVEBU_SPI_A3700_BYTE_LEN ; + +writel (data, ®->cfg); + +return 0 ; +} + +static int mvebu_spi_ofdata_to_platdata (struct udevice *bus) +{ +struct mvebu_spi_platdata *plat =dev_get_platdata (bus); + + plat->spireg = (struct spi_reg *)dev_get_addr (bus);Quoted 8 lines
drivers/spi/mvebu_a3700_spi.c line 259
Quoted 3 lines
drivers/spi/mvebu_a3700_spi.c new file +3
-0+ + plat->clock =fdtdec_get_int (gd->fdt_blob, bus->of_offset, +"clock-frequency" ,160000 );I think this is not related to spi, global clock is it? usually we can't use clock-frequency we set the clock with the help of spi-max-frequency.
This is the input clock to the SPI IP core in the SoC. And in most drivers I've seen so far, this frequency is configured via some macros / defines. E.g.:
CONFIG_SYS_TCLKCONFIG_CQSPI_REF_CLK
...
Quoted 5 lines
Best would be if this SPI input clock could be read via some clock driver infrastructure. But this is something that we don't have for MVEBU in U-Boot yet. So I can either switch back to some define for this value here or leave it as the DT property for now.
OK, use the dt and add FIXME with some proper comment.
thanks!
Signature · 4 lines
Jagan Teki Free Software Engineer | www.openedev.com U-Boot, Linux | Upstream Maintainer Hyderabad, India.
PATCH v3 2/15 spi: Add driver for Marvell Armada 3700 SoC
In reply to Stefan RoeseThe SPI IP core in the Marvell Armada 3700 is similar to the one in the other Armada SoCs. But the differences are big enough that it makes sense to introduce a new driver instead of cluttering the old kirkwood driver with #ifdef's.
Signed-off-by Stefan Roese <[email protected]>
Cc Nadav Haklai <[email protected]>
Cc Kostya Porotchkin <[email protected]>
Cc Wilson Ding <[email protected]>
Cc Victor Gu <[email protected]>
Cc Hua Jing <[email protected]>
Cc Terry Zhou <[email protected]>
Cc Hanna Hawa <[email protected]>
Cc Haim Boot <[email protected]>
Cc Jagan Teki <[email protected]>
---
v3:
- Really use hz now in equation
- Add comment that the DT property for the input clock is deprecated and the clock infrastructure should be used, once available for mvebu in U-Boot
v2:
- Evaluated hz and used values provided by the DT in mvebu_spi_set_speed() as suggested by Jagan
drivers/spi/Kconfig | 7 + drivers/spi/Makefile | 1 + drivers/spi/mvebu_a3700_spi.c | 297 ++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 305 insertions(+) create mode 100644 drivers/spi/mvebu_a3700_spi.c
drivers/spi/Kconfig +7 -0
@@ -68,6 +68,13 @@ config ICH_SPI access the SPI NOR flash on platforms embedding this Intel ICH IP core. +config MVEBU_A3700_SPI + bool "Marvell Armada 3700 SPI driver" + help + Enable the Marvell Armada 3700 SPI driver. This driver can be + used to access the SPI NOR flash on platforms embedding this + Marvell IP core. + config PIC32_SPI bool "Microchip PIC32 SPI driver" depends on MACH_PIC32
drivers/spi/Makefile +1 -0
@@ -37,6 +37,7 @@ obj-$(CONFIG_KIRKWOOD_SPI) += kirkwood_spi.o obj-$(CONFIG_LPC32XX_SSP) += lpc32xx_ssp.o obj-$(CONFIG_MPC52XX_SPI) += mpc52xx_spi.o obj-$(CONFIG_MPC8XXX_SPI) += mpc8xxx_spi.o +obj-$(CONFIG_MVEBU_A3700_SPI) += mvebu_a3700_spi.o obj-$(CONFIG_MXC_SPI) += mxc_spi.o obj-$(CONFIG_MXS_SPI) += mxs_spi.o obj-$(CONFIG_OMAP3_SPI) += omap3_spi.o
drivers/spi/mvebu_a3700_spi.c new file +297 -0
297 lines not on this page · raw message
Signature · 1 line
2.9.3
PATCH v3 2/15 spi: Add driver for Marvell Armada 3700 SoC
Quoted 76 lines · Stefan Roese
The SPI IP core in the Marvell Armada 3700 is similar to the one in the other Armada SoCs. But the differences are big enough that it makes sense to introduce a new driver instead of cluttering the old kirkwood driver with #ifdef's.
Signed-off-by Stefan Roese <[email protected]>Cc Nadav Haklai <[email protected]>Cc Kostya Porotchkin <[email protected]>Cc Wilson Ding <[email protected]>Cc Victor Gu <[email protected]>Cc Hua Jing <[email protected]>Cc Terry Zhou <[email protected]>Cc Hanna Hawa <[email protected]>Cc Haim Boot <[email protected]>Cc Jagan Teki <[email protected]>---
v3:
- Really use hz now in equation
- Add comment that the DT property for the input clock is deprecated and the clock infrastructure should be used, once available for mvebu in U-Bootv2:
- Evaluated hz and used values provided by the DT inmvebu_spi_set_speed()as suggested by Jagandrivers/spi/Kconfig | 7 + drivers/spi/Makefile | 1 + drivers/spi/mvebu_a3700_spi.c | 297 ++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 305 insertions(+) create mode 100644 drivers/spi/mvebu_a3700_spi.cdrivers/spi/Kconfig +7
-0@@ -68,6 +68,13 @@ config ICH_SPI access the SPI NOR flash on platforms embedding this Intel ICH IP core. +config MVEBU_A3700_SPI + bool "Marvell Armada 3700 SPI driver" + help + Enable the Marvell Armada 3700 SPI driver. This driver can be + used to access the SPI NOR flash on platforms embedding this + Marvell IP core. + config PIC32_SPI bool "Microchip PIC32 SPI driver" depends on MACH_PIC32drivers/spi/Makefile +1
-0@@ -37,6 +37,7 @@ obj-$(CONFIG_KIRKWOOD_SPI) += kirkwood_spi.o obj-$(CONFIG_LPC32XX_SSP) += lpc32xx_ssp.o obj-$(CONFIG_MPC52XX_SPI) += mpc52xx_spi.o obj-$(CONFIG_MPC8XXX_SPI) += mpc8xxx_spi.o +obj-$(CONFIG_MVEBU_A3700_SPI) += mvebu_a3700_spi.o obj-$(CONFIG_MXC_SPI) += mxc_spi.o obj-$(CONFIG_MXS_SPI) += mxs_spi.o obj-$(CONFIG_OMAP3_SPI) += omap3_spi.odrivers/spi/mvebu_a3700_spi.c new file +8
-0@@ -0,0 +1,297 @@ +/* +* Copyright (C) 2015 Marvell International Ltd. +* +* Copyright (C) 2016 Stefan Roese <[email protected]> +* +* SPDX-License-Identifier: GPL-2.0+ +*/ +
drivers/spi/mvebu_a3700_spi.c line 18
Quoted 10 lines
drivers/spi/mvebu_a3700_spi.c new file +10
-0+#include <common.h> +#include <dm.h> +#include <malloc.h> +#include <spi.h> +#include <wait_bit.h> +#include <asm/io.h> + +DECLARE_GLOBAL_DATA_PTR ; + +#define SPI_TIMEOUT 10000
Can you remove this - sorry, never looked previously.
Reviewed-by Jagan Teki <[email protected]>
thanks!
Signature · 4 lines
Jagan Teki Free Software Engineer | www.openedev.com U-Boot, Linux | Upstream Maintainer Hyderabad, India.
PATCH v3 2/15 spi: Add driver for Marvell Armada 3700 SoC
Quoted 81 lines · Jagan Teki
Quoted 80 lines · Stefan Roese
The SPI IP core in the Marvell Armada 3700 is similar to the one in the other Armada SoCs. But the differences are big enough that it makes sense to introduce a new driver instead of cluttering the old kirkwood driver with #ifdef's.
Signed-off-by Stefan Roese <[email protected]>Cc Nadav Haklai <[email protected]>Cc Kostya Porotchkin <[email protected]>Cc Wilson Ding <[email protected]>Cc Victor Gu <[email protected]>Cc Hua Jing <[email protected]>Cc Terry Zhou <[email protected]>Cc Hanna Hawa <[email protected]>Cc Haim Boot <[email protected]>Cc Jagan Teki <[email protected]>---
v3:
- Really use hz now in equation
- Add comment that the DT property for the input clock is deprecated and the clock infrastructure should be used, once available for mvebu in U-Bootv2:
- Evaluated hz and used values provided by the DT inmvebu_spi_set_speed()as suggested by Jagandrivers/spi/Kconfig | 7 + drivers/spi/Makefile | 1 + drivers/spi/mvebu_a3700_spi.c | 297 ++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 305 insertions(+) create mode 100644 drivers/spi/mvebu_a3700_spi.cdrivers/spi/Kconfig +7
-0@@ -68,6 +68,13 @@ config ICH_SPI access the SPI NOR flash on platforms embedding this Intel ICH IP core. +config MVEBU_A3700_SPI + bool "Marvell Armada 3700 SPI driver" + help + Enable the Marvell Armada 3700 SPI driver. This driver can be + used to access the SPI NOR flash on platforms embedding this + Marvell IP core. + config PIC32_SPI bool "Microchip PIC32 SPI driver" depends on MACH_PIC32drivers/spi/Makefile +1
-0@@ -37,6 +37,7 @@ obj-$(CONFIG_KIRKWOOD_SPI) += kirkwood_spi.o obj-$(CONFIG_LPC32XX_SSP) += lpc32xx_ssp.o obj-$(CONFIG_MPC52XX_SPI) += mpc52xx_spi.o obj-$(CONFIG_MPC8XXX_SPI) += mpc8xxx_spi.o +obj-$(CONFIG_MVEBU_A3700_SPI) += mvebu_a3700_spi.o obj-$(CONFIG_MXC_SPI) += mxc_spi.o obj-$(CONFIG_MXS_SPI) += mxs_spi.o obj-$(CONFIG_OMAP3_SPI) += omap3_spi.odrivers/spi/mvebu_a3700_spi.c new file +12
-0@@ -0,0 +1,297 @@ +/* +* Copyright (C) 2015 Marvell International Ltd. +* +* Copyright (C) 2016 Stefan Roese <[email protected]> +* +* SPDX-License-Identifier: GPL-2.0+ +*/ + +#include <common.h> +#include <dm.h> +#include <malloc.h> +#include <spi.h>
Quoted 8 lines
drivers/spi/mvebu_a3700_spi.c line 18
Quoted 6 lines
drivers/spi/mvebu_a3700_spi.c new file +6
-0+#include <wait_bit.h> +#include <asm/io.h> + +DECLARE_GLOBAL_DATA_PTR ; + +#define SPI_TIMEOUT 10000Can you remove this - sorry, never looked previously.
Done.
Quoted 1 line
Reviewed-by Jagan Teki <[email protected]>
Added.
Thanks,
Stefan
PATCH 3/15 net: mvneta: Make driver 64bit safe
In reply to Stefan RoeseThe mvneta driver is also used on the ARMv8 64bit Armada 3700 SoC. This patch fixes the compilation warnings seen on this 64bit platform.
Signed-off-by Stefan Roese <[email protected]>
Cc Nadav Haklai <[email protected]>
Cc Kostya Porotchkin <[email protected]>
Cc Wilson Ding <[email protected]>
Cc Victor Gu <[email protected]>
Cc Hua Jing <[email protected]>
Cc Terry Zhou <[email protected]>
Cc Hanna Hawa <[email protected]>
Cc Haim Boot <[email protected]>
Cc Joe Hershberger <[email protected]>
--- drivers/net/mvneta.c | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-)
drivers/net/mvneta.c +8 -8
@@ -1022,7 +1022,7 @@ static int mvneta_txq_init(struct mvneta_port *pp, txq->size = pp->tx_ring_size;/* Allocate memory for TX descriptors */ - txq->descs_phys = (u32 )txq->descs; + txq->descs_phys = (dma_addr_t )txq->descs;if (txq->descs ==NULL )return -ENOMEM ;
@@ -1504,10 +1504,10 @@ static int mvneta_send(struct udevice *dev, void *packet, int length)/* Get a descriptor for the first part of the packet */ tx_desc =mvneta_txq_next_desc_get (txq); - tx_desc->buf_phys_addr = (u32 )packet; + tx_desc->buf_phys_addr = (u32 )(uintptr_t )packet; tx_desc->data_size = length; -flush_dcache_range ((u32 )packet, - (u32 )packet +ALIGN (length,PKTALIGN )); +flush_dcache_range ((ulong )packet, + (ulong )packet +ALIGN (length,PKTALIGN ));/* First and Last descriptor */ tx_desc->command =MVNETA_TX_L4_CSUM_NOT |MVNETA_TXD_FLZ_DESC ;
@@ -1563,7 +1563,7 @@ static int mvneta_recv(struct udevice *dev, int flags, uchar **packetp) rx_bytes = rx_desc->data_size -6 ;/* give packet to stack - skip on first 2 bytes */ - data = (u8 *)rx_desc->buf_cookie +2 ; + data = (u8 *)(uintptr_t )rx_desc->buf_cookie +2 ;/* * No cache invalidation needed here, since the rx_buffer's are * located in a uncached memory region
@@ -1594,13 +1594,13 @@ static int mvneta_probe(struct udevice *dev)if (!buffer_loc.tx_descs) {/* Align buffer area for descs and rx_buffers to 1MiB */ bd_space =memalign (1 <<MMU_SECTION_SHIFT ,BD_SPACE ); -mmu_set_region_dcache_behaviour ((u32 )bd_space,BD_SPACE , +mmu_set_region_dcache_behaviour ((phys_addr_t )bd_space,BD_SPACE ,DCACHE_OFF ); buffer_loc.tx_descs = (struct mvneta_tx_desc *)bd_space; buffer_loc.rx_descs = (struct mvneta_rx_desc *) - ((u32 )bd_space + + ((phys_addr_t )bd_space +MVNETA_MAX_TXD *sizeof (struct mvneta_tx_desc )); - buffer_loc.rx_buffers = (u32) + buffer_loc.rx_buffers = (phys_addr_t) (bd_space +MVNETA_MAX_TXD *sizeof (struct mvneta_tx_desc ) +MVNETA_MAX_RXD *sizeof (struct mvneta_rx_desc ));
Signature · 1 line
2.9.3
PATCH 3/15 net: mvneta: Make driver 64bit safe
Quoted 13 lines · Stefan Roese
The mvneta driver is also used on the ARMv8 64bit Armada 3700 SoC. This patch fixes the compilation warnings seen on this 64bit platform.
Signed-off-by Stefan Roese <[email protected]>Cc Nadav Haklai <[email protected]>Cc Kostya Porotchkin <[email protected]>Cc Wilson Ding <[email protected]>Cc Victor Gu <[email protected]>Cc Hua Jing <[email protected]>Cc Terry Zhou <[email protected]>Cc Hanna Hawa <[email protected]>Cc Haim Boot <[email protected]>Cc Joe Hershberger <[email protected]>
Acked-by Joe Hershberger <[email protected]>
PATCH 3/15 net: mvneta: Make driver 64bit safe
Quoted 15 lines · Joe Hershberger
Quoted 13 lines · Stefan Roese
The mvneta driver is also used on the ARMv8 64bit Armada 3700 SoC. This patch fixes the compilation warnings seen on this 64bit platform.
Signed-off-by Stefan Roese <[email protected]>Cc Nadav Haklai <[email protected]>Cc Kostya Porotchkin <[email protected]>Cc Wilson Ding <[email protected]>Cc Victor Gu <[email protected]>Cc Hua Jing <[email protected]>Cc Terry Zhou <[email protected]>Cc Hanna Hawa <[email protected]>Cc Haim Boot <[email protected]>Cc Joe Hershberger <[email protected]>
Quoted 1 line
Acked-by Joe Hershberger <[email protected]>
Thanks Joe. Are you okay with me including this patch, and the other mvneta one (once v2 is accepted / acked) via my Marvell repository?
Thanks,
Stefan
PATCH 3/15 net: mvneta: Make driver 64bit safe
Hi Stefan,
Quoted 19 lines · Stefan Roese
Quoted 18 lines · Joe Hershberger
Quoted 14 lines · Stefan Roese
The mvneta driver is also used on the ARMv8 64bit Armada 3700 SoC. This patch fixes the compilation warnings seen on this 64bit platform.
Signed-off-by Stefan Roese <[email protected]>Cc Nadav Haklai <[email protected]>Cc Kostya Porotchkin <[email protected]>Cc Wilson Ding <[email protected]>Cc Victor Gu <[email protected]>Cc Hua Jing <[email protected]>Cc Terry Zhou <[email protected]>Cc Hanna Hawa <[email protected]>Cc Haim Boot <[email protected]>Cc Joe Hershberger <[email protected]>
Quoted 6 lines
Quoted 1 line
Acked-by Joe Hershberger <[email protected]>Thanks Joe. Are you okay with me including this patch, and the other mvneta one (once v2 is accepted / acked) via my Marvell repository?
Yes, for sure.
Cheers,
-Joe
PATCH 4/15 net: mvneta: Add support for Armada 3700 SoC
In reply to Stefan RoeseThis patch adds support for the Armada 3700 SoC to the Marvell mvneta network driver.
Not like A380, in Armada3700, there are two layers of decode windows for GBE:
First layer is: GbE Address window that resides inside the GBE unit, Second layer is: Fabric address window which is located in the NIC400
(South Fabric).
To simplify the address decode configuration for Armada3700, we bypass the first layer of GBE decode window by setting the first window to 4GB.
Signed-off-by Stefan Roese <[email protected]>
Cc Nadav Haklai <[email protected]>
Cc Kostya Porotchkin <[email protected]>
Cc Wilson Ding <[email protected]>
Cc Victor Gu <[email protected]>
Cc Hua Jing <[email protected]>
Cc Terry Zhou <[email protected]>
Cc Hanna Hawa <[email protected]>
Cc Haim Boot <[email protected]>
Cc Joe Hershberger <[email protected]>
--- drivers/net/mvneta.c | 39 ++++++++++++++++++++++++++++++++++++++- 1 file changed, 38 insertions(+), 1 deletion(-)
drivers/net/mvneta.c +38 -1
@@ -91,7 +91,10 @@ DECLARE_GLOBAL_DATA_PTR;#define MVNETA_WIN_BASE (w) (0x2200 + ((w) << 3))#define MVNETA_WIN_SIZE (w) (0x2204 + ((w) << 3))#define MVNETA_WIN_REMAP (w) (0x2280 + ((w) << 2)) +#define MVNETA_WIN_SIZE_MASK (0xffff0000)#define MVNETA_BASE_ADDR_ENABLE 0x2290 +#define MVNETA_PORT_ACCESS_PROTECT 0x2294 +#define MVNETA_PORT_ACCESS_PROTECT_WIN0_RW 0x3#define MVNETA_PORT_CONFIG 0x2400#define MVNETA_UNI_PROMISC_MODE BIT(0)#define MVNETA_DEF_RXQ (q) ((q) << 1)
@@ -1241,6 +1244,36 @@ static int mvneta_init2(struct mvneta_port *pp) }/* platform glue : initialize decoding windows */ + +/* +* Not like A380, in Armada3700, there are two layers of decode windows for GBE: +* First layer is: GbE Address window that resides inside the GBE unit, +* Second layer is: Fabric address window which is located in the NIC400 +* (South Fabric). +* To simplify the address decode configuration for Armada3700, we bypass the +* first layer of GBE decode window by setting the first window to 4GB. +*/ +static void mvneta_bypass_mbus_windows (struct mvneta_port *pp) +{ +u32 tmp_value; + +/* +* Set window size to 4GB, to bypass GBE address decode, leave the +* work to MBUS decode window +*/ +mvreg_write (pp,MVNETA_WIN_SIZE (0 ),MVNETA_WIN_SIZE_MASK ); + +/* Enable GBE address decode window 0 by set bit 0 to 0 */ + tmp_value =mvreg_read (pp,MVNETA_BASE_ADDR_ENABLE ); + tmp_value = tmp_value & ~(1 ); +mvreg_write (pp,MVNETA_BASE_ADDR_ENABLE , tmp_value); + +/* Set GBE address decode window 0 to full Access (read or write) */ + tmp_value =mvreg_read (pp,MVNETA_PORT_ACCESS_PROTECT ); + tmp_value = tmp_value |MVNETA_PORT_ACCESS_PROTECT_WIN0_RW ; +mvreg_write (pp,MVNETA_PORT_ACCESS_PROTECT , tmp_value); +} +static void mvneta_conf_mbus_windows (struct mvneta_port *pp) {const struct mbus_dram_target_info *dram;
@@ -1609,7 +1642,10 @@ static int mvneta_probe(struct udevice *dev) pp->base = (void __iomem *)pdata->iobase;/* Configure MBUS address windows */ -mvneta_conf_mbus_windows (pp); +if (of_device_is_compatible (dev,"marvell,armada-3700-neta" )) +mvneta_bypass_mbus_windows (pp); +else +mvneta_conf_mbus_windows (pp);/* PHY interface is already decoded in mvneta_ofdata_to_platdata() */ pp->phy_interface = pdata->phy_interface;
@@ -1672,6 +1708,7 @@ static int mvneta_ofdata_to_platdata(struct udevice *dev)static const struct udevice_id mvneta_ids[] = { { .compatible ="marvell,armada-370-neta" }, { .compatible ="marvell,armada-xp-neta" }, + { .compatible ="marvell,armada-3700-neta" }, { } };
Signature · 1 line
2.9.3
PATCH 4/15 net: mvneta: Add support for Armada 3700 SoC
Quoted 55 lines · Stefan Roese
This patch adds support for the Armada 3700 SoC to the Marvell mvneta network driver.
Not like A380, in Armada3700, there are two layers of decode windows for GBE:
First layer is: GbE Address window that resides inside the GBE unit, Second layer is: Fabric address window which is located in the NIC400(South Fabric).
To simplify the address decode configuration for Armada3700, we bypass the first layer of GBE decode window by setting the first window to 4GB.Signed-off-by Stefan Roese <[email protected]>Cc Nadav Haklai <[email protected]>Cc Kostya Porotchkin <[email protected]>Cc Wilson Ding <[email protected]>Cc Victor Gu <[email protected]>Cc Hua Jing <[email protected]>Cc Terry Zhou <[email protected]>Cc Hanna Hawa <[email protected]>Cc Haim Boot <[email protected]>Cc Joe Hershberger <[email protected]>--- drivers/net/mvneta.c | 39 ++++++++++++++++++++++++++++++++++++++- 1 file changed, 38 insertions(+), 1 deletion(-)drivers/net/mvneta.c +15
-0@@ -91,7 +91,10 @@ DECLARE_GLOBAL_DATA_PTR;#define MVNETA_WIN_BASE (w) (0x2200 + ((w) << 3))#define MVNETA_WIN_SIZE (w) (0x2204 + ((w) << 3))#define MVNETA_WIN_REMAP (w) (0x2280 + ((w) << 2)) +#define MVNETA_WIN_SIZE_MASK (0xffff0000)#define MVNETA_BASE_ADDR_ENABLE 0x2290 +#define MVNETA_PORT_ACCESS_PROTECT 0x2294 +#define MVNETA_PORT_ACCESS_PROTECT_WIN0_RW 0x3#define MVNETA_PORT_CONFIG 0x2400#define MVNETA_UNI_PROMISC_MODE BIT(0)#define MVNETA_DEF_RXQ (q) ((q) << 1)@@ -1241,6 +1244,36 @@ static int mvneta_init2(struct mvneta_port *pp) }/* platform glue : initialize decoding windows */ + +/* +* Not like A380, in Armada3700, there are two layers of decode windows for GBE: +* First layer is: GbE Address window that resides inside the GBE unit, +* Second layer is: Fabric address window which is located in the NIC400 +* (South Fabric). +* To simplify the address decode configuration for Armada3700, we bypass the +* first layer of GBE decode window by setting the first window to 4GB. +*/ +static void mvneta_bypass_mbus_windows (struct mvneta_port *pp) +{ +u32 tmp_value;
drivers/net/mvneta.c static int mvneta_init2(struct mvneta_port *pp) · line 1268
Quoted 10 lines
drivers/net/mvneta.c +10
-0+ +/* +* Set window size to 4GB, to bypass GBE address decode, leave the +* work to MBUS decode window +*/ +mvreg_write (pp,MVNETA_WIN_SIZE (0 ),MVNETA_WIN_SIZE_MASK ); + +/* Enable GBE address decode window 0 by set bit 0 to 0 */ + tmp_value =mvreg_read (pp,MVNETA_BASE_ADDR_ENABLE ); + tmp_value = tmp_value & ~(1 );
It would be good to have a defined name for this bitfield above like the others.
Also, you could use:
#define MVNETA_BASE_ADDR_ENABLE_BIT 0 clear_bit(MVNETA_BASE_ADDR_ENABLE_BIT, pp->base + MVNETA_BASE_ADDR_ENABLE);
drivers/net/mvneta.c static int mvneta_init2(struct mvneta_port *pp) · line 1274
Quoted 6 lines
drivers/net/mvneta.c +6
-0+mvreg_write (pp,MVNETA_BASE_ADDR_ENABLE , tmp_value); + +/* Set GBE address decode window 0 to full Access (read or write) */ + tmp_value =mvreg_read (pp,MVNETA_PORT_ACCESS_PROTECT ); + tmp_value = tmp_value |MVNETA_PORT_ACCESS_PROTECT_WIN0_RW ; +mvreg_write (pp,MVNETA_PORT_ACCESS_PROTECT , tmp_value);
Or:
setbits_le32(pp->base + MVNETA_PORT_ACCESS_PROTECT, MVNETA_PORT_ACCESS_PROTECT_WIN0_RW)
Quoted 32 lines
drivers/net/mvneta.c +7
-2+} +static void mvneta_conf_mbus_windows (struct mvneta_port *pp) {const struct mbus_dram_target_info *dram;@@ -1609,7 +1642,10 @@ static int mvneta_probe(struct udevice *dev) pp->base = (void __iomem *)pdata->iobase;/* Configure MBUS address windows */ -mvneta_conf_mbus_windows (pp); +if (of_device_is_compatible (dev,"marvell,armada-3700-neta" )) +mvneta_bypass_mbus_windows (pp); +else +mvneta_conf_mbus_windows (pp);/* PHY interface is already decoded in mvneta_ofdata_to_platdata() */ pp->phy_interface = pdata->phy_interface;@@ -1672,6 +1708,7 @@ static int mvneta_ofdata_to_platdata(struct udevice *dev)static const struct udevice_id mvneta_ids[] = { { .compatible ="marvell,armada-370-neta" }, { .compatible ="marvell,armada-xp-neta" }, + { .compatible ="marvell,armada-3700-neta" }, { } }; --2.9.3
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PATCH v2 4/15 net: mvneta: Add support for Armada 3700 SoC
In reply to Stefan RoeseThis patch adds support for the Armada 3700 SoC to the Marvell mvneta network driver.
Not like A380, in Armada3700, there are two layers of decode windows for GBE:
First layer is: GbE Address window that resides inside the GBE unit, Second layer is: Fabric address window which is located in the NIC400
(South Fabric).
To simplify the address decode configuration for Armada3700, we bypass the first layer of GBE decode window by setting the first window to 4GB.
Signed-off-by Stefan Roese <[email protected]>
Cc Nadav Haklai <[email protected]>
Cc Kostya Porotchkin <[email protected]>
Cc Wilson Ding <[email protected]>
Cc Victor Gu <[email protected]>
Cc Hua Jing <[email protected]>
Cc Terry Zhou <[email protected]>
Cc Hanna Hawa <[email protected]>
Cc Haim Boot <[email protected]>
Cc Joe Hershberger <[email protected]>
---
v2:
- Use clr/setbits_le32 as suggested by Joe
drivers/net/mvneta.c | 36 +++++++++++++++++++++++++++++++++++- 1 file changed, 35 insertions(+), 1 deletion(-)
drivers/net/mvneta.c +35 -1
@@ -91,7 +91,11 @@ DECLARE_GLOBAL_DATA_PTR;#define MVNETA_WIN_BASE (w) (0x2200 + ((w) << 3))#define MVNETA_WIN_SIZE (w) (0x2204 + ((w) << 3))#define MVNETA_WIN_REMAP (w) (0x2280 + ((w) << 2)) +#define MVNETA_WIN_SIZE_MASK (0xffff0000)#define MVNETA_BASE_ADDR_ENABLE 0x2290 +#define MVNETA_BASE_ADDR_ENABLE_BIT 0x1 +#define MVNETA_PORT_ACCESS_PROTECT 0x2294 +#define MVNETA_PORT_ACCESS_PROTECT_WIN0_RW 0x3#define MVNETA_PORT_CONFIG 0x2400#define MVNETA_UNI_PROMISC_MODE BIT(0)#define MVNETA_DEF_RXQ (q) ((q) << 1)
@@ -1241,6 +1245,32 @@ static int mvneta_init2(struct mvneta_port *pp) }/* platform glue : initialize decoding windows */ + +/* +* Not like A380, in Armada3700, there are two layers of decode windows for GBE: +* First layer is: GbE Address window that resides inside the GBE unit, +* Second layer is: Fabric address window which is located in the NIC400 +* (South Fabric). +* To simplify the address decode configuration for Armada3700, we bypass the +* first layer of GBE decode window by setting the first window to 4GB. +*/ +static void mvneta_bypass_mbus_windows (struct mvneta_port *pp) +{ +/* +* Set window size to 4GB, to bypass GBE address decode, leave the +* work to MBUS decode window +*/ +mvreg_write (pp,MVNETA_WIN_SIZE (0 ),MVNETA_WIN_SIZE_MASK ); + +/* Enable GBE address decode window 0 by set bit 0 to 0 */ +clrbits_le32 (pp->base +MVNETA_BASE_ADDR_ENABLE , +MVNETA_BASE_ADDR_ENABLE_BIT ); + +/* Set GBE address decode window 0 to full Access (read or write) */ +setbits_le32 (pp->base +MVNETA_PORT_ACCESS_PROTECT , +MVNETA_PORT_ACCESS_PROTECT_WIN0_RW ); +} +static void mvneta_conf_mbus_windows (struct mvneta_port *pp) {const struct mbus_dram_target_info *dram;
@@ -1609,7 +1639,10 @@ static int mvneta_probe(struct udevice *dev) pp->base = (void __iomem *)pdata->iobase;/* Configure MBUS address windows */ -mvneta_conf_mbus_windows (pp); +if (of_device_is_compatible (dev,"marvell,armada-3700-neta" )) +mvneta_bypass_mbus_windows (pp); +else +mvneta_conf_mbus_windows (pp);/* PHY interface is already decoded in mvneta_ofdata_to_platdata() */ pp->phy_interface = pdata->phy_interface;
@@ -1672,6 +1705,7 @@ static int mvneta_ofdata_to_platdata(struct udevice *dev)static const struct udevice_id mvneta_ids[] = { { .compatible ="marvell,armada-370-neta" }, { .compatible ="marvell,armada-xp-neta" }, + { .compatible ="marvell,armada-3700-neta" }, { } };
Signature · 1 line
2.9.3
PATCH v2 4/15 net: mvneta: Add support for Armada 3700 SoC
Quoted 10 lines · Stefan Roese
This patch adds support for the Armada 3700 SoC to the Marvell mvneta network driver.
Not like A380, in Armada3700, there are two layers of decode windows for GBE:
First layer is: GbE Address window that resides inside the GBE unit, Second layer is: Fabric address window which is located in the NIC400(South Fabric).
To simplify the address decode configuration for Armada3700, we bypass the first layer of GBE decode window by setting the first window to 4GB.
Quoted 10 lines
Signed-off-by Stefan Roese <[email protected]>Cc Nadav Haklai <[email protected]>Cc Kostya Porotchkin <[email protected]>Cc Wilson Ding <[email protected]>Cc Victor Gu <[email protected]>Cc Hua Jing <[email protected]>Cc Terry Zhou <[email protected]>Cc Hanna Hawa <[email protected]>Cc Haim Boot <[email protected]>Cc Joe Hershberger <[email protected]>
Acked-by Joe Hershberger <[email protected]>
PATCH 5/15 usb: xhci: Add Marvell MVEBU xHCI support
In reply to Stefan RoeseThis patch adds DM based support for the xHCI USB 3.0 controller integrated in the Armada 3700 SoC. It may be extended to be used by other MVEBU SoCs as well.
Signed-off-by Stefan Roese <[email protected]>
Cc Nadav Haklai <[email protected]>
Cc Kostya Porotchkin <[email protected]>
Cc Wilson Ding <[email protected]>
Cc Victor Gu <[email protected]>
Cc Hua Jing <[email protected]>
Cc Terry Zhou <[email protected]>
Cc Hanna Hawa <[email protected]>
Cc Haim Boot <[email protected]>
Cc Marek Vasut <[email protected]>
--- drivers/usb/host/Kconfig | 9 ++++ drivers/usb/host/Makefile | 1 + drivers/usb/host/xhci-mvebu.c | 96 +++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 106 insertions(+) create mode 100644 drivers/usb/host/xhci-mvebu.c
drivers/usb/host/Kconfig +9 -0
@@ -28,6 +28,15 @@ config USB_XHCI_DWC3 Say Y or if your system has a Dual Role SuperSpeed USB controller based on the DesignWare USB3 IP Core. +config USB_XHCI_MVEBU + bool "MVEBU USB 3.0 support" + default y + depends on ARCH_MVEBU + help + Choose this option to add support for USB 3.0 driver on mvebu + SoCs, which includes Armada8K, Armada3700 and other Armada + family SoCs. + endif # USB_XHCI_HCD config USB_EHCI_HCD
drivers/usb/host/Makefile +1 -0
@@ -60,6 +60,7 @@ obj-$(CONFIG_USB_XHCI_ZYNQMP) += xhci-zynqmp.o obj-$(CONFIG_USB_XHCI_KEYSTONE) += xhci-keystone.o obj-$(CONFIG_USB_XHCI_EXYNOS) += xhci-exynos5.o obj-$(CONFIG_USB_XHCI_FSL) += xhci-fsl.o +obj-$(CONFIG_USB_XHCI_MVEBU) += xhci-mvebu.o obj-$(CONFIG_USB_XHCI_OMAP) += xhci-omap.o obj-$(CONFIG_USB_XHCI_PCI) += xhci-pci.o obj-$(CONFIG_USB_XHCI_UNIPHIER) += xhci-uniphier.o
drivers/usb/host/xhci-mvebu.c new file +96 -0
96 lines not on this page · raw message
Signature · 1 line
2.9.3
PATCH 5/15 usb: xhci: Add Marvell MVEBU xHCI support
Quoted 14 lines · Stefan Roese
This patch adds DM based support for the xHCI USB 3.0 controller integrated in the Armada 3700 SoC. It may be extended to be used by other MVEBU SoCs as well.
Signed-off-by Stefan Roese <[email protected]>Cc Nadav Haklai <[email protected]>Cc Kostya Porotchkin <[email protected]>Cc Wilson Ding <[email protected]>Cc Victor Gu <[email protected]>Cc Hua Jing <[email protected]>Cc Terry Zhou <[email protected]>Cc Hanna Hawa <[email protected]>Cc Haim Boot <[email protected]>Cc Marek Vasut <[email protected]>
Quoted 1 line
---
Acked-by Marek Vasut <[email protected]>
Signature · 2 lines
Best regards, Marek Vasut
PATCH 6/15 usb: ehci: ehci-marvell.c: Add Armada 3700 support (ARMv8)
In reply to Stefan RoeseThis patch adds DM based support for the Armada 3700 EHCI controller. The address windows don't need to get configured in this case. The difference here is detected via DT compatible property at runtime.
With this support and the DM xHCI driver, both XHCI and eHCI can be used simultaniously on the MVEBU boards now.
Signed-off-by Stefan Roese <[email protected]>
Cc Nadav Haklai <[email protected]>
Cc Kostya Porotchkin <[email protected]>
Cc Wilson Ding <[email protected]>
Cc Victor Gu <[email protected]>
Cc Hua Jing <[email protected]>
Cc Terry Zhou <[email protected]>
Cc Hanna Hawa <[email protected]>
Cc Haim Boot <[email protected]>
Cc Marek Vasut <[email protected]>
--- drivers/usb/host/ehci-marvell.c | 59 ++++++++++++++++++++++++++++++++++++----- 1 file changed, 52 insertions(+), 7 deletions(-)
drivers/usb/host/ehci-marvell.c +52 -7
@@ -26,6 +26,16 @@ DECLARE_GLOBAL_DATA_PTR;#define USB_WINDOW_BASE (i) (0x324 + ((i) << 4))#define USB_TARGET_DRAM 0x0 +#define USB2_SBUSCFG_OFF 0x90 + +#define USB_SBUSCFG_BAWR_OFF 0x6 +#define USB_SBUSCFG_BARD_OFF 0x3 +#define USB_SBUSCFG_AHBBRST_OFF 0x0 + +#define USB_SBUSCFG_BAWR_ALIGN_64B 0x4 +#define USB_SBUSCFG_BARD_ALIGN_64B 0x4 +#define USB_SBUSCFG_AHBBRST_INCR16 0x7 +/* * USB 2.0 Bridge Address Decoding registers setup */
@@ -41,7 +51,7 @@ struct ehci_mvebu_priv {* to the common mvebu archticture including the mbus setup, this * will be the only function needed to configure the access windows */ -static void usb_brg_adrdec_setup (u32 base) +static void usb_brg_adrdec_setup (void *base) {const struct mbus_dram_target_info *dram;int i;
@@ -66,6 +76,29 @@ static void usb_brg_adrdec_setup(u32 base) } } +static void marvell_ehci_powerup_fixup (struct ehci_ctrl *ctrl, +uint32_t *status_reg,uint32_t *reg) +{ +struct ehci_mvebu_priv *priv = ctrl->priv; + +/* +* Set default value for reg SBUSCFG, which is Control for the AMBA +* system bus interface: +* BAWR = BARD = 4 : Align rd/wr bursts packets larger than 64 bytes +* AHBBRST = 7 : Align AHB burst for packets larger than 64 bytes +*/ +writel ((USB_SBUSCFG_BAWR_ALIGN_64B <<USB_SBUSCFG_BAWR_OFF ) | + (USB_SBUSCFG_BARD_ALIGN_64B <<USB_SBUSCFG_BARD_OFF ) | + (USB_SBUSCFG_AHBBRST_INCR16 <<USB_SBUSCFG_AHBBRST_OFF ), + priv->hcd_base +USB2_SBUSCFG_OFF ); + +mdelay (50 ); +} + +static struct ehci_ops marvell_ehci_ops = { + .powerup_fixup =NULL , +}; +static int ehci_mvebu_probe (struct udevice *dev) {struct ehci_mvebu_priv *priv =dev_get_priv (dev);
@@ -81,17 +114,28 @@ static int ehci_mvebu_probe(struct udevice *dev)return -ENXIO ; } -usb_brg_adrdec_setup (priv->hcd_base); +/* +* For SoCs without hlock like Armada3700 we need to program the sbuscfg +* reg to guarantee AHB master's burst will not overrun or underrun +* the FIFO. Otherwise all USB2 write option will fail. +* Also, the address decoder doesn't need to get setup with this +* SoC, so don't call usb_brg_adrdec_setup(). +*/ +if (of_device_is_compatible (dev,"marvell,armada3700-ehci" )) + marvell_ehci_ops.powerup_fixup = marvell_ehci_powerup_fixup; +else +usb_brg_adrdec_setup ((void *)priv->hcd_base); hccr = (struct ehci_hccr *)(priv->hcd_base +0x100 ); hcor = (struct ehci_hcor *) - ((u32 )hccr +HC_LENGTH (ehci_readl (&hccr->cr_capbase))); + ((uintptr_t )hccr +HC_LENGTH (ehci_readl (&hccr->cr_capbase))); -debug ("ehci-marvell: init hccr %x and hcor %x hc_length %d\n" , - (u32 )hccr, (u32 )hcor, - (u32 )HC_LENGTH (ehci_readl (&hccr->cr_capbase))); +debug ("ehci-marvell: init hccr %lx and hcor %lx hc_length %ld\n" , + (uintptr_t )hccr, (uintptr_t )hcor, + (uintptr_t )HC_LENGTH (ehci_readl (&hccr->cr_capbase))); -return ehci_register (dev, hccr, hcor,NULL ,0 ,USB_INIT_HOST ); +return ehci_register (dev, hccr, hcor, &marvell_ehci_ops,0 , +USB_INIT_HOST ); }static int ehci_mvebu_remove (struct udevice *dev)
@@ -107,6 +151,7 @@ static int ehci_mvebu_remove(struct udevice *dev)static const struct udevice_id ehci_usb_ids[] = { { .compatible ="marvell,orion-ehci" , }, + { .compatible ="marvell,armada3700-ehci" , }, { } };
Signature · 1 line
2.9.3
PATCH 6/15 usb: ehci: ehci-marvell.c: Add Armada 3700 support (ARMv8)
Quoted 17 lines · Stefan Roese
This patch adds DM based support for the Armada 3700 EHCI controller. The address windows don't need to get configured in this case. The difference here is detected via DT compatible property at runtime.
With this support and the DM xHCI driver, both XHCI and eHCI can be used simultaniously on the MVEBU boards now.
Signed-off-by Stefan Roese <[email protected]>Cc Nadav Haklai <[email protected]>Cc Kostya Porotchkin <[email protected]>Cc Wilson Ding <[email protected]>Cc Victor Gu <[email protected]>Cc Hua Jing <[email protected]>Cc Terry Zhou <[email protected]>Cc Hanna Hawa <[email protected]>Cc Haim Boot <[email protected]>Cc Marek Vasut <[email protected]>
Quoted 1 line
---
Acked-by Marek Vasut <[email protected]>
Feel free to pick this all up via the marvell tree if that helps.
Signature · 2 lines
Best regards, Marek Vasut
PATCH 6/15 usb: ehci: ehci-marvell.c: Add Armada 3700 support (ARMv8)
Hi Marek,
Quoted 20 lines · Marek Vasut
Quoted 17 lines · Stefan Roese
This patch adds DM based support for the Armada 3700 EHCI controller. The address windows don't need to get configured in this case. The difference here is detected via DT compatible property at runtime.
With this support and the DM xHCI driver, both XHCI and eHCI can be used simultaniously on the MVEBU boards now.
Signed-off-by Stefan Roese <[email protected]>Cc Nadav Haklai <[email protected]>Cc Kostya Porotchkin <[email protected]>Cc Wilson Ding <[email protected]>Cc Victor Gu <[email protected]>Cc Hua Jing <[email protected]>Cc Terry Zhou <[email protected]>Cc Hanna Hawa <[email protected]>Cc Haim Boot <[email protected]>Cc Marek Vasut <[email protected]>Quoted 1 line
---
Quoted 3 lines
Acked-by Marek Vasut <[email protected]>Feel free to pick this all up via the marvell tree if that helps.
Thanks, yes that makes things a bit easier. Will do once everything is clear.
Thanks,
Stefan
PATCH 7/15 drivers/phy: Add Marvell SerDes / PHY drivers used on Armada 3k
In reply to Stefan RoeseThis version is based on the Marvell U-Boot version with this patch applied as latest patch:
Git ID 7f408573: "fix: comphy: cp110: add comphy initialization for usb device mode" from 2016-07-05.
Signed-off-by Stefan Roese <[email protected]>
Cc Nadav Haklai <[email protected]>
Cc Kostya Porotchkin <[email protected]>
Cc Wilson Ding <[email protected]>
Cc Victor Gu <[email protected]>
Cc Hua Jing <[email protected]>
Cc Terry Zhou <[email protected]>
Cc Hanna Hawa <[email protected]>
Cc Haim Boot <[email protected]>
--- drivers/Kconfig | 2 + drivers/Makefile | 1 + drivers/phy/marvell/Kconfig | 9 + drivers/phy/marvell/Makefile | 7 + drivers/phy/marvell/comphy.h | 139 +++++ drivers/phy/marvell/comphy_a3700.c | 962 +++++++++++++++++++++++++++++++ drivers/phy/marvell/comphy_a3700.h | 275 +++++++++ drivers/phy/marvell/comphy_core.c | 197 +++++++ drivers/phy/marvell/comphy_hpipe.h | 382 ++++++++++++ drivers/phy/marvell/comphy_mux.c | 118 ++++ include/dt-bindings/comphy/comphy_data.h | 61 ++ 11 files changed, 2153 insertions(+) create mode 100644 drivers/phy/marvell/Kconfig create mode 100644 drivers/phy/marvell/Makefile create mode 100644 drivers/phy/marvell/comphy.h create mode 100644 drivers/phy/marvell/comphy_a3700.c create mode 100644 drivers/phy/marvell/comphy_a3700.h create mode 100644 drivers/phy/marvell/comphy_core.c create mode 100644 drivers/phy/marvell/comphy_hpipe.h create mode 100644 drivers/phy/marvell/comphy_mux.c create mode 100644 include/dt-bindings/comphy/comphy_data.h
drivers/Kconfig +2 -0
@@ -46,6 +46,8 @@ source "drivers/pci/Kconfig" source "drivers/pcmcia/Kconfig" +source "drivers/phy/marvell/Kconfig" + source "drivers/pinctrl/Kconfig" source "drivers/power/Kconfig"
drivers/Makefile +1 -0
@@ -56,6 +56,7 @@ obj-y += misc/ obj-y += pcmcia/ obj-y += dfu/ obj-$(CONFIG_X86) += pch/ +obj-y += phy/marvell/ obj-y += rtc/ obj-y += sound/ obj-y += spmi/
drivers/phy/marvell/Kconfig new file +9 -0
@@ -0,0 +1,9 @@ +config MVEBU_COMPHY_SUPPORT + bool "ComPhy SerDes driver" + default n + help + Choose this option to add support + for Comphy driver. + This driver passes over the lanes + and initialize the lane depends on the + type and speed.
drivers/phy/marvell/Makefile new file +7 -0
@@ -0,0 +1,7 @@ +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-$(CONFIG_MVEBU_COMPHY_SUPPORT) += comphy_core.o +obj-$(CONFIG_MVEBU_COMPHY_SUPPORT) += comphy_mux.o +obj-$(CONFIG_ARMADA_3700) += comphy_a3700.o
drivers/phy/marvell/comphy.h new file +139 -0
139 lines not on this page · raw message
drivers/phy/marvell/comphy_a3700.c new file +962 -0
962 lines not on this page · raw message
drivers/phy/marvell/comphy_a3700.h new file +275 -0
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drivers/phy/marvell/comphy_core.c new file +197 -0
197 lines not on this page · raw message
drivers/phy/marvell/comphy_hpipe.h new file +382 -0
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drivers/phy/marvell/comphy_mux.c new file +118 -0
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include/dt-bindings/comphy/comphy_data.h new file +61 -0
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Signature · 1 line
2.9.3
PATCH 8/15 arm64: mvebu: Armada 3700: Add Armada 37xx dts files
In reply to Stefan RoeseThis patch integrates the Armada 3700 dts files from the latest submission on the linux-arm-kernel mailing list.
Signed-off-by Stefan Roese <[email protected]>
Cc Nadav Haklai <[email protected]>
Cc Kostya Porotchkin <[email protected]>
Cc Wilson Ding <[email protected]>
Cc Victor Gu <[email protected]>
Cc Hua Jing <[email protected]>
Cc Terry Zhou <[email protected]>
Cc Hanna Hawa <[email protected]>
Cc Haim Boot <[email protected]>
--- arch/arm/dts/Makefile | 1 + arch/arm/dts/armada-371x.dtsi | 53 +++++++++++++++ arch/arm/dts/armada-3720-db.dts | 78 +++++++++++++++++++++ arch/arm/dts/armada-372x.dtsi | 62 +++++++++++++++++ arch/arm/dts/armada-37xx.dtsi | 145 ++++++++++++++++++++++++++++++++++++++++ 5 files changed, 339 insertions(+) create mode 100644 arch/arm/dts/armada-371x.dtsi create mode 100644 arch/arm/dts/armada-3720-db.dts create mode 100644 arch/arm/dts/armada-372x.dtsi create mode 100644 arch/arm/dts/armada-37xx.dtsi
arch/arm/dts/Makefile +1 -0
@@ -67,6 +67,7 @@ dtb-$(CONFIG_TEGRA) += tegra20-harmony.dtb \ tegra210-p2571.dtb dtb-$(CONFIG_ARCH_MVEBU) += \ + armada-3720-db.dtb \ armada-375-db.dtb \ armada-388-clearfog.dtb \ armada-388-gp.dtb \
arch/arm/dts/armada-371x.dtsi new file +53 -0
53 lines not on this page · raw message
arch/arm/dts/armada-3720-db.dts new file +78 -0
78 lines not on this page · raw message
arch/arm/dts/armada-372x.dtsi new file +62 -0
62 lines not on this page · raw message
arch/arm/dts/armada-37xx.dtsi new file +145 -0
145 lines not on this page · raw message
Signature · 1 line
2.9.3
PATCH 9/15 arm64: mvebu: Armada 3700: Add SPI device tree nodes
In reply to Stefan RoeseThis patch adds the SPI device tree nodes that are still missing to the Armada 3700 dts files.
Signed-off-by Stefan Roese <[email protected]>
Cc Nadav Haklai <[email protected]>
Cc Kostya Porotchkin <[email protected]>
Cc Wilson Ding <[email protected]>
Cc Victor Gu <[email protected]>
Cc Hua Jing <[email protected]>
Cc Terry Zhou <[email protected]>
Cc Hanna Hawa <[email protected]>
Cc Haim Boot <[email protected]>
--- arch/arm/dts/armada-3720-db.dts | 17 +++++++++++++++++ arch/arm/dts/armada-37xx.dtsi | 11 +++++++++++ 2 files changed, 28 insertions(+)
arch/arm/dts/armada-3720-db.dts +17 -0
@@ -56,6 +56,10 @@ stdout-path = "serial0:115200n8"; }; + aliases { + spi0 = &spi0; + }; + memory { device_type = "memory"; reg = <0x00000000 0x00000000 0x00000000 0x20000000>;
@@ -67,6 +71,19 @@ status = "okay"; }; +&spi0 { + status = "okay"; + + spi-flash at 0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "st,m25p128", "jedec,spi-nor"; + reg = <0>; /* Chip select 0 */ + spi-max-frequency = <50000000>; + m25p,fast-read; + }; +}; + /* Exported on the micro USB connector CON32 through an FTDI */ &uart0 { status = "okay";
arch/arm/dts/armada-37xx.dtsi +11 -0
@@ -140,6 +140,17 @@ reg = <0x1d00000 0x10000>, /* GICD */ <0x1d40000 0x40000>; /* GICR */ }; + + spi0: spi at 10600 { + compatible = "marvell,armada-3700-spi"; + reg = <0x10600 0x50>; + #address-cells = <1>; + #size-cells = <0>; + #clock-cells = <0>; + clock-frequency = <160000>; + spi-max-frequency = <40000>; + status = "disabled"; + }; }; }; };
Signature · 1 line
2.9.3
PATCH 9/15 arm64: mvebu: Armada 3700: Add SPI device tree nodes
Quoted 33 lines · Stefan Roese
This patch adds the SPI device tree nodes that are still missing to the Armada 3700 dts files.
Signed-off-by Stefan Roese <[email protected]>Cc Nadav Haklai <[email protected]>Cc Kostya Porotchkin <[email protected]>Cc Wilson Ding <[email protected]>Cc Victor Gu <[email protected]>Cc Hua Jing <[email protected]>Cc Terry Zhou <[email protected]>Cc Hanna Hawa <[email protected]>Cc Haim Boot <[email protected]>--- arch/arm/dts/armada-3720-db.dts | 17 +++++++++++++++++ arch/arm/dts/armada-37xx.dtsi | 11 +++++++++++ 2 files changed, 28 insertions(+)arch/arm/dts/armada-3720-db.dts +4
-0@@ -56,6 +56,10 @@ stdout-path = "serial0:115200n8"; }; + aliases { + spi0 = &spi0; + }; + memory { device_type = "memory"; reg = <0x00000000 0x00000000 0x00000000 0x20000000>;
arch/arm/dts/armada-3720-db.dts line 80
Quoted 10 lines
arch/arm/dts/armada-3720-db.dts +7
-0@@ -67,6 +71,19 @@ status = "okay"; }; +&spi0 { + status = "okay"; + + spi-flash at 0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "st,m25p128", "jedec,spi-nor";
Use spi-flash instead of jedec,spi-nor
thanks!
Signature · 4 lines
Jagan Teki Free Software Engineer | www.openedev.com U-Boot, Linux | Upstream Maintainer Hyderabad, India.
PATCH v2 9/15 arm64: mvebu: Armada 3700: Add SPI device tree nodes
In reply to Stefan RoeseThis patch adds the SPI device tree nodes that are still missing to the Armada 3700 dts files.
Signed-off-by Stefan Roese <[email protected]>
Cc Nadav Haklai <[email protected]>
Cc Kostya Porotchkin <[email protected]>
Cc Wilson Ding <[email protected]>
Cc Victor Gu <[email protected]>
Cc Hua Jing <[email protected]>
Cc Terry Zhou <[email protected]>
Cc Hanna Hawa <[email protected]>
Cc Haim Boot <[email protected]>
---
v2:
- Use "spi-flash" instead of "jedec,spi-nor" as suggested by Jagan
arch/arm/dts/armada-3720-db.dts | 17 +++++++++++++++++ arch/arm/dts/armada-37xx.dtsi | 11 +++++++++++ 2 files changed, 28 insertions(+)
arch/arm/dts/armada-3720-db.dts +17 -0
@@ -56,6 +56,10 @@ stdout-path = "serial0:115200n8"; }; + aliases { + spi0 = &spi0; + }; + memory { device_type = "memory"; reg = <0x00000000 0x00000000 0x00000000 0x20000000>;
@@ -67,6 +71,19 @@ status = "okay"; }; +&spi0 { + status = "okay"; + + spi-flash at 0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "st,m25p128", "spi-flash"; + reg = <0>; /* Chip select 0 */ + spi-max-frequency = <50000000>; + m25p,fast-read; + }; +}; + /* Exported on the micro USB connector CON32 through an FTDI */ &uart0 { status = "okay";
arch/arm/dts/armada-37xx.dtsi +11 -0
@@ -140,6 +140,17 @@ reg = <0x1d00000 0x10000>, /* GICD */ <0x1d40000 0x40000>; /* GICR */ }; + + spi0: spi at 10600 { + compatible = "marvell,armada-3700-spi"; + reg = <0x10600 0x50>; + #address-cells = <1>; + #size-cells = <0>; + #clock-cells = <0>; + clock-frequency = <160000>; + spi-max-frequency = <40000>; + status = "disabled"; + }; }; }; };
Signature · 1 line
2.9.3
PATCH v2 9/15 arm64: mvebu: Armada 3700: Add SPI device tree nodes
Quoted 12 lines · Stefan Roese
This patch adds the SPI device tree nodes that are still missing to the Armada 3700 dts files.
Signed-off-by Stefan Roese <[email protected]>Cc Nadav Haklai <[email protected]>Cc Kostya Porotchkin <[email protected]>Cc Wilson Ding <[email protected]>Cc Victor Gu <[email protected]>Cc Hua Jing <[email protected]>Cc Terry Zhou <[email protected]>Cc Hanna Hawa <[email protected]>Cc Haim Boot <[email protected]>
Quoted 3 lines
---
v2:
- Use "spi-flash" instead of "jedec,spi-nor" as suggested by Jagan
Reviewed-by Jagan Teki <[email protected]>
thanks!
Signature · 4 lines
Jagan Teki Free Software Engineer | www.openedev.com U-Boot, Linux | Upstream Maintainer Hyderabad, India.
PATCH 10/15 arm64: mvebu: Armada 3700: Add ethernet device tree nodes
In reply to Stefan RoeseThis patch adds the ethernet device tree nodes that are still missing to the Armada 3700 dts files.
Signed-off-by Stefan Roese <[email protected]>
Cc Nadav Haklai <[email protected]>
Cc Kostya Porotchkin <[email protected]>
Cc Wilson Ding <[email protected]>
Cc Victor Gu <[email protected]>
Cc Hua Jing <[email protected]>
Cc Terry Zhou <[email protected]>
Cc Hanna Hawa <[email protected]>
Cc Haim Boot <[email protected]>
--- arch/arm/dts/armada-3720-db.dts | 6 ++++++ arch/arm/dts/armada-37xx.dtsi | 12 ++++++++++++ 2 files changed, 18 insertions(+)
arch/arm/dts/armada-3720-db.dts +6 -0
@@ -57,6 +57,7 @@ }; aliases { + ethernet0 = ð0; spi0 = &spi0; };
@@ -66,6 +67,11 @@ }; }; +ð0 { + status = "okay"; + phy-mode = "rgmii"; +}; + /* CON3 */ &sata { status = "okay";
arch/arm/dts/armada-37xx.dtsi +12 -0
@@ -141,6 +141,18 @@ <0x1d40000 0x40000>; /* GICR */ }; + eth0: neta at 30000 { + compatible = "marvell,armada-3700-neta"; + reg = <0x30000 0x20>; + status = "disabled"; + }; + + eth1: neta at 40000 { + compatible = "marvell,armada-3700-neta"; + reg = <0x40000 0x20>; + status = "disabled"; + }; + spi0: spi at 10600 { compatible = "marvell,armada-3700-spi"; reg = <0x10600 0x50>;
Signature · 1 line
2.9.3
PATCH 11/15 arm64: mvebu: Armada 3700: Add I2C device tree nodes
In reply to Stefan RoeseThis patch adds the I2C device tree nodes that are still missing to the Armada 3700 dts files.
Signed-off-by Stefan Roese <[email protected]>
Cc Nadav Haklai <[email protected]>
Cc Kostya Porotchkin <[email protected]>
Cc Wilson Ding <[email protected]>
Cc Victor Gu <[email protected]>
Cc Hua Jing <[email protected]>
Cc Terry Zhou <[email protected]>
Cc Hanna Hawa <[email protected]>
Cc Haim Boot <[email protected]>
--- arch/arm/dts/armada-3720-db.dts | 5 +++++ arch/arm/dts/armada-37xx.dtsi | 6 ++++++ 2 files changed, 11 insertions(+)
arch/arm/dts/armada-3720-db.dts +5 -0
@@ -58,6 +58,7 @@ aliases { ethernet0 = ð0; + i2c0 = &i2c0; spi0 = &spi0; };
@@ -72,6 +73,10 @@ phy-mode = "rgmii"; }; +&i2c0 { + status = "okay"; +}; + /* CON3 */ &sata { status = "okay";
arch/arm/dts/armada-37xx.dtsi +6 -0
@@ -153,6 +153,12 @@ status = "disabled"; }; + i2c0: i2c at 11000 { + compatible = "marvell,armada-3700-i2c"; + reg = <0x11000 0x100>; + status = "disabled"; + }; + spi0: spi at 10600 { compatible = "marvell,armada-3700-spi"; reg = <0x10600 0x50>;
Signature · 1 line
2.9.3
PATCH 12/15 arm64: mvebu: Armada 3700: Add COMPHY device tree nodes
In reply to Stefan RoeseThis patch adds the COMPHY device tree nodes that are still missing to the Armada 3700 dts files.
Signed-off-by Stefan Roese <[email protected]>
Cc Nadav Haklai <[email protected]>
Cc Kostya Porotchkin <[email protected]>
Cc Wilson Ding <[email protected]>
Cc Victor Gu <[email protected]>
Cc Hua Jing <[email protected]>
Cc Terry Zhou <[email protected]>
Cc Hanna Hawa <[email protected]>
Cc Haim Boot <[email protected]>
--- arch/arm/dts/armada-3720-db.dts | 12 ++++++++++++ arch/arm/dts/armada-37xx.dtsi | 9 +++++++++ 2 files changed, 21 insertions(+)
arch/arm/dts/armada-3720-db.dts +12 -0
@@ -68,6 +68,18 @@ }; }; +&comphy { + phy0 { + phy-type = <PHY_TYPE_PEX0>; + phy-speed = <PHY_SPEED_2_5G>; + }; + + phy1 { + phy-type = <PHY_TYPE_USB3_HOST0>; + phy-speed = <PHY_SPEED_5G>; + }; +}; + ð0 { status = "okay"; phy-mode = "rgmii";
arch/arm/dts/armada-37xx.dtsi +9 -0
@@ -45,6 +45,7 @@ */ #include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/comphy/comphy_data.h> / { model = "Marvell Armada 37xx SoC";
@@ -169,6 +170,14 @@ spi-max-frequency = <40000>; status = "disabled"; }; + + comphy: comphy at 18300 { + compatible = "marvell,mvebu-comphy", "marvell,comphy-armada-3700"; + reg = <0x18300 0x28>, + <0x1f300 0x3d000>; + mux-bitcount = <1>; + max-lanes = <2>; + }; }; }; };
Signature · 1 line
2.9.3
PATCH 13/15 arm64: mvebu: Armada 3700: Add USB device tree nodes
In reply to Stefan RoeseThis patch adds the USB device tree nodes that are still missing to the Armada 3700 dts files.
Signed-off-by Stefan Roese <[email protected]>
Cc Nadav Haklai <[email protected]>
Cc Kostya Porotchkin <[email protected]>
Cc Wilson Ding <[email protected]>
Cc Victor Gu <[email protected]>
Cc Hua Jing <[email protected]>
Cc Terry Zhou <[email protected]>
Cc Hanna Hawa <[email protected]>
Cc Haim Boot <[email protected]>
--- arch/arm/dts/armada-3720-db.dts | 5 +++++ arch/arm/dts/armada-37xx.dtsi | 6 ++++++ 2 files changed, 11 insertions(+)
arch/arm/dts/armada-3720-db.dts +5 -0
@@ -112,6 +112,11 @@ status = "okay"; }; +/* CON29 */ +&usb2 { + status = "okay"; +}; + /* CON31 */ &usb3 { status = "okay";
arch/arm/dts/armada-37xx.dtsi +6 -0
@@ -114,6 +114,12 @@ status = "disabled"; }; + usb2: usb at 5e000 { + compatible = "marvell,armada3700-ehci"; + reg = <0x5e000 0x450>; + status = "disabled"; + }; + xor at 60900 { compatible = "marvell,armada-3700-xor"; reg = <0x60900 0x100
Signature · 1 line
2.9.3
PATCH 14/15 arm64: mvebu: Add support for the Marvell Armada 3700 SoC
In reply to Stefan RoeseThe Armada 3700 integrates the following interfaces (not complete list):
- Dual Cortex-A53 ARMv8
- USB 3.0
- SATA 3.0
- PCIe 2.0
- 2 x Gigabit Ethernet 1Gbps / 2.5Gbps
- ...
This patch adds basic support for this ARMv8 based SoC into U-Boot. Future patches will integrate other device drivers and board support for the Marvell DB-88F3720 development board.
Signed-off-by Stefan Roese <[email protected]>
Cc Nadav Haklai <[email protected]>
Cc Kostya Porotchkin <[email protected]>
Cc Wilson Ding <[email protected]>
Cc Victor Gu <[email protected]>
Cc Hua Jing <[email protected]>
Cc Terry Zhou <[email protected]>
Cc Hanna Hawa <[email protected]>
Cc Haim Boot <[email protected]>
--- arch/arm/Kconfig | 6 - arch/arm/mach-mvebu/Kconfig | 25 ++++- arch/arm/mach-mvebu/Makefile | 15 ++- arch/arm/mach-mvebu/armada3700/Makefile | 8 ++ arch/arm/mach-mvebu/armada3700/cpu.c | 188 ++++++++++++++++++++++++++++++++ arch/arm/mach-mvebu/armada3700/sata.c | 45 ++++++++ arch/arm/mach-mvebu/include/mach/cpu.h | 7 ++ arch/arm/mach-mvebu/include/mach/soc.h | 2 +- 8 files changed, 284 insertions(+), 12 deletions(-) create mode 100644 arch/arm/mach-mvebu/armada3700/Makefile create mode 100644 arch/arm/mach-mvebu/armada3700/cpu.c create mode 100644 arch/arm/mach-mvebu/armada3700/sata.c
arch/arm/Kconfig +0 -6
@@ -165,8 +165,6 @@ config KIRKWOOD config ARCH_MVEBU bool "Marvell MVEBU family (Armada XP/375/38x)" - select CPU_V7 - select SUPPORT_SPL select OF_CONTROL select OF_SEPARATE select DM
@@ -174,10 +172,6 @@ config ARCH_MVEBU select DM_SERIAL select DM_SPI select DM_SPI_FLASH - select SPL_DM - select SPL_DM_SEQ_ALIAS - select SPL_OF_CONTROL - select SPL_SIMPLE_BUS config TARGET_DEVKIT3250 bool "Support devkit3250"
arch/arm/mach-mvebu/Kconfig +24 -1
@@ -1,14 +1,37 @@ if ARCH_MVEBU +config ARMADA_32BIT + bool + select CPU_V7 + select SUPPORT_SPL + select SPL_DM + select SPL_DM_SEQ_ALIAS + select SPL_OF_CONTROL + select SPL_SIMPLE_BUS + +config ARMADA_64BIT + bool + select ARM64 + +# ARMv7 SoCs... config ARMADA_375 bool + select ARMADA_32BIT config ARMADA_38X bool + select ARMADA_32BIT config ARMADA_XP bool + select ARMADA_32BIT + +# ARMv8 SoCs... +config ARMADA_3700 + bool + select ARM64 +# Armada XP/38x SoC types... config MV78230 bool select ARMADA_XP
@@ -26,7 +49,7 @@ config DB_88F6820_GP select ARMADA_38X choice - prompt "Marvell MVEBU (Armada XP/375/38x) board select" + prompt "Marvell MVEBU (Armada XP/375/38x/3700) board select" optional config TARGET_CLEARFOG
arch/arm/mach-mvebu/Makefile +11 -4
@@ -1,16 +1,22 @@ # -# Copyright (C) 2014-2015 Stefan Roese <[email protected]> +# Copyright (C) 2014-2016 Stefan Roese <[email protected]> # # SPDX-License-Identifier: GPL-2.0+ # +ifdef CONFIG_ARM64 + +obj-$(CONFIG_ARMADA_3700) += armada3700/ + +else # CONFIG_ARM64 + ifdef CONFIG_KIRKWOOD obj-y = dram.o obj-y += gpio.o obj-y += timer.o -else +else # CONFIG_KIRKWOOD obj-y = cpu.o obj-y += dram.o
@@ -18,7 +24,7 @@ ifndef CONFIG_SPL_BUILD obj-$(CONFIG_ARMADA_375) += ../../../drivers/ddr/marvell/axp/xor.o obj-$(CONFIG_ARMADA_38X) += ../../../drivers/ddr/marvell/a38x/xor.o obj-$(CONFIG_ARMADA_XP) += ../../../drivers/ddr/marvell/axp/xor.o -endif +endif # CONFIG_SPL_BUILD obj-y += gpio.o obj-y += mbus.o obj-y += timer.o
@@ -28,4 +34,5 @@ obj-$(CONFIG_SPL_BUILD) += lowlevel_spl.o obj-$(CONFIG_ARMADA_38X) += serdes/a38x/ obj-$(CONFIG_ARMADA_XP) += serdes/axp/ -endif +endif # CONFIG_KIRKWOOD +endif # CONFIG_ARM64
arch/arm/mach-mvebu/armada3700/Makefile new file +8 -0
@@ -0,0 +1,8 @@ +# +# Copyright (C) 2016 Stefan Roese <[email protected]> +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y = cpu.o +obj-y += sata.o
arch/arm/mach-mvebu/armada3700/cpu.c new file +188 -0
188 lines not on this page · raw message
arch/arm/mach-mvebu/armada3700/sata.c new file +45 -0
45 lines not on this page · raw message
arch/arm/mach-mvebu/include/mach/cpu.h +7 -0
@@ -166,5 +166,12 @@ struct mvebu_lcd_info {int mvebu_lcd_register_init (struct mvebu_lcd_info *lcd_info); +/* +* get_ref_clk +* +* return: reference clock in MHz (25 or 40) +*/ +u32 get_ref_clk (void ); +#endif /* __ASSEMBLY__ */ #endif /* _MVEBU_CPU_H */
arch/arm/mach-mvebu/include/mach/soc.h +1 -1
@@ -37,7 +37,7 @@/* SOC specific definations */ #define INTREG_BASE 0xd0000000#define INTREG_BASE_ADDR_REG (INTREG_BASE + 0x20080) -#if defined(CONFIG_SPL_BUILD ) +#if defined(CONFIG_SPL_BUILD ) || defined(CONFIG_ARMADA_3700 )/* * The SPL U-Boot version still runs with the default * address for the internal registers, configured by
Signature · 1 line
2.9.3
PATCH 15/15 arm64: mvebu: Add Armada 3700 db-88f3720 development board support
In reply to Stefan RoeseThis patch adds basic support for the Marvell Armada 3700 DB-88F3720 development board. Supported are the following interfaces:
- UART
- SPI (incl. SPI NOR)
- I2C
- Ethernet
Signed-off-by Stefan Roese <[email protected]>
Cc Nadav Haklai <[email protected]>
Cc Kostya Porotchkin <[email protected]>
Cc Wilson Ding <[email protected]>
Cc Victor Gu <[email protected]>
Cc Hua Jing <[email protected]>
Cc Terry Zhou <[email protected]>
Cc Hanna Hawa <[email protected]>
Cc Haim Boot <[email protected]>
--- arch/arm/mach-mvebu/Kconfig | 7 ++ board/Marvell/mvebu_db-88f3720/MAINTAINERS | 6 ++ board/Marvell/mvebu_db-88f3720/Makefile | 7 ++ board/Marvell/mvebu_db-88f3720/board.c | 134 ++++++++++++++++++++++++++ configs/mvebu_db-88f3720_defconfig | 49 ++++++++++ include/configs/mvebu_db-88f3720.h | 145 +++++++++++++++++++++++++++++ 6 files changed, 348 insertions(+) create mode 100644 board/Marvell/mvebu_db-88f3720/MAINTAINERS create mode 100644 board/Marvell/mvebu_db-88f3720/Makefile create mode 100644 board/Marvell/mvebu_db-88f3720/board.c create mode 100644 configs/mvebu_db-88f3720_defconfig create mode 100644 include/configs/mvebu_db-88f3720.h
arch/arm/mach-mvebu/Kconfig +7 -0
@@ -56,6 +56,10 @@ config TARGET_CLEARFOG bool "Support ClearFog" select DB_88F6820_GP +config TARGET_MVEBU_DB_88F3720 + bool "Support DB-88F3720 Armada 3720" + select ARMADA_3700 + config TARGET_DB_88F6720 bool "Support DB-88F6720 Armada 375" select ARMADA_375
@@ -84,6 +88,7 @@ endchoice config SYS_BOARD default "clearfog" if TARGET_CLEARFOG + default "mvebu_db-88f3720" if TARGET_MVEBU_DB_88F3720 default "db-88f6720" if TARGET_DB_88F6720 default "db-88f6820-gp" if TARGET_DB_88F6820_GP default "db-mv784mp-gp" if TARGET_DB_MV784MP_GP
@@ -93,6 +98,7 @@ config SYS_BOARD config SYS_CONFIG_NAME default "clearfog" if TARGET_CLEARFOG + default "mvebu_db-88f3720" if TARGET_MVEBU_DB_88F3720 default "db-88f6720" if TARGET_DB_88F6720 default "db-88f6820-gp" if TARGET_DB_88F6820_GP default "db-mv784mp-gp" if TARGET_DB_MV784MP_GP
@@ -102,6 +108,7 @@ config SYS_CONFIG_NAME config SYS_VENDOR default "Marvell" if TARGET_DB_MV784MP_GP + default "Marvell" if TARGET_MVEBU_DB_88F3720 default "Marvell" if TARGET_DB_88F6720 default "Marvell" if TARGET_DB_88F6820_GP default "solidrun" if TARGET_CLEARFOG
board/Marvell/mvebu_db-88f3720/MAINTAINERS new file +6 -0
@@ -0,0 +1,6 @@ +MVEBU_DB_88F3720 BOARD +M: Stefan Roese <[email protected]> +S: Maintained +F: board/Marvell/mvebu_db-88f3720/ +F: include/configs/mvebu_db-88f3720.h +F: configs/mvebu_db-88f3720_defconfig
board/Marvell/mvebu_db-88f3720/Makefile new file +7 -0
@@ -0,0 +1,7 @@ +# +# Copyright (C) 2016 Stefan Roese <[email protected]> +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y := board.o
board/Marvell/mvebu_db-88f3720/board.c new file +134 -0
134 lines not on this page · raw message
configs/mvebu_db-88f3720_defconfig new file +49 -0
49 lines not on this page · raw message
include/configs/mvebu_db-88f3720.h new file +145 -0
145 lines not on this page · raw message
Signature · 1 line
2.9.3