drivers/phy: Add Marvell SerDes / PHY drivers used on Armada 7K/8K

index 5c50e9c..df5b7d5 100644
@@ -60,6 +60,9 @@
 #define COMMON_PHY_SD_CTRL1_RXAUI0_MASK		\
 	(0x1 << COMMON_PHY_SD_CTRL1_RXAUI0_OFFSET)
 
+/* ToDo: Get this address via DT */
+#define MVEBU_CP0_REGS_BASE			0xF2000000UL
+
 #define DFX_DEV_GEN_CTRL12			(MVEBU_CP0_REGS_BASE + 0x400280)
 #define DFX_DEV_GEN_PCIE_CLK_SRC_OFFSET		7
 #define DFX_DEV_GEN_PCIE_CLK_SRC_MASK		\

@@ -117,10 +120,21 @@ static inline int comphy_a3700_init(struct chip_serdes_phy_config *ptr_chip_cfg,
 	return -1;
 }
 #endif
-int comphy_ap806_init(struct chip_serdes_phy_config *ptr_chip_cfg,
-		      struct comphy_map *serdes_map);
+
+#ifdef CONFIG_ARMADA_8K
 int comphy_cp110_init(struct chip_serdes_phy_config *ptr_chip_cfg,
 		      struct comphy_map *serdes_map);
+#else
+static inline int comphy_cp110_init(struct chip_serdes_phy_config *ptr_chip_cfg,
+		      struct comphy_map *serdes_map)
+{
+	/*
+	 * This function should never be called in this configuration, so
+	 * lets return an error here.
+	 */
+	return -1;
+}
+#endif
 
 void comphy_dedicated_phys_init(void);
 

index 519bc16..799e034 100644
@@ -139,6 +139,9 @@ static int comphy_probe(struct udevice *dev)
 	if (of_device_is_compatible(dev, "marvell,comphy-armada-3700"))
 		chip_cfg->ptr_comphy_chip_init = comphy_a3700_init;
 
+	if (of_device_is_compatible(dev, "marvell,comphy-cp110"))
+		chip_cfg->ptr_comphy_chip_init = comphy_cp110_init;
+
 	/*
 	 * Bail out if no chip_init function is defined, e.g. no
 	 * compatible node is found

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index 0c9b500..179e910 100644
@@ -78,6 +78,14 @@
 #define HPIPE_KVCO_CALIB_CTRL_MAX_PLL_MASK	\
 	(0x1 << HPIPE_KVCO_CALIB_CTRL_MAX_PLL_OFFSET)
 
+#define HPIPE_CAL_REG1_REG			0xc
+#define HPIPE_CAL_REG_1_EXT_TXIMP_OFFSET	10
+#define HPIPE_CAL_REG_1_EXT_TXIMP_MASK		\
+	(0x1f << HPIPE_CAL_REG_1_EXT_TXIMP_OFFSET)
+#define HPIPE_CAL_REG_1_EXT_TXIMP_EN_OFFSET	15
+#define HPIPE_CAL_REG_1_EXT_TXIMP_EN_MASK	\
+	(0x1 << HPIPE_CAL_REG_1_EXT_TXIMP_EN_OFFSET)
+
 #define HPIPE_SQUELCH_FFE_SETTING_REG           0x018
 
 #define HPIPE_DFE_REG0				0x01C

@@ -94,6 +102,9 @@
 	(0x1 << HPIPE_DFE_F3_F5_DFE_CTRL_OFFSET)
 
 #define HPIPE_G1_SET_0_REG			0x034
+#define HPIPE_G1_SET_0_G1_TX_AMP_OFFSET		1
+#define HPIPE_G1_SET_0_G1_TX_AMP_MASK		\
+	(0x1f << HPIPE_G1_SET_0_G1_TX_AMP_OFFSET)
 #define HPIPE_G1_SET_0_G1_TX_EMPH1_OFFSET	7
 #define HPIPE_G1_SET_0_G1_TX_EMPH1_MASK		\
 	(0xf << HPIPE_G1_SET_0_G1_TX_EMPH1_OFFSET)

@@ -145,6 +156,14 @@
 #define HPIPE_ISOLATE_MODE_GEN_TX_MASK		\
 	(0xf << HPIPE_ISOLATE_MODE_GEN_TX_OFFSET)
 
+#define HPIPE_G1_SET_2_REG			0xf4
+#define HPIPE_G1_SET_2_G1_TX_EMPH0_OFFSET	0
+#define HPIPE_G1_SET_2_G1_TX_EMPH0_MASK		\
+	(0xf << HPIPE_G1_SET_2_G1_TX_EMPH0_OFFSET)
+#define HPIPE_G1_SET_2_G1_TX_EMPH0_EN_OFFSET	4
+#define HPIPE_G1_SET_2_G1_TX_EMPH0_EN_MASK	\
+	(0x1 << HPIPE_G1_SET_2_G1_TX_EMPH0_MASK)
+
 #define HPIPE_VTHIMPCAL_CTRL_REG                0x104
 
 #define HPIPE_PCIE_REG0                         0x120

@@ -164,6 +183,9 @@
 #define HPIPE_MISC_CLK100M_125M_OFFSET		4
 #define HPIPE_MISC_CLK100M_125M_MASK		\
 	(0x1 << HPIPE_MISC_CLK100M_125M_OFFSET)
+#define HPIPE_MISC_ICP_FORCE_OFFSET		5
+#define HPIPE_MISC_ICP_FORCE_MASK		\
+	(0x1 << HPIPE_MISC_ICP_FORCE_OFFSET)
 #define HPIPE_MISC_TXDCLK_2X_OFFSET		6
 #define HPIPE_MISC_TXDCLK_2X_MASK		\
 	(0x1 << HPIPE_MISC_TXDCLK_2X_OFFSET)

@@ -197,6 +219,14 @@
 #define HPIPE_SMAPLER_MASK			\
 	(0x1 << HPIPE_SMAPLER_OFFSET)
 
+#define HPIPE_TX_REG1_REG			0x174
+#define HPIPE_TX_REG1_TX_EMPH_RES_OFFSET	5
+#define HPIPE_TX_REG1_TX_EMPH_RES_MASK		\
+	(0x3 << HPIPE_TX_REG1_TX_EMPH_RES_OFFSET)
+#define HPIPE_TX_REG1_SLC_EN_OFFSET		10
+#define HPIPE_TX_REG1_SLC_EN_MASK		\
+	(0x3f << HPIPE_TX_REG1_SLC_EN_OFFSET)
+
 #define HPIPE_PWR_CTR_DTL_REG			0x184
 #define HPIPE_PWR_CTR_DTL_FLOOP_EN_OFFSET	2
 #define HPIPE_PWR_CTR_DTL_FLOOP_EN_MASK		\

@@ -262,6 +292,9 @@
 	(0x1 << HPIPE_TX_SWEEP_PRESET_EN_OFFSET)
 
 #define HPIPE_G1_SETTINGS_3_REG			0x440
+#define HPIPE_G1_SETTINGS_3_G1_FBCK_SEL_OFFSET	9
+#define HPIPE_G1_SETTINGS_3_G1_FBCK_SEL_MASK	\
+	(0x1 << HPIPE_G1_SETTINGS_3_G1_FBCK_SEL_OFFSET)
 
 #define HPIPE_G1_SETTINGS_4_REG			0x444
 #define HPIPE_G1_SETTINGS_4_G1_DFE_RES_OFFSET	8

@@ -289,6 +322,11 @@
 #define HPIPE_DFE_CTRL_28_PIPE4_MASK		\
 	(0x1 << HPIPE_DFE_CTRL_28_PIPE4_OFFSET)
 
+#define HPIPE_G1_SETTING_5_REG			0x538
+#define HPIPE_G1_SETTING_5_G1_ICP_OFFSET	0
+#define HPIPE_G1_SETTING_5_G1_ICP_MASK		\
+	(0xf << HPIPE_G1_SETTING_5_G1_ICP_OFFSET)
+
 #define HPIPE_LANE_CONFIG0_REG			0x600
 #define HPIPE_LANE_CONFIG0_TXDEEMPH0_OFFSET	0
 #define HPIPE_LANE_CONFIG0_TXDEEMPH0_MASK	\

new file mode 100644
index 0000000..be2ba54
@@ -0,0 +1,30 @@
+/*
+ * Copyright (C) 2015-2016 Marvell International Ltd.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _SATA_H_
+#define _SATA_H_
+
+/* SATA3 Unit address */
+#define SATA3_VENDOR_ADDRESS		0xA0
+#define SATA3_VENDOR_ADDR_OFSSET	0
+#define SATA3_VENDOR_ADDR_MASK		(0xFFFFFFFF << SATA3_VENDOR_ADDR_OFSSET)
+#define SATA3_VENDOR_DATA		0xA4
+
+#define SATA_CONTROL_REG		0x0
+#define SATA3_CTRL_SATA0_PD_OFFSET	6
+#define SATA3_CTRL_SATA0_PD_MASK	(1 << SATA3_CTRL_SATA0_PD_OFFSET)
+#define SATA3_CTRL_SATA1_PD_OFFSET	14
+#define SATA3_CTRL_SATA1_PD_MASK	(1 << SATA3_CTRL_SATA1_PD_OFFSET)
+#define SATA3_CTRL_SATA1_ENABLE_OFFSET	22
+#define SATA3_CTRL_SATA1_ENABLE_MASK	(1 << SATA3_CTRL_SATA1_ENABLE_OFFSET)
+#define SATA3_CTRL_SATA_SSU_OFFSET	23
+#define SATA3_CTRL_SATA_SSU_MASK	(1 << SATA3_CTRL_SATA_SSU_OFFSET)
+
+#define SATA_MBUS_SIZE_SELECT_REG	0x4
+#define SATA_MBUS_REGRET_EN_OFFSET	7
+#define SATA_MBUS_REGRET_EN_MASK	(0x1 << SATA_MBUS_REGRET_EN_OFFSET)
+
+#endif /* _SATA_H_ */

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index e09e87a..23c241a 100644
@@ -79,6 +79,7 @@ static int xhci_usb_ofdata_to_platdata(struct udevice *dev)
 
 static const struct udevice_id xhci_usb_ids[] = {
 	{ .compatible = "marvell,armada3700-xhci" },
+	{ .compatible = "marvell,armada-8k-xhci" },
 	{ }
 };
 

index e3e783a..cd99737 100644
@@ -45,7 +45,7 @@ u16 *ataid[AHCI_MAX_PORTS];
 #define WAIT_MS_FLUSH	5000
 #define WAIT_MS_LINKUP	200
 
-static inline void __iomem *ahci_port_base(void __iomem *base, u32 port)
+__weak void __iomem *ahci_port_base(void __iomem *base, u32 port)
 {
 	return base + 0x100 + (port * 0x80);
 }

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index 063d6cc..731fe65 100644
@@ -46,6 +46,8 @@
  * required for the Linux kernel.
  */
 #define SOC_REGS_PHY_BASE	0xd0000000
+#elif defined(CONFIG_ARMADA_8K)
+#define SOC_REGS_PHY_BASE	0xf0000000
 #else
 #define SOC_REGS_PHY_BASE	0xf1000000
 #endif

similarity index 77%
rename from arch/arm/mach-mvebu/armada3700/sata.c
rename to arch/arm/mach-mvebu/sata.c
index e0e8381..140a295 100644
@@ -19,6 +19,14 @@ __weak int board_ahci_enable(void)
 	return 0;
 }
 
+#ifdef CONFIG_ARMADA_8K
+/* CP110 has different AHCI port addresses */
+void __iomem *ahci_port_base(void __iomem *base, u32 port)
+{
+	return base + 0x10000 + (port * 0x10000);
+}
+#endif
+
 static int mvebu_ahci_probe(struct udevice *dev)
 {
 	/*

@@ -34,6 +42,7 @@ static int mvebu_ahci_probe(struct udevice *dev)
 
 static const struct udevice_id mvebu_ahci_ids[] = {
 	{ .compatible = "marvell,armada-3700-ahci" },
+	{ .compatible = "marvell,armada-8k-ahci" },
 	{ }
 };
 

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