arm64: arch_timer: Add device tree binding for A-008585 erratum
Subsystems (7)
PATCH v6 1/4 arm64: arch_timer: Add device tree binding for A-008585 erratum
This erratum describes a bug in logic outside the core, so MIDR can't be used to identify its presence, and reading an SoC-specific revision register from common arch timer code would be awkward. So, describe it in the device tree.
--- Documentation/devicetree/bindings/arm/arch_timer.txt | 6 ++++++ 1 file changed, 6 insertions(+)
Documentation/devicetree/bindings/arm/arch_timer.txt +6 -0
@@ -25,6 +25,12 @@ to deliver its interrupts via SPIs. - always-on : a boolean property. If present, the timer is powered through an always-on power domain, therefore it never loses context. +- fsl,erratum-a008585 : A boolean property. Indicates the presence of + QorIQ erratum A-008585, which says that reading the counter is + unreliable unless the same value is returned by back-to-back reads. + This also affects writes to the tval register, due to the implicit + counter read. + ** Optional properties: - arm,cpu-registers-not-fw-configured : Firmware does not initialize
Signature · 1 line
2.7.4
PATCH v6 2/4 arm64: dts: Add timer erratum property for LS2080A and LS1043A
--- arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi | 1 + arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi | 1 + 2 files changed, 2 insertions(+)
arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi +1 -0
@@ -123,6 +123,7 @@ <1 14 0x1>, /* Physical Non-Secure PPI */ <1 11 0x1>, /* Virtual PPI */ <1 10 0x1>; /* Hypervisor PPI */ + fsl,erratum-a008585; }; pmu {
arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi +1 -0
@@ -195,6 +195,7 @@ <1 14 0x8>, /* Physical Non-Secure PPI, active-low */ <1 11 0x8>, /* Virtual PPI, active-low */ <1 10 0x8>; /* Hypervisor PPI, active-low */ + fsl,erratum-a008585; }; pmu {
Signature · 1 line
2.7.4
PATCH v6 2/4 arm64: dts: Add timer erratum property for LS2080A and LS1043A
With a commit message along the lines of:
Both the LS1043A and LS2080A platforms are affected by the Freescale A008585 erratum. Advertise it in their respective device trees.
Quoted 24 lines · Scott Wood
Signed-off-by Scott Wood <[email protected]>--- arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi | 1 + arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi | 1 + 2 files changed, 2 insertions(+)arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi +1
-0@@ -123,6 +123,7 @@ <1 14 0x1>, /* Physical Non-Secure PPI */ <1 11 0x1>, /* Virtual PPI */ <1 10 0x1>; /* Hypervisor PPI */ + fsl,erratum-a008585; }; pmu {arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi +0
-0
arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi line 201
Quoted 7 lines
arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi +1
-0@@ -195,6 +195,7 @@ <1 14 0x8>, /* Physical Non-Secure PPI, active-low */ <1 11 0x8>, /* Virtual PPI, active-low */ <1 10 0x8>; /* Hypervisor PPI, active-low */ + fsl,erratum-a008585; }; pmu {
M.
Signature · 1 line
Jazz is not dead. It just smells funny...
PATCH v6 2/4 arm64: dts: Add timer erratum property for LS2080A and LS1043A
Quoted 4 lines · Marc Zyngier
With a commit message along the lines of:
Both the LS1043A and LS2080A platforms are affected by the Freescale A008585 erratum. Advertise it in their respective device trees.
<snip>
Quoted 1 line
Acked-by Marc Zyngier <[email protected]>
Thanks, Marc. I queued up the patch with the suggested commit log added.
Shawn
PATCH v6 2/4 arm64: dts: Add timer erratum property for LS2080A and LS1043A
In reply to Scott WoodQuoted 5 lines · Scott Wood
Signed-off-by Scott Wood <[email protected]>--- arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi | 1 + arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi | 1 + 2 files changed, 2 insertions(+)
This patch conflicts with mainline, but I've queued the other three patches in the series in the arm64 tree.
Please send the updated .dts changes via arm-soc.
Will
PATCH v6 2/4 arm64: dts: Add timer erratum property for LS2080A and LS1043A
Quoted 8 lines · Will Deacon
Quoted 5 lines · Scott Wood
Signed-off-by Scott Wood <[email protected]>--- arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi | 1 + arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi | 1 + 2 files changed, 2 insertions(+)This patch conflicts with mainline,
Thanks for the heads-up.
Quoted 4 lines
but I've queued the other three
patches in the series in the arm64 tree.Please send the updated .dts changes via arm-soc.
I will send this to arm-soc when v4.9-rc1 comes out with driver changes in place.
Shawn
PATCH v6 3/4 arm64: arch_timer: Work around QorIQ Erratum A-008585
In reply to Scott WoodErratum A-008585 says that the ARM generic timer counter "has the potential to contain an erroneous value for a small number of core clock cycles every time the timer value changes". Accesses to TVAL (both read and write) are also affected due to the implicit counter read. Accesses to CVAL are not affected.
The workaround is to reread TVAL and count registers until successive reads return the same value. Writes to TVAL are replaced with an equivalent write to CVAL.
The workaround is to reread TVAL and count registers until successive reads return the same value, and when writing TVAL to retry until counter reads before and after the write return the same value.
The workaround is enabled if the fsl,erratum-a008585 property is found in the timer node in the device tree. This can be overridden with the clocksource.arm_arch_timer.fsl-a008585 boot parameter, which allows KVM users to enable the workaround until a mechanism is implemented to automatically communicate this information.
This erratum can be found on LS1043A and LS2080A.
---
v6:
- Addressed feedback from Mark Rutland
v5:
- Export arch_timer_read_ool_enabled so that get_cycles() can be called from modules.
v4:
- Undef ARCH_TIMER_REG_READ after use
v3:
- Used cval rather than a loop for the write side of the erratum
- Added a Kconfig control
- Moved the device tree binding into its own patch
- Added erratum to silicon-errata.txt
- Changed function names to contain the erratum name
- Factored out the setting of erratum versions of set_next_event to improve readability
- Added a comment clarifying that the timeout is arbitrary
v2:
Significant rework based on feedback, including using static_key, disabling VDSO counter access rather than adding the workaround to the VDSO, and uninlining the loops.
Dropped the separate property for indicating that writes to TVAL are affected, as I believe that's just a side effect of the implicit counter read being corrupted, and thus a chip that is affected by one will always be affected by the other.
Dropped the arm32 portion as it seems there was confusion about whether LS1021A is affected. Currently I am being told that it is not affected.
I considered writing to CVAL rather than looping on TVAL writes, but that would still have required separate set_next_event() code for the erratum, and adding CVAL to the enum would have required a bunch of extra handlers in switch statements (even where unused, due to compiler warnings about unhandled enum values) including in an arm32 header. It seemed better to avoid the arm32 interaction and new untested accessors.
--- Documentation/arm64/silicon-errata.txt | 2 + Documentation/kernel-parameters.txt | 9 +++ arch/arm64/include/asm/arch_timer.h | 47 ++++++++++++++- drivers/clocksource/Kconfig | 10 ++++ drivers/clocksource/arm_arch_timer.c | 104 +++++++++++++++++++++++++++++++++ 5 files changed, 169 insertions(+), 3 deletions(-)
Documentation/arm64/silicon-errata.txt +2 -0
@@ -60,3 +60,5 @@ stable kernels. | Cavium | ThunderX GICv3 | #23154 | CAVIUM_ERRATUM_23154 | | Cavium | ThunderX Core | #27456 | CAVIUM_ERRATUM_27456 | | Cavium | ThunderX SMMUv2 | #27704 | N/A | +| | | | | +| Freescale/NXP | LS2080A/LS1043A | A-008585 | FSL_ERRATUM_A008585 |
Documentation/kernel-parameters.txt +9 -0
@@ -698,6 +698,15 @@ bytes respectively. Such letter suffixes can also be entirely omitted. loops can be debugged more effectively on production systems. + clocksource.arm_arch_timer.fsl-a008585= + [ARM64] + Format: <bool> + Enable/disable the workaround of Freescale/NXP + erratum A-008585. This can be useful for KVM + guests, if the guest device tree doesn't show the + erratum. If unspecified, the workaround is + enabled based on the device tree. + clearcpuid=BITNUM [X86] Disable CPUID feature X for the kernel. See arch/x86/include/asm/cpufeatures.h for the valid bit
arch/arm64/include/asm/arch_timer.h +44 -3
75 lines not on this page · raw message
drivers/clocksource/Kconfig +10 -0
@@ -305,6 +305,16 @@ config ARM_ARCH_TIMER_EVTSTREAM This must be disabled for hardware validation purposes to detect any hardware anomalies of missing events. +config FSL_ERRATUM_A008585 + bool "Workaround for Freescale/NXP Erratum A-008585" + default y + depends on ARM_ARCH_TIMER && ARM64 + help + This option enables a workaround for Freescale/NXP Erratum + A-008585 ("ARM generic timer may contain an erroneous + value"). The workaround will only be active if the + fsl,erratum-a008585 property is found in the timer node. + config ARM_GLOBAL_TIMER bool "Support for the ARM global timer" if COMPILE_TEST select CLKSRC_OF if OF
drivers/clocksource/arm_arch_timer.c +104 -0
140 lines not on this page · raw message
Signature · 1 line
2.7.4
PATCH v6 3/4 arm64: arch_timer: Work around QorIQ Erratum A-008585
Quoted 139 lines · Scott Wood
Erratum A-008585 says that the ARM generic timer counter "has the potential to contain an erroneous value for a small number of core clock cycles every time the timer value changes". Accesses to TVAL (both read and write) are also affected due to the implicit counter read. Accesses to CVAL are not affected.
The workaround is to reread TVAL and count registers until successive reads return the same value. Writes to TVAL are replaced with an equivalent write to CVAL.
The workaround is to reread TVAL and count registers until successive reads return the same value, and when writing TVAL to retry until counter reads before and after the write return the same value.
The workaround is enabled if the fsl,erratum-a008585 property is found in the timer node in the device tree. This can be overridden with the clocksource.arm_arch_timer.fsl-a008585 boot parameter, which allows KVM users to enable the workaround until a mechanism is implemented to automatically communicate this information.
This erratum can be found on LS1043A and LS2080A.
Signed-off-by Scott Wood <[email protected]>---
v6:
- Addressed feedback from Mark Rutlandv5:
- Exportarch_timer_read_ool_enabledso thatget_cycles()can be called from modules.v4:
- UndefARCH_TIMER_REG_READafter usev3:
- Used cval rather than a loop for the write side of the erratum
- Added aKconfigcontrol
- Moved the device tree binding into its own patch
- Added erratum to silicon-errata.txt
- Changed function names to contain the erratum name
- Factored out the setting of erratum versions ofset_next_eventto improve readability
- Added a comment clarifying that the timeout is arbitraryv2:
Significant rework based on feedback, including usingstatic_key, disabling VDSO counter access rather than adding the workaround to the VDSO, and uninlining the loops.Dropped the separate property for indicating that writes to TVAL are affected, as I believe that's just a side effect of the implicit counter read being corrupted, and thus a chip that is affected by one will always be affected by the other.
Dropped the arm32 portion as it seems there was confusion about whether LS1021A is affected. Currently I am being told that it is not affected.
I considered writing to CVAL rather than looping on TVAL writes, but that would still have required separate
set_next_event()code for the erratum, and adding CVAL to the enum would have required a bunch of extra handlers in switch statements (even where unused, due to compiler warnings about unhandled enum values) including in an arm32 header. It seemed better to avoid the arm32 interaction and new untested accessors.Signed-off-by Scott Wood <[email protected]>--- Documentation/arm64/silicon-errata.txt | 2 + Documentation/kernel-parameters.txt | 9 +++ arch/arm64/include/asm/arch_timer.h | 47 ++++++++++++++- drivers/clocksource/Kconfig | 10 ++++ drivers/clocksource/arm_arch_timer.c | 104 +++++++++++++++++++++++++++++++++ 5 files changed, 169 insertions(+), 3 deletions(-)Documentation/arm64/silicon-errata.txt +2
-0@@ -60,3 +60,5 @@ stable kernels. | Cavium | ThunderX GICv3 | #23154 | CAVIUM_ERRATUM_23154 | | Cavium | ThunderX Core | #27456 | CAVIUM_ERRATUM_27456 | | Cavium | ThunderX SMMUv2 | #27704 | N/A | +| | | | | +| Freescale/NXP | LS2080A/LS1043A | A-008585 | FSL_ERRATUM_A008585 |Documentation/kernel-parameters.txt +9
-0@@ -698,6 +698,15 @@ bytes respectively. Such letter suffixes can also be entirely omitted. loops can be debugged more effectively on production systems. + clocksource.arm_arch_timer.fsl-a008585= + [ARM64] + Format: <bool> + Enable/disable the workaround of Freescale/NXP + erratum A-008585. This can be useful for KVM + guests, if the guest device tree doesn't show the + erratum. If unspecified, the workaround is + enabled based on the device tree. + clearcpuid=BITNUM [X86] Disable CPUID feature X for the kernel. See arch/x86/include/asm/cpufeatures.h for the valid bitarch/arm64/include/asm/arch_timer.h +22
-0@@ -24,10 +24,51 @@#include <linux/bug.h> #include <linux/init.h> +#include <linux/jump_label.h> #include <linux/types.h> #include <clocksource/arm_arch_timer.h> +#if IS_ENABLED (CONFIG_FSL_ERRATUM_A008585 ) +extern struct static_key_false arch_timer_read_ool_enabled; +#define needs_fsl_a008585_workaround () \ + static_branch_unlikely(&arch_timer_read_ool_enabled) +#else +#define needs_fsl_a008585_workaround () false +#endif + +u32 __fsl_a008585_read_cntp_tval_el0 (void ); +u32 __fsl_a008585_read_cntv_tval_el0 (void ); +u64 __fsl_a008585_read_cntvct_el0 (void ); + +/* +* The number of retries is an arbitrary value well beyond the highest number +* of iterations the loop has been observed to take. +*/ +#define __fsl_a008585_read_reg (reg) ({ \ + u64 _old, _new; \ + int _retries = 200; \ + \ + do { \
arch/arm64/include/asm/arch_timer.h line 62
Quoted 10 lines
arch/arm64/include/asm/arch_timer.h +10
-0+ _old =read_sysreg (reg); \ + _new =read_sysreg (reg); \ + _retries--; \ + }while (unlikely (_old != _new) && _retries); \ + \ +WARN_ON_ONCE (!_retries); \ + _new; \ +}) + +#define arch_timer_unstable_reg_read (reg) \
I think this name is the only thing I don't like about this patch, because it is only unstable if the workaround is on. This is a minor thing and it can be addressed when/after merging it. No need to respin it on this account.
The usual question is "Who takes it?". I'm quite keen on it, as my LS2085 is otherwise completely unusable.
Thanks,
M.
Signature · 1 line
Jazz is not dead. It just smells funny...
PATCH v6 4/4 arm/arm64: arch_timer: Use archdata to indicate vdso suitability
In reply to Scott WoodInstead of comparing the name to a magic string, use archdata to explicitly communicate whether the arch timer is suitable for direct vdso access.
--- arch/arm/Kconfig | 1 + arch/arm/include/asm/clocksource.h | 8 ++++++++ arch/arm/kernel/vdso.c | 2 +- arch/arm64/Kconfig | 1 + arch/arm64/include/asm/clocksource.h | 8 ++++++++ arch/arm64/kernel/vdso.c | 2 +- drivers/clocksource/arm_arch_timer.c | 11 +++-------- 7 files changed, 23 insertions(+), 10 deletions(-) create mode 100644 arch/arm/include/asm/clocksource.h create mode 100644 arch/arm64/include/asm/clocksource.h
arch/arm/Kconfig +1 -0
@@ -1,6 +1,7 @@ config ARM bool default y + select ARCH_CLOCKSOURCE_DATA select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE select ARCH_HAS_DEVMEM_IS_ALLOWED select ARCH_HAS_ELF_RANDOMIZE
arch/arm/include/asm/clocksource.h new file +8 -0
@@ -0,0 +1,8 @@ +#ifndef _ASM_CLOCKSOURCE_H +#define _ASM_CLOCKSOURCE_H + +struct arch_clocksource_data { +bool vdso_direct;/* Usable for direct VDSO access? */ +}; + +#endif
arch/arm/kernel/vdso.c +1 -1
@@ -270,7 +270,7 @@ static bool tk_is_cntvct(const struct timekeeper *tk)if (!IS_ENABLED (CONFIG_ARM_ARCH_TIMER ))return false; -if (strcmp (tk->tkr_mono.clock->name,"arch_sys_counter" ) !=0 ) +if (!tk->tkr_mono.clock->archdata.vdso_direct)return false;return true;
arch/arm64/Kconfig +1 -0
@@ -4,6 +4,7 @@ config ARM64 select ACPI_GENERIC_GSI if ACPI select ACPI_REDUCED_HARDWARE_ONLY if ACPI select ACPI_MCFG if ACPI + select ARCH_CLOCKSOURCE_DATA select ARCH_HAS_DEVMEM_IS_ALLOWED select ARCH_HAS_ACPI_TABLE_UPGRADE if ACPI select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
arch/arm64/include/asm/clocksource.h new file +8 -0
@@ -0,0 +1,8 @@ +#ifndef _ASM_CLOCKSOURCE_H +#define _ASM_CLOCKSOURCE_H + +struct arch_clocksource_data { +bool vdso_direct;/* Usable for direct VDSO access? */ +}; + +#endif
arch/arm64/kernel/vdso.c +1 -1
@@ -201,7 +201,7 @@ up_fail:*/ void update_vsyscall (struct timekeeper *tk) { -u32 use_syscall =strcmp (tk->tkr_mono.clock->name,"arch_sys_counter" ); +u32 use_syscall = !tk->tkr_mono.clock->archdata.vdso_direct; ++vdso_data->tb_seq_count;smp_wmb ();
drivers/clocksource/arm_arch_timer.c +3 -8
@@ -602,23 +602,18 @@ static void __init arch_counter_register(unsigned type)else arch_timer_read_counter = arch_counter_get_cntpct; + clocksource_counter.archdata.vdso_direct = true; +#ifdef CONFIG_FSL_ERRATUM_A008585 /* * Don't use the vdso fastpath if errata require using * the out-of-line counter accessor. */ if (static_branch_unlikely (&arch_timer_read_ool_enabled)) - clocksource_counter.name ="arch_sys_counter_ool" ; + clocksource_counter.archdata.vdso_direct = false;#endif }else { arch_timer_read_counter = arch_counter_get_cntvct_mem; - -/* If the clocksource name is "arch_sys_counter" the -* VDSO will attempt to read the CP15-based counter. -* Ensure this does not happen when CP15-based -* counter is not available. -*/ - clocksource_counter.name ="arch_mem_counter" ; } start_count =arch_timer_read_counter ();
Signature · 1 line
2.7.4
Russell King - ARM Linux
maintainerPATCH v6 4/4 arm/arm64: arch_timer: Use archdata to indicate vdso suitability
It helps to add the appropriate people to your email if you want to get a change into the kernel. Will has had to point this message out to me.
Quoted 49 lines · Scott Wood
Instead of comparing the name to a magic string, use archdata to explicitly communicate whether the arch timer is suitable for direct vdso access.
Signed-off-by Scott Wood <[email protected]>Acked-by Will Deacon <[email protected]>--- arch/arm/Kconfig | 1 + arch/arm/include/asm/clocksource.h | 8 ++++++++ arch/arm/kernel/vdso.c | 2 +- arch/arm64/Kconfig | 1 + arch/arm64/include/asm/clocksource.h | 8 ++++++++ arch/arm64/kernel/vdso.c | 2 +- drivers/clocksource/arm_arch_timer.c | 11 +++-------- 7 files changed, 23 insertions(+), 10 deletions(-) create mode 100644 arch/arm/include/asm/clocksource.h create mode 100644 arch/arm64/include/asm/clocksource.harch/arm/Kconfig +1
-0@@ -1,6 +1,7 @@ config ARM bool default y + select ARCH_CLOCKSOURCE_DATA select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE select ARCH_HAS_DEVMEM_IS_ALLOWED select ARCH_HAS_ELF_RANDOMIZEarch/arm/include/asm/clocksource.h new file +8
-0@@ -0,0 +1,8 @@ +#ifndef _ASM_CLOCKSOURCE_H +#define _ASM_CLOCKSOURCE_H + +struct arch_clocksource_data { +bool vdso_direct;/* Usable for direct VDSO access? */ +}; + +#endif arch/arm/kernel/vdso.c +0
-0
arch/arm/kernel/vdso.c static bool tk_is_cntvct(const struct timekeeper *tk) · line 276
Quoted 8 lines
arch/arm/kernel/vdso.c +1
-1@@ -270,7 +270,7 @@ static bool tk_is_cntvct(const struct timekeeper *tk)if (!IS_ENABLED (CONFIG_ARM_ARCH_TIMER ))return false; -if (strcmp (tk->tkr_mono.clock->name,"arch_sys_counter" ) !=0 ) +if (!tk->tkr_mono.clock->archdata.vdso_direct)return false;return true;
For the ARM bits:
Signature · 3 lines
RMK's Patch system: http://www.armlinux.org.uk/developer/patches/ FTTC broadband for 0.8mile line: currently at 9.6Mbps down 400kbps up according to speedtest.net.
PATCH v6 4/4 arm/arm64: arch_timer: Use archdata to indicate vdso suitability
In reply to Scott WoodQuoted 6 lines · Scott Wood
Instead of comparing the name to a magic string, use archdata to explicitly communicate whether the arch timer is suitable for direct vdso access.
Signed-off-by Scott Wood <[email protected]>Acked-by Will Deacon <[email protected]>
Quoted 11 lines
--- arch/arm/Kconfig | 1 + arch/arm/include/asm/clocksource.h | 8 ++++++++ arch/arm/kernel/vdso.c | 2 +- arch/arm64/Kconfig | 1 + arch/arm64/include/asm/clocksource.h | 8 ++++++++ arch/arm64/kernel/vdso.c | 2 +- drivers/clocksource/arm_arch_timer.c | 11 +++-------- 7 files changed, 23 insertions(+), 10 deletions(-) create mode 100644 arch/arm/include/asm/clocksource.h create mode 100644 arch/arm64/include/asm/clocksource.h
M.
Signature · 1 line
Jazz is not dead. It just smells funny...
PATCH v6 1/4 arm64: arch_timer: Add device tree binding for A-008585 erratum
In reply to Scott WoodQuoted 10 lines · Scott Wood
This erratum describes a bug in logic outside the core, so MIDR can't be used to identify its presence, and reading an SoC-specific revision register from common arch timer code would be awkward. So, describe it in the device tree.
Signed-off-by Scott Wood <[email protected]>Acked-by Rob Herring <[email protected]>--- Documentation/devicetree/bindings/arm/arch_timer.txt | 6 ++++++ 1 file changed, 6 insertions(+)
M.
Signature · 1 line
Jazz is not dead. It just smells funny...