arm: print the cache config option in hex instead of decimal

PATCH New Keerthy 3 participants 12 messages Oct 29, 2016 – Nov 13, 2016 Arm (32-bit)

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Keerthy

author

2016-10-29 09:49 UTC #0 lore raw

PATCH v2 1/2 arm: print the cache config option in hex instead of decimal

Printing the option value in hex makes it more comprehensible.

Signed-off-by Keerthy <[email protected]>

---
 arch/arm/lib/cache-cp15.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

arch/arm/lib/cache-cp15.c +1 -1

index 70e94f0..e9f9fc9 100644
@@ -71,7 +71,7 @@ void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size,
 
 	end = ALIGN(start + size, MMU_SECTION_SIZE) >> MMU_SECTION_SHIFT;
 	start = start >> MMU_SECTION_SHIFT;
-	debug("%s: start=%pa, size=%zu, option=%d\n", __func__, &start, size,
+	debug("%s: start=%pa, size=%zu, option=0x%x\n", __func__, &start, size,
 	      option);
 	for (upto = start; upto < end; upto++)
 		set_section_dcache(upto, option);

Signature · 1 line

1.9.1

Keerthy

author

2016-10-29 09:49 UTC #1 lore raw

PATCH v2 2/2 arm: Set TTB XN bit in case DCACHE_OFF for LPAE mode

While we setup the mmu initially we mark set_section_dcache with DCACHE_OFF flag. In case of non-LPAE mode the DCACHE_OFF macro is rightly defined with TTB_SECT_XN_MASK set so as to mark all the 4GB XN. In case of LPAE mode XN(Execute-never) bit is not set with DCACHE_OFF. Hence XN bit is not set by default for DCACHE_OFF which keeps all the regions execute okay and this leads to random speculative fetches in random memory regions which was eventually caught by kernel omap-l3-noc driver.

Fix this to mark the regions as XN by default.

Signed-off-by Keerthy <[email protected]>

Reviewed-by Alexander Graf <[email protected]>

---

Changes in v2:

* Changed printing option value from decimal to hex.

 arch/arm/include/asm/system.h | 2 +-
 arch/arm/lib/cache-cp15.c     | 5 +++++
 2 files changed, 6 insertions(+), 1 deletion(-)

arch/arm/include/asm/system.h +1 -1

index b928bd8..2f430ad 100644
@@ -329,7 +329,7 @@ static inline void set_dacr(unsigned int val)
 
 /* options available for data cache on each page */
 enum dcache_option {
-	DCACHE_OFF = TTB_SECT | TTB_SECT_MAIR(0),
+	DCACHE_OFF = TTB_SECT | TTB_SECT_MAIR(0) | TTB_SECT_XN_MASK,
 	DCACHE_WRITETHROUGH = TTB_SECT | TTB_SECT_MAIR(1),
 	DCACHE_WRITEBACK = TTB_SECT | TTB_SECT_MAIR(2),
 	DCACHE_WRITEALLOC = TTB_SECT | TTB_SECT_MAIR(3),

arch/arm/lib/cache-cp15.c +5 -0

index e9f9fc9..e9bbcf5 100644
@@ -71,8 +71,13 @@ void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size,
 
 	end = ALIGN(start + size, MMU_SECTION_SIZE) >> MMU_SECTION_SHIFT;
 	start = start >> MMU_SECTION_SHIFT;
+#ifdef CONFIG_ARMV7_LPAE
+	debug("%s: start=%pa, size=%zu, option=%llx\n", __func__, &start, size,
+	      option);
+#else
 	debug("%s: start=%pa, size=%zu, option=0x%x\n", __func__, &start, size,
 	      option);
+#endif
 	for (upto = start; upto < end; upto++)
 		set_section_dcache(upto, option);

Signature · 1 line

1.9.1

Tom Rini

2016-10-29 17:41 UTC #2 lore raw

PATCH v2 2/2 arm: Set TTB XN bit in case DCACHE_OFF for LPAE mode

Quoted 9 lines · Keerthy

While we setup the mmu initially we mark set_section_dcache with DCACHE_OFF flag. In case of non-LPAE mode the DCACHE_OFF macro is rightly defined with TTB_SECT_XN_MASK set so as to mark all the 4GB XN. In case of LPAE mode XN(Execute-never) bit is not set with DCACHE_OFF. Hence XN bit is not set by default for DCACHE_OFF which keeps all the regions execute okay and this leads to random speculative fetches in random memory regions which was eventually caught by kernel omap-l3-noc driver.

Quoted 4 lines

Fix this to mark the regions as XN by default.
Signed-off-by Keerthy <[email protected]>
Reviewed-by Alexander Graf <[email protected]>

Reviewed-by Tom Rini <[email protected]>

Signature · 8 lines

Tom
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Marek Vasut

2016-10-29 17:44 UTC #3 lore raw

PATCH v2 2/2 arm: Set TTB XN bit in case DCACHE_OFF for LPAE mode

Quoted 11 lines · Tom Rini

Quoted 9 lines · Keerthy
While we setup the mmu initially we mark set_section_dcache with DCACHE_OFF flag. In case of non-LPAE mode the DCACHE_OFF macro is rightly defined with TTB_SECT_XN_MASK set so as to mark all the 4GB XN. In case of LPAE mode XN(Execute-never) bit is not set with DCACHE_OFF. Hence XN bit is not set by default for DCACHE_OFF which keeps all the regions execute okay and this leads to random speculative fetches in random memory regions which was eventually caught by kernel omap-l3-noc driver.

Quoted 7 lines

Quoted 4 lines
Fix this to mark the regions as XN by default.
Signed-off-by Keerthy <[email protected]>
Reviewed-by Alexander Graf <[email protected]>
Reviewed-by Tom Rini <[email protected]>

Isn't this patch exactly undoing the following one ?

commit 8890c2fbe6ed4c5ca9a61f21e846a55f8f2c38fc

Author: Marek Vasut <>
Date:   Tue Dec 29 19:44:02 2015 +0100

arm: Remove S bit from MMU section entry

Restore the old behavior of the MMU section entries configuration, which is without the S-bit.

Signature · 2 lines

Best regards,
Marek Vasut

Tom Rini

2016-10-29 17:47 UTC #4 lore raw

PATCH v2 2/2 arm: Set TTB XN bit in case DCACHE_OFF for LPAE mode

Quoted 21 lines · Marek Vasut

Quoted 11 lines · Tom Rini
Quoted 9 lines · Keerthy
While we setup the mmu initially we mark set_section_dcache with DCACHE_OFF flag. In case of non-LPAE mode the DCACHE_OFF macro is rightly defined with TTB_SECT_XN_MASK set so as to mark all the 4GB XN. In case of LPAE mode XN(Execute-never) bit is not set with DCACHE_OFF. Hence XN bit is not set by default for DCACHE_OFF which keeps all the regions execute okay and this leads to random speculative fetches in random memory regions which was eventually caught by kernel omap-l3-noc driver.
Quoted 7 lines
Quoted 4 lines
Fix this to mark the regions as XN by default.
Signed-off-by Keerthy <[email protected]>
Reviewed-by Alexander Graf <[email protected]>
Reviewed-by Tom Rini <[email protected]>
Isn't this patch exactly undoing the following one ?

Quoted 8 lines

commit 8890c2fbe6ed4c5ca9a61f21e846a55f8f2c38fc
Author: Marek Vasut <>
Date:   Tue Dec 29 19:44:02 2015 +0100
arm: Remove S bit from MMU section entry
Restore the old behavior of the MMU section entries configuration, which is without the S-bit.

Is it? I guess perhaps you and Keerthy need to chat then as there's some other problem they're addressing.

Signature · 8 lines

Tom
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Marek Vasut

2016-10-29 17:49 UTC #5 lore raw

PATCH v2 2/2 arm: Set TTB XN bit in case DCACHE_OFF for LPAE mode

Quoted 26 lines · Tom Rini

Quoted 25 lines · Marek Vasut
Quoted 11 lines · Tom Rini
Quoted 9 lines · Keerthy
While we setup the mmu initially we mark set_section_dcache with DCACHE_OFF flag. In case of non-LPAE mode the DCACHE_OFF macro is rightly defined with TTB_SECT_XN_MASK set so as to mark all the 4GB XN. In case of LPAE mode XN(Execute-never) bit is not set with DCACHE_OFF. Hence XN bit is not set by default for DCACHE_OFF which keeps all the regions execute okay and this leads to random speculative fetches in random memory regions which was eventually caught by kernel omap-l3-noc driver.
Quoted 7 lines
Quoted 4 lines
Fix this to mark the regions as XN by default.
Signed-off-by Keerthy <[email protected]>
Reviewed-by Alexander Graf <[email protected]>
Reviewed-by Tom Rini <[email protected]>
Isn't this patch exactly undoing the following one ?
commit 8890c2fbe6ed4c5ca9a61f21e846a55f8f2c38fc
Author: Marek Vasut <>
Date:   Tue Dec 29 19:44:02 2015 +0100

Quoted 7 lines

Quoted 4 lines
arm: Remove S bit from MMU section entry
Restore the old behavior of the MMU section entries configuration, which is without the S-bit.
Is it? I guess perhaps you and Keerthy need to chat then as there's some other problem they're addressing.

Ummmm, wait a second, I think this one adds XN bit and the previous one removed S bit. I think I was wrong, but please double-check this. I recall we had some odd cache issues on V7 back then.

Signature · 2 lines

Best regards,
Marek Vasut

Keerthy

author

2016-10-30 01:59 UTC #6 lore raw

PATCH v2 2/2 arm: Set TTB XN bit in case DCACHE_OFF for LPAE mode

Quoted 32 lines · Marek Vasut

Quoted 31 lines · Tom Rini
Quoted 29 lines · Marek Vasut
Quoted 11 lines · Tom Rini
Quoted 9 lines · Keerthy
While we setup the mmu initially we mark set_section_dcache with DCACHE_OFF flag. In case of non-LPAE mode the DCACHE_OFF macro is rightly defined with TTB_SECT_XN_MASK set so as to mark all the 4GB XN. In case of LPAE mode XN(Execute-never) bit is not set with DCACHE_OFF. Hence XN bit is not set by default for DCACHE_OFF which keeps all the regions execute okay and this leads to random speculative fetches in random memory regions which was eventually caught by kernel omap-l3-noc driver.
Quoted 7 lines
Quoted 4 lines
Fix this to mark the regions as XN by default.
Signed-off-by Keerthy <[email protected]>
Reviewed-by Alexander Graf <[email protected]>
Reviewed-by Tom Rini <[email protected]>
Isn't this patch exactly undoing the following one ?
commit 8890c2fbe6ed4c5ca9a61f21e846a55f8f2c38fc
Author: Marek Vasut <>
Date:   Tue Dec 29 19:44:02 2015 +0100
arm: Remove S bit from MMU section entry
Restore the old behavior of the MMU section entries configuration, which is without the S-bit.

Quoted 6 lines

Quoted 2 lines
Is it? I guess perhaps you and Keerthy need to chat then as there's some other problem they're addressing.
Ummmm, wait a second, I think this one adds XN bit and the previous one removed S bit. I think I was wrong, but please double-check this. I recall we had some odd cache issues on V7 back then.

Marek,

First and foremost if we git blame on the file:
arch/arm/include/asm/system.h

your commit:
8890c2fbe6ed4c5ca9a61f21e846a55f8f2c38fc

arm: Remove S bit from MMU section entry

It is removing S bit under
#elif defined(CONFIG_CPU_V7)

I am adding the missing XN bit under:
#ifdef CONFIG_ARMV7_LPAE

So we are dealing with different modes.

In a nutshell your patch removes S bit from MMU section entry for non-LPAE cases for ARMV7 and mine adds XN bit for LPAE cases.

Hope this clears out the confusion.

- Keerthy

Quoted 1 line

Marek Vasut

2016-10-30 12:00 UTC #7 lore raw

PATCH v2 2/2 arm: Set TTB XN bit in case DCACHE_OFF for LPAE mode

Quoted 60 lines · Keerthy

Quoted 34 lines · Marek Vasut
Quoted 33 lines · Tom Rini
Quoted 31 lines · Marek Vasut
Quoted 13 lines · Tom Rini
Quoted 11 lines · Keerthy
While we setup the mmu initially we mark set_section_dcache with DCACHE_OFF flag. In case of non-LPAE mode the DCACHE_OFF macro is rightly defined with TTB_SECT_XN_MASK set so as to mark all the 4GB XN. In case of LPAE mode XN(Execute-never) bit is not set with DCACHE_OFF. Hence XN bit is not set by default for DCACHE_OFF which keeps all the regions execute okay and this leads to random speculative
fetches in random memory regions which was eventually caught by kernel
omap-l3-noc driver.
Quoted 7 lines
Quoted 4 lines
Fix this to mark the regions as XN by default.
Signed-off-by Keerthy <[email protected]>
Reviewed-by Alexander Graf <[email protected]>
Reviewed-by Tom Rini <[email protected]>
Isn't this patch exactly undoing the following one ?
commit 8890c2fbe6ed4c5ca9a61f21e846a55f8f2c38fc
Author: Marek Vasut <>
Date:   Tue Dec 29 19:44:02 2015 +0100
arm: Remove S bit from MMU section entry
Restore the old behavior of the MMU section entries configuration, which is without the S-bit.
Quoted 6 lines
Quoted 2 lines
Is it? I guess perhaps you and Keerthy need to chat then as there's some other problem they're addressing.
Ummmm, wait a second, I think this one adds XN bit and the previous one removed S bit. I think I was wrong, but please double-check this. I recall we had some odd cache issues on V7 back then.
Marek,
First and foremost if we git blame on the file:
arch/arm/include/asm/system.h
your commit:
8890c2fbe6ed4c5ca9a61f21e846a55f8f2c38fc
arm: Remove S bit from MMU section entry
It is removing S bit under
#elif defined(CONFIG_CPU_V7)
I am adding the missing XN bit under:
#ifdef CONFIG_ARMV7_LPAE

Quoted 6 lines

So we are dealing with different modes.
In a nutshell your patch removes S bit from MMU section entry for non-LPAE cases for ARMV7 and mine adds XN bit for LPAE cases.
Hope this clears out the confusion.

Yeah, it does, thanks.

Signature · 2 lines

Best regards,
Marek Vasut

Keerthy

author

2016-11-07 04:07 UTC #8 lore raw

PATCH v2 2/2 arm: Set TTB XN bit in case DCACHE_OFF for LPAE mode

Quoted 61 lines · Marek Vasut

Quoted 60 lines · Keerthy
Quoted 34 lines · Marek Vasut
Quoted 33 lines · Tom Rini
Quoted 31 lines · Marek Vasut
Quoted 13 lines · Tom Rini
Quoted 11 lines · Keerthy
While we setup the mmu initially we mark set_section_dcache with DCACHE_OFF flag. In case of non-LPAE mode the DCACHE_OFF macro is rightly defined with TTB_SECT_XN_MASK set so as to mark all the 4GB XN. In case of LPAE mode XN(Execute-never) bit is not set with DCACHE_OFF. Hence XN bit is not set by default for DCACHE_OFF which keeps all the regions execute okay and this leads to random speculative
fetches in random memory regions which was eventually caught by kernel
omap-l3-noc driver.
Quoted 7 lines
Quoted 4 lines
Fix this to mark the regions as XN by default.
Signed-off-by Keerthy <[email protected]>
Reviewed-by Alexander Graf <[email protected]>
Reviewed-by Tom Rini <[email protected]>
Isn't this patch exactly undoing the following one ?
commit 8890c2fbe6ed4c5ca9a61f21e846a55f8f2c38fc
Author: Marek Vasut <>
Date:   Tue Dec 29 19:44:02 2015 +0100
arm: Remove S bit from MMU section entry
Restore the old behavior of the MMU section entries configuration, which is without the S-bit.
Quoted 6 lines
Quoted 2 lines
Is it? I guess perhaps you and Keerthy need to chat then as there's some other problem they're addressing.
Ummmm, wait a second, I think this one adds XN bit and the previous one removed S bit. I think I was wrong, but please double-check this. I recall we had some odd cache issues on V7 back then.
Marek,
First and foremost if we git blame on the file:
arch/arm/include/asm/system.h
your commit:
8890c2fbe6ed4c5ca9a61f21e846a55f8f2c38fc
arm: Remove S bit from MMU section entry
It is removing S bit under
#elif defined(CONFIG_CPU_V7)
I am adding the missing XN bit under:
#ifdef CONFIG_ARMV7_LPAE

Quoted 9 lines

Quoted 6 lines
So we are dealing with different modes.
In a nutshell your patch removes S bit from MMU section entry for non-LPAE cases for ARMV7 and mine adds XN bit for LPAE cases.
Hope this clears out the confusion.
Yeah, it does, thanks.

I hope this patch can be pulled if there are no further concerns.

Thanks,
Keerthy

Tom Rini

2016-11-13 20:56 UTC #9 lore raw

PATCH v2 2/2 arm: Set TTB XN bit in case DCACHE_OFF for LPAE mode

In reply to Keerthy

Quoted 9 lines · Keerthy

While we setup the mmu initially we mark set_section_dcache with DCACHE_OFF flag. In case of non-LPAE mode the DCACHE_OFF macro is rightly defined with TTB_SECT_XN_MASK set so as to mark all the 4GB XN. In case of LPAE mode XN(Execute-never) bit is not set with DCACHE_OFF. Hence XN bit is not set by default for DCACHE_OFF which keeps all the regions execute okay and this leads to random speculative fetches in random memory regions which was eventually caught by kernel omap-l3-noc driver.

Quoted 5 lines

Fix this to mark the regions as XN by default.
Signed-off-by Keerthy <[email protected]>
Reviewed-by Alexander Graf <[email protected]>
Reviewed-by Tom Rini <[email protected]>

Applied to u-boot/master, thanks!

Signature · 8 lines

Tom
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Tom Rini

2016-10-29 17:41 UTC #10 lore raw

PATCH v2 1/2 arm: print the cache config option in hex instead of decimal

In reply to Keerthy

Quoted 3 lines · Keerthy

Printing the option value in hex makes it more comprehensible.
Signed-off-by Keerthy <[email protected]>

Reviewed-by Tom Rini <[email protected]>

Signature · 8 lines

Tom
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Tom Rini

2016-11-13 20:56 UTC #11 lore raw

PATCH v2 1/2 arm: print the cache config option in hex instead of decimal

In reply to Keerthy

Quoted 4 lines · Keerthy

Printing the option value in hex makes it more comprehensible.
Signed-off-by Keerthy <[email protected]>
Reviewed-by Tom Rini <[email protected]>

Applied to u-boot/master, thanks!

Signature · 8 lines

Tom
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