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imx: add imx6ull support

PATCH Superseded Peter Chen 4 participants 13 messages Nov 1, 2016 – Nov 8, 2016

Subsystems (7)
Device tree bindings Arm (32-bit) Arm sub-architectures Arm i.MX and Layerscape +3 more subsystems

v1 of 3 Superseded Latest is v3 →

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Peter Chen

author
#0 lore raw

cover imx: add imx6ull support

Hi Shawn,

In this series, it adds support for imx6ull SoC which is a derived SoC from imx6ul, and imx6ull is pin-to-pin compatible with imx6ul, the basic functions are tested at imx6ull evk.

Bai Ping (1):
clk: imx: clk-imx6ul: add clk support for imx6ull

Peter Chen (2):
ARM: imx6u: add imx6ull support
ARM: imx: mach-imx6ul: add imx6ull support

 arch/arm/boot/dts/Makefile               |   3 +-
 arch/arm/boot/dts/imx6u-14x14-evk.dts    | 475 ++++++++++++++++
 arch/arm/boot/dts/imx6u-14x14-evk.dtsi   | 487 ++++++++++++++++
 arch/arm/boot/dts/imx6u.dtsi             | 942 +++++++++++++++++++++++++++++++
 arch/arm/boot/dts/imx6ul-14x14-evk.dts   | 479 +---------------
 arch/arm/boot/dts/imx6ul.dtsi            | 936 +-----------------------------
 arch/arm/boot/dts/imx6ull-14x14-evk.dts  |  17 +
 arch/arm/boot/dts/imx6ull-pinfunc.h      |  57 ++
 arch/arm/boot/dts/imx6ull.dtsi           |  10 +
 arch/arm/mach-imx/mach-imx6ul.c          |   3 +-
 drivers/clk/imx/clk-imx6ul.c             |  74 ++-
 include/dt-bindings/clock/imx6ul-clock.h |  15 +-
 12 files changed, 2072 insertions(+), 1426 deletions(-)
 create mode 100644 arch/arm/boot/dts/imx6u-14x14-evk.dts
 create mode 100644 arch/arm/boot/dts/imx6u-14x14-evk.dtsi
 create mode 100644 arch/arm/boot/dts/imx6u.dtsi
 create mode 100644 arch/arm/boot/dts/imx6ull-14x14-evk.dts
 create mode 100644 arch/arm/boot/dts/imx6ull-pinfunc.h
 create mode 100644 arch/arm/boot/dts/imx6ull.dtsi
Signature · 1 line
2.7.4
author
#1 lore raw

PATCH 1/3 ARM: imx6u: add imx6ull support

It is the 10th processor in the well-known imx6 series, and derived from imx6ul but cost optimized. The more information about imx6ull can be found at:

http://www.nxp.com/products/microcontrollers-and-processors/
arm-processors/i.mx-applications-processors/i.mx-6-processors /i.mx6qp/i.mx-6ull-single-core-processor-with-arm-cortex-a7-core :i.MX6ULL

In this patch, it moves common dts between imx6ul* and imx6ull* as new files named imx6u*, and the specific part for imx6ul and imx6ull are individual file.

Signed-off-by Peter Chen <[email protected]>
---
 arch/arm/boot/dts/Makefile              |   3 +-
 arch/arm/boot/dts/imx6u-14x14-evk.dts   | 475 ++++++++++++++++
 arch/arm/boot/dts/imx6u-14x14-evk.dtsi  | 487 +++++++++++++++++
 arch/arm/boot/dts/imx6u.dtsi            | 942 ++++++++++++++++++++++++++++++++
 arch/arm/boot/dts/imx6ul-14x14-evk.dts  | 479 +---------------
 arch/arm/boot/dts/imx6ul.dtsi           | 936 +------------------------------
 arch/arm/boot/dts/imx6ull-14x14-evk.dts |  17 +
 arch/arm/boot/dts/imx6ull-pinfunc.h     |  57 ++
 arch/arm/boot/dts/imx6ull.dtsi          |  10 +
 9 files changed, 1993 insertions(+), 1413 deletions(-)
 create mode 100644 arch/arm/boot/dts/imx6u-14x14-evk.dts
 create mode 100644 arch/arm/boot/dts/imx6u-14x14-evk.dtsi
 create mode 100644 arch/arm/boot/dts/imx6u.dtsi
 create mode 100644 arch/arm/boot/dts/imx6ull-14x14-evk.dts
 create mode 100644 arch/arm/boot/dts/imx6ull-pinfunc.h
 create mode 100644 arch/arm/boot/dts/imx6ull.dtsi
arch/arm/boot/dts/Makefile +2 -1
index befcd26..3d6e199 100644
@@ -423,7 +423,8 @@ dtb-$(CONFIG_SOC_IMX6UL) += \
 	imx6ul-pico-hobbit.dtb \
 	imx6ul-tx6ul-0010.dtb \
 	imx6ul-tx6ul-0011.dtb \
-	imx6ul-tx6ul-mainboard.dtb
+	imx6ul-tx6ul-mainboard.dtb \
+	imx6ull-14x14-evk.dtb
 dtb-$(CONFIG_SOC_IMX7D) += \
 	imx7d-cl-som-imx7.dtb \
 	imx7d-colibri-eval-v3.dtb \
arch/arm/boot/dts/imx6u-14x14-evk.dts new file +475 -0

475 lines not on this page · raw message

arch/arm/boot/dts/imx6u-14x14-evk.dtsi new file +487 -0

487 lines not on this page · raw message

arch/arm/boot/dts/imx6u.dtsi new file +942 -0

942 lines not on this page · raw message

arch/arm/boot/dts/imx6ul-14x14-evk.dts +1 -478

487 lines not on this page · raw message

arch/arm/boot/dts/imx6ul.dtsi +2 -934

600 lines not on this page · raw message

arch/arm/boot/dts/imx6ull-14x14-evk.dts new file +17 -0
new file mode 100644
index 0000000..64c38bc

Lines of this file are not shown. View the raw message.

arch/arm/boot/dts/imx6ull-pinfunc.h new file +57 -0

57 lines not on this page · raw message

arch/arm/boot/dts/imx6ull.dtsi new file +10 -0
new file mode 100644
index 0000000..afd9796

Lines of this file are not shown. View the raw message.

The rest of this diff is not shown. View the raw message.

Signature · 1 line
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#2 lore raw

PATCH 1/3 ARM: imx6u: add imx6ull support

Quoted 4 lines · Peter Chen

It is the 10th processor in the well-known imx6 series, and derived from imx6ul but cost optimized. The more information about imx6ull can be found at:

Quoted 8 lines

http://www.nxp.com/products/microcontrollers-and-processors/
arm-processors/i.mx-applications-processors/i.mx-6-processors /i.mx6qp/i.mx-6ull-single-core-processor-with-arm-cortex-a7-core :i.MX6ULL

In this patch, it moves common dts between imx6ul* and imx6ull* as new files named imx6u*, and the specific part for imx6ul and imx6ull are individual file.

No. That only helps churn the tree and git history. Please keep using imx6ul.dtsi and simply have it be included by imx6ull.dtsi.

Quoted 40 lines
Signed-off-by Peter Chen <[email protected]>
---
 arch/arm/boot/dts/Makefile              |   3 +-
 arch/arm/boot/dts/imx6u-14x14-evk.dts   | 475 ++++++++++++++++
 arch/arm/boot/dts/imx6u-14x14-evk.dtsi  | 487 +++++++++++++++++
 arch/arm/boot/dts/imx6u.dtsi            | 942 ++++++++++++++++++++++++++++++++
 arch/arm/boot/dts/imx6ul-14x14-evk.dts  | 479 +---------------
 arch/arm/boot/dts/imx6ul.dtsi           | 936 +------------------------------
 arch/arm/boot/dts/imx6ull-14x14-evk.dts |  17 +
 arch/arm/boot/dts/imx6ull-pinfunc.h     |  57 ++
 arch/arm/boot/dts/imx6ull.dtsi          |  10 +
 9 files changed, 1993 insertions(+), 1413 deletions(-)
 create mode 100644 arch/arm/boot/dts/imx6u-14x14-evk.dts
 create mode 100644 arch/arm/boot/dts/imx6u-14x14-evk.dtsi
 create mode 100644 arch/arm/boot/dts/imx6u.dtsi
 create mode 100644 arch/arm/boot/dts/imx6ull-14x14-evk.dts
 create mode 100644 arch/arm/boot/dts/imx6ull-pinfunc.h
 create mode 100644 arch/arm/boot/dts/imx6ull.dtsi
arch/arm/boot/dts/Makefile +2 -1
index befcd26..3d6e199 100644
@@ -423,7 +423,8 @@ dtb-$(CONFIG_SOC_IMX6UL) += \
 	imx6ul-pico-hobbit.dtb \
 	imx6ul-tx6ul-0010.dtb \
 	imx6ul-tx6ul-0011.dtb \
-	imx6ul-tx6ul-mainboard.dtb
+	imx6ul-tx6ul-mainboard.dtb \
+	imx6ull-14x14-evk.dtb
 dtb-$(CONFIG_SOC_IMX7D) += \
 	imx7d-cl-som-imx7.dtb \
 	imx7d-colibri-eval-v3.dtb \
arch/arm/boot/dts/imx6u-14x14-evk.dts new file +0 -0
new file mode 100644
index 0000000..ba8614c

arch/arm/boot/dts/imx6u-14x14-evk.dts line 7

Quoted 7 lines
arch/arm/boot/dts/imx6u-14x14-evk.dts new file +7 -0
@@ -0,0 +1,475 @@
+/*
+ * Copyright (C) 2015 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */

For new DT files, please consider to use GPL/X11 dual license. You should be able to find a lot of examples in arch/arm/boot/dts.

<snip>

Quoted 13 lines
arch/arm/boot/dts/imx6ull-pinfunc.h new file +7 -0
new file mode 100644
index 0000000..fca0036
@@ -0,0 +1,57 @@
+/*
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */

arch/arm/boot/dts/imx6ull-pinfunc.h line 17

Quoted 10 lines
arch/arm/boot/dts/imx6ull-pinfunc.h new file +10 -0
+
+#ifndef __DTS_IMX6ULL_PINFUNC_H
+#define __DTS_IMX6ULL_PINFUNC_H
+
+#include "imx6ul-pinfunc.h"
+/*
+ * The pin function ID is a tuple of
+ * <mux_reg conf_reg input_reg mux_mode input_val>
+ */
+#define MX6UL_PAD_ENET2_RX_DATA0__EPDC_SDDO08                    0x00E4 0x0370 0x0000 0x9 0x0

Can we name these imx6ull specific defines MX6ULL_xxx, so that we know they should only be used in imx6ull specific dts?

Quoted 16 lines
arch/arm/boot/dts/imx6ull-pinfunc.h new file +16 -0
+#define MX6UL_PAD_ENET2_RX_DATA1__EPDC_SDDO09                    0x00E8 0x0374 0x0000 0x9 0x0
+#define MX6UL_PAD_ENET2_RX_EN__EPDC_SDDO10                       0x00EC 0x0378 0x0000 0x9 0x0
+#define MX6UL_PAD_ENET2_TX_DATA0__EPDC_SDDO11                    0x00F0 0x037C 0x0000 0x9 0x0
+#define MX6UL_PAD_ENET2_TX_DATA1__EPDC_SDDO12                    0x00F4 0x0380 0x0000 0x9 0x0
+#define MX6UL_PAD_ENET2_TX_EN__EPDC_SDDO13                       0x00F8 0x0384 0x0000 0x9 0x0
+#define MX6UL_PAD_ENET2_TX_CLK__EPDC_SDDO14                      0x00FC 0x0388 0x0000 0x9 0x0
+#define MX6UL_PAD_ENET2_RX_ER__EPDC_SDDO15                       0x0100 0x038C 0x0000 0x9 0x0
+#define MX6UL_PAD_LCD_CLK__EPDC_SDCLK                            0x0104 0x0390 0x0000 0x9 0x0
+#define MX6UL_PAD_LCD_ENABLE__EPDC_SDLE                          0x0108 0x0394 0x0000 0x9 0x0
+#define MX6UL_PAD_LCD_HSYNC__EPDC_SDOE                           0x010C 0x0398 0x0000 0x9 0x0
+#define MX6UL_PAD_LCD_VSYNC__EPDC_SDCE0                          0x0110 0x039C 0x0000 0x9 0x0
+#define MX6UL_PAD_LCD_RESET__EPDC_GDOE                           0x0114 0x03A0 0x0000 0x9 0x0
+#define MX6UL_PAD_LCD_DATA00__EPDC_SDDO00                        0x0118 0x03A4 0x0000 0x9 0x0
+#define MX6UL_PAD_LCD_DATA01__EPDC_SDDO01                        0x011C 0x03A8 0x0000 0x9 0x0
+#define MX6UL_PAD_LCD_DATA02__EPDC_SDDO02                        0x0120 0x03AC 0x0000 0x9 0x0
+#define MX6UL_PAD_LCD_DATA03__EPDC_SDDO03                        0x0124 0x03B0 0x0000 0x9 0x0

arch/arm/boot/dts/imx6ull-pinfunc.h line 43

Quoted 10 lines
arch/arm/boot/dts/imx6ull-pinfunc.h new file +10 -0
+#define MX6UL_PAD_LCD_DATA04__EPDC_SDDO04                        0x0128 0x03B4 0x0000 0x9 0x0
+#define MX6UL_PAD_LCD_DATA05__EPDC_SDDO05                        0x012C 0x03B8 0x0000 0x9 0x0
+#define MX6UL_PAD_LCD_DATA06__EPDC_SDDO06                        0x0130 0x03BC 0x0000 0x9 0x0
+#define MX6UL_PAD_LCD_DATA07__EPDC_SDDO07                        0x0134 0x03C0 0x0000 0x9 0x0
+#define MX6UL_PAD_LCD_DATA14__EPDC_SDSHR                         0x0150 0x03DC 0x0000 0x9 0x0
+#define MX6UL_PAD_LCD_DATA15__EPDC_GDRL                          0x0154 0x03E0 0x0000 0x9 0x0
+#define MX6UL_PAD_LCD_DATA16__EPDC_GDCLK                         0x0158 0x03E4 0x0000 0x9 0x0
+#define MX6UL_PAD_LCD_DATA17__EPDC_GDSP                          0x015C 0x03E8 0x0000 0x9 0x0
+#define MX6UL_PAD_LCD_DATA21__EPDC_SDCE1                         0x016C 0x03F8 0x0000 0x9 0x0
+

Why this new line?

Shawn

Quoted 38 lines
arch/arm/boot/dts/imx6ull-pinfunc.h new file +14 -0
+#define MX6UL_PAD_CSI_MCLK__ESAI_TX3_RX2                          0x01D4 0x0460 0x0000 0x9 0x0
+#define MX6UL_PAD_CSI_PIXCLK__ESAI_TX2_RX3                        0x01D8 0x0464 0x0000 0x9 0x0
+#define MX6UL_PAD_CSI_VSYNC__ESAI_TX4_RX1                         0x01DC 0x0468 0x0000 0x9 0x0
+#define MX6UL_PAD_CSI_HSYNC__ESAI_TX1                             0x01E0 0x046C 0x0000 0x9 0x0
+#define MX6UL_PAD_CSI_DATA00__ESAI_TX_HF_CLK                      0x01E4 0x0470 0x0000 0x9 0x0
+#define MX6UL_PAD_CSI_DATA01__ESAI_RX_HF_CLK                      0x01E8 0x0474 0x0000 0x9 0x0
+#define MX6UL_PAD_CSI_DATA02__ESAI_RX_FS                          0x01EC 0x0478 0x0000 0x9 0x0
+#define MX6UL_PAD_CSI_DATA03__ESAI_RX_CLK                         0x01F0 0x047C 0x0000 0x9 0x0
+#define MX6UL_PAD_CSI_DATA04__ESAI_TX_FS                          0x01F4 0x0480 0x0000 0x9 0x0
+#define MX6UL_PAD_CSI_DATA05__ESAI_TX_CLK                         0x01F8 0x0484 0x0000 0x9 0x0
+#define MX6UL_PAD_CSI_DATA06__ESAI_TX5_RX0                        0x01FC 0x0488 0x0000 0x9 0x0
+#define MX6UL_PAD_CSI_DATA07__ESAI_T0                             0x0200 0x048C 0x0000 0x9 0x0
+
+#endif /* __DTS_IMX6ULL_PINFUNC_H */
arch/arm/boot/dts/imx6ull.dtsi new file +10 -0
new file mode 100644
index 0000000..afd9796
@@ -0,0 +1,10 @@
+/*
+ * Copyright 2016 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include "imx6u.dtsi"
+#include "imx6ull-pinfunc.h"
Signature · 7 lines
2.7.4


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author
#3 lore raw

PATCH 1/3 ARM: imx6u: add imx6ull support

Thanks, Shawn. All comments will be adopted in v2.

Peter

Quoted 149 lines
Quoted 4 lines

In this patch, it moves common dts between imx6ul* and imx6ull* as new files named imx6u*, and the specific part for imx6ul and imx6ull are individual file.

No. That only helps churn the tree and git history. Please keep using imx6ul.dtsi and simply have it be included by imx6ull.dtsi.

Quoted 7 lines
Signed-off-by Peter Chen <[email protected]>
---
 arch/arm/boot/dts/Makefile              |   3 +-
 arch/arm/boot/dts/imx6u-14x14-evk.dts   | 475 ++++++++++++++++
 arch/arm/boot/dts/imx6u-14x14-evk.dtsi  | 487 +++++++++++++++++
 arch/arm/boot/dts/imx6u.dtsi            | 942

++++++++++++++++++++++++++++++++

Quoted 34 lines
 arch/arm/boot/dts/imx6ul-14x14-evk.dts  | 479 +---------------
 arch/arm/boot/dts/imx6ul.dtsi           | 936 +------------------------------
 arch/arm/boot/dts/imx6ull-14x14-evk.dts |  17 +
 arch/arm/boot/dts/imx6ull-pinfunc.h     |  57 ++
 arch/arm/boot/dts/imx6ull.dtsi          |  10 +
 9 files changed, 1993 insertions(+), 1413 deletions(-)  create mode
100644 arch/arm/boot/dts/imx6u-14x14-evk.dts
 create mode 100644 arch/arm/boot/dts/imx6u-14x14-evk.dtsi
 create mode 100644 arch/arm/boot/dts/imx6u.dtsi  create mode 100644
arch/arm/boot/dts/imx6ull-14x14-evk.dts
 create mode 100644 arch/arm/boot/dts/imx6ull-pinfunc.h
 create mode 100644 arch/arm/boot/dts/imx6ull.dtsi
arch/arm/boot/dts/Makefile +2 -1
index befcd26..3d6e199 100644
@@ -423,7 +423,8 @@ dtb-$(CONFIG_SOC_IMX6UL) += \
 	imx6ul-pico-hobbit.dtb \
 	imx6ul-tx6ul-0010.dtb \
 	imx6ul-tx6ul-0011.dtb \
-	imx6ul-tx6ul-mainboard.dtb
+	imx6ul-tx6ul-mainboard.dtb \
+	imx6ull-14x14-evk.dtb
 dtb-$(CONFIG_SOC_IMX7D) += \
 	imx7d-cl-som-imx7.dtb \
 	imx7d-colibri-eval-v3.dtb \
arch/arm/boot/dts/imx6u-14x14-evk.dts new file +0 -0
new file mode 100644
index 0000000..ba8614c

arch/arm/boot/dts/imx6u-14x14-evk.dts line 8

Quoted 8 lines
arch/arm/boot/dts/imx6u-14x14-evk.dts new file +8 -0
@@ -0,0 +1,475 @@
+/*
+ * Copyright (C) 2015 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */

For new DT files, please consider to use GPL/X11 dual license. You should be able to find a lot of examples in arch/arm/boot/dts.

<snip>

Quoted 14 lines
arch/arm/boot/dts/imx6ull-pinfunc.h new file +7 -0
new file mode 100644
index 0000000..fca0036
@@ -0,0 +1,57 @@
+/*
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.

arch/arm/boot/dts/imx6ull-pinfunc.h line 17

Quoted 10 lines
arch/arm/boot/dts/imx6ull-pinfunc.h new file +10 -0
+ */
+
+#ifndef __DTS_IMX6ULL_PINFUNC_H
+#define __DTS_IMX6ULL_PINFUNC_H
+
+#include "imx6ul-pinfunc.h"
+/*
+ * The pin function ID is a tuple of
+ * <mux_reg conf_reg input_reg mux_mode input_val>  */
+#define MX6UL_PAD_ENET2_RX_DATA0__EPDC_SDDO08

0x00E4 0x0370 0x0000 0x9 0x0

Can we name these imx6ull specific defines MX6ULL_xxx, so that we know they should only be used in imx6ull specific dts?

arch/arm/boot/dts/imx6ull-pinfunc.h line 18

Quoted 1 line
arch/arm/boot/dts/imx6ull-pinfunc.h new file +1 -0
+#define MX6UL_PAD_ENET2_RX_DATA1__EPDC_SDDO09

0x00E8 0x0374 0x0000 0x9 0x0

arch/arm/boot/dts/imx6ull-pinfunc.h line 19

Quoted 1 line
arch/arm/boot/dts/imx6ull-pinfunc.h new file +1 -0
+#define MX6UL_PAD_ENET2_RX_EN__EPDC_SDDO10                       0x00EC

0x0378 0x0000 0x9 0x0

arch/arm/boot/dts/imx6ull-pinfunc.h line 20

Quoted 1 line
arch/arm/boot/dts/imx6ull-pinfunc.h new file +1 -0
+#define MX6UL_PAD_ENET2_TX_DATA0__EPDC_SDDO11

0x00F0 0x037C 0x0000 0x9 0x0

arch/arm/boot/dts/imx6ull-pinfunc.h line 21

Quoted 1 line
arch/arm/boot/dts/imx6ull-pinfunc.h new file +1 -0
+#define MX6UL_PAD_ENET2_TX_DATA1__EPDC_SDDO12

0x00F4 0x0380 0x0000 0x9 0x0

arch/arm/boot/dts/imx6ull-pinfunc.h line 22

Quoted 1 line
arch/arm/boot/dts/imx6ull-pinfunc.h new file +1 -0
+#define MX6UL_PAD_ENET2_TX_EN__EPDC_SDDO13                       0x00F8

0x0384 0x0000 0x9 0x0

arch/arm/boot/dts/imx6ull-pinfunc.h line 23

Quoted 1 line
arch/arm/boot/dts/imx6ull-pinfunc.h new file +1 -0
+#define MX6UL_PAD_ENET2_TX_CLK__EPDC_SDDO14                      0x00FC

0x0388 0x0000 0x9 0x0

arch/arm/boot/dts/imx6ull-pinfunc.h line 24

Quoted 1 line
arch/arm/boot/dts/imx6ull-pinfunc.h new file +1 -0
+#define MX6UL_PAD_ENET2_RX_ER__EPDC_SDDO15                       0x0100

0x038C 0x0000 0x9 0x0

arch/arm/boot/dts/imx6ull-pinfunc.h line 25

Quoted 1 line
arch/arm/boot/dts/imx6ull-pinfunc.h new file +1 -0
+#define MX6UL_PAD_LCD_CLK__EPDC_SDCLK                            0x0104

0x0390 0x0000 0x9 0x0

arch/arm/boot/dts/imx6ull-pinfunc.h line 26

Quoted 1 line
arch/arm/boot/dts/imx6ull-pinfunc.h new file +1 -0
+#define MX6UL_PAD_LCD_ENABLE__EPDC_SDLE                          0x0108

0x0394 0x0000 0x9 0x0

arch/arm/boot/dts/imx6ull-pinfunc.h line 27

Quoted 1 line
arch/arm/boot/dts/imx6ull-pinfunc.h new file +1 -0
+#define MX6UL_PAD_LCD_HSYNC__EPDC_SDOE                           0x010C

0x0398 0x0000 0x9 0x0

arch/arm/boot/dts/imx6ull-pinfunc.h line 28

Quoted 1 line
arch/arm/boot/dts/imx6ull-pinfunc.h new file +1 -0
+#define MX6UL_PAD_LCD_VSYNC__EPDC_SDCE0                          0x0110

0x039C 0x0000 0x9 0x0

arch/arm/boot/dts/imx6ull-pinfunc.h line 29

Quoted 1 line
arch/arm/boot/dts/imx6ull-pinfunc.h new file +1 -0
+#define MX6UL_PAD_LCD_RESET__EPDC_GDOE                           0x0114

0x03A0 0x0000 0x9 0x0

arch/arm/boot/dts/imx6ull-pinfunc.h line 30

Quoted 1 line
arch/arm/boot/dts/imx6ull-pinfunc.h new file +1 -0
+#define MX6UL_PAD_LCD_DATA00__EPDC_SDDO00                        0x0118

0x03A4 0x0000 0x9 0x0

arch/arm/boot/dts/imx6ull-pinfunc.h line 31

Quoted 1 line
arch/arm/boot/dts/imx6ull-pinfunc.h new file +1 -0
+#define MX6UL_PAD_LCD_DATA01__EPDC_SDDO01                        0x011C

0x03A8 0x0000 0x9 0x0

arch/arm/boot/dts/imx6ull-pinfunc.h line 32

Quoted 1 line
arch/arm/boot/dts/imx6ull-pinfunc.h new file +1 -0
+#define MX6UL_PAD_LCD_DATA02__EPDC_SDDO02                        0x0120

0x03AC 0x0000 0x9 0x0

arch/arm/boot/dts/imx6ull-pinfunc.h line 33

Quoted 1 line
arch/arm/boot/dts/imx6ull-pinfunc.h new file +1 -0
+#define MX6UL_PAD_LCD_DATA03__EPDC_SDDO03                        0x0124

0x03B0 0x0000 0x9 0x0

arch/arm/boot/dts/imx6ull-pinfunc.h line 34

Quoted 1 line
arch/arm/boot/dts/imx6ull-pinfunc.h new file +1 -0
+#define MX6UL_PAD_LCD_DATA04__EPDC_SDDO04                        0x0128

0x03B4 0x0000 0x9 0x0

arch/arm/boot/dts/imx6ull-pinfunc.h line 35

Quoted 1 line
arch/arm/boot/dts/imx6ull-pinfunc.h new file +1 -0
+#define MX6UL_PAD_LCD_DATA05__EPDC_SDDO05                        0x012C

0x03B8 0x0000 0x9 0x0

arch/arm/boot/dts/imx6ull-pinfunc.h line 36

Quoted 1 line
arch/arm/boot/dts/imx6ull-pinfunc.h new file +1 -0
+#define MX6UL_PAD_LCD_DATA06__EPDC_SDDO06                        0x0130

0x03BC 0x0000 0x9 0x0

arch/arm/boot/dts/imx6ull-pinfunc.h line 37

Quoted 1 line
arch/arm/boot/dts/imx6ull-pinfunc.h new file +1 -0
+#define MX6UL_PAD_LCD_DATA07__EPDC_SDDO07                        0x0134

0x03C0 0x0000 0x9 0x0

arch/arm/boot/dts/imx6ull-pinfunc.h line 38

Quoted 1 line
arch/arm/boot/dts/imx6ull-pinfunc.h new file +1 -0
+#define MX6UL_PAD_LCD_DATA14__EPDC_SDSHR                         0x0150

0x03DC 0x0000 0x9 0x0

arch/arm/boot/dts/imx6ull-pinfunc.h line 39

Quoted 1 line
arch/arm/boot/dts/imx6ull-pinfunc.h new file +1 -0
+#define MX6UL_PAD_LCD_DATA15__EPDC_GDRL                          0x0154

0x03E0 0x0000 0x9 0x0

arch/arm/boot/dts/imx6ull-pinfunc.h line 40

Quoted 1 line
arch/arm/boot/dts/imx6ull-pinfunc.h new file +1 -0
+#define MX6UL_PAD_LCD_DATA16__EPDC_GDCLK                         0x0158

0x03E4 0x0000 0x9 0x0

arch/arm/boot/dts/imx6ull-pinfunc.h line 41

Quoted 1 line
arch/arm/boot/dts/imx6ull-pinfunc.h new file +1 -0
+#define MX6UL_PAD_LCD_DATA17__EPDC_GDSP                          0x015C

0x03E8 0x0000 0x9 0x0

arch/arm/boot/dts/imx6ull-pinfunc.h line 42

Quoted 1 line
arch/arm/boot/dts/imx6ull-pinfunc.h new file +1 -0
+#define MX6UL_PAD_LCD_DATA21__EPDC_SDCE1                         0x016C

0x03F8 0x0000 0x9 0x0

arch/arm/boot/dts/imx6ull-pinfunc.h line 43

Quoted 1 line
arch/arm/boot/dts/imx6ull-pinfunc.h new file +1 -0
+

Why this new line?

Shawn

author
#4 lore raw

PATCH 2/3 ARM: imx: mach-imx6ul: add imx6ull support

In reply to Peter Chen

imx6ull is derived SoC from imx6ul.

Signed-off-by Peter Chen <[email protected]>
---
 arch/arm/mach-imx/mach-imx6ul.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)
arch/arm/mach-imx/mach-imx6ul.c +2 -1
index 58a2b88..0b24630 100644
@@ -89,10 +89,11 @@ static void __init imx6ul_init_late(void)
 
 static const char * const imx6ul_dt_compat[] __initconst = {
 	"fsl,imx6ul",
+	"fsl,imx6ull",
 	NULL,
 };
 
-DT_MACHINE_START(IMX6UL, "Freescale i.MX6 Ultralite (Device Tree)")
+DT_MACHINE_START(IMX6UL, "Freescale i.MX6 UltraLite (Device Tree)")
 	.init_irq	= imx6ul_init_irq,
 	.init_machine	= imx6ul_init_machine,
 	.init_late	= imx6ul_init_late,
Signature · 1 line
2.7.4
reviewer
#5 lore raw

PATCH 2/3 ARM: imx: mach-imx6ul: add imx6ull support

Quoted 12 lines · Peter Chen

imx6ull is derived SoC from imx6ul.

Signed-off-by Peter Chen <[email protected]>
---
 arch/arm/mach-imx/mach-imx6ul.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)
arch/arm/mach-imx/mach-imx6ul.c +0 -0
index 58a2b88..0b24630 100644

arch/arm/mach-imx/mach-imx6ul.c static void __init imx6ul_init_late(void) · line 96

Quoted 9 lines
arch/arm/mach-imx/mach-imx6ul.c +2 -1
@@ -89,10 +89,11 @@ static void __init imx6ul_init_late(void)
 
 static const char * const imx6ul_dt_compat[] __initconst = {
        "fsl,imx6ul",
+       "fsl,imx6ull",
        NULL,
 };
 
-DT_MACHINE_START(IMX6UL, "Freescale i.MX6 Ultralite (Device Tree)")
+DT_MACHINE_START(IMX6UL, "Freescale i.MX6 UltraLite (Device Tree)")

Is this change really needed?

author
#6 lore raw

PATCH 2/3 ARM: imx: mach-imx6ul: add imx6ull support

Quoted 22 lines · Peter Chen
Quoted 19 lines

imx6ull is derived SoC from imx6ul.

Signed-off-by Peter Chen <[email protected]>
---
 arch/arm/mach-imx/mach-imx6ul.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)
(quoted diff) +0 -0

b/arch/arm/mach-imx/mach-imx6ul.c index 58a2b88..0b24630 100644

arch/arm/mach-imx/mach-imx6ul.c +1 -0
@@ -89,10 +89,11 @@ static void __init imx6ul_init_late(void)
 
 static const char * const imx6ul_dt_compat[] __initconst = {
        "fsl,imx6ul",
+       "fsl,imx6ull",
        NULL,
 };
Quoted 4 lines

arch/arm/mach-imx/mach-imx6ul.c static void __init imx6ul_init_late(void) · line 96

Quoted 2 lines
arch/arm/mach-imx/mach-imx6ul.c +1 -1
-DT_MACHINE_START(IMX6UL, "Freescale i.MX6 Ultralite (Device Tree)")
+DT_MACHINE_START(IMX6UL, "Freescale i.MX6 UltraLite (Device Tree)")

Is this change really needed?

This change does not be related with imx6ull support, but also a needed change since the formal name is capital letter "L", if you are concerned with that, I can delete this change.

Peter

reviewer
#7 lore raw

PATCH 2/3 ARM: imx: mach-imx6ul: add imx6ull support

Quoted 3 lines · Peter Chen

This change does not be related with imx6ull support, but also a needed change since the formal name is capital letter "L", if you are concerned with that, I can delete this change.

Just make it as a separate patch then. Thanks

author
#8 lore raw

PATCH 3/3 clk: imx: clk-imx6ul: add clk support for imx6ull

In reply to Peter Chen

From: Bai Ping <[email protected]>

imx6ull is the derived SoC from imx6ul

Cc Michael Turquette <[email protected]>
Cc Stephen Boyd <[email protected]>
Signed-off-by Peng Fan <[email protected]>
Signed-off-by Bai Ping <[email protected]>
Signed-off-by Peter Chen <[email protected]>
---
 drivers/clk/imx/clk-imx6ul.c             | 74 +++++++++++++++++++++++++++-----
 include/dt-bindings/clock/imx6ul-clock.h | 15 ++++++-
 2 files changed, 77 insertions(+), 12 deletions(-)
drivers/clk/imx/clk-imx6ul.c +63 -11
index d1d7787..ceb99a7 100644
@@ -64,6 +64,11 @@ static const char *perclk_sels[] = { "ipg", "osc", };
 static const char *lcdif_sels[] = { "lcdif_podf", "ipp_di0", "ipp_di1", "ldb_di0", "ldb_di1", };
 static const char *csi_sels[] = { "osc", "pll2_pfd2_396m", "pll3_120m", "pll3_pfd1_540m", };
 static const char *sim_sels[] = { "sim_podf", "ipp_di0", "ipp_di1", "ldb_di0", "ldb_di1", };
+/* epdc_pre_sels, epdc_sels, esai_sels only exists on i.MX6ULL */
+static const char *epdc_pre_sels[] = { "pll2_bus", "pll3_usb_otg", "pll5_video_div", "pll2_pfd0_352m", "pll2_pfd2_396m", "pll3_pfd2_508m", };
+static const char *esai_sels[] = { "pll4_audio_div", "pll3_pfd2_508m", "pll5_video_div", "pll3_usb_otg", };
+static const char *epdc_sels[] = { "epdc_podf", "ipp_di0", "ipp_di1", "ldb_di0", "ldb_di1", };
+
 
 static struct clk *clks[IMX6UL_CLK_END];
 static struct clk_onecell_data clk_data;

@@ -102,6 +107,17 @@ static u32 share_count_audio;
 static u32 share_count_sai1;
 static u32 share_count_sai2;
 static u32 share_count_sai3;
+static u32 share_count_esai;
+
+static inline int clk_on_imx6ul(void)
+{
+	return of_machine_is_compatible("fsl,imx6ul");
+}
+
+static inline int clk_on_imx6ull(void)
+{
+	return of_machine_is_compatible("fsl,imx6ull");
+}
 
 static void __init imx6ul_clocks_init(struct device_node *ccm_node)
 {

@@ -238,12 +254,19 @@ static void __init imx6ul_clocks_init(struct device_node *ccm_node)
 	clks[IMX6UL_CLK_QSPI1_SEL]	  = imx_clk_mux("qspi1_sel",    base + 0x1c, 7,  3, qspi1_sels, ARRAY_SIZE(qspi1_sels));
 	clks[IMX6UL_CLK_PERCLK_SEL]	  = imx_clk_mux("perclk_sel",	base + 0x1c, 6,  1, perclk_sels, ARRAY_SIZE(perclk_sels));
 	clks[IMX6UL_CLK_CAN_SEL]	  = imx_clk_mux("can_sel",	base + 0x20, 8,  2, can_sels, ARRAY_SIZE(can_sels));
+	if (clk_on_imx6ull())
+		clks[IMX6UL_CLK_ESAI_SEL]	  = imx_clk_mux("esai_sel",	base + 0x20, 19, 2, esai_sels, ARRAY_SIZE(esai_sels));
 	clks[IMX6UL_CLK_UART_SEL]	  = imx_clk_mux("uart_sel",	base + 0x24, 6,  1, uart_sels, ARRAY_SIZE(uart_sels));
 	clks[IMX6UL_CLK_ENFC_SEL]	  = imx_clk_mux("enfc_sel",	base + 0x2c, 15, 3, enfc_sels, ARRAY_SIZE(enfc_sels));
 	clks[IMX6UL_CLK_LDB_DI0_SEL]	  = imx_clk_mux("ldb_di0_sel",	base + 0x2c, 9,  3, ldb_di0_sels, ARRAY_SIZE(ldb_di0_sels));
 	clks[IMX6UL_CLK_SPDIF_SEL]	  = imx_clk_mux("spdif_sel",	base + 0x30, 20, 2, spdif_sels, ARRAY_SIZE(spdif_sels));
-	clks[IMX6UL_CLK_SIM_PRE_SEL]	  = imx_clk_mux("sim_pre_sel",	base + 0x34, 15, 3, sim_pre_sels, ARRAY_SIZE(sim_pre_sels));
-	clks[IMX6UL_CLK_SIM_SEL]	  = imx_clk_mux("sim_sel",	base + 0x34, 9, 3, sim_sels, ARRAY_SIZE(sim_sels));
+	if (clk_on_imx6ul()) {
+		clks[IMX6UL_CLK_SIM_PRE_SEL] 	  = imx_clk_mux("sim_pre_sel",	base + 0x34, 15, 3, sim_pre_sels, ARRAY_SIZE(sim_pre_sels));
+		clks[IMX6UL_CLK_SIM_SEL]	  = imx_clk_mux("sim_sel", 	base + 0x34, 9, 3, sim_sels, ARRAY_SIZE(sim_sels));
+	} else if (clk_on_imx6ull()) {
+		clks[IMX6UL_CLK_EPDC_PRE_SEL]	  = imx_clk_mux("epdc_pre_sel",	base + 0x34, 15, 3, epdc_pre_sels, ARRAY_SIZE(epdc_pre_sels));
+		clks[IMX6UL_CLK_EPDC_SEL]	  = imx_clk_mux("epdc_sel",	base + 0x34, 9, 3, epdc_sels, ARRAY_SIZE(epdc_sels));
+	}
 	clks[IMX6UL_CLK_ECSPI_SEL]	  = imx_clk_mux("ecspi_sel",	base + 0x38, 18, 1, ecspi_sels, ARRAY_SIZE(ecspi_sels));
 	clks[IMX6UL_CLK_LCDIF_PRE_SEL]	  = imx_clk_mux("lcdif_pre_sel", base + 0x38, 15, 3, lcdif_pre_sels, ARRAY_SIZE(lcdif_pre_sels));
 	clks[IMX6UL_CLK_LCDIF_SEL]	  = imx_clk_mux("lcdif_sel",	base + 0x38, 9, 3, lcdif_sels, ARRAY_SIZE(lcdif_sels));

@@ -276,6 +299,10 @@ static void __init imx6ul_clocks_init(struct device_node *ccm_node)
 	clks[IMX6UL_CLK_SAI3_PODF]	= imx_clk_divider("sai3_podf",	   "sai3_pred",		base + 0x28, 16, 6);
 	clks[IMX6UL_CLK_SAI1_PRED]	= imx_clk_divider("sai1_pred",	   "sai1_sel",		base + 0x28, 6,	 3);
 	clks[IMX6UL_CLK_SAI1_PODF]	= imx_clk_divider("sai1_podf",	   "sai1_pred",		base + 0x28, 0,	 6);
+	if (clk_on_imx6ull()) {
+		clks[IMX6UL_CLK_ESAI_PRED]	= imx_clk_divider("esai_pred",     "esai_sel",		base + 0x28, 9,  3);
+		clks[IMX6UL_CLK_ESAI_PODF]	= imx_clk_divider("esai_podf",     "esai_pred",		base + 0x28, 25, 3);
+	}
 	clks[IMX6UL_CLK_ENFC_PRED]	= imx_clk_divider("enfc_pred",	   "enfc_sel",		base + 0x2c, 18, 3);
 	clks[IMX6UL_CLK_ENFC_PODF]	= imx_clk_divider("enfc_podf",	   "enfc_pred",		base + 0x2c, 21, 6);
 	clks[IMX6UL_CLK_SAI2_PRED]	= imx_clk_divider("sai2_pred",	   "sai2_sel",		base + 0x2c, 6,	 3);

@@ -298,9 +325,15 @@ static void __init imx6ul_clocks_init(struct device_node *ccm_node)
 	clks[IMX6UL_CLK_APBHDMA]	= imx_clk_gate2("apbh_dma",	"bch_podf",	base + 0x68,	4);
 	clks[IMX6UL_CLK_ASRC_IPG]	= imx_clk_gate2_shared("asrc_ipg",	"ahb",	base + 0x68,	6, &share_count_asrc);
 	clks[IMX6UL_CLK_ASRC_MEM]	= imx_clk_gate2_shared("asrc_mem",	"ahb",	base + 0x68,	6, &share_count_asrc);
-	clks[IMX6UL_CLK_CAAM_MEM]	= imx_clk_gate2("caam_mem",	"ahb",		base + 0x68,	8);
-	clks[IMX6UL_CLK_CAAM_ACLK]	= imx_clk_gate2("caam_aclk",	"ahb",		base + 0x68,	10);
-	clks[IMX6UL_CLK_CAAM_IPG]	= imx_clk_gate2("caam_ipg",	"ipg",		base + 0x68,	12);
+	if (clk_on_imx6ul()) {
+		clks[IMX6UL_CLK_CAAM_MEM]	= imx_clk_gate2("caam_mem",	"ahb",		base + 0x68,	8);
+		clks[IMX6UL_CLK_CAAM_ACLK]	= imx_clk_gate2("caam_aclk",	"ahb",		base + 0x68,	10);
+		clks[IMX6UL_CLK_CAAM_IPG]	= imx_clk_gate2("caam_ipg",	"ipg",		base + 0x68,	12);
+	} else if (clk_on_imx6ull()) {
+		clks[IMX6UL_CLK_DCP_CLK]	= imx_clk_gate2("dcp",		"ahb",		base + 0x68,	10);
+		clks[IMX6UL_CLK_ENET]		= imx_clk_gate2("enet",		"ipg",		base + 0x68,	12);
+		clks[IMX6UL_CLK_ENET_AHB]	= imx_clk_gate2("enet_ahb",	"ahb",		base + 0x68,	12);
+	}
 	clks[IMX6UL_CLK_CAN1_IPG]	= imx_clk_gate2("can1_ipg",	"ipg",		base + 0x68,	14);
 	clks[IMX6UL_CLK_CAN1_SERIAL]	= imx_clk_gate2("can1_serial",	"can_podf",	base + 0x68,	16);
 	clks[IMX6UL_CLK_CAN2_IPG]	= imx_clk_gate2("can2_ipg",	"ipg",		base + 0x68,	18);

@@ -309,7 +342,10 @@ static void __init imx6ul_clocks_init(struct device_node *ccm_node)
 	clks[IMX6UL_CLK_GPT2_SERIAL]	= imx_clk_gate2("gpt2_serial",	"perclk",	base + 0x68,	26);
 	clks[IMX6UL_CLK_UART2_IPG]	= imx_clk_gate2("uart2_ipg",	"ipg",		base + 0x68,	28);
 	clks[IMX6UL_CLK_UART2_SERIAL]	= imx_clk_gate2("uart2_serial",	"uart_podf",	base + 0x68,	28);
-	clks[IMX6UL_CLK_AIPSTZ3]	= imx_clk_gate2("aips_tz3",	"ahb",		base + 0x68,	30);
+	if (clk_on_imx6ul())
+		clks[IMX6UL_CLK_AIPSTZ3]	= imx_clk_gate2("aips_tz3",	"ahb",		base + 0x68,	30);
+	else if (clk_on_imx6ull())
+		clks[IMX6UL_CLK_AIPSTZ3]	= imx_clk_gate2("aips_tz3",	"ahb",		 base + 0x80,	18);
 
 	/* CCGR1 */
 	clks[IMX6UL_CLK_ECSPI1]		= imx_clk_gate2("ecspi1",	"ecspi_podf",	base + 0x6c,	0);

@@ -328,6 +364,11 @@ static void __init imx6ul_clocks_init(struct device_node *ccm_node)
 	clks[IMX6UL_CLK_UART4_SERIAL]	= imx_clk_gate2("uart4_serail",	"uart_podf",	base + 0x6c,	24);
 
 	/* CCGR2 */
+	if (clk_on_imx6ull()) {
+		clks[IMX6UL_CLK_ESAI_EXTAL]	= imx_clk_gate2_shared("esai_extal",	"esai_podf",	base + 0x70,	0, &share_count_esai);
+		clks[IMX6UL_CLK_ESAI_IPG]	= imx_clk_gate2_shared("esai_ipg",	"ahb",		base + 0x70,	0, &share_count_esai);
+		clks[IMX6UL_CLK_ESAI_MEM]	= imx_clk_gate2_shared("esai_mem",	"ahb",		base + 0x70,	0, &share_count_esai);
+	}
 	clks[IMX6UL_CLK_CSI]		= imx_clk_gate2("csi",		"csi_podf",		base + 0x70,	2);
 	clks[IMX6UL_CLK_I2C1]		= imx_clk_gate2("i2c1",		"perclk",	base + 0x70,	6);
 	clks[IMX6UL_CLK_I2C2]		= imx_clk_gate2("i2c2",		"perclk",	base + 0x70,	8);

@@ -340,8 +381,13 @@ static void __init imx6ul_clocks_init(struct device_node *ccm_node)
 	/* CCGR3 */
 	clks[IMX6UL_CLK_UART5_IPG]	= imx_clk_gate2("uart5_ipg",	"ipg",		base + 0x74,	2);
 	clks[IMX6UL_CLK_UART5_SERIAL]	= imx_clk_gate2("uart5_serial",	"uart_podf",	base + 0x74,	2);
-	clks[IMX6UL_CLK_ENET]		= imx_clk_gate2("enet",		"ipg",		base + 0x74,	4);
-	clks[IMX6UL_CLK_ENET_AHB]	= imx_clk_gate2("enet_ahb",	"ahb",		base + 0x74,	4);
+	if (clk_on_imx6ul()) {
+		clks[IMX6UL_CLK_ENET]		= imx_clk_gate2("enet",		"ipg",		base + 0x74,	4);
+		clks[IMX6UL_CLK_ENET_AHB]	= imx_clk_gate2("enet_ahb",	"ahb",		base + 0x74,	4);
+	} else if (clk_on_imx6ull()) {
+		clks[IMX6UL_CLK_EPDC_ACLK]	= imx_clk_gate2("epdc_aclk",	"axi",		base + 0x74,	4);
+		clks[IMX6UL_CLK_EPDC_PIX]	= imx_clk_gate2("epdc_pix",	"epdc_podf",	base + 0x74,	4);
+	}
 	clks[IMX6UL_CLK_UART6_IPG]	= imx_clk_gate2("uart6_ipg",	"ipg",		base + 0x74,	6);
 	clks[IMX6UL_CLK_UART6_SERIAL]	= imx_clk_gate2("uart6_serial",	"uart_podf",	base + 0x74,	6);
 	clks[IMX6UL_CLK_LCDIF_PIX]	= imx_clk_gate2("lcdif_pix",	"lcdif_podf",	base + 0x74,	10);

@@ -385,8 +431,10 @@ static void __init imx6ul_clocks_init(struct device_node *ccm_node)
 	clks[IMX6UL_CLK_USBOH3]		= imx_clk_gate2("usboh3",	"ipg",		 base + 0x80,	0);
 	clks[IMX6UL_CLK_USDHC1]		= imx_clk_gate2("usdhc1",	"usdhc1_podf",	 base + 0x80,	2);
 	clks[IMX6UL_CLK_USDHC2]		= imx_clk_gate2("usdhc2",	"usdhc2_podf",	 base + 0x80,	4);
-	clks[IMX6UL_CLK_SIM1]		= imx_clk_gate2("sim1",		"sim_sel",	 base + 0x80,	6);
-	clks[IMX6UL_CLK_SIM2]		= imx_clk_gate2("sim2",		"sim_sel",	 base + 0x80,	8);
+	if (clk_on_imx6ul()) {
+		clks[IMX6UL_CLK_SIM1]		= imx_clk_gate2("sim1",		"sim_sel",	 base + 0x80,	6);
+		clks[IMX6UL_CLK_SIM2]		= imx_clk_gate2("sim2",		"sim_sel",	 base + 0x80,	8);
+	}
 	clks[IMX6UL_CLK_EIM]		= imx_clk_gate2("eim",		"eim_slow_podf", base + 0x80,	10);
 	clks[IMX6UL_CLK_PWM8]		= imx_clk_gate2("pwm8",		"perclk",	 base + 0x80,	16);
 	clks[IMX6UL_CLK_UART8_IPG]	= imx_clk_gate2("uart8_ipg",	"ipg",		 base + 0x80,	14);

@@ -430,6 +478,7 @@ static void __init imx6ul_clocks_init(struct device_node *ccm_node)
 	clk_set_rate(clks[IMX6UL_CLK_ENET_REF], 50000000);
 	clk_set_rate(clks[IMX6UL_CLK_ENET2_REF], 50000000);
 	clk_set_rate(clks[IMX6UL_CLK_CSI], 24000000);
+	clk_set_rate(clks[IMX6UL_CLK_PLL3_PFD2], 320000000);
 
 	/* keep all the clks on just for bringup */
 	for (i = 0; i < ARRAY_SIZE(clks_init_on); i++)

@@ -441,7 +490,10 @@ static void __init imx6ul_clocks_init(struct device_node *ccm_node)
 	}
 
 	clk_set_parent(clks[IMX6UL_CLK_CAN_SEL], clks[IMX6UL_CLK_PLL3_60M]);
-	clk_set_parent(clks[IMX6UL_CLK_SIM_PRE_SEL], clks[IMX6UL_CLK_PLL3_USB_OTG]);
+	if (clk_on_imx6ul())
+		clk_set_parent(clks[IMX6UL_CLK_SIM_PRE_SEL], clks[IMX6UL_CLK_PLL3_USB_OTG]);
+	else if (clk_on_imx6ull())
+		clk_set_parent(clks[IMX6UL_CLK_EPDC_PRE_SEL], clks[IMX6UL_CLK_PLL3_PFD2]);
 
 	clk_set_parent(clks[IMX6UL_CLK_ENFC_SEL], clks[IMX6UL_CLK_PLL2_PFD2]);
 }
include/dt-bindings/clock/imx6ul-clock.h +14 -1
index fd8aee8..563fd5b 100644
@@ -236,6 +236,19 @@
 #define IMX6UL_CLK_PLL3_120M		223
 #define IMX6UL_CLK_KPP			224
 
-#define IMX6UL_CLK_END			225
+/* For i.MX6ULL */
+#define IMX6UL_CLK_ESAI_PRED		225
+#define IMX6UL_CLK_ESAI_PODF		226
+#define IMX6UL_CLK_ESAI_EXTAL		227
+#define IMX6UL_CLK_ESAI_MEM		228
+#define IMX6UL_CLK_ESAI_IPG		229
+#define IMX6UL_CLK_DCP_CLK		230
+#define IMX6UL_CLK_EPDC_PRE_SEL		231
+#define IMX6UL_CLK_EPDC_SEL		232
+#define IMX6UL_CLK_EPDC_PODF		233
+#define IMX6UL_CLK_EPDC_ACLK		234
+#define IMX6UL_CLK_EPDC_PIX		235
+#define IMX6UL_CLK_ESAI_SEL		236
+#define IMX6UL_CLK_END			237
 
 #endif /* __DT_BINDINGS_CLOCK_IMX6UL_H */
Signature · 1 line
2.7.4
#9 lore raw

PATCH 3/3 clk: imx: clk-imx6ul: add clk support for imx6ull

Quoted 12 lines · Peter Chen
drivers/clk/imx/clk-imx6ul.c +4 -2
 	clks[IMX6UL_CLK_USDHC1]		= imx_clk_gate2("usdhc1",	"usdhc1_podf",	 base + 0x80,	2);
 	clks[IMX6UL_CLK_USDHC2]		= imx_clk_gate2("usdhc2",	"usdhc2_podf",	 base + 0x80,	4);
-	clks[IMX6UL_CLK_SIM1]		= imx_clk_gate2("sim1",		"sim_sel",	 base + 0x80,	6);
-	clks[IMX6UL_CLK_SIM2]		= imx_clk_gate2("sim2",		"sim_sel",	 base + 0x80,	8);
+	if (clk_on_imx6ul()) {
+		clks[IMX6UL_CLK_SIM1]		= imx_clk_gate2("sim1",		"sim_sel",	 base + 0x80,	6);
+		clks[IMX6UL_CLK_SIM2]		= imx_clk_gate2("sim2",		"sim_sel",	 base + 0x80,	8);
+	}
 	clks[IMX6UL_CLK_EIM]		= imx_clk_gate2("eim",		"eim_slow_podf", base + 0x80,	10);
 	clks[IMX6UL_CLK_PWM8]		= imx_clk_gate2("pwm8",		"perclk",	 base + 0x80,	16);
 	clks[IMX6UL_CLK_UART8_IPG]	= imx_clk_gate2("uart8_ipg",	"ipg",		 base + 0x80,	14);

drivers/clk/imx/clk-imx6ul.c static void __init imx6ul_clocks_init(struct device_node *ccm_node) · line 481

Quoted 4 lines
drivers/clk/imx/clk-imx6ul.c +1 -0
@@ -430,6 +478,7 @@ static void __init imx6ul_clocks_init(struct device_node *ccm_node)
 	clk_set_rate(clks[IMX6UL_CLK_ENET_REF], 50000000);
 	clk_set_rate(clks[IMX6UL_CLK_ENET2_REF], 50000000);
 	clk_set_rate(clks[IMX6UL_CLK_CSI], 24000000);
+	clk_set_rate(clks[IMX6UL_CLK_PLL3_PFD2], 320000000);

Can you use assigned clock rates for this instead?

Quoted 2 lines
drivers/clk/imx/clk-imx6ul.c +0 -0
 	/* keep all the clks on just for bringup */
Signature · 2 lines
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
author
#10 lore raw

PATCH 3/3 clk: imx: clk-imx6ul: add clk support for imx6ull

Quoted 23 lines · Peter Chen
Quoted 1 line

clks[IMX6UL_CLK_USDHC1] = imx_clk_gate2("usdhc1",

	"usdhc1_podf",	 base + 0x80,	2);
Quoted 1 line

clks[IMX6UL_CLK_USDHC2] = imx_clk_gate2("usdhc2",

	"usdhc2_podf",	 base + 0x80,	4);

Review

Quoted 1 line
(quoted diff) +0 -1
-	clks[IMX6UL_CLK_SIM1]		= imx_clk_gate2("sim1",

	"sim_sel",	 base + 0x80,	6);

Review

Quoted 1 line
(quoted diff) +0 -1
-	clks[IMX6UL_CLK_SIM2]		= imx_clk_gate2("sim2",

	"sim_sel",	 base + 0x80,	8);

Review

Quoted 2 lines
(quoted diff) +2 -0
+	if (clk_on_imx6ul()) {
+		clks[IMX6UL_CLK_SIM1]		= imx_clk_gate2("sim1",

	"sim_sel",	 base + 0x80,	6);

Review

Quoted 1 line
(quoted diff) +1 -0
+		clks[IMX6UL_CLK_SIM2]		= imx_clk_gate2("sim2",

	"sim_sel",	 base + 0x80,	8);

Review

Quoted 2 lines
(quoted diff) +1 -0
+	}
 	clks[IMX6UL_CLK_EIM]		= imx_clk_gate2("eim",

	"eim_slow_podf", base + 0x80,	10);
Quoted 1 line

clks[IMX6UL_CLK_PWM8] = imx_clk_gate2("pwm8",

	"perclk",	 base + 0x80,	16);
Quoted 1 line

clks[IMX6UL_CLK_UART8_IPG] = imx_clk_gate2("uart8_ipg", "ipg",

	 base + 0x80,	14);
Quoted 9 lines

Review static void __init imx6ul_clocks_init(struct device_node

Quoted 1 line
(quoted diff) +0 -0
@@ -430,6 +478,7 @@ static void __init imx6ul_clocks_init(struct device_node

*ccm_node)

drivers/clk/imx/clk-imx6ul.c static void __init imx6ul_clocks_init(struct device_node *ccm_node) · line 481

Quoted 4 lines
drivers/clk/imx/clk-imx6ul.c +1 -0
 	clk_set_rate(clks[IMX6UL_CLK_ENET_REF], 50000000);
 	clk_set_rate(clks[IMX6UL_CLK_ENET2_REF], 50000000);
 	clk_set_rate(clks[IMX6UL_CLK_CSI], 24000000);
+	clk_set_rate(clks[IMX6UL_CLK_PLL3_PFD2], 320000000);

Can you use assigned clock rates for this instead?

Thanks, I will move it to dts.

Peter

#11 lore raw

PATCH 3/3 clk: imx: clk-imx6ul: add clk support for imx6ull

In reply to Peter Chen
Quoted 19 lines · Peter Chen

From: Bai Ping <[email protected]>

imx6ull is the derived SoC from imx6ul

Cc Michael Turquette <[email protected]>
Cc Stephen Boyd <[email protected]>
Signed-off-by Peng Fan <[email protected]>
Signed-off-by Bai Ping <[email protected]>
Signed-off-by Peter Chen <[email protected]>
---
 drivers/clk/imx/clk-imx6ul.c             | 74 +++++++++++++++++++++++++++-----
 include/dt-bindings/clock/imx6ul-clock.h | 15 ++++++-
 2 files changed, 77 insertions(+), 12 deletions(-)
drivers/clk/imx/clk-imx6ul.c +0 -0
index d1d7787..ceb99a7 100644

drivers/clk/imx/clk-imx6ul.c static const char *perclk_sels[] = { "ipg", "osc", }; · line 71

Quoted 8 lines
drivers/clk/imx/clk-imx6ul.c +5 -0
@@ -64,6 +64,11 @@ static const char *perclk_sels[] = { "ipg", "osc", };
 static const char *lcdif_sels[] = { "lcdif_podf", "ipp_di0", "ipp_di1", "ldb_di0", "ldb_di1", };
 static const char *csi_sels[] = { "osc", "pll2_pfd2_396m", "pll3_120m", "pll3_pfd1_540m", };
 static const char *sim_sels[] = { "sim_podf", "ipp_di0", "ipp_di1", "ldb_di0", "ldb_di1", };
+/* epdc_pre_sels, epdc_sels, esai_sels only exists on i.MX6ULL */
+static const char *epdc_pre_sels[] = { "pll2_bus", "pll3_usb_otg", "pll5_video_div", "pll2_pfd0_352m", "pll2_pfd2_396m", "pll3_pfd2_508m", };
+static const char *esai_sels[] = { "pll4_audio_div", "pll3_pfd2_508m", "pll5_video_div", "pll3_usb_otg", };
+static const char *epdc_sels[] = { "epdc_podf", "ipp_di0", "ipp_di1", "ldb_di0", "ldb_di1", };
+

The new line is not needed. There is already one below.

Quoted 3 lines
drivers/clk/imx/clk-imx6ul.c +0 -0
 static struct clk *clks[IMX6UL_CLK_END];
 static struct clk_onecell_data clk_data;

<snip>

Quoted 12 lines
include/dt-bindings/clock/imx6ul-clock.h +3 -1
index fd8aee8..563fd5b 100644
@@ -236,6 +236,19 @@
 #define IMX6UL_CLK_PLL3_120M		223
 #define IMX6UL_CLK_KPP			224
 
-#define IMX6UL_CLK_END			225
+/* For i.MX6ULL */
+#define IMX6UL_CLK_ESAI_PRED		225
+#define IMX6UL_CLK_ESAI_PODF		226

include/dt-bindings/clock/imx6ul-clock.h line 251

Quoted 10 lines
include/dt-bindings/clock/imx6ul-clock.h +10 -0
+#define IMX6UL_CLK_ESAI_EXTAL		227
+#define IMX6UL_CLK_ESAI_MEM		228
+#define IMX6UL_CLK_ESAI_IPG		229
+#define IMX6UL_CLK_DCP_CLK		230
+#define IMX6UL_CLK_EPDC_PRE_SEL		231
+#define IMX6UL_CLK_EPDC_SEL		232
+#define IMX6UL_CLK_EPDC_PODF		233
+#define IMX6UL_CLK_EPDC_ACLK		234
+#define IMX6UL_CLK_EPDC_PIX		235
+#define IMX6UL_CLK_ESAI_SEL		236

Can we have these imx6ull only clocks named after IMX6ULL_xxx?

Shawn

Quoted 6 lines
include/dt-bindings/clock/imx6ul-clock.h +1 -0
+#define IMX6UL_CLK_END			237
 
 #endif /* __DT_BINDINGS_CLOCK_IMX6UL_H */
Signature · 1 line
2.7.4
author
#12 lore raw

PATCH 3/3 clk: imx: clk-imx6ul: add clk support for imx6ull

Thanks, Shawn. All comments will be adopted in v2.

Peter

Quoted 30 lines

Review

Quoted 4 lines

+"pll4_audio_div", "pll3_pfd2_508m", "pll5_video_div", "pll3_usb_otg",

(quoted diff) +3 -0
+}; static const char *epdc_sels[] = { "epdc_podf", "ipp_di0",
+"ipp_di1", "ldb_di0", "ldb_di1", };
+

The new line is not needed. There is already one below.

Quoted 9 lines

static struct clk *clks[IMX6UL_CLK_END]; static struct
clk_onecell_data clk_data;

include/dt-bindings/clock/imx6ul-clock.h +3 -1
-#define IMX6UL_CLK_END			225
+/* For i.MX6ULL */
+#define IMX6UL_CLK_ESAI_PRED		225
+#define IMX6UL_CLK_ESAI_PODF		226

include/dt-bindings/clock/imx6ul-clock.h line 251

Quoted 10 lines
include/dt-bindings/clock/imx6ul-clock.h +10 -0
+#define IMX6UL_CLK_ESAI_EXTAL		227
+#define IMX6UL_CLK_ESAI_MEM		228
+#define IMX6UL_CLK_ESAI_IPG		229
+#define IMX6UL_CLK_DCP_CLK		230
+#define IMX6UL_CLK_EPDC_PRE_SEL		231
+#define IMX6UL_CLK_EPDC_SEL		232
+#define IMX6UL_CLK_EPDC_PODF		233
+#define IMX6UL_CLK_EPDC_ACLK		234
+#define IMX6UL_CLK_EPDC_PIX		235
+#define IMX6UL_CLK_ESAI_SEL		236

Can we have these imx6ull only clocks named after IMX6ULL_xxx?

Shawn