ARM: dmaengine: sun6i: share the dma driver with sun50i
Subsystems (2)
PATCH v2 1/1 ARM: dmaengine: sun6i: share the dma driver with sun50i
Add soc a64 dma support.
Signed-off-by Hao Zhang <[email protected]>
--- drivers/dma/sun6i-dma.c | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+)
drivers/dma/sun6i-dma.c +19 -0
@@ -1028,11 +1028,23 @@ static struct sun6i_dma_config sun8i_h3_dma_cfg = { .nr_max_vchans = 34, }; +/* +* The A64 has 8 physical channels, a maximum DRQ port id of 27, +* and a total of 38 usable source and destination endpoints. +*/ + +static struct sun6i_dma_config sun50i_a64_dma_cfg = { + .nr_max_channels =8 , + .nr_max_requests =27 , + .nr_max_vchans =38 , +}; +static const struct of_device_id sun6i_dma_match[] = { { .compatible ="allwinner,sun6i-a31-dma" , .data = &sun6i_a31_dma_cfg }, { .compatible ="allwinner,sun8i-a23-dma" , .data = &sun8i_a23_dma_cfg }, { .compatible ="allwinner,sun8i-a83t-dma" , .data = &sun8i_a83t_dma_cfg }, { .compatible ="allwinner,sun8i-h3-dma" , .data = &sun8i_h3_dma_cfg }, + { .compatible ="allwinner,sun50i-a64-dma" , .data = &sun50i_a64_dma_cfg }, {/* sentinel */ } };MODULE_DEVICE_TABLE (of, sun6i_dma_match);
@@ -1110,6 +1122,13 @@ static int sun6i_dma_probe(struct platform_device *pdev) sdc->slave.dst_addr_widths =BIT (DMA_SLAVE_BUSWIDTH_1_BYTE ) |BIT (DMA_SLAVE_BUSWIDTH_2_BYTES ) |BIT (DMA_SLAVE_BUSWIDTH_4_BYTES ); + +if (of_device_is_compatible (pdev->dev.of_node, +"allwinner,sun50i-a64-dma" )) { + sdc->slave.src_addr_widths |=BIT (DMA_SLAVE_BUSWIDTH_8_BYTES ); + sdc->slave.dst_addr_widths |=BIT (DMA_SLAVE_BUSWIDTH_8_BYTES ); + } + sdc->slave.directions =BIT (DMA_DEV_TO_MEM ) |BIT (DMA_MEM_TO_DEV ); sdc->slave.residue_granularity =DMA_RESIDUE_GRANULARITY_BURST ;
Signature · 1 line
2.7.4
Quoted 22 lines · Hao Zhang
Add soc a64 dma support.
Signed-off-by Hao Zhang <[email protected]>--- drivers/dma/sun6i-dma.c | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+)drivers/dma/sun6i-dma.c +7
-0@@ -1028,11 +1028,23 @@ static struct sun6i_dma_config sun8i_h3_dma_cfg = { .nr_max_vchans = 34, }; +/* +* The A64 has 8 physical channels, a maximum DRQ port id of 27, +* and a total of 38 usable source and destination endpoints. +*/ + +static struct sun6i_dma_config sun50i_a64_dma_cfg = { + .nr_max_channels =8 ,
drivers/dma/sun6i-dma.c static struct sun6i_dma_config sun8i_h3_dma_cfg = { · line 1047
Quoted 10 lines
drivers/dma/sun6i-dma.c +5
-0+ .nr_max_requests = 27, + .nr_max_vchans = 38, +}; +static const struct of_device_id sun6i_dma_match[] = { { .compatible ="allwinner,sun6i-a31-dma" , .data = &sun6i_a31_dma_cfg }, { .compatible ="allwinner,sun8i-a23-dma" , .data = &sun8i_a23_dma_cfg }, { .compatible ="allwinner,sun8i-a83t-dma" , .data = &sun8i_a83t_dma_cfg }, { .compatible ="allwinner,sun8i-h3-dma" , .data = &sun8i_h3_dma_cfg }, + { .compatible ="allwinner,sun50i-a64-dma" , .data = &sun50i_a64_dma_cfg },
You need to add that compatible to the DT binding documentation.
Quoted 4 lines
drivers/dma/sun6i-dma.c +0
-0{/* sentinel */ } };MODULE_DEVICE_TABLE (of, sun6i_dma_match);
drivers/dma/sun6i-dma.c static int sun6i_dma_probe(struct platform_device *pdev) · line 1131
Quoted 10 lines
drivers/dma/sun6i-dma.c +7
-0@@ -1110,6 +1122,13 @@ static int sun6i_dma_probe(struct platform_device *pdev) sdc->slave.dst_addr_widths =BIT (DMA_SLAVE_BUSWIDTH_1_BYTE ) |BIT (DMA_SLAVE_BUSWIDTH_2_BYTES ) |BIT (DMA_SLAVE_BUSWIDTH_4_BYTES ); + +if (of_device_is_compatible (pdev->dev.of_node, +"allwinner,sun50i-a64-dma" )) { + sdc->slave.src_addr_widths |=BIT (DMA_SLAVE_BUSWIDTH_8_BYTES ); + sdc->slave.dst_addr_widths |=BIT (DMA_SLAVE_BUSWIDTH_8_BYTES ); + } +
You'll also need to change convert_buswidth, it will reject any width higher than 4 bytes.
Maxime
Signature · 10 lines
Maxime Ripard, Free Electrons Embedded Linux and Kernel engineering http://free-electrons.com -------------- next part -------------- A non-text attachment was scrubbed... Name: signature.asc Type: application/pgp-signature Size: 801 bytes Desc: not available URL: <http://lists.infradead.org/pipermail/linux-arm-kernel/attachments/20161106/61c65236/attachment.sig>