Skip to contentSkip to conversation

drm/tegra: add tiling FB modifiers

PATCH Applied Alexandre Courbot 4 participants 6 messages Nov 8, 2016 – Mar 20, 2017

Subsystems (4)
DRM drivers DRM misc Tegra architecture support DRM drivers for NVIDIA Tegra
lore
Share & tools
lore

Alexandre Courbot

author
#0 lore raw

PATCH 1/1 drm/tegra: add tiling FB modifiers

Add FB modifiers to allow user-space to specify that a surface is in one of the two tiling formats supported by Tegra chips, and add support in the tegradrm driver to handle them properly. This is necessary for the display controller to directly display buffers generated by the GPU.

This feature is intended to replace the dedicated IOCTL enabled by TEGRA_STAGING and to provide a non-staging alternative to that solution.

Signed-off-by Alexandre Courbot <[email protected]>
---
 drivers/gpu/drm/tegra/drm.c   |  2 ++
 drivers/gpu/drm/tegra/fb.c    | 23 +++++++++++++++++++---
 include/uapi/drm/drm_fourcc.h | 45 +++++++++++++++++++++++++++++++++++++++++++
 3 files changed, 67 insertions(+), 3 deletions(-)
drivers/gpu/drm/tegra/drm.c +2 -0
index a9630c2d6cb3..36b4b30a5164 100644
@@ -161,6 +161,8 @@ static int tegra_drm_load(struct drm_device *drm, unsigned long flags)
 	drm->mode_config.max_width = 4096;
 	drm->mode_config.max_height = 4096;
 
+	drm->mode_config.allow_fb_modifiers = true;
+
 	drm->mode_config.funcs = &tegra_drm_mode_funcs;
 
 	err = tegra_drm_fb_prepare(drm);
drivers/gpu/drm/tegra/fb.c +20 -3
index e6d71fa4028e..2fded58b2ca5 100644
@@ -52,9 +52,26 @@ int tegra_fb_get_tiling(struct drm_framebuffer *framebuffer,
 			struct tegra_bo_tiling *tiling)
 {
 	struct tegra_fb *fb = to_tegra_fb(framebuffer);
-
-	/* TODO: handle YUV formats? */
-	*tiling = fb->planes[0]->tiling;
+	uint64_t modifier = fb->base.modifier[0];
+
+	switch (fourcc_mod_tegra_mod(modifier)) {
+	case NV_FORMAT_MOD_TEGRA_TILED:
+		tiling->mode = TEGRA_BO_TILING_MODE_TILED;
+		tiling->value = 0;
+		break;
+
+	case NV_FORMAT_MOD_TEGRA_16BX2_BLOCK(0):
+		tiling->mode = TEGRA_BO_TILING_MODE_BLOCK;
+		tiling->value = fourcc_mod_tegra_param(modifier);
+		if (tiling->value > 5)
+			return -EINVAL;
+		break;
+
+	default:
+		/* TODO: handle YUV formats? */
+		*tiling = fb->planes[0]->tiling;
+		break;
+	}
 
 	return 0;
 }
include/uapi/drm/drm_fourcc.h +45 -0

51 lines not on this page · raw message

Signature · 1 line
2.10.2
#1 lore raw
Quoted 43 lines · Alexandre Courbot

Add FB modifiers to allow user-space to specify that a surface is in one of the two tiling formats supported by Tegra chips, and add support in the tegradrm driver to handle them properly. This is necessary for the display controller to directly display buffers generated by the GPU.

This feature is intended to replace the dedicated IOCTL enabled by TEGRA_STAGING and to provide a non-staging alternative to that solution.

Signed-off-by Alexandre Courbot <[email protected]>
---
 drivers/gpu/drm/tegra/drm.c   |  2 ++
 drivers/gpu/drm/tegra/fb.c    | 23 +++++++++++++++++++---
 include/uapi/drm/drm_fourcc.h | 45 +++++++++++++++++++++++++++++++++++++++++++
 3 files changed, 67 insertions(+), 3 deletions(-)
drivers/gpu/drm/tegra/drm.c +2 -0
index a9630c2d6cb3..36b4b30a5164 100644
@@ -161,6 +161,8 @@ static int tegra_drm_load(struct drm_device *drm, unsigned long flags)
        drm->mode_config.max_width = 4096;
        drm->mode_config.max_height = 4096;
 
+       drm->mode_config.allow_fb_modifiers = true;
+
        drm->mode_config.funcs = &tegra_drm_mode_funcs;
 
        err = tegra_drm_fb_prepare(drm);
drivers/gpu/drm/tegra/fb.c +3 -3
index e6d71fa4028e..2fded58b2ca5 100644
@@ -52,9 +52,26 @@ int tegra_fb_get_tiling(struct drm_framebuffer *framebuffer,
                        struct tegra_bo_tiling *tiling)
 {
        struct tegra_fb *fb = to_tegra_fb(framebuffer);
-
-       /* TODO: handle YUV formats? */
-       *tiling = fb->planes[0]->tiling;
+       uint64_t modifier = fb->base.modifier[0];
+
+       switch (fourcc_mod_tegra_mod(modifier)) {

drivers/gpu/drm/tegra/fb.c int tegra_fb_get_tiling(struct drm_framebuffer *framebuffer, · line 67

Quoted 10 lines
drivers/gpu/drm/tegra/fb.c +10 -0
+       case NV_FORMAT_MOD_TEGRA_TILED:
+               tiling->mode = TEGRA_BO_TILING_MODE_TILED;
+               tiling->value = 0;
+               break;
+
+       case NV_FORMAT_MOD_TEGRA_16BX2_BLOCK(0):
+               tiling->mode = TEGRA_BO_TILING_MODE_BLOCK;
+               tiling->value = fourcc_mod_tegra_param(modifier);
+               if (tiling->value > 5)
+                       return -EINVAL;

Shouldn't this contain some hardware-check for the support? AFAIK, not all Tegras support all block-heights (if even this mode at all?)...
_______________________________________________
dri-devel mailing list
[email protected]
https://lists.freedesktop.org/mailman/listinfo/dri-devel

author
#2 lore raw
Quoted 49 lines · Erik Faye-Lund
Quoted 48 lines · Alexandre Courbot

Add FB modifiers to allow user-space to specify that a surface is in one of the two tiling formats supported by Tegra chips, and add support in the tegradrm driver to handle them properly. This is necessary for the display controller to directly display buffers generated by the GPU.

This feature is intended to replace the dedicated IOCTL enabled by TEGRA_STAGING and to provide a non-staging alternative to that solution.

Signed-off-by Alexandre Courbot <[email protected]>
---
 drivers/gpu/drm/tegra/drm.c   |  2 ++
 drivers/gpu/drm/tegra/fb.c    | 23 +++++++++++++++++++---
 include/uapi/drm/drm_fourcc.h | 45 +++++++++++++++++++++++++++++++++++++++++++
 3 files changed, 67 insertions(+), 3 deletions(-)
drivers/gpu/drm/tegra/drm.c +2 -0
index a9630c2d6cb3..36b4b30a5164 100644
@@ -161,6 +161,8 @@ static int tegra_drm_load(struct drm_device *drm, unsigned long flags)
        drm->mode_config.max_width = 4096;
        drm->mode_config.max_height = 4096;
 
+       drm->mode_config.allow_fb_modifiers = true;
+
        drm->mode_config.funcs = &tegra_drm_mode_funcs;
 
        err = tegra_drm_fb_prepare(drm);
drivers/gpu/drm/tegra/fb.c +8 -3
index e6d71fa4028e..2fded58b2ca5 100644
@@ -52,9 +52,26 @@ int tegra_fb_get_tiling(struct drm_framebuffer *framebuffer,
                        struct tegra_bo_tiling *tiling)
 {
        struct tegra_fb *fb = to_tegra_fb(framebuffer);
-
-       /* TODO: handle YUV formats? */
-       *tiling = fb->planes[0]->tiling;
+       uint64_t modifier = fb->base.modifier[0];
+
+       switch (fourcc_mod_tegra_mod(modifier)) {
+       case NV_FORMAT_MOD_TEGRA_TILED:
+               tiling->mode = TEGRA_BO_TILING_MODE_TILED;
+               tiling->value = 0;
+               break;
+
Quoted 8 lines

drivers/gpu/drm/tegra/fb.c int tegra_fb_get_tiling(struct drm_framebuffer *framebuffer, · line 67

Quoted 5 lines
drivers/gpu/drm/tegra/fb.c +5 -0
+       case NV_FORMAT_MOD_TEGRA_16BX2_BLOCK(0):
+               tiling->mode = TEGRA_BO_TILING_MODE_BLOCK;
+               tiling->value = fourcc_mod_tegra_param(modifier);
+               if (tiling->value > 5)
+                       return -EINVAL;

Shouldn't this contain some hardware-check for the support? AFAIK, not all Tegras support all block-heights (if even this mode at all?)...

tegra_dc_setup_window does that check later (check the test on dc->soc->supports_block_linear). At the moment no error message is displayed though (and it seems like we are writing a stale value in DC_WIN_BUFFER_ADDR_MODE if the SoC doesn't support block linear and the tiling mode is TEGRA_BO_TILING_MODE_BLOCK?)

#3 lore raw
Quoted 59 lines · Alexandre Courbot
Quoted 49 lines · Erik Faye-Lund
Quoted 48 lines · Alexandre Courbot

Add FB modifiers to allow user-space to specify that a surface is in one of the two tiling formats supported by Tegra chips, and add support in the tegradrm driver to handle them properly. This is necessary for the display controller to directly display buffers generated by the GPU.

This feature is intended to replace the dedicated IOCTL enabled by TEGRA_STAGING and to provide a non-staging alternative to that solution.

Signed-off-by Alexandre Courbot <[email protected]>
---
 drivers/gpu/drm/tegra/drm.c   |  2 ++
 drivers/gpu/drm/tegra/fb.c    | 23 +++++++++++++++++++---
 include/uapi/drm/drm_fourcc.h | 45 +++++++++++++++++++++++++++++++++++++++++++
 3 files changed, 67 insertions(+), 3 deletions(-)
drivers/gpu/drm/tegra/drm.c +2 -0
index a9630c2d6cb3..36b4b30a5164 100644
@@ -161,6 +161,8 @@ static int tegra_drm_load(struct drm_device *drm, unsigned long flags)
        drm->mode_config.max_width = 4096;
        drm->mode_config.max_height = 4096;
 
+       drm->mode_config.allow_fb_modifiers = true;
+
        drm->mode_config.funcs = &tegra_drm_mode_funcs;
 
        err = tegra_drm_fb_prepare(drm);
drivers/gpu/drm/tegra/fb.c +8 -3
index e6d71fa4028e..2fded58b2ca5 100644
@@ -52,9 +52,26 @@ int tegra_fb_get_tiling(struct drm_framebuffer *framebuffer,
                        struct tegra_bo_tiling *tiling)
 {
        struct tegra_fb *fb = to_tegra_fb(framebuffer);
-
-       /* TODO: handle YUV formats? */
-       *tiling = fb->planes[0]->tiling;
+       uint64_t modifier = fb->base.modifier[0];
+
+       switch (fourcc_mod_tegra_mod(modifier)) {
+       case NV_FORMAT_MOD_TEGRA_TILED:
+               tiling->mode = TEGRA_BO_TILING_MODE_TILED;
+               tiling->value = 0;
+               break;
+
Quoted 8 lines

drivers/gpu/drm/tegra/fb.c int tegra_fb_get_tiling(struct drm_framebuffer *framebuffer, · line 67

Quoted 5 lines
drivers/gpu/drm/tegra/fb.c +5 -0
+       case NV_FORMAT_MOD_TEGRA_16BX2_BLOCK(0):
+               tiling->mode = TEGRA_BO_TILING_MODE_BLOCK;
+               tiling->value = fourcc_mod_tegra_param(modifier);
+               if (tiling->value > 5)
+                       return -EINVAL;

Shouldn't this contain some hardware-check for the support? AFAIK, not all Tegras support all block-heights (if even this mode at all?)...

Quoted 5 lines

tegra_dc_setup_window does that check later (check the test on dc->soc->supports_block_linear). At the moment no error message is displayed though (and it seems like we are writing a stale value in DC_WIN_BUFFER_ADDR_MODE if the SoC doesn't support block linear and the tiling mode is TEGRA_BO_TILING_MODE_BLOCK?)

tegra_plane_atomic_check() has a check for this, as well as an error message. ->atomic_check() will always run before actually setting the mode, or applying the plane state, so it effectively guards against a user specifying a format that the hardware doesn't support.

Thierry

_______________________________________________
dri-devel mailing list
[email protected]
https://lists.freedesktop.org/mailman/listinfo/dri-devel

#4 lore raw
In reply to Alexandre Courbot
Quoted 10 lines · Alexandre Courbot

Add FB modifiers to allow user-space to specify that a surface is in one of the two tiling formats supported by Tegra chips, and add support in the tegradrm driver to handle them properly. This is necessary for the display controller to directly display buffers generated by the GPU.

This feature is intended to replace the dedicated IOCTL enabled by TEGRA_STAGING and to provide a non-staging alternative to that solution.

Signed-off-by Alexandre Courbot <[email protected]>

Ack on the drm_fourcc.h part, I think that's the amount of detail in comments that's reasonable. Feel free to merge through tegra trees. -Daniel

Quoted 116 lines
---
 drivers/gpu/drm/tegra/drm.c   |  2 ++
 drivers/gpu/drm/tegra/fb.c    | 23 +++++++++++++++++++---
 include/uapi/drm/drm_fourcc.h | 45 +++++++++++++++++++++++++++++++++++++++++++
 3 files changed, 67 insertions(+), 3 deletions(-)
drivers/gpu/drm/tegra/drm.c +2 -0
index a9630c2d6cb3..36b4b30a5164 100644
@@ -161,6 +161,8 @@ static int tegra_drm_load(struct drm_device *drm, unsigned long flags)
 	drm->mode_config.max_width = 4096;
 	drm->mode_config.max_height = 4096;
 
+	drm->mode_config.allow_fb_modifiers = true;
+
 	drm->mode_config.funcs = &tegra_drm_mode_funcs;
 
 	err = tegra_drm_fb_prepare(drm);
drivers/gpu/drm/tegra/fb.c +20 -3
index e6d71fa4028e..2fded58b2ca5 100644
@@ -52,9 +52,26 @@ int tegra_fb_get_tiling(struct drm_framebuffer *framebuffer,
 			struct tegra_bo_tiling *tiling)
 {
 	struct tegra_fb *fb = to_tegra_fb(framebuffer);
-
-	/* TODO: handle YUV formats? */
-	*tiling = fb->planes[0]->tiling;
+	uint64_t modifier = fb->base.modifier[0];
+
+	switch (fourcc_mod_tegra_mod(modifier)) {
+	case NV_FORMAT_MOD_TEGRA_TILED:
+		tiling->mode = TEGRA_BO_TILING_MODE_TILED;
+		tiling->value = 0;
+		break;
+
+	case NV_FORMAT_MOD_TEGRA_16BX2_BLOCK(0):
+		tiling->mode = TEGRA_BO_TILING_MODE_BLOCK;
+		tiling->value = fourcc_mod_tegra_param(modifier);
+		if (tiling->value > 5)
+			return -EINVAL;
+		break;
+
+	default:
+		/* TODO: handle YUV formats? */
+		*tiling = fb->planes[0]->tiling;
+		break;
+	}
 
 	return 0;
 }
include/uapi/drm/drm_fourcc.h +45 -0
index a5890bf44c0a..967dfab16881 100644
@@ -233,6 +233,51 @@ extern "C" {
  */
 #define DRM_FORMAT_MOD_SAMSUNG_64_32_TILE	fourcc_mod_code(SAMSUNG, 1)
 
+
+/* NVIDIA Tegra frame buffer modifiers */
+
+/*
+ * Some modifiers take parameters, for example the number of vertical GOBs in
+ * a block. Reserve the lower 32 bits for parameters
+ */
+#define __fourcc_mod_tegra_mode_shift 32
+#define fourcc_mod_tegra_code(val, params) \
+	fourcc_mod_code(NV, ((((__u64)val) << __fourcc_mod_tegra_mode_shift) | params))
+#define fourcc_mod_tegra_mod(m) \
+	(m & ~((1ULL << __fourcc_mod_tegra_mode_shift) - 1))
+#define fourcc_mod_tegra_param(m) \
+	(m & ((1ULL << __fourcc_mod_tegra_mode_shift) - 1))
+
+/*
+ * Tegra Tiled Layout, used by Tegra 2, 3 and 4.
+ *
+ * Pixels are arranged in simple tiles of 16 x 16 bytes.
+ */
+#define NV_FORMAT_MOD_TEGRA_TILED fourcc_mod_tegra_code(1, 0)
+
+/*
+ * Tegra 16Bx2 Block Linear layout, used by TK1/TX1
+ *
+ * Pixels are arranged in 64x8 Groups Of Bytes (GOBs). GOBs are then stacked
+ * vertically by a power of 2 (1 to 32 GOBs) to form a block.
+ *
+ * Within a GOB, data is ordered as 16B x 2 lines sectors laid in Z-shape.
+ *
+ * Parameter 'v' is the log2 encoding of the number of GOBs stacked vertically.
+ * Valid values are:
+ *
+ * 0 == ONE_GOB
+ * 1 == TWO_GOBS
+ * 2 == FOUR_GOBS
+ * 3 == EIGHT_GOBS
+ * 4 == SIXTEEN_GOBS
+ * 5 == THIRTYTWO_GOBS
+ *
+ * Chapter 20 "Pixel Memory Formats" of the Tegra X1 TRM describes this format
+ * in full detail.
+ */
+#define NV_FORMAT_MOD_TEGRA_16BX2_BLOCK(v) fourcc_mod_tegra_code(2, v)
+
 #if defined(__cplusplus)
 }
 #endif
Signature · 6 lines
2.10.2

_______________________________________________
dri-devel mailing list
[email protected]
https://lists.freedesktop.org/mailman/listinfo/dri-devel
Signature · 7 lines
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
_______________________________________________
dri-devel mailing list
[email protected]
https://lists.freedesktop.org/mailman/listinfo/dri-devel
Applied
#5 lore raw
In reply to Alexandre Courbot
Quoted 9 lines · Alexandre Courbot

Add FB modifiers to allow user-space to specify that a surface is in one of the two tiling formats supported by Tegra chips, and add support in the tegradrm driver to handle them properly. This is necessary for the display controller to directly display buffers generated by the GPU.

This feature is intended to replace the dedicated IOCTL enabled by TEGRA_STAGING and to provide a non-staging alternative to that solution.

Quoted 6 lines
Signed-off-by Alexandre Courbot <[email protected]>
---
 drivers/gpu/drm/tegra/drm.c   |  2 ++
 drivers/gpu/drm/tegra/fb.c    | 23 +++++++++++++++++++---
 include/uapi/drm/drm_fourcc.h | 45 +++++++++++++++++++++++++++++++++++++++++++
 3 files changed, 67 insertions(+), 3 deletions(-)

Applied, thanks.

Thierry

_______________________________________________
dri-devel mailing list
[email protected]
https://lists.freedesktop.org/mailman/listinfo/dri-devel