MIPS: add support for XBurst cores
PATCH v3 1/2 MIPS: add support for XBurst cores
The Ingenic XBurst is a MIPS32R2 microprocessor.
It has a bug in the FPU that can generate incorrect results in certain cases. The problem shows up when you have several fused madd instructions in sequence with dependant operands.
Using the -mno-fused-madd option prevents gcc from emitting these instructions. This patch adds changes to the toolchain wrapper to use that option.
---
Changes v2 -> v3:
- Improve commit log and add help section. (Suggested by Arnout)
Changes v1 -> v2:
- Do not add -mmxu to the wrapper.
--- arch/Config.in.mips | 14 ++++++++++++++ toolchain/toolchain-wrapper.c | 3 +++ toolchain/toolchain-wrapper.mk | 5 +++++ 3 files changed, 22 insertions(+)
arch/Config.in.mips +14 -0
@@ -63,6 +63,19 @@ config BR2_mips_p5600 bool "P5600" depends on !BR2_ARCH_IS_64 select BR2_MIPS_CPU_MIPS32R5 +config BR2_mips_xburst + bool "XBurst" + depends on !BR2_ARCH_IS_64 + select BR2_MIPS_CPU_MIPS32R2 + help + The Ingenic XBurst is a MIPS32R2 microprocessor. It has a bug + in the FPU that can generate incorrect results in certain + cases. The problem shows up when you have several fused madd + instructions in sequence with dependant operands. This + requires the -mno-fused-madd compiler option to be used in + order to prevent emitting these instructions. + + See http://www.ingenic.com/en/?xburst.html config BR2_mips_64 bool "Generic MIPS64" depends on BR2_ARCH_IS_64
@@ -137,6 +150,7 @@ config BR2_GCC_TARGET_ARCH default "m5101" if BR2_mips_m5101 default "m6201" if BR2_mips_m6201 default "p5600" if BR2_mips_p5600 + default "mips32r2" if BR2_mips_xburst default "mips64" if BR2_mips_64 default "mips64r2" if BR2_mips_64r2 default "mips64r5" if BR2_mips_64r5
toolchain/toolchain-wrapper.c +3 -0
@@ -66,6 +66,9 @@ static char *predef_args[] = {#ifdef BR_OMIT_LOCK_PREFIX "-Wa,-momit-lock-prefix=yes",#endif +#ifdef BR_NO_FUSED_MADD + "-mno-fused-madd", +#endif #ifdef BR_BINFMT_FLAT "-Wl,-elf2flt",#endif
toolchain/toolchain-wrapper.mk +5 -0
@@ -26,6 +26,11 @@ ifeq ($(BR2_x86_x1000),y) TOOLCHAIN_WRAPPER_ARGS += -DBR_OMIT_LOCK_PREFIX endif +# Avoid FPU bug on XBurst CPUs +ifeq ($(BR2_mips_xburst),y) +TOOLCHAIN_WRAPPER_ARGS += -DBR_NO_FUSED_MADD +endif + ifeq ($(BR2_CCACHE_USE_BASEDIR),y) TOOLCHAIN_WRAPPER_ARGS += -DBR_CCACHE_BASEDIR='"$(BASE_DIR)"' endif
Signature · 1 line
2.10.1
PATCH v3 2/2 ci20_defconfig: use XBurst CPU
---
Changes v1 -> v3:
- None.
--- configs/ci20_defconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
configs/ci20_defconfig +1 -1
@@ -1,6 +1,6 @@ # architecture BR2_mipsel=y -BR2_mips_32r2=y +BR2_mips_xburst=y # BR2_MIPS_SOFT_FLOAT is not set # Linux headers same as kernel, a 3.18 series
Signature · 1 line
2.10.1
PATCH v3 1/2 MIPS: add support for XBurst cores
In reply to Vicente Olivert RieraHello,
Quoted 16 lines · Vicente Olivert Riera
The Ingenic XBurst is a MIPS32R2 microprocessor.
It has a bug in the FPU that can generate incorrect results in certain cases. The problem shows up when you have several fused madd instructions in sequence with dependant operands.
Using the -mno-fused-madd option prevents gcc from emitting these instructions. This patch adds changes to the toolchain wrapper to use that option.
Signed-off-by Vicente Olivert Riera <[email protected]>---
Changes v2 -> v3:
- Improve commit log and add help section. (Suggested by Arnout)
Changes v1 -> v2:
- Do not add -mmxu to the wrapper.
Quoted 5 lines
--- arch/Config.in.mips | 14 ++++++++++++++ toolchain/toolchain-wrapper.c | 3 +++ toolchain/toolchain-wrapper.mk | 5 +++++ 3 files changed, 22 insertions(+)
I've applied both patches to master. Even though it's adding a new architecture entry, it's really a bug fix needed for the ci20_defconfig, which is why I've chosen to apply this to master.
Thanks!
Thomas
Signature · 3 lines
Thomas Petazzoni, CTO, Free Electrons Embedded Linux, Kernel and Android engineering http://free-electrons.com