imx: add imx6ull support
Subsystems (7)
v2 cover imx: add imx6ull support
Hi Shawn,
In this series, it adds support for imx6ull SoC which is a derived SoC from imx6ul, and imx6ull is pin-to-pin compatible with imx6ul, the basic functions are tested at imx6ull 14x14 evk, and imx6ul 14x14 evk is tested too to avoid regression.
Changes for v2:
- Keep imx6ul.dtsi unchanging, and using GPL/X11 dual license for new dts file. [Patch 1/3]
- Using IMX6ULL prefix for both imx6ull dedicated pin and clock name. [Patch 1/3, 3/3]
- Delete useless changes for patch 2/3.
- Delete blank line for patch 3/3.
- Using assigned-clocks for imx6ull 14x14 evk. [Patch 1/3, 3/3]
Bai Ping (1):
clk: imx: clk-imx6ul: add clk support for imx6ull
Peter Chen (2):
ARM: imx6ull: add imx6ull support
ARM: imx: mach-imx6ul: add imx6ull support
arch/arm/boot/dts/Makefile | 3 +- arch/arm/boot/dts/imx6u-14x14-evk.dtsi | 487 +++++++++++++++++++++++++++++++ arch/arm/boot/dts/imx6ul-14x14-evk.dts | 479 +----------------------------- arch/arm/boot/dts/imx6ull-14x14-evk.dts | 55 ++++ arch/arm/boot/dts/imx6ull-pinfunc.h | 56 ++++ arch/arm/boot/dts/imx6ull.dtsi | 43 +++ arch/arm/mach-imx/mach-imx6ul.c | 1 + drivers/clk/imx/clk-imx6ul.c | 72 ++++- include/dt-bindings/clock/imx6ul-clock.h | 15 +- 9 files changed, 720 insertions(+), 491 deletions(-) create mode 100644 arch/arm/boot/dts/imx6u-14x14-evk.dtsi create mode 100644 arch/arm/boot/dts/imx6ull-14x14-evk.dts create mode 100644 arch/arm/boot/dts/imx6ull-pinfunc.h create mode 100644 arch/arm/boot/dts/imx6ull.dtsi
Signature · 1 line
2.7.4
PATCH v2 1/3 ARM: imx6ull: add imx6ull support
It is the 10th processor in the well-known imx6 series, and derived from imx6ul but cost optimized. The more information about imx6ull can be found at:
http://www.nxp.com/products/microcontrollers-and-processors/
arm-processors/i.mx-applications-processors/i.mx-6-processors /i.mx6qp/i.mx-6ull-single-core-processor-with-arm-cortex-a7-core :i.MX6ULL
In this patch, for SoC part, the imx6ull.dtsi includes imx6ul.dtsi; for board part (imx6ul/imx6ull 14x14 evk), it has a common board file imx6u-14x14-evk.dtsi, and this file is included by both imx6ul-14x14-evk.dts and imx6ull-14x14-evk.dts.
--- arch/arm/boot/dts/Makefile | 3 +- arch/arm/boot/dts/imx6u-14x14-evk.dtsi | 487 ++++++++++++++++++++++++++++++++ arch/arm/boot/dts/imx6ul-14x14-evk.dts | 479 +------------------------------ arch/arm/boot/dts/imx6ull-14x14-evk.dts | 55 ++++ arch/arm/boot/dts/imx6ull-pinfunc.h | 56 ++++ arch/arm/boot/dts/imx6ull.dtsi | 43 +++ 6 files changed, 644 insertions(+), 479 deletions(-) create mode 100644 arch/arm/boot/dts/imx6u-14x14-evk.dtsi create mode 100644 arch/arm/boot/dts/imx6ull-14x14-evk.dts create mode 100644 arch/arm/boot/dts/imx6ull-pinfunc.h create mode 100644 arch/arm/boot/dts/imx6ull.dtsi
arch/arm/boot/dts/Makefile +2 -1
@@ -423,7 +423,8 @@ dtb-$(CONFIG_SOC_IMX6UL) += \ imx6ul-pico-hobbit.dtb \ imx6ul-tx6ul-0010.dtb \ imx6ul-tx6ul-0011.dtb \ - imx6ul-tx6ul-mainboard.dtb + imx6ul-tx6ul-mainboard.dtb \ + imx6ull-14x14-evk.dtb dtb-$(CONFIG_SOC_IMX7D) += \ imx7d-cl-som-imx7.dtb \ imx7d-colibri-eval-v3.dtb \
arch/arm/boot/dts/imx6u-14x14-evk.dtsi new file +487 -0
487 lines not on this page · raw message
arch/arm/boot/dts/imx6ul-14x14-evk.dts +1 -478
487 lines not on this page · raw message
arch/arm/boot/dts/imx6ull-14x14-evk.dts new file +55 -0
55 lines not on this page · raw message
arch/arm/boot/dts/imx6ull-pinfunc.h new file +56 -0
56 lines not on this page · raw message
arch/arm/boot/dts/imx6ull.dtsi new file +43 -0
43 lines not on this page · raw message
Signature · 1 line
2.7.4
PATCH v2 1/3 ARM: imx6ull: add imx6ull support
Quoted 14 lines · Peter Chen
It is the 10th processor in the well-known imx6 series, and derived from imx6ul but cost optimized. The more information about imx6ull can be found at:
http://www.nxp.com/products/microcontrollers-and-processors/
arm-processors/i.mx-applications-processors/i.mx-6-processors /i.mx6qp/i.mx-6ull-single-core-processor-with-arm-cortex-a7-core :i.MX6ULLIn this patch, for SoC part, the
imx6ull.dtsiincludesimx6ul.dtsi; for board part (imx6ul/imx6ull 14x14 evk), it has a common board fileimx6u-14x14-evk.dtsi, and this file is included by bothimx6ul-14x14-evk.dtsandimx6ull-14x14-evk.dts.
Quoted 5 lines
Signed-off-by Peter Chen <[email protected]>--- arch/arm/boot/dts/Makefile | 3 +- arch/arm/boot/dts/imx6u-14x14-evk.dtsi | 487 ++++++++++++++++++++++++++++++++ arch/arm/boot/dts/imx6ul-14x14-evk.dts | 479 +------------------------------
What's the real change between imx6u-14x14-evk.dtsi and imx6ul-14x14-evk.dts? Instead of renaming the file, I would like to have imx6ull-14x14-evk.dts include imx6ul-14x14-evk.dts directly, if we can work out the difference within imx6ull-14x14-evk.dts.
Shawn
Quoted 8 lines
arch/arm/boot/dts/imx6ull-14x14-evk.dts | 55 ++++ arch/arm/boot/dts/imx6ull-pinfunc.h | 56 ++++ arch/arm/boot/dts/imx6ull.dtsi | 43 +++ 6 files changed, 644 insertions(+), 479 deletions(-) create mode 100644 arch/arm/boot/dts/imx6u-14x14-evk.dtsi create mode 100644 arch/arm/boot/dts/imx6ull-14x14-evk.dts create mode 100644 arch/arm/boot/dts/imx6ull-pinfunc.h create mode 100644 arch/arm/boot/dts/imx6ull.dtsi
PATCH v2 1/3 ARM: imx6ull: add imx6ull support
Best regards,
Peter Chen
Quoted 33 lines
-----Original Message-----
From: Shawn Guo [mailto:shawnguo at kernel.org]
Sent: Monday, November 14, 2016 1:49 PM
To: Peter Chen <[email protected]>
Cc: sboyd at codeaurora.org; mturquette at baylibre.com; linux-arm- kernel at lists.infradead.org; kernel at pengutronix.de; devicetree at vger.kernel.org; robh+dt at kernel.org; Fabio Estevam <[email protected]>; mark.rutland at arm.com; linux-clk at vger.kernel.org
Subject: Re: [PATCH v2 1/3] ARM: imx6ull: add imx6ull supportQuoted 14 lines · Peter Chen
It is the 10th processor in the well-known imx6 series, and derived from imx6ul but cost optimized. The more information about imx6ull can be found at:
http://www.nxp.com/products/microcontrollers-and-processors/
arm-processors/i.mx-applications-processors/i.mx-6-processors /i.mx6qp/i.mx-6ull-single-core-processor-with-arm-cortex-a7-core :i.MX6ULLIn this patch, for SoC part, the
imx6ull.dtsiincludesimx6ul.dtsi; for board part (imx6ul/imx6ull 14x14 evk), it has a common board fileimx6u-14x14-evk.dtsi, and this file is included by bothimx6ul-14x14-evk.dtsandimx6ull-14x14-evk.dts.Quoted 7 lines
Signed-off-by Peter Chen <[email protected]>--- arch/arm/boot/dts/Makefile | 3 +- arch/arm/boot/dts/imx6u-14x14-evk.dtsi | 487++++++++++++++++++++++++++++++++
arch/arm/boot/dts/imx6ul-14x14-evk.dts| 479
+------------------------------
Quoted 5 lines
What's the real change between
imx6u-14x14-evk.dtsiandimx6ul-14x14-evk.dts? Instead of renaming the file, I would like to haveimx6ull-14x14-evk.dtsincludeimx6ul-14x14-evk.dtsdirectly, if we can work out the difference within imx6ull-14x14-evk.dts.
The main difference is compatible string, I can't include two compatible strings in one dts file, the dts build will fail for that.
imx6ull-14x14-evk.dts
/ {
model = "Freescale i.MX6 UlltraLite 14x14 EVK Board";
compatible = "fsl,imx6ull-14x14-evk", "fsl,imx6ull";
};imx6ul-14x14-evk.dts
/ {
model = "Freescale i.MX6 UltraLite 14x14 EVK Board";
compatible = "fsl,imx6ul-14x14-evk", "fsl,imx6ul";
};Peter
PATCH v2 1/3 ARM: imx6ull: add imx6ull support
Quoted 9 lines · Peter Chen
The main difference is compatible string, I can't include two compatible strings in one dts file, the dts build will fail for that.
imx6ull-14x14-evk.dts/ { model = "Freescale i.MX6 UlltraLite 14x14 EVK Board"; compatible = "fsl,imx6ull-14x14-evk", "fsl,imx6ull"; };
Quoted 5 lines
imx6ul-14x14-evk.dts/ { model = "Freescale i.MX6 UltraLite 14x14 EVK Board"; compatible = "fsl,imx6ul-14x14-evk", "fsl,imx6ul"; };
I created imx6ull-14x14-evk.dts like below, and DTC seems happy with it.
#include "imx6ul-14x14-evk.dts"
/ {
model = "Freescale i.MX6 UlltraLite 14x14 EVK Board";
compatible = "fsl,imx6ull-14x14-evk", "fsl,imx6ull";
};Shawn
PATCH v2 1/3 ARM: imx6ull: add imx6ull support
Quoted 15 lines · Peter Chen
Quoted 4 lines
The main difference is compatible string, I can't include two compatible strings in one dts file, the dts build will fail for that.
imx6ull-14x14-evk.dtsQuoted 8 lines
/ { model = "Freescale i.MX6 UlltraLite 14x14 EVK Board"; compatible = "fsl,imx6ull-14x14-evk", "fsl,imx6ull"; };
imx6ul-14x14-evk.dts/ { model = "Freescale i.MX6 UltraLite 14x14 EVK Board"; compatible = "fsl,imx6ul-14x14-evk", "fsl,imx6ul"; };
Quoted 8 lines
I created
imx6ull-14x14-evk.dtslike below, and DTC seems happy with it.#include "
imx6ul-14x14-evk.dts"/ { model = "Freescale i.MX6 UlltraLite 14x14 EVK Board"; compatible = "fsl,imx6ull-14x14-evk", "fsl,imx6ull"; };
Thanks for trying it, the problem why my dtc building fail is I have two
" /dts-v1/;" at dts file (one is from imx6ul-14x14-evk.dts) . I will follow your suggestion.
Peter
PATCH v2 2/3 ARM: imx: mach-imx6ul: add imx6ull support
In reply to Peter Chenimx6ull is derived SoC from imx6ul.
--- arch/arm/mach-imx/mach-imx6ul.c | 1 + 1 file changed, 1 insertion(+)
arch/arm/mach-imx/mach-imx6ul.c +1 -0
@@ -89,6 +89,7 @@ static void __init imx6ul_init_late(void)static const char *const imx6ul_dt_compat[]__initconst = {"fsl,imx6ul" , +"fsl,imx6ull" ,NULL , };
Signature · 1 line
2.7.4
PATCH v2 3/3 clk: imx: clk-imx6ul: add clk support for imx6ull
In reply to Peter ChenFrom: Bai Ping <[email protected]>
imx6ull is the derived SoC from imx6ul
--- drivers/clk/imx/clk-imx6ul.c | 72 +++++++++++++++++++++++++++----- include/dt-bindings/clock/imx6ul-clock.h | 15 ++++++- 2 files changed, 75 insertions(+), 12 deletions(-)
drivers/clk/imx/clk-imx6ul.c +61 -11
@@ -64,6 +64,10 @@ static const char *perclk_sels[] = { "ipg", "osc", };static const char *lcdif_sels[] = {"lcdif_podf" ,"ipp_di0" ,"ipp_di1" ,"ldb_di0" ,"ldb_di1" , };static const char *csi_sels[] = {"osc" ,"pll2_pfd2_396m" ,"pll3_120m" ,"pll3_pfd1_540m" , };static const char *sim_sels[] = {"sim_podf" ,"ipp_di0" ,"ipp_di1" ,"ldb_di0" ,"ldb_di1" , }; +/* epdc_pre_sels, epdc_sels, esai_sels only exists on i.MX6ULL */ +static const char *epdc_pre_sels[] = {"pll2_bus" ,"pll3_usb_otg" ,"pll5_video_div" ,"pll2_pfd0_352m" ,"pll2_pfd2_396m" ,"pll3_pfd2_508m" , }; +static const char *esai_sels[] = {"pll4_audio_div" ,"pll3_pfd2_508m" ,"pll5_video_div" ,"pll3_usb_otg" , }; +static const char *epdc_sels[] = {"epdc_podf" ,"ipp_di0" ,"ipp_di1" ,"ldb_di0" ,"ldb_di1" , };static struct clk *clks[IMX6UL_CLK_END ];static struct clk_onecell_data clk_data;
@@ -102,6 +106,17 @@ static u32 share_count_audio;static u32 share_count_sai1;static u32 share_count_sai2;static u32 share_count_sai3; +static u32 share_count_esai; + +static inline int clk_on_imx6ul (void ) +{ +return of_machine_is_compatible ("fsl,imx6ul" ); +} + +static inline int clk_on_imx6ull (void ) +{ +return of_machine_is_compatible ("fsl,imx6ull" ); +}static void __init imx6ul_clocks_init (struct device_node *ccm_node) {
@@ -238,12 +253,19 @@ static void __init imx6ul_clocks_init(struct device_node *ccm_node) clks[IMX6UL_CLK_QSPI1_SEL ] =imx_clk_mux ("qspi1_sel" , base +0x1c ,7 ,3 , qspi1_sels,ARRAY_SIZE (qspi1_sels)); clks[IMX6UL_CLK_PERCLK_SEL ] =imx_clk_mux ("perclk_sel" , base +0x1c ,6 ,1 , perclk_sels,ARRAY_SIZE (perclk_sels)); clks[IMX6UL_CLK_CAN_SEL ] =imx_clk_mux ("can_sel" , base +0x20 ,8 ,2 , can_sels,ARRAY_SIZE (can_sels)); +if (clk_on_imx6ull ()) + clks[IMX6ULL_CLK_ESAI_SEL ] =imx_clk_mux ("esai_sel" , base +0x20 ,19 ,2 , esai_sels,ARRAY_SIZE (esai_sels)); clks[IMX6UL_CLK_UART_SEL ] =imx_clk_mux ("uart_sel" , base +0x24 ,6 ,1 , uart_sels,ARRAY_SIZE (uart_sels)); clks[IMX6UL_CLK_ENFC_SEL ] =imx_clk_mux ("enfc_sel" , base +0x2c ,15 ,3 , enfc_sels,ARRAY_SIZE (enfc_sels)); clks[IMX6UL_CLK_LDB_DI0_SEL ] =imx_clk_mux ("ldb_di0_sel" , base +0x2c ,9 ,3 , ldb_di0_sels,ARRAY_SIZE (ldb_di0_sels)); clks[IMX6UL_CLK_SPDIF_SEL ] =imx_clk_mux ("spdif_sel" , base +0x30 ,20 ,2 , spdif_sels,ARRAY_SIZE (spdif_sels)); - clks[IMX6UL_CLK_SIM_PRE_SEL ] =imx_clk_mux ("sim_pre_sel" , base +0x34 ,15 ,3 , sim_pre_sels,ARRAY_SIZE (sim_pre_sels)); - clks[IMX6UL_CLK_SIM_SEL ] =imx_clk_mux ("sim_sel" , base +0x34 ,9 ,3 , sim_sels,ARRAY_SIZE (sim_sels)); +if (clk_on_imx6ul ()) { + clks[IMX6UL_CLK_SIM_PRE_SEL ] =imx_clk_mux ("sim_pre_sel" , base +0x34 ,15 ,3 , sim_pre_sels,ARRAY_SIZE (sim_pre_sels)); + clks[IMX6UL_CLK_SIM_SEL ] =imx_clk_mux ("sim_sel" , base +0x34 ,9 ,3 , sim_sels,ARRAY_SIZE (sim_sels)); + }else if (clk_on_imx6ull ()) { + clks[IMX6ULL_CLK_EPDC_PRE_SEL ] =imx_clk_mux ("epdc_pre_sel" , base +0x34 ,15 ,3 , epdc_pre_sels,ARRAY_SIZE (epdc_pre_sels)); + clks[IMX6ULL_CLK_EPDC_SEL ] =imx_clk_mux ("epdc_sel" , base +0x34 ,9 ,3 , epdc_sels,ARRAY_SIZE (epdc_sels)); + } clks[IMX6UL_CLK_ECSPI_SEL ] =imx_clk_mux ("ecspi_sel" , base +0x38 ,18 ,1 , ecspi_sels,ARRAY_SIZE (ecspi_sels)); clks[IMX6UL_CLK_LCDIF_PRE_SEL ] =imx_clk_mux ("lcdif_pre_sel" , base +0x38 ,15 ,3 , lcdif_pre_sels,ARRAY_SIZE (lcdif_pre_sels)); clks[IMX6UL_CLK_LCDIF_SEL ] =imx_clk_mux ("lcdif_sel" , base +0x38 ,9 ,3 , lcdif_sels,ARRAY_SIZE (lcdif_sels));
@@ -276,6 +298,10 @@ static void __init imx6ul_clocks_init(struct device_node *ccm_node) clks[IMX6UL_CLK_SAI3_PODF ] =imx_clk_divider ("sai3_podf" ,"sai3_pred" , base +0x28 ,16 ,6 ); clks[IMX6UL_CLK_SAI1_PRED ] =imx_clk_divider ("sai1_pred" ,"sai1_sel" , base +0x28 ,6 ,3 ); clks[IMX6UL_CLK_SAI1_PODF ] =imx_clk_divider ("sai1_podf" ,"sai1_pred" , base +0x28 ,0 ,6 ); +if (clk_on_imx6ull ()) { + clks[IMX6ULL_CLK_ESAI_PRED ] =imx_clk_divider ("esai_pred" ,"esai_sel" , base +0x28 ,9 ,3 ); + clks[IMX6ULL_CLK_ESAI_PODF ] =imx_clk_divider ("esai_podf" ,"esai_pred" , base +0x28 ,25 ,3 ); + } clks[IMX6UL_CLK_ENFC_PRED ] =imx_clk_divider ("enfc_pred" ,"enfc_sel" , base +0x2c ,18 ,3 ); clks[IMX6UL_CLK_ENFC_PODF ] =imx_clk_divider ("enfc_podf" ,"enfc_pred" , base +0x2c ,21 ,6 ); clks[IMX6UL_CLK_SAI2_PRED ] =imx_clk_divider ("sai2_pred" ,"sai2_sel" , base +0x2c ,6 ,3 );
@@ -298,9 +324,15 @@ static void __init imx6ul_clocks_init(struct device_node *ccm_node) clks[IMX6UL_CLK_APBHDMA ] =imx_clk_gate2 ("apbh_dma" ,"bch_podf" , base +0x68 ,4 ); clks[IMX6UL_CLK_ASRC_IPG ] =imx_clk_gate2_shared ("asrc_ipg" ,"ahb" , base +0x68 ,6 , &share_count_asrc); clks[IMX6UL_CLK_ASRC_MEM ] =imx_clk_gate2_shared ("asrc_mem" ,"ahb" , base +0x68 ,6 , &share_count_asrc); - clks[IMX6UL_CLK_CAAM_MEM ] =imx_clk_gate2 ("caam_mem" ,"ahb" , base +0x68 ,8 ); - clks[IMX6UL_CLK_CAAM_ACLK ] =imx_clk_gate2 ("caam_aclk" ,"ahb" , base +0x68 ,10 ); - clks[IMX6UL_CLK_CAAM_IPG ] =imx_clk_gate2 ("caam_ipg" ,"ipg" , base +0x68 ,12 ); +if (clk_on_imx6ul ()) { + clks[IMX6UL_CLK_CAAM_MEM ] =imx_clk_gate2 ("caam_mem" ,"ahb" , base +0x68 ,8 ); + clks[IMX6UL_CLK_CAAM_ACLK ] =imx_clk_gate2 ("caam_aclk" ,"ahb" , base +0x68 ,10 ); + clks[IMX6UL_CLK_CAAM_IPG ] =imx_clk_gate2 ("caam_ipg" ,"ipg" , base +0x68 ,12 ); + }else if (clk_on_imx6ull ()) { + clks[IMX6ULL_CLK_DCP_CLK ] =imx_clk_gate2 ("dcp" ,"ahb" , base +0x68 ,10 ); + clks[IMX6UL_CLK_ENET ] =imx_clk_gate2 ("enet" ,"ipg" , base +0x68 ,12 ); + clks[IMX6UL_CLK_ENET_AHB ] =imx_clk_gate2 ("enet_ahb" ,"ahb" , base +0x68 ,12 ); + } clks[IMX6UL_CLK_CAN1_IPG ] =imx_clk_gate2 ("can1_ipg" ,"ipg" , base +0x68 ,14 ); clks[IMX6UL_CLK_CAN1_SERIAL ] =imx_clk_gate2 ("can1_serial" ,"can_podf" , base +0x68 ,16 ); clks[IMX6UL_CLK_CAN2_IPG ] =imx_clk_gate2 ("can2_ipg" ,"ipg" , base +0x68 ,18 );
@@ -309,7 +341,10 @@ static void __init imx6ul_clocks_init(struct device_node *ccm_node) clks[IMX6UL_CLK_GPT2_SERIAL ] =imx_clk_gate2 ("gpt2_serial" ,"perclk" , base +0x68 ,26 ); clks[IMX6UL_CLK_UART2_IPG ] =imx_clk_gate2 ("uart2_ipg" ,"ipg" , base +0x68 ,28 ); clks[IMX6UL_CLK_UART2_SERIAL ] =imx_clk_gate2 ("uart2_serial" ,"uart_podf" , base +0x68 ,28 ); - clks[IMX6UL_CLK_AIPSTZ3 ] =imx_clk_gate2 ("aips_tz3" ,"ahb" , base +0x68 ,30 ); +if (clk_on_imx6ul ()) + clks[IMX6UL_CLK_AIPSTZ3 ] =imx_clk_gate2 ("aips_tz3" ,"ahb" , base +0x68 ,30 ); +else if (clk_on_imx6ull ()) + clks[IMX6UL_CLK_AIPSTZ3 ] =imx_clk_gate2 ("aips_tz3" ,"ahb" , base +0x80 ,18 );/* CCGR1 */ clks[IMX6UL_CLK_ECSPI1 ] =imx_clk_gate2 ("ecspi1" ,"ecspi_podf" , base +0x6c ,0 );
@@ -328,6 +363,11 @@ static void __init imx6ul_clocks_init(struct device_node *ccm_node) clks[IMX6UL_CLK_UART4_SERIAL ] =imx_clk_gate2 ("uart4_serail" ,"uart_podf" , base +0x6c ,24 );/* CCGR2 */ +if (clk_on_imx6ull ()) { + clks[IMX6ULL_CLK_ESAI_EXTAL ] =imx_clk_gate2_shared ("esai_extal" ,"esai_podf" , base +0x70 ,0 , &share_count_esai); + clks[IMX6ULL_CLK_ESAI_IPG ] =imx_clk_gate2_shared ("esai_ipg" ,"ahb" , base +0x70 ,0 , &share_count_esai); + clks[IMX6ULL_CLK_ESAI_MEM ] =imx_clk_gate2_shared ("esai_mem" ,"ahb" , base +0x70 ,0 , &share_count_esai); + } clks[IMX6UL_CLK_CSI ] =imx_clk_gate2 ("csi" ,"csi_podf" , base +0x70 ,2 ); clks[IMX6UL_CLK_I2C1 ] =imx_clk_gate2 ("i2c1" ,"perclk" , base +0x70 ,6 ); clks[IMX6UL_CLK_I2C2 ] =imx_clk_gate2 ("i2c2" ,"perclk" , base +0x70 ,8 );
@@ -340,8 +380,13 @@ static void __init imx6ul_clocks_init(struct device_node *ccm_node)/* CCGR3 */ clks[IMX6UL_CLK_UART5_IPG ] =imx_clk_gate2 ("uart5_ipg" ,"ipg" , base +0x74 ,2 ); clks[IMX6UL_CLK_UART5_SERIAL ] =imx_clk_gate2 ("uart5_serial" ,"uart_podf" , base +0x74 ,2 ); - clks[IMX6UL_CLK_ENET ] =imx_clk_gate2 ("enet" ,"ipg" , base +0x74 ,4 ); - clks[IMX6UL_CLK_ENET_AHB ] =imx_clk_gate2 ("enet_ahb" ,"ahb" , base +0x74 ,4 ); +if (clk_on_imx6ul ()) { + clks[IMX6UL_CLK_ENET ] =imx_clk_gate2 ("enet" ,"ipg" , base +0x74 ,4 ); + clks[IMX6UL_CLK_ENET_AHB ] =imx_clk_gate2 ("enet_ahb" ,"ahb" , base +0x74 ,4 ); + }else if (clk_on_imx6ull ()) { + clks[IMX6ULL_CLK_EPDC_ACLK ] =imx_clk_gate2 ("epdc_aclk" ,"axi" , base +0x74 ,4 ); + clks[IMX6ULL_CLK_EPDC_PIX ] =imx_clk_gate2 ("epdc_pix" ,"epdc_podf" , base +0x74 ,4 ); + } clks[IMX6UL_CLK_UART6_IPG ] =imx_clk_gate2 ("uart6_ipg" ,"ipg" , base +0x74 ,6 ); clks[IMX6UL_CLK_UART6_SERIAL ] =imx_clk_gate2 ("uart6_serial" ,"uart_podf" , base +0x74 ,6 ); clks[IMX6UL_CLK_LCDIF_PIX ] =imx_clk_gate2 ("lcdif_pix" ,"lcdif_podf" , base +0x74 ,10 );
@@ -385,8 +430,10 @@ static void __init imx6ul_clocks_init(struct device_node *ccm_node) clks[IMX6UL_CLK_USBOH3 ] =imx_clk_gate2 ("usboh3" ,"ipg" , base +0x80 ,0 ); clks[IMX6UL_CLK_USDHC1 ] =imx_clk_gate2 ("usdhc1" ,"usdhc1_podf" , base +0x80 ,2 ); clks[IMX6UL_CLK_USDHC2 ] =imx_clk_gate2 ("usdhc2" ,"usdhc2_podf" , base +0x80 ,4 ); - clks[IMX6UL_CLK_SIM1 ] =imx_clk_gate2 ("sim1" ,"sim_sel" , base +0x80 ,6 ); - clks[IMX6UL_CLK_SIM2 ] =imx_clk_gate2 ("sim2" ,"sim_sel" , base +0x80 ,8 ); +if (clk_on_imx6ul ()) { + clks[IMX6UL_CLK_SIM1 ] =imx_clk_gate2 ("sim1" ,"sim_sel" , base +0x80 ,6 ); + clks[IMX6UL_CLK_SIM2 ] =imx_clk_gate2 ("sim2" ,"sim_sel" , base +0x80 ,8 ); + } clks[IMX6UL_CLK_EIM ] =imx_clk_gate2 ("eim" ,"eim_slow_podf" , base +0x80 ,10 ); clks[IMX6UL_CLK_PWM8 ] =imx_clk_gate2 ("pwm8" ,"perclk" , base +0x80 ,16 ); clks[IMX6UL_CLK_UART8_IPG ] =imx_clk_gate2 ("uart8_ipg" ,"ipg" , base +0x80 ,14 );
@@ -441,7 +488,10 @@ static void __init imx6ul_clocks_init(struct device_node *ccm_node) }clk_set_parent (clks[IMX6UL_CLK_CAN_SEL ], clks[IMX6UL_CLK_PLL3_60M ]); -clk_set_parent (clks[IMX6UL_CLK_SIM_PRE_SEL ], clks[IMX6UL_CLK_PLL3_USB_OTG ]); +if (clk_on_imx6ul ()) +clk_set_parent (clks[IMX6UL_CLK_SIM_PRE_SEL ], clks[IMX6UL_CLK_PLL3_USB_OTG ]); +else if (clk_on_imx6ull ()) +clk_set_parent (clks[IMX6ULL_CLK_EPDC_PRE_SEL ], clks[IMX6UL_CLK_PLL3_PFD2 ]);clk_set_parent (clks[IMX6UL_CLK_ENFC_SEL ], clks[IMX6UL_CLK_PLL2_PFD2 ]); }
include/dt-bindings/clock/imx6ul-clock.h +14 -1
@@ -236,6 +236,19 @@#define IMX6UL_CLK_PLL3_120M 223#define IMX6UL_CLK_KPP 224 -#define IMX6UL_CLK_END 225 +/* For i.MX6ULL */ +#define IMX6ULL_CLK_ESAI_PRED 225 +#define IMX6ULL_CLK_ESAI_PODF 226 +#define IMX6ULL_CLK_ESAI_EXTAL 227 +#define IMX6ULL_CLK_ESAI_MEM 228 +#define IMX6ULL_CLK_ESAI_IPG 229 +#define IMX6ULL_CLK_DCP_CLK 230 +#define IMX6ULL_CLK_EPDC_PRE_SEL 231 +#define IMX6ULL_CLK_EPDC_SEL 232 +#define IMX6ULL_CLK_EPDC_PODF 233 +#define IMX6ULL_CLK_EPDC_ACLK 234 +#define IMX6ULL_CLK_EPDC_PIX 235 +#define IMX6ULL_CLK_ESAI_SEL 236 +#define IMX6UL_CLK_END 237#endif /* __DT_BINDINGS_CLOCK_IMX6UL_H */
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2.7.4