FPGA changes

RFC PATCH New Chris Packham 3 participants 21 messages Nov 22, 2016 – Nov 25, 2016 FPGA manager framework

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Chris Packham

author

2016-11-22 08:48 UTC #0 lore raw

cover FPGA changes

Patches 1-3,5-6 are moving existing options to Kconfig. I haven't touched all the boards that use these options so they are still present in the whitelist. Hopefully someone more familiar with the zynq boards can build on top of these.

Patches 4 and 7 are the functional changes I actually want to introduce. We have some boards where the FPGA images require the reverse bitstream mode. I think this may be some setting in the Xilinx tools but it seems to be permanently set in the images coming out of our hardware team.

Chris Packham (7):
fpga: CONFIG_SYS_FPGA_PROG_FEEDBACK -> CONFIG_FPGA_PROG_FEEDBACK
fpga: add Kconfig support for Xilinx Spartan devices Move CONFIG_FPGA_SPARTAN options to defconfig fpga/spartan3: make output quieter
fpga: add Kconfig for CONFIG_FPGA_PROG_FEEDBACK
Move FPGA_PROG_FEEDBACK to defconfig
fpga/spartan3: add reverse bitstream mode

 README                           |  2 +-
 board/astro/mcf5373l/fpga.c      |  4 ++--
 configs/PMC440_defconfig         |  3 +++
 configs/apf27_defconfig          |  3 +++
 configs/astro_mcf5373l_defconfig |  3 +++
 configs/mt_ventoux_defconfig     |  3 +++
 configs/x600_defconfig           |  2 ++
 drivers/fpga/ACEX1K.c            |  8 ++++----
 drivers/fpga/Kconfig             | 24 ++++++++++++++++++++++++
 drivers/fpga/cyclon2.c           | 10 +++++-----
 drivers/fpga/spartan2.c          | 22 +++++++++++-----------
 drivers/fpga/spartan3.c          | 32 ++++++++++++++++++++++----------
 drivers/fpga/virtex2.c           | 18 +++++++++---------
 include/configs/M54455EVB.h      |  2 +-
 include/configs/PMC440.h         |  4 ----
 include/configs/apf27.h          |  6 ------
 include/configs/astro_mcf5373l.h |  4 ----
 include/configs/mt_ventoux.h     |  5 -----
 include/configs/x600.h           |  3 ---
 scripts/config_whitelist.txt     |  2 +-
 20 files changed, 94 insertions(+), 66 deletions(-)

Signature · 1 line

2.10.2

Chris Packham

author

2016-11-22 08:48 UTC #1 lore raw

RFC PATCH 1/7 fpga: CONFIG_SYS_FPGA_PROG_FEEDBACK -> CONFIG_FPGA_PROG_FEEDBACK

Prepare for move to Kconfig by removing "SYS" from the existing macros.

Signed-off-by Chris Packham <[email protected]>

---

 README                           |  2 +-
 board/astro/mcf5373l/fpga.c      |  4 ++--
 drivers/fpga/ACEX1K.c            |  8 ++++----
 drivers/fpga/cyclon2.c           | 10 +++++-----
 drivers/fpga/spartan2.c          | 22 +++++++++++-----------
 drivers/fpga/spartan3.c          | 20 ++++++++++----------
 drivers/fpga/virtex2.c           | 18 +++++++++---------
 include/configs/M54455EVB.h      |  2 +-
 include/configs/apf27.h          |  2 +-
 include/configs/astro_mcf5373l.h |  2 +-
 include/configs/mt_ventoux.h     |  4 ++--
 scripts/config_whitelist.txt     |  2 +-
 12 files changed, 48 insertions(+), 48 deletions(-)

README +1 -1

index 47bc215fe9c5..fdc194ab9792 100644
@@ -2536,7 +2536,7 @@ The following options need to be configured:
 		Enable support for fpga loadbp command - load partial bitstream
 		(Xilinx only)
 
-		CONFIG_SYS_FPGA_PROG_FEEDBACK
+		CONFIG_FPGA_PROG_FEEDBACK
 
 		Enable printing of hash marks during FPGA configuration.

board/astro/mcf5373l/fpga.c +2 -2

index 53e00728c3d8..1b53fd2521e3 100644
@@ -128,7 +128,7 @@ int altera_write_fn(const void *buf, size_t len, int flush, int cookie)
 #if defined(CONFIG_HW_WATCHDOG) || defined(CONFIG_WATCHDOG)
 			WATCHDOG_RESET();
 #endif
-#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
+#ifdef CONFIG_FPGA_PROG_FEEDBACK
 			putc('.');	/* let them know we are alive */
 #endif
 #ifdef CONFIG_SYS_FPGA_CHECK_CTRLC

@@ -347,7 +347,7 @@ int xilinx_fastwr_config_fn(void *buf, size_t len, int flush, int cookie)
 #if defined(CONFIG_HW_WATCHDOG) || defined(CONFIG_WATCHDOG)
 			WATCHDOG_RESET();
 #endif
-#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
+#ifdef CONFIG_FPGA_PROG_FEEDBACK
 			putc('.');	/* let them know we are alive */
 #endif
 #ifdef CONFIG_SYS_FPGA_CHECK_CTRLC

drivers/fpga/ACEX1K.c +4 -4

index 1627f0e6ffde..1fb60e5983c3 100644
@@ -112,7 +112,7 @@ static int ACEX1K_ps_load(Altera_desc *desc, const void *buf, size_t bsize)
 				"done:\t0x%p\n\n",
 				__FUNCTION__, &fn, fn, fn->config, fn->status,
 				fn->clk, fn->data, fn->done);
-#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
+#ifdef CONFIG_FPGA_PROG_FEEDBACK
 		printf ("Loading FPGA Device %d...", cookie);
 #endif

@@ -188,7 +188,7 @@ static int ACEX1K_ps_load(Altera_desc *desc, const void *buf, size_t bsize)
 				i --;
 			} while (i > 0);
 
-#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
+#ifdef CONFIG_FPGA_PROG_FEEDBACK
 			if (bytecount % (bsize / 40) == 0)
 				putc ('.');		/* let them know we are alive */
 #endif

@@ -196,7 +196,7 @@ static int ACEX1K_ps_load(Altera_desc *desc, const void *buf, size_t bsize)
 
 		CONFIG_FPGA_DELAY ();
 
-#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
+#ifdef CONFIG_FPGA_PROG_FEEDBACK
 		putc (' ');			/* terminate the dotted line */
 #endif

@@ -223,7 +223,7 @@ static int ACEX1K_ps_load(Altera_desc *desc, const void *buf, size_t bsize)
 
 	ret_val = FPGA_SUCCESS;
 
-#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
+#ifdef CONFIG_FPGA_PROG_FEEDBACK
 		if (ret_val == FPGA_SUCCESS) {
 			puts ("Done.\n");
 		}

drivers/fpga/cyclon2.c +5 -5

index 8ab7679b48f7..2be1c1a40a23 100644
@@ -115,7 +115,7 @@ static int CYC2_ps_load(Altera_desc *desc, const void *buf, size_t bsize)
 				"done:\t0x%p\n\n",
 				__FUNCTION__, &fn, fn, fn->config, fn->status,
 				fn->write, fn->done);
-#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
+#ifdef CONFIG_FPGA_PROG_FEEDBACK
 		printf ("Loading FPGA Device %d...", cookie);
 #endif

@@ -153,13 +153,13 @@ static int CYC2_ps_load(Altera_desc *desc, const void *buf, size_t bsize)
 			(*fn->abort) (cookie);
 			return FPGA_FAIL;
 		}
-#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
+#ifdef CONFIG_FPGA_PROG_FEEDBACK
 		puts(" OK? ...");
 #endif
 
 		CONFIG_FPGA_DELAY ();
 
-#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
+#ifdef CONFIG_FPGA_PROG_FEEDBACK
 		putc (' ');			/* terminate the dotted line */
 #endif

@@ -172,13 +172,13 @@ static int CYC2_ps_load(Altera_desc *desc, const void *buf, size_t bsize)
 		(*fn->abort) (cookie);
 		return (FPGA_FAIL);
 	}
-#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
+#ifdef CONFIG_FPGA_PROG_FEEDBACK
 	puts(" OK\n");
 #endif
 
 	ret_val = FPGA_SUCCESS;
 
-#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
+#ifdef CONFIG_FPGA_PROG_FEEDBACK
 	if (ret_val == FPGA_SUCCESS) {
 		puts ("Done.\n");
 	}

drivers/fpga/spartan2.c +11 ~~-11~~

index 859fb3c7787a..45e8534cdcb5 100644
@@ -16,7 +16,7 @@
 #endif
 
 #undef CONFIG_SYS_FPGA_CHECK_BUSY
-#undef CONFIG_SYS_FPGA_PROG_FEEDBACK
+#undef CONFIG_FPGA_PROG_FEEDBACK
 
 /* Note: The assumption is that we cannot possibly run fast enough to
  * overrun the device (the Slave Parallel mode can free run at 50MHz).

@@ -135,7 +135,7 @@ static int spartan2_sp_load(xilinx_desc *desc, const void *buf, size_t bsize)
 		 * Continuous Data Loading in Slave Parallel Mode for
 		 * the Spartan-II Family.
 		 */
-#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
+#ifdef CONFIG_FPGA_PROG_FEEDBACK
 		printf ("Loading FPGA Device %d...\n", cookie);
 #endif
 		/*

@@ -197,7 +197,7 @@ static int spartan2_sp_load(xilinx_desc *desc, const void *buf, size_t bsize)
 			}
 #endif
 
-#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
+#ifdef CONFIG_FPGA_PROG_FEEDBACK
 			if (bytecount % (bsize / 40) == 0)
 				putc ('.');		/* let them know we are alive */
 #endif

@@ -207,7 +207,7 @@ static int spartan2_sp_load(xilinx_desc *desc, const void *buf, size_t bsize)
 		(*fn->cs) (false, true, cookie);	/* Deassert the chip select */
 		(*fn->wr) (false, true, cookie);	/* Deassert the write pin */
 
-#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
+#ifdef CONFIG_FPGA_PROG_FEEDBACK
 		putc ('\n');			/* terminate the dotted line */
 #endif

@@ -235,7 +235,7 @@ static int spartan2_sp_load(xilinx_desc *desc, const void *buf, size_t bsize)
 		if (*fn->post)
 			(*fn->post) (cookie);
 
-#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
+#ifdef CONFIG_FPGA_PROG_FEEDBACK
 		if (ret_val == FPGA_SUCCESS)
 			puts ("Done.\n");
 		else

@@ -271,7 +271,7 @@ static int spartan2_sp_dump(xilinx_desc *desc, const void *buf, size_t bsize)
 			(*fn->clk) (false, true, cookie);	/* Deassert the clock pin */
 			(*fn->clk) (true, true, cookie);	/* Assert the clock pin */
 			(*fn->rdata) (&(data[bytecount++]), cookie);	/* read the data */
-#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
+#ifdef CONFIG_FPGA_PROG_FEEDBACK
 			if (bytecount % (bsize / 40) == 0)
 				putc ('.');		/* let them know we are alive */
 #endif

@@ -281,7 +281,7 @@ static int spartan2_sp_dump(xilinx_desc *desc, const void *buf, size_t bsize)
 		(*fn->clk) (false, true, cookie);	/* Deassert the clock pin */
 		(*fn->clk) (true, true, cookie);	/* Assert the clock pin */
 
-#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
+#ifdef CONFIG_FPGA_PROG_FEEDBACK
 		putc ('\n');			/* terminate the dotted line */
 #endif
 		puts ("Done.\n");

@@ -323,7 +323,7 @@ static int spartan2_ss_load(xilinx_desc *desc, const void *buf, size_t bsize)
 				"done:\t0x%p\n\n",
 				__FUNCTION__, &fn, fn, fn->pgm, fn->init,
 				fn->clk, fn->wr, fn->done);
-#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
+#ifdef CONFIG_FPGA_PROG_FEEDBACK
 		printf ("Loading FPGA Device %d...\n", cookie);
 #endif

@@ -386,7 +386,7 @@ static int spartan2_ss_load(xilinx_desc *desc, const void *buf, size_t bsize)
 				i --;
 			} while (i > 0);
 
-#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
+#ifdef CONFIG_FPGA_PROG_FEEDBACK
 			if (bytecount % (bsize / 40) == 0)
 				putc ('.');		/* let them know we are alive */
 #endif

@@ -394,7 +394,7 @@ static int spartan2_ss_load(xilinx_desc *desc, const void *buf, size_t bsize)
 
 		CONFIG_FPGA_DELAY ();
 
-#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
+#ifdef CONFIG_FPGA_PROG_FEEDBACK
 		putc ('\n');			/* terminate the dotted line */
 #endif

@@ -426,7 +426,7 @@ static int spartan2_ss_load(xilinx_desc *desc, const void *buf, size_t bsize)
 		if (*fn->post)
 			(*fn->post) (cookie);
 
-#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
+#ifdef CONFIG_FPGA_PROG_FEEDBACK
 		if (ret_val == FPGA_SUCCESS)
 			puts ("Done.\n");
 		else

drivers/fpga/spartan3.c +10 ~~-10~~

index b0213e69992b..759ad95e2afc 100644
@@ -139,7 +139,7 @@ static int spartan3_sp_load(xilinx_desc *desc, const void *buf, size_t bsize)
 		 * Continuous Data Loading in Slave Parallel Mode for
 		 * the Spartan-II Family.
 		 */
-#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
+#ifdef CONFIG_FPGA_PROG_FEEDBACK
 		printf ("Loading FPGA Device %d...\n", cookie);
 #endif
 		/*

@@ -201,7 +201,7 @@ static int spartan3_sp_load(xilinx_desc *desc, const void *buf, size_t bsize)
 			}
 #endif
 
-#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
+#ifdef CONFIG_FPGA_PROG_FEEDBACK
 			if (bytecount % (bsize / 40) == 0)
 				putc ('.');		/* let them know we are alive */
 #endif

@@ -211,7 +211,7 @@ static int spartan3_sp_load(xilinx_desc *desc, const void *buf, size_t bsize)
 		(*fn->cs) (false, true, cookie);	/* Deassert the chip select */
 		(*fn->wr) (false, true, cookie);	/* Deassert the write pin */
 
-#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
+#ifdef CONFIG_FPGA_PROG_FEEDBACK
 		putc ('\n');			/* terminate the dotted line */
 #endif

@@ -241,7 +241,7 @@ static int spartan3_sp_load(xilinx_desc *desc, const void *buf, size_t bsize)
 		if (*fn->post)
 			(*fn->post) (cookie);
 
-#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
+#ifdef CONFIG_FPGA_PROG_FEEDBACK
 		if (ret_val == FPGA_SUCCESS)
 			puts ("Done.\n");
 		else

@@ -277,7 +277,7 @@ static int spartan3_sp_dump(xilinx_desc *desc, const void *buf, size_t bsize)
 			(*fn->clk) (false, true, cookie);	/* Deassert the clock pin */
 			(*fn->clk) (true, true, cookie);	/* Assert the clock pin */
 			(*fn->rdata) (&(data[bytecount++]), cookie);	/* read the data */
-#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
+#ifdef CONFIG_FPGA_PROG_FEEDBACK
 			if (bytecount % (bsize / 40) == 0)
 				putc ('.');		/* let them know we are alive */
 #endif

@@ -287,7 +287,7 @@ static int spartan3_sp_dump(xilinx_desc *desc, const void *buf, size_t bsize)
 		(*fn->clk) (false, true, cookie);	/* Deassert the clock pin */
 		(*fn->clk) (true, true, cookie);	/* Assert the clock pin */
 
-#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
+#ifdef CONFIG_FPGA_PROG_FEEDBACK
 		putc ('\n');			/* terminate the dotted line */
 #endif
 		puts ("Done.\n");

@@ -329,7 +329,7 @@ static int spartan3_ss_load(xilinx_desc *desc, const void *buf, size_t bsize)
 				"done:\t0x%p\n\n",
 				__FUNCTION__, &fn, fn, fn->pgm, fn->init,
 				fn->clk, fn->wr, fn->done);
-#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
+#ifdef CONFIG_FPGA_PROG_FEEDBACK
 		printf ("Loading FPGA Device %d...\n", cookie);
 #endif

@@ -401,7 +401,7 @@ static int spartan3_ss_load(xilinx_desc *desc, const void *buf, size_t bsize)
 					i --;
 				} while (i > 0);
 
-#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
+#ifdef CONFIG_FPGA_PROG_FEEDBACK
 				if (bytecount % (bsize / 40) == 0)
 					putc ('.');		/* let them know we are alive */
 #endif

@@ -410,7 +410,7 @@ static int spartan3_ss_load(xilinx_desc *desc, const void *buf, size_t bsize)
 
 		CONFIG_FPGA_DELAY ();
 
-#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
+#ifdef CONFIG_FPGA_PROG_FEEDBACK
 		putc ('\n');			/* terminate the dotted line */
 #endif

@@ -444,7 +444,7 @@ static int spartan3_ss_load(xilinx_desc *desc, const void *buf, size_t bsize)
 		if (*fn->post)
 			(*fn->post) (cookie);
 
-#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
+#ifdef CONFIG_FPGA_PROG_FEEDBACK
 		if (ret_val == FPGA_SUCCESS)
 			puts ("Done.\n");
 		else

drivers/fpga/virtex2.c +9 -9

index f7cf02ab5b30..cf7723c46f64 100644
@@ -39,8 +39,8 @@
 #define CONFIG_FPGA_DELAY()
 #endif
 
-#ifndef CONFIG_SYS_FPGA_PROG_FEEDBACK
-#define CONFIG_SYS_FPGA_PROG_FEEDBACK
+#ifndef CONFIG_FPGA_PROG_FEEDBACK
+#define CONFIG_FPGA_PROG_FEEDBACK
 #endif
 
 /*

@@ -190,7 +190,7 @@ static int virtex2_ssm_load(xilinx_desc *desc, const void *buf, size_t bsize)
 				fn->clk, fn->cs, fn->wr, fn->rdata, fn->wdata,
 				fn->busy, fn->abort, fn->post);
 
-#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
+#ifdef CONFIG_FPGA_PROG_FEEDBACK
 		printf ("Initializing FPGA Device %d...\n", cookie);
 #endif
 		/*

@@ -294,7 +294,7 @@ static int virtex2_ssm_load(xilinx_desc *desc, const void *buf, size_t bsize)
 			}
 #endif
 
-#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
+#ifdef CONFIG_FPGA_PROG_FEEDBACK
 			if (bytecount % (bsize / 40) == 0)
 				putc ('.');
 #endif

@@ -307,7 +307,7 @@ static int virtex2_ssm_load(xilinx_desc *desc, const void *buf, size_t bsize)
 		(*fn->cs) (false, true, cookie);
 		(*fn->wr) (false, true, cookie);
 
-#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
+#ifdef CONFIG_FPGA_PROG_FEEDBACK
 		putc ('\n');
 #endif

@@ -329,7 +329,7 @@ static int virtex2_ssm_load(xilinx_desc *desc, const void *buf, size_t bsize)
 		}
 
 		if (ret_val == FPGA_SUCCESS) {
-#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
+#ifdef CONFIG_FPGA_PROG_FEEDBACK
 			printf ("Initialization of FPGA device %d complete\n", cookie);
 #endif
 			/*

@@ -339,7 +339,7 @@ static int virtex2_ssm_load(xilinx_desc *desc, const void *buf, size_t bsize)
 				(*fn->post) (cookie);
 			}
 		} else {
-#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
+#ifdef CONFIG_FPGA_PROG_FEEDBACK
 			printf ("** Initialization of FPGA device %d FAILED\n",
 					cookie);
 #endif

@@ -382,7 +382,7 @@ static int virtex2_ssm_dump(xilinx_desc *desc, const void *buf, size_t bsize)
 			(*fn->clk) (false, true, cookie);
 			(*fn->clk) (true, true, cookie);
 			(*fn->rdata) (&(data[bytecount++]), cookie);
-#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
+#ifdef CONFIG_FPGA_PROG_FEEDBACK
 			if (bytecount % (bsize / 40) == 0)
 				putc ('.');
 #endif

@@ -395,7 +395,7 @@ static int virtex2_ssm_dump(xilinx_desc *desc, const void *buf, size_t bsize)
 		(*fn->clk) (false, true, cookie);
 		(*fn->clk) (true, true, cookie);
 
-#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
+#ifdef CONFIG_FPGA_PROG_FEEDBACK
 		putc ('\n');
 #endif
 		puts ("Done.\n");

include/configs/M54455EVB.h +1 -1

index abec3737a498..d80521664611 100644
@@ -193,7 +193,7 @@
 /* experiment
 #define CONFIG_FPGA
 #define CONFIG_FPGA_COUNT	1
-#define CONFIG_SYS_FPGA_PROG_FEEDBACK
+#define CONFIG_FPGA_PROG_FEEDBACK
 #define CONFIG_SYS_FPGA_CHECK_CTRLC
 */

include/configs/apf27.h +1 -1

index b903ba53d1dc..a97ba9f39c50 100644
@@ -267,7 +267,7 @@
 #define CONFIG_FPGA_XILINX
 #define CONFIG_FPGA_SPARTAN3
 #define CONFIG_SYS_FPGA_WAIT		250 /* 250 ms */
-#define CONFIG_SYS_FPGA_PROG_FEEDBACK
+#define CONFIG_FPGA_PROG_FEEDBACK
 #define CONFIG_SYS_FPGA_CHECK_CTRLC
 #define CONFIG_SYS_FPGA_CHECK_ERROR

include/configs/astro_mcf5373l.h +1 -1

index e8dca0b2ccdc..0af356bcb49d 100644
@@ -209,7 +209,7 @@
 #define	CONFIG_FPGA_SPARTAN3
 #define CONFIG_FPGA_ALTERA
 #define CONFIG_FPGA_CYCLON2
-#define CONFIG_SYS_FPGA_PROG_FEEDBACK
+#define CONFIG_FPGA_PROG_FEEDBACK
 #define CONFIG_SYS_FPGA_WAIT		1000
 
 /* End of user parameters to be customized */

include/configs/mt_ventoux.h +2 -2

index 2420612800fb..1353b11b1250 100644
@@ -45,11 +45,11 @@
 #define CONFIG_FPGA
 #define CONFIG_FPGA_XILINX
 #define CONFIG_FPGA_SPARTAN3
-#define CONFIG_SYS_FPGA_PROG_FEEDBACK
+#define CONFIG_FPGA_PROG_FEEDBACK
 #define CONFIG_SYS_FPGA_WAIT	10000
 #define CONFIG_MAX_FPGA_DEVICES	1
 #define CONFIG_FPGA_DELAY() udelay(1)
-#define CONFIG_SYS_FPGA_PROG_FEEDBACK
+#define CONFIG_FPGA_PROG_FEEDBACK
 
 #define CONFIG_SPLASH_SCREEN
 #define CONFIG_VIDEO_BMP_RLE8

scripts/config_whitelist.txt +1 -1

index fc2a08a85661..4a2e894367a6 100644
@@ -5314,7 +5314,7 @@ CONFIG_SYS_FPGA_PHY0_INT
 CONFIG_SYS_FPGA_PHY1_INT
 CONFIG_SYS_FPGA_PRG
 CONFIG_SYS_FPGA_PROG
-CONFIG_SYS_FPGA_PROG_FEEDBACK
+CONFIG_FPGA_PROG_FEEDBACK
 CONFIG_SYS_FPGA_PROG_TIME
 CONFIG_SYS_FPGA_PTR
 CONFIG_SYS_FPGA_REG_BASE

Signature · 1 line

2.10.2

Michal Simek

2016-11-23 12:09 UTC #2 lore raw

RFC PATCH 1/7 fpga: CONFIG_SYS_FPGA_PROG_FEEDBACK -> CONFIG_FPGA_PROG_FEEDBACK

Quoted 477 lines · Chris Packham

Prepare for move to Kconfig by removing "SYS" from the existing macros.

Signed-off-by Chris Packham <[email protected]>

---

 README                           |  2 +-
 board/astro/mcf5373l/fpga.c      |  4 ++--
 drivers/fpga/ACEX1K.c            |  8 ++++----
 drivers/fpga/cyclon2.c           | 10 +++++-----
 drivers/fpga/spartan2.c          | 22 +++++++++++-----------
 drivers/fpga/spartan3.c          | 20 ++++++++++----------
 drivers/fpga/virtex2.c           | 18 +++++++++---------
 include/configs/M54455EVB.h      |  2 +-
 include/configs/apf27.h          |  2 +-
 include/configs/astro_mcf5373l.h |  2 +-
 include/configs/mt_ventoux.h     |  4 ++--
 scripts/config_whitelist.txt     |  2 +-
 12 files changed, 48 insertions(+), 48 deletions(-)

README +1 -1

index 47bc215fe9c5..fdc194ab9792 100644
@@ -2536,7 +2536,7 @@ The following options need to be configured:
 		Enable support for fpga loadbp command - load partial bitstream
 		(Xilinx only)
 
-		CONFIG_SYS_FPGA_PROG_FEEDBACK
+		CONFIG_FPGA_PROG_FEEDBACK
 
 		Enable printing of hash marks during FPGA configuration.

board/astro/mcf5373l/fpga.c +2 -2

index 53e00728c3d8..1b53fd2521e3 100644
@@ -128,7 +128,7 @@ int altera_write_fn(const void *buf, size_t len, int flush, int cookie)
 #if defined(CONFIG_HW_WATCHDOG) || defined(CONFIG_WATCHDOG)
 			WATCHDOG_RESET();
 #endif
-#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
+#ifdef CONFIG_FPGA_PROG_FEEDBACK
 			putc('.');	/* let them know we are alive */
 #endif
 #ifdef CONFIG_SYS_FPGA_CHECK_CTRLC

@@ -347,7 +347,7 @@ int xilinx_fastwr_config_fn(void *buf, size_t len, int flush, int cookie)
 #if defined(CONFIG_HW_WATCHDOG) || defined(CONFIG_WATCHDOG)
 			WATCHDOG_RESET();
 #endif
-#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
+#ifdef CONFIG_FPGA_PROG_FEEDBACK
 			putc('.');	/* let them know we are alive */
 #endif
 #ifdef CONFIG_SYS_FPGA_CHECK_CTRLC

drivers/fpga/ACEX1K.c +4 -4

index 1627f0e6ffde..1fb60e5983c3 100644
@@ -112,7 +112,7 @@ static int ACEX1K_ps_load(Altera_desc *desc, const void *buf, size_t bsize)
 				"done:\t0x%p\n\n",
 				__FUNCTION__, &fn, fn, fn->config, fn->status,
 				fn->clk, fn->data, fn->done);
-#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
+#ifdef CONFIG_FPGA_PROG_FEEDBACK
 		printf ("Loading FPGA Device %d...", cookie);
 #endif

@@ -188,7 +188,7 @@ static int ACEX1K_ps_load(Altera_desc *desc, const void *buf, size_t bsize)
 				i --;
 			} while (i > 0);
 
-#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
+#ifdef CONFIG_FPGA_PROG_FEEDBACK
 			if (bytecount % (bsize / 40) == 0)
 				putc ('.');		/* let them know we are alive */
 #endif

@@ -196,7 +196,7 @@ static int ACEX1K_ps_load(Altera_desc *desc, const void *buf, size_t bsize)
 
 		CONFIG_FPGA_DELAY ();
 
-#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
+#ifdef CONFIG_FPGA_PROG_FEEDBACK
 		putc (' ');			/* terminate the dotted line */
 #endif

@@ -223,7 +223,7 @@ static int ACEX1K_ps_load(Altera_desc *desc, const void *buf, size_t bsize)
 
 	ret_val = FPGA_SUCCESS;
 
-#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
+#ifdef CONFIG_FPGA_PROG_FEEDBACK
 		if (ret_val == FPGA_SUCCESS) {
 			puts ("Done.\n");
 		}

drivers/fpga/cyclon2.c +5 -5

index 8ab7679b48f7..2be1c1a40a23 100644
@@ -115,7 +115,7 @@ static int CYC2_ps_load(Altera_desc *desc, const void *buf, size_t bsize)
 				"done:\t0x%p\n\n",
 				__FUNCTION__, &fn, fn, fn->config, fn->status,
 				fn->write, fn->done);
-#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
+#ifdef CONFIG_FPGA_PROG_FEEDBACK
 		printf ("Loading FPGA Device %d...", cookie);
 #endif

@@ -153,13 +153,13 @@ static int CYC2_ps_load(Altera_desc *desc, const void *buf, size_t bsize)
 			(*fn->abort) (cookie);
 			return FPGA_FAIL;
 		}
-#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
+#ifdef CONFIG_FPGA_PROG_FEEDBACK
 		puts(" OK? ...");
 #endif
 
 		CONFIG_FPGA_DELAY ();
 
-#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
+#ifdef CONFIG_FPGA_PROG_FEEDBACK
 		putc (' ');			/* terminate the dotted line */
 #endif

@@ -172,13 +172,13 @@ static int CYC2_ps_load(Altera_desc *desc, const void *buf, size_t bsize)
 		(*fn->abort) (cookie);
 		return (FPGA_FAIL);
 	}
-#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
+#ifdef CONFIG_FPGA_PROG_FEEDBACK
 	puts(" OK\n");
 #endif
 
 	ret_val = FPGA_SUCCESS;
 
-#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
+#ifdef CONFIG_FPGA_PROG_FEEDBACK
 	if (ret_val == FPGA_SUCCESS) {
 		puts ("Done.\n");
 	}

drivers/fpga/spartan2.c +11 ~~-11~~

index 859fb3c7787a..45e8534cdcb5 100644
@@ -16,7 +16,7 @@
 #endif
 
 #undef CONFIG_SYS_FPGA_CHECK_BUSY
-#undef CONFIG_SYS_FPGA_PROG_FEEDBACK
+#undef CONFIG_FPGA_PROG_FEEDBACK
 
 /* Note: The assumption is that we cannot possibly run fast enough to
  * overrun the device (the Slave Parallel mode can free run at 50MHz).

@@ -135,7 +135,7 @@ static int spartan2_sp_load(xilinx_desc *desc, const void *buf, size_t bsize)
 		 * Continuous Data Loading in Slave Parallel Mode for
 		 * the Spartan-II Family.
 		 */
-#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
+#ifdef CONFIG_FPGA_PROG_FEEDBACK
 		printf ("Loading FPGA Device %d...\n", cookie);
 #endif
 		/*

@@ -197,7 +197,7 @@ static int spartan2_sp_load(xilinx_desc *desc, const void *buf, size_t bsize)
 			}
 #endif
 
-#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
+#ifdef CONFIG_FPGA_PROG_FEEDBACK
 			if (bytecount % (bsize / 40) == 0)
 				putc ('.');		/* let them know we are alive */
 #endif

@@ -207,7 +207,7 @@ static int spartan2_sp_load(xilinx_desc *desc, const void *buf, size_t bsize)
 		(*fn->cs) (false, true, cookie);	/* Deassert the chip select */
 		(*fn->wr) (false, true, cookie);	/* Deassert the write pin */
 
-#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
+#ifdef CONFIG_FPGA_PROG_FEEDBACK
 		putc ('\n');			/* terminate the dotted line */
 #endif

@@ -235,7 +235,7 @@ static int spartan2_sp_load(xilinx_desc *desc, const void *buf, size_t bsize)
 		if (*fn->post)
 			(*fn->post) (cookie);
 
-#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
+#ifdef CONFIG_FPGA_PROG_FEEDBACK
 		if (ret_val == FPGA_SUCCESS)
 			puts ("Done.\n");
 		else

@@ -271,7 +271,7 @@ static int spartan2_sp_dump(xilinx_desc *desc, const void *buf, size_t bsize)
 			(*fn->clk) (false, true, cookie);	/* Deassert the clock pin */
 			(*fn->clk) (true, true, cookie);	/* Assert the clock pin */
 			(*fn->rdata) (&(data[bytecount++]), cookie);	/* read the data */
-#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
+#ifdef CONFIG_FPGA_PROG_FEEDBACK
 			if (bytecount % (bsize / 40) == 0)
 				putc ('.');		/* let them know we are alive */
 #endif

@@ -281,7 +281,7 @@ static int spartan2_sp_dump(xilinx_desc *desc, const void *buf, size_t bsize)
 		(*fn->clk) (false, true, cookie);	/* Deassert the clock pin */
 		(*fn->clk) (true, true, cookie);	/* Assert the clock pin */
 
-#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
+#ifdef CONFIG_FPGA_PROG_FEEDBACK
 		putc ('\n');			/* terminate the dotted line */
 #endif
 		puts ("Done.\n");

@@ -323,7 +323,7 @@ static int spartan2_ss_load(xilinx_desc *desc, const void *buf, size_t bsize)
 				"done:\t0x%p\n\n",
 				__FUNCTION__, &fn, fn, fn->pgm, fn->init,
 				fn->clk, fn->wr, fn->done);
-#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
+#ifdef CONFIG_FPGA_PROG_FEEDBACK
 		printf ("Loading FPGA Device %d...\n", cookie);
 #endif

@@ -386,7 +386,7 @@ static int spartan2_ss_load(xilinx_desc *desc, const void *buf, size_t bsize)
 				i --;
 			} while (i > 0);
 
-#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
+#ifdef CONFIG_FPGA_PROG_FEEDBACK
 			if (bytecount % (bsize / 40) == 0)
 				putc ('.');		/* let them know we are alive */
 #endif

@@ -394,7 +394,7 @@ static int spartan2_ss_load(xilinx_desc *desc, const void *buf, size_t bsize)
 
 		CONFIG_FPGA_DELAY ();
 
-#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
+#ifdef CONFIG_FPGA_PROG_FEEDBACK
 		putc ('\n');			/* terminate the dotted line */
 #endif

@@ -426,7 +426,7 @@ static int spartan2_ss_load(xilinx_desc *desc, const void *buf, size_t bsize)
 		if (*fn->post)
 			(*fn->post) (cookie);
 
-#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
+#ifdef CONFIG_FPGA_PROG_FEEDBACK
 		if (ret_val == FPGA_SUCCESS)
 			puts ("Done.\n");
 		else

drivers/fpga/spartan3.c +10 ~~-10~~

index b0213e69992b..759ad95e2afc 100644
@@ -139,7 +139,7 @@ static int spartan3_sp_load(xilinx_desc *desc, const void *buf, size_t bsize)
 		 * Continuous Data Loading in Slave Parallel Mode for
 		 * the Spartan-II Family.
 		 */
-#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
+#ifdef CONFIG_FPGA_PROG_FEEDBACK
 		printf ("Loading FPGA Device %d...\n", cookie);
 #endif
 		/*

@@ -201,7 +201,7 @@ static int spartan3_sp_load(xilinx_desc *desc, const void *buf, size_t bsize)
 			}
 #endif
 
-#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
+#ifdef CONFIG_FPGA_PROG_FEEDBACK
 			if (bytecount % (bsize / 40) == 0)
 				putc ('.');		/* let them know we are alive */
 #endif

@@ -211,7 +211,7 @@ static int spartan3_sp_load(xilinx_desc *desc, const void *buf, size_t bsize)
 		(*fn->cs) (false, true, cookie);	/* Deassert the chip select */
 		(*fn->wr) (false, true, cookie);	/* Deassert the write pin */
 
-#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
+#ifdef CONFIG_FPGA_PROG_FEEDBACK
 		putc ('\n');			/* terminate the dotted line */
 #endif

@@ -241,7 +241,7 @@ static int spartan3_sp_load(xilinx_desc *desc, const void *buf, size_t bsize)
 		if (*fn->post)
 			(*fn->post) (cookie);
 
-#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
+#ifdef CONFIG_FPGA_PROG_FEEDBACK
 		if (ret_val == FPGA_SUCCESS)
 			puts ("Done.\n");
 		else

@@ -277,7 +277,7 @@ static int spartan3_sp_dump(xilinx_desc *desc, const void *buf, size_t bsize)
 			(*fn->clk) (false, true, cookie);	/* Deassert the clock pin */
 			(*fn->clk) (true, true, cookie);	/* Assert the clock pin */
 			(*fn->rdata) (&(data[bytecount++]), cookie);	/* read the data */
-#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
+#ifdef CONFIG_FPGA_PROG_FEEDBACK
 			if (bytecount % (bsize / 40) == 0)
 				putc ('.');		/* let them know we are alive */
 #endif

@@ -287,7 +287,7 @@ static int spartan3_sp_dump(xilinx_desc *desc, const void *buf, size_t bsize)
 		(*fn->clk) (false, true, cookie);	/* Deassert the clock pin */
 		(*fn->clk) (true, true, cookie);	/* Assert the clock pin */
 
-#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
+#ifdef CONFIG_FPGA_PROG_FEEDBACK
 		putc ('\n');			/* terminate the dotted line */
 #endif
 		puts ("Done.\n");

@@ -329,7 +329,7 @@ static int spartan3_ss_load(xilinx_desc *desc, const void *buf, size_t bsize)
 				"done:\t0x%p\n\n",
 				__FUNCTION__, &fn, fn, fn->pgm, fn->init,
 				fn->clk, fn->wr, fn->done);
-#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
+#ifdef CONFIG_FPGA_PROG_FEEDBACK
 		printf ("Loading FPGA Device %d...\n", cookie);
 #endif

@@ -401,7 +401,7 @@ static int spartan3_ss_load(xilinx_desc *desc, const void *buf, size_t bsize)
 					i --;
 				} while (i > 0);
 
-#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
+#ifdef CONFIG_FPGA_PROG_FEEDBACK
 				if (bytecount % (bsize / 40) == 0)
 					putc ('.');		/* let them know we are alive */
 #endif

@@ -410,7 +410,7 @@ static int spartan3_ss_load(xilinx_desc *desc, const void *buf, size_t bsize)
 
 		CONFIG_FPGA_DELAY ();
 
-#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
+#ifdef CONFIG_FPGA_PROG_FEEDBACK
 		putc ('\n');			/* terminate the dotted line */
 #endif

@@ -444,7 +444,7 @@ static int spartan3_ss_load(xilinx_desc *desc, const void *buf, size_t bsize)
 		if (*fn->post)
 			(*fn->post) (cookie);
 
-#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
+#ifdef CONFIG_FPGA_PROG_FEEDBACK
 		if (ret_val == FPGA_SUCCESS)
 			puts ("Done.\n");
 		else

drivers/fpga/virtex2.c +9 -9

index f7cf02ab5b30..cf7723c46f64 100644
@@ -39,8 +39,8 @@
 #define CONFIG_FPGA_DELAY()
 #endif
 
-#ifndef CONFIG_SYS_FPGA_PROG_FEEDBACK
-#define CONFIG_SYS_FPGA_PROG_FEEDBACK
+#ifndef CONFIG_FPGA_PROG_FEEDBACK
+#define CONFIG_FPGA_PROG_FEEDBACK
 #endif
 
 /*

@@ -190,7 +190,7 @@ static int virtex2_ssm_load(xilinx_desc *desc, const void *buf, size_t bsize)
 				fn->clk, fn->cs, fn->wr, fn->rdata, fn->wdata,
 				fn->busy, fn->abort, fn->post);
 
-#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
+#ifdef CONFIG_FPGA_PROG_FEEDBACK
 		printf ("Initializing FPGA Device %d...\n", cookie);
 #endif
 		/*

@@ -294,7 +294,7 @@ static int virtex2_ssm_load(xilinx_desc *desc, const void *buf, size_t bsize)
 			}
 #endif
 
-#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
+#ifdef CONFIG_FPGA_PROG_FEEDBACK
 			if (bytecount % (bsize / 40) == 0)
 				putc ('.');
 #endif

@@ -307,7 +307,7 @@ static int virtex2_ssm_load(xilinx_desc *desc, const void *buf, size_t bsize)
 		(*fn->cs) (false, true, cookie);
 		(*fn->wr) (false, true, cookie);
 
-#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
+#ifdef CONFIG_FPGA_PROG_FEEDBACK
 		putc ('\n');
 #endif

@@ -329,7 +329,7 @@ static int virtex2_ssm_load(xilinx_desc *desc, const void *buf, size_t bsize)
 		}
 
 		if (ret_val == FPGA_SUCCESS) {
-#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
+#ifdef CONFIG_FPGA_PROG_FEEDBACK
 			printf ("Initialization of FPGA device %d complete\n", cookie);
 #endif
 			/*

@@ -339,7 +339,7 @@ static int virtex2_ssm_load(xilinx_desc *desc, const void *buf, size_t bsize)
 				(*fn->post) (cookie);
 			}
 		} else {
-#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
+#ifdef CONFIG_FPGA_PROG_FEEDBACK
 			printf ("** Initialization of FPGA device %d FAILED\n",
 					cookie);
 #endif

@@ -382,7 +382,7 @@ static int virtex2_ssm_dump(xilinx_desc *desc, const void *buf, size_t bsize)
 			(*fn->clk) (false, true, cookie);
 			(*fn->clk) (true, true, cookie);
 			(*fn->rdata) (&(data[bytecount++]), cookie);
-#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
+#ifdef CONFIG_FPGA_PROG_FEEDBACK
 			if (bytecount % (bsize / 40) == 0)
 				putc ('.');
 #endif

@@ -395,7 +395,7 @@ static int virtex2_ssm_dump(xilinx_desc *desc, const void *buf, size_t bsize)
 		(*fn->clk) (false, true, cookie);
 		(*fn->clk) (true, true, cookie);
 
-#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
+#ifdef CONFIG_FPGA_PROG_FEEDBACK
 		putc ('\n');
 #endif
 		puts ("Done.\n");

include/configs/M54455EVB.h +1 -1

index abec3737a498..d80521664611 100644
@@ -193,7 +193,7 @@
 /* experiment
 #define CONFIG_FPGA
 #define CONFIG_FPGA_COUNT	1
-#define CONFIG_SYS_FPGA_PROG_FEEDBACK
+#define CONFIG_FPGA_PROG_FEEDBACK
 #define CONFIG_SYS_FPGA_CHECK_CTRLC
 */

include/configs/apf27.h +1 -1

index b903ba53d1dc..a97ba9f39c50 100644
@@ -267,7 +267,7 @@
 #define CONFIG_FPGA_XILINX
 #define CONFIG_FPGA_SPARTAN3
 #define CONFIG_SYS_FPGA_WAIT		250 /* 250 ms */
-#define CONFIG_SYS_FPGA_PROG_FEEDBACK
+#define CONFIG_FPGA_PROG_FEEDBACK
 #define CONFIG_SYS_FPGA_CHECK_CTRLC
 #define CONFIG_SYS_FPGA_CHECK_ERROR

include/configs/astro_mcf5373l.h +1 -1

index e8dca0b2ccdc..0af356bcb49d 100644
@@ -209,7 +209,7 @@
 #define	CONFIG_FPGA_SPARTAN3
 #define CONFIG_FPGA_ALTERA
 #define CONFIG_FPGA_CYCLON2
-#define CONFIG_SYS_FPGA_PROG_FEEDBACK
+#define CONFIG_FPGA_PROG_FEEDBACK
 #define CONFIG_SYS_FPGA_WAIT		1000
 
 /* End of user parameters to be customized */

include/configs/mt_ventoux.h +2 -2

index 2420612800fb..1353b11b1250 100644
@@ -45,11 +45,11 @@
 #define CONFIG_FPGA
 #define CONFIG_FPGA_XILINX
 #define CONFIG_FPGA_SPARTAN3
-#define CONFIG_SYS_FPGA_PROG_FEEDBACK
+#define CONFIG_FPGA_PROG_FEEDBACK
 #define CONFIG_SYS_FPGA_WAIT	10000
 #define CONFIG_MAX_FPGA_DEVICES	1
 #define CONFIG_FPGA_DELAY() udelay(1)
-#define CONFIG_SYS_FPGA_PROG_FEEDBACK
+#define CONFIG_FPGA_PROG_FEEDBACK
 
 #define CONFIG_SPLASH_SCREEN
 #define CONFIG_VIDEO_BMP_RLE8

scripts/config_whitelist.txt +0 -0

index fc2a08a85661..4a2e894367a6 100644

scripts/config_whitelist.txt CONFIG_SYS_FPGA_PHY0_INT · line 5320

Quoted 8 lines

scripts/config_whitelist.txt +1 -1

@@ -5314,7 +5314,7 @@ CONFIG_SYS_FPGA_PHY0_INT
 CONFIG_SYS_FPGA_PHY1_INT
 CONFIG_SYS_FPGA_PRG
 CONFIG_SYS_FPGA_PROG
-CONFIG_SYS_FPGA_PROG_FEEDBACK
+CONFIG_FPGA_PROG_FEEDBACK
 CONFIG_SYS_FPGA_PROG_TIME
 CONFIG_SYS_FPGA_PTR
 CONFIG_SYS_FPGA_REG_BASE

This is breaking buildman. You should introduce Kconfig option in first patch and than this one.

[u-boot]$ ./tools/buildman/buildman apf27 -c 2 boards.cfg is up to date. Nothing to do.
Building current source for 1 boards (1 thread, 8 jobs per thread)
arm: + apf27 )
+comm: file 2 is not in sorted order
+Error: You must add new CONFIG options using Kconfig +The following new ad-hoc CONFIG options were detected:
+CONFIG_FPGA_PROG_FEEDBACK
+
+Please add these via Kconfig instead. Find a suitable Kconfig +file and add a 'config' or 'menuconfig' option. +make[1]: *** [all] Error 1
+make: *** [sub-make] Error 2

    0    0    1 /1      apf27

Thanks,
Michal

Chris Packham

author

2016-11-24 23:57 UTC #3 lore raw

RFC PATCH 1/7 fpga: CONFIG_SYS_FPGA_PROG_FEEDBACK -> CONFIG_FPGA_PROG_FEEDBACK

(dropped addresses that we're bouncing from Cc, hope I got Jagans new address right).

Quoted 13 lines · Michal Simek

Quoted 4 lines · Chris Packham
Prepare for move to Kconfig by removing "SYS" from the existing macros.
Signed-off-by Chris Packham <[email protected]>
---
This is breaking buildman. You should introduce Kconfig option in first patch and than this one.
[u-boot]$ ./tools/buildman/buildman apf27 -c 2 boards.cfg is up to date. Nothing to do.
Building current source for 1 boards (1 thread, 8 jobs per thread)
arm: + apf27 )

Review

Quoted 10 lines

(quoted diff) +9 -0

+comm: file 2 is not in sorted order
+Error: You must add new CONFIG options using Kconfig
+The following new ad-hoc CONFIG options were detected:
+CONFIG_FPGA_PROG_FEEDBACK
+
+Please add these via Kconfig instead. Find a suitable Kconfig
+file and add a 'config' or 'menuconfig' option.
+make[1]: *** [all] Error 1
+make: *** [sub-make] Error 2
    0    0    1 /1      apf27

So I agree that this should probably be closer to the other two patches. But won't I have the same problem either way. Unless I squash this with "Move FPGA_PROG_FEEDBACK to defconfig" which I can do Is that acceptable to everyone.

Quoted 4 lines

Thanks,
Michal

Michal Simek

2016-11-25 06:57 UTC #4 lore raw

RFC PATCH 1/7 fpga: CONFIG_SYS_FPGA_PROG_FEEDBACK -> CONFIG_FPGA_PROG_FEEDBACK

Quoted 24 lines · Chris Packham

(dropped addresses that we're bouncing from Cc, hope I got Jagans new address right).
Quoted 20 lines · Michal Simek
Quoted 4 lines · Chris Packham
Prepare for move to Kconfig by removing "SYS" from the existing macros.
Signed-off-by Chris Packham <[email protected]>
---
This is breaking buildman. You should introduce Kconfig option in first patch and than this one.
[u-boot]$ ./tools/buildman/buildman apf27 -c 2 boards.cfg is up to date. Nothing to do.
Building current source for 1 boards (1 thread, 8 jobs per thread)
arm: + apf27 )
(quoted diff) +7 -0
+comm: file 2 is not in sorted order
+Error: You must add new CONFIG options using Kconfig
+The following new ad-hoc CONFIG options were detected:
+CONFIG_FPGA_PROG_FEEDBACK
+
+Please add these via Kconfig instead. Find a suitable Kconfig
+file and add a 'config' or 'menuconfig' option.

Quoted 8 lines

Review
Quoted 3 lines
(quoted diff) +2 -0
+make[1]: *** [all] Error 1
+make: *** [sub-make] Error 2
    0    0    1 /1      apf27
So I agree that this should probably be closer to the other two patches. But won't I have the same problem either way. Unless I squash this with "Move FPGA_PROG_FEEDBACK to defconfig" which I can do Is that acceptable to everyone.

you shouldn't break buildman.
You don't need to squash patches - there is no reason for that. Add option to Kconfig in the first patch. Then convert macros in the second patch and then move option from configs to defconfig in third patch. This way will keep buildman happy.

Thanks,
Michal

Chris Packham

author

2016-11-22 08:48 UTC #5 lore raw

RFC PATCH 2/7 fpga: add Kconfig support for Xilinx Spartan devices

In reply to Chris Packham

Signed-off-by Chris Packham <[email protected]>

---

 drivers/fpga/Kconfig | 11 +++++++++++
 1 file changed, 11 insertions(+)

drivers/fpga/Kconfig +11 -0

index f3f6bf7f6747..d137ab2df1d7 100644
@@ -17,4 +17,15 @@ config FPGA_ZYNQMPPL
 	  Enable FPGA driver for loading bitstream in BIT and BIN format
 	  on Xilinx Zynq UltraScale+ (ZynqMP) device.
 
+config FPGA_SPARTAN3
+	bool "Enable Xilinx Spartan-III driver"
+	depends on FPGA_XILINX
+	help
+	  Enable FPGA driver for Xilinx Spartan-III devices.
+
+config FPGA_SPARTAN2
+	bool "Enable Xilinx Spartan-II driver"
+	depends on FPGA_XILINX
+	help
+	  Enable FPGA driver for Xilinx Spartan-II devices.
 endmenu

Signature · 1 line

2.10.2

Michal Simek

2016-11-23 12:10 UTC #6 lore raw

RFC PATCH 2/7 fpga: add Kconfig support for Xilinx Spartan devices

Quoted 17 lines · Chris Packham

Signed-off-by Chris Packham <[email protected]>

---

 drivers/fpga/Kconfig | 11 +++++++++++
 1 file changed, 11 insertions(+)

drivers/fpga/Kconfig +2 -0

index f3f6bf7f6747..d137ab2df1d7 100644
@@ -17,4 +17,15 @@ config FPGA_ZYNQMPPL
 	  Enable FPGA driver for loading bitstream in BIT and BIN format
 	  on Xilinx Zynq UltraScale+ (ZynqMP) device.
 
+config FPGA_SPARTAN3
+	bool "Enable Xilinx Spartan-III driver"

drivers/fpga/Kconfig config FPGA_ZYNQMPPL · line 31

Quoted 10 lines

drivers/fpga/Kconfig +9 -0

+	depends on FPGA_XILINX
+	help
+	  Enable FPGA driver for Xilinx Spartan-III devices.
+
+config FPGA_SPARTAN2
+	bool "Enable Xilinx Spartan-II driver"
+	depends on FPGA_XILINX
+	help
+	  Enable FPGA driver for Xilinx Spartan-II devices.
 endmenu

Acked-by Michal Simek <[email protected]>

Thanks,
Michal

Signature · 14 lines

Michal Simek, Ing. (M.Eng), OpenPGP -> KeyID: FE3D1F91
w: www.monstr.eu p: +42-0-721842854
Maintainer of Linux kernel - Xilinx Microblaze
Maintainer of Linux kernel - Xilinx Zynq ARM and ZynqMP ARM64 SoCs
U-Boot custodian - Xilinx Microblaze/Zynq/ZynqMP SoCs


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Chris Packham

author

2016-11-22 08:48 UTC #7 lore raw

RFC PATCH 3/7 Move CONFIG_FPGA_SPARTAN options to defconfig

In reply to Chris Packham

Signed-off-by Chris Packham <[email protected]>

---

 configs/PMC440_defconfig         | 3 +++
 configs/apf27_defconfig          | 2 ++
 configs/astro_mcf5373l_defconfig | 2 ++
 configs/mt_ventoux_defconfig     | 2 ++
 configs/x600_defconfig           | 2 ++
 include/configs/PMC440.h         | 4 ----
 include/configs/apf27.h          | 5 -----
 include/configs/astro_mcf5373l.h | 3 ---
 include/configs/mt_ventoux.h     | 3 ---
 include/configs/x600.h           | 3 ---
 10 files changed, 11 insertions(+), 18 deletions(-)

configs/PMC440_defconfig +3 -0

index cd2f0d2a5b4b..8a2e9c964e14 100644
@@ -16,6 +16,9 @@ CONFIG_CMD_DHCP=y
 CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_FAT=y
+CONFIG_FPGA_XILINX=y
+CONFIG_FPGA_SPARTAN3=y
+CONFIG_FPGA_SPARTAN2=y
 CONFIG_SYS_NS16550=y
 CONFIG_USB=y
 CONFIG_USB_STORAGE=y

configs/apf27_defconfig +2 -0

index a02e180d2f2c..f8f177ad56ce 100644
@@ -21,4 +21,6 @@ CONFIG_CMD_CACHE=y
 CONFIG_CMD_EXT2=y
 CONFIG_CMD_FAT=y
 CONFIG_CMD_UBI=y
+CONFIG_FPGA_XILINX=y
+CONFIG_FPGA_SPARTAN3=y
 CONFIG_OF_LIBFDT=y

configs/astro_mcf5373l_defconfig +2 -0

index 94e931eabadc..5ea1b66e5b2a 100644
@@ -9,3 +9,5 @@ CONFIG_CMD_I2C=y
 # CONFIG_CMD_NET is not set
 # CONFIG_CMD_NFS is not set
 CONFIG_CMD_CACHE=y
+CONFIG_FPGA_XILINX=y
+CONFIG_FPGA_SPARTAN3=y

configs/mt_ventoux_defconfig +2 -0

index 9e330a7f44ca..d4e58395cf22 100644
@@ -24,6 +24,8 @@ CONFIG_CMD_CACHE=y
 CONFIG_CMD_EXT2=y
 CONFIG_CMD_FAT=y
 CONFIG_CMD_UBI=y
+CONFIG_FPGA_XILINX=y
+CONFIG_FPGA_SPARTAN3=y
 CONFIG_SYS_NS16550=y
 CONFIG_USB=y
 CONFIG_USB_ULPI_VIEWPORT_OMAP=y

configs/x600_defconfig +2 -0

index 65b7d9565aac..0db6b5c6ba20 100644
@@ -26,6 +26,8 @@ CONFIG_CMD_CACHE=y
 CONFIG_CMD_FAT=y
 CONFIG_CMD_FS_GENERIC=y
 CONFIG_CMD_UBI=y
+CONFIG_FPGA_XILINX=y
+CONFIG_FPGA_SPARTAN3=y
 CONFIG_SYS_I2C_DW=y
 CONFIG_NETDEVICES=y
 CONFIG_ETH_DESIGNWARE=y

include/configs/PMC440.h +0 -4

index 2e7f6e480323..750f8447220c 100644
@@ -343,10 +343,6 @@
 /*-----------------------------------------------------------------------
  * FPGA stuff
  *----------------------------------------------------------------------*/
-#define CONFIG_FPGA
-#define CONFIG_FPGA_XILINX
-#define CONFIG_FPGA_SPARTAN2
-#define CONFIG_FPGA_SPARTAN3
 
 #define CONFIG_FPGA_COUNT	2
 /*-----------------------------------------------------------------------

include/configs/apf27.h +0 -5

index a97ba9f39c50..00798fa1027f 100644
@@ -260,12 +260,7 @@
 /*
  * FPGA
  */
-#ifndef CONFIG_SPL_BUILD
-#define CONFIG_FPGA
-#endif
 #define CONFIG_FPGA_COUNT		1
-#define CONFIG_FPGA_XILINX
-#define CONFIG_FPGA_SPARTAN3
 #define CONFIG_SYS_FPGA_WAIT		250 /* 250 ms */
 #define CONFIG_FPGA_PROG_FEEDBACK
 #define CONFIG_SYS_FPGA_CHECK_CTRLC

include/configs/astro_mcf5373l.h +0 -3

index 0af356bcb49d..d5d6540ec9b9 100644
@@ -204,9 +204,6 @@
 #define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE
 
 #define CONFIG_FPGA_COUNT	1
-#define CONFIG_FPGA
-#define	CONFIG_FPGA_XILINX
-#define	CONFIG_FPGA_SPARTAN3
 #define CONFIG_FPGA_ALTERA
 #define CONFIG_FPGA_CYCLON2
 #define CONFIG_FPGA_PROG_FEEDBACK

include/configs/mt_ventoux.h +0 -3

index 1353b11b1250..b6198dbdf6d3 100644
@@ -42,9 +42,6 @@
  * FPGA
  */
 #define CONFIG_CMD_FPGA_LOADMK
-#define CONFIG_FPGA
-#define CONFIG_FPGA_XILINX
-#define CONFIG_FPGA_SPARTAN3
 #define CONFIG_FPGA_PROG_FEEDBACK
 #define CONFIG_SYS_FPGA_WAIT	10000
 #define CONFIG_MAX_FPGA_DEVICES	1

include/configs/x600.h +0 -3

index 5e51f6535624..a879c4c7c113 100644
@@ -96,9 +96,6 @@
 #define CONFIG_SYS_I2C_RTC_ADDR	0x68
 
 /* FPGA config options */
-#define CONFIG_FPGA
-#define CONFIG_FPGA_XILINX
-#define CONFIG_FPGA_SPARTAN3
 #define CONFIG_FPGA_COUNT	1
 
 /* USB EHCI options */

Signature · 1 line

2.10.2

Michal Simek

2016-11-23 12:14 UTC #8 lore raw

RFC PATCH 3/7 Move CONFIG_FPGA_SPARTAN options to defconfig

Quoted 96 lines · Chris Packham

Signed-off-by Chris Packham <[email protected]>

---

 configs/PMC440_defconfig         | 3 +++
 configs/apf27_defconfig          | 2 ++
 configs/astro_mcf5373l_defconfig | 2 ++
 configs/mt_ventoux_defconfig     | 2 ++
 configs/x600_defconfig           | 2 ++
 include/configs/PMC440.h         | 4 ----
 include/configs/apf27.h          | 5 -----
 include/configs/astro_mcf5373l.h | 3 ---
 include/configs/mt_ventoux.h     | 3 ---
 include/configs/x600.h           | 3 ---
 10 files changed, 11 insertions(+), 18 deletions(-)

configs/PMC440_defconfig +3 -0

index cd2f0d2a5b4b..8a2e9c964e14 100644
@@ -16,6 +16,9 @@ CONFIG_CMD_DHCP=y
 CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_FAT=y
+CONFIG_FPGA_XILINX=y
+CONFIG_FPGA_SPARTAN3=y
+CONFIG_FPGA_SPARTAN2=y
 CONFIG_SYS_NS16550=y
 CONFIG_USB=y
 CONFIG_USB_STORAGE=y

configs/apf27_defconfig +2 -0

index a02e180d2f2c..f8f177ad56ce 100644
@@ -21,4 +21,6 @@ CONFIG_CMD_CACHE=y
 CONFIG_CMD_EXT2=y
 CONFIG_CMD_FAT=y
 CONFIG_CMD_UBI=y
+CONFIG_FPGA_XILINX=y
+CONFIG_FPGA_SPARTAN3=y
 CONFIG_OF_LIBFDT=y

configs/astro_mcf5373l_defconfig +2 -0

index 94e931eabadc..5ea1b66e5b2a 100644
@@ -9,3 +9,5 @@ CONFIG_CMD_I2C=y
 # CONFIG_CMD_NET is not set
 # CONFIG_CMD_NFS is not set
 CONFIG_CMD_CACHE=y
+CONFIG_FPGA_XILINX=y
+CONFIG_FPGA_SPARTAN3=y

configs/mt_ventoux_defconfig +2 -0

index 9e330a7f44ca..d4e58395cf22 100644
@@ -24,6 +24,8 @@ CONFIG_CMD_CACHE=y
 CONFIG_CMD_EXT2=y
 CONFIG_CMD_FAT=y
 CONFIG_CMD_UBI=y
+CONFIG_FPGA_XILINX=y
+CONFIG_FPGA_SPARTAN3=y
 CONFIG_SYS_NS16550=y
 CONFIG_USB=y
 CONFIG_USB_ULPI_VIEWPORT_OMAP=y

configs/x600_defconfig +2 -0

index 65b7d9565aac..0db6b5c6ba20 100644
@@ -26,6 +26,8 @@ CONFIG_CMD_CACHE=y
 CONFIG_CMD_FAT=y
 CONFIG_CMD_FS_GENERIC=y
 CONFIG_CMD_UBI=y
+CONFIG_FPGA_XILINX=y
+CONFIG_FPGA_SPARTAN3=y
 CONFIG_SYS_I2C_DW=y
 CONFIG_NETDEVICES=y
 CONFIG_ETH_DESIGNWARE=y

include/configs/PMC440.h +0 -4

index 2e7f6e480323..750f8447220c 100644
@@ -343,10 +343,6 @@
 /*-----------------------------------------------------------------------
  * FPGA stuff
  *----------------------------------------------------------------------*/
-#define CONFIG_FPGA
-#define CONFIG_FPGA_XILINX
-#define CONFIG_FPGA_SPARTAN2
-#define CONFIG_FPGA_SPARTAN3
 
 #define CONFIG_FPGA_COUNT	2
 /*-----------------------------------------------------------------------

include/configs/apf27.h +0 -0

index a97ba9f39c50..00798fa1027f 100644

include/configs/apf27.h line 265

Quoted 6 lines

include/configs/apf27.h +0 -3

@@ -260,12 +260,7 @@
 /*
  * FPGA
  */
-#ifndef CONFIG_SPL_BUILD
-#define CONFIG_FPGA
-#endif

Isn't this causing some compilation issue for SPL case?

Thanks,
Michal

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Chris Packham

author

2016-11-25 00:53 UTC #9 lore raw

RFC PATCH 3/7 Move CONFIG_FPGA_SPARTAN options to defconfig

Quoted 6 lines · Michal Simek

Quoted 2 lines · Chris Packham
Signed-off-by Chris Packham <[email protected]>
---
Isn't this causing some compilation issue for SPL case?

I have compile tested apf27 and didn't see an issue. I'm guessing none of the FPGA infrastructure is available in SPL.

Chris Packham

author

2016-11-25 08:39 UTC #10 lore raw

RFC PATCH 3/7 Move CONFIG_FPGA_SPARTAN options to defconfig

Quoted 10 lines · Chris Packham

Quoted 6 lines · Michal Simek
Quoted 2 lines · Chris Packham
Signed-off-by Chris Packham <[email protected]>
---
Isn't this causing some compilation issue for SPL case?
I have compile tested apf27 and didn't see an issue. I'm guessing none of the FPGA infrastructure is available in SPL.

A better non-guess answer is that yes indeed all of drivers/fgpa is not included in SPL. But CONFIG_FPGA now ends up defined and nm tells me I've probably broken that board

nm spl/u-boot-spl | grep fpga_init
U fpga_init

So how is this usually handled? I can surround the code in board/armadeus/apf27 with #ifndef CONFIG_SPL_BUILD but that seems kind of hacky.

Chris Packham

author

2016-11-22 08:48 UTC #11 lore raw

RFC PATCH 4/7 fpga/spartan3: make output quieter

In reply to Chris Packham

Suppress some putc calls with CONFIG_SYS_FPGA_PROG_FEEDBACK.

Signed-off-by Chris Packham <[email protected]>

---

 drivers/fpga/spartan3.c | 4 ++++
 1 file changed, 4 insertions(+)

drivers/fpga/spartan3.c +4 -0

index 759ad95e2afc..34aa097ab6c2 100644
@@ -428,7 +428,9 @@ static int spartan3_ss_load(xilinx_desc *desc, const void *buf, size_t bsize)
 			CONFIG_FPGA_DELAY ();
 			(*fn->clk) (true, true, cookie);	/* Assert the clock pin */
 
+#ifdef CONFIG_FPGA_PROG_FEEDBACK
 			putc ('*');
+#endif
 
 			if (get_timer (ts) > CONFIG_SYS_FPGA_WAIT) {	/* check the time */
 				puts ("** Timeout waiting for DONE to clear.\n");

@@ -436,7 +438,9 @@ static int spartan3_ss_load(xilinx_desc *desc, const void *buf, size_t bsize)
 				break;
 			}
 		}
+#ifdef CONFIG_FPGA_PROG_FEEDBACK
 		putc ('\n');			/* terminate the dotted line */
+#endif
 
 		/*
 		 * Run the post configuration function if there is one.

Signature · 1 line

2.10.2

Michal Simek

2016-11-23 12:14 UTC #12 lore raw

RFC PATCH 4/7 fpga/spartan3: make output quieter

Quoted 24 lines · Chris Packham

Suppress some putc calls with CONFIG_SYS_FPGA_PROG_FEEDBACK.

Signed-off-by Chris Packham <[email protected]>

---

 drivers/fpga/spartan3.c | 4 ++++
 1 file changed, 4 insertions(+)

drivers/fpga/spartan3.c +2 -0

index 759ad95e2afc..34aa097ab6c2 100644
@@ -428,7 +428,9 @@ static int spartan3_ss_load(xilinx_desc *desc, const void *buf, size_t bsize)
 			CONFIG_FPGA_DELAY ();
 			(*fn->clk) (true, true, cookie);	/* Assert the clock pin */
 
+#ifdef CONFIG_FPGA_PROG_FEEDBACK
 			putc ('*');
+#endif
 
 			if (get_timer (ts) > CONFIG_SYS_FPGA_WAIT) {	/* check the time */
 				puts ("** Timeout waiting for DONE to clear.\n");

drivers/fpga/spartan3.c static int spartan3_ss_load(xilinx_desc *desc, const void *buf, size_t bsize) · line 446

Quoted 9 lines

drivers/fpga/spartan3.c +2 -0

@@ -436,7 +438,9 @@ static int spartan3_ss_load(xilinx_desc *desc, const void *buf, size_t bsize)
 				break;
 			}
 		}
+#ifdef CONFIG_FPGA_PROG_FEEDBACK
 		putc ('\n');			/* terminate the dotted line */
+#endif
 
 		/*
 		 * Run the post configuration function if there is one.

How does the output look like?

Thanks,
Michal

Signature · 14 lines

Michal Simek, Ing. (M.Eng), OpenPGP -> KeyID: FE3D1F91
w: www.monstr.eu p: +42-0-721842854
Maintainer of Linux kernel - Xilinx Microblaze
Maintainer of Linux kernel - Xilinx Zynq ARM and ZynqMP ARM64 SoCs
U-Boot custodian - Xilinx Microblaze/Zynq/ZynqMP SoCs


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Chris Packham

author

2016-11-22 08:49 UTC #13 lore raw

RFC PATCH 5/7 fpga: add Kconfig for CONFIG_FPGA_PROG_FEEDBACK

In reply to Chris Packham

Signed-off-by Chris Packham <[email protected]>

---

 drivers/fpga/Kconfig | 6 ++++++
 1 file changed, 6 insertions(+)

drivers/fpga/Kconfig +6 -0

index d137ab2df1d7..1b3b03c8f938 100644
@@ -28,4 +28,10 @@ config FPGA_SPARTAN2
 	depends on FPGA_XILINX
 	help
 	  Enable FPGA driver for Xilinx Spartan-II devices.
+
+config FPGA_PROG_FEEDBACK
+	bool "FPGA programming feedback"
+	help
+	  Enable printing of hash marks during FPGA configuration.
+
 endmenu

Signature · 1 line

2.10.2

Michal Simek

2016-11-23 12:13 UTC #14 lore raw

RFC PATCH 5/7 fpga: add Kconfig for CONFIG_FPGA_PROG_FEEDBACK

Quoted 12 lines · Chris Packham

Signed-off-by Chris Packham <[email protected]>
---
 drivers/fpga/Kconfig | 6 ++++++
 1 file changed, 6 insertions(+)
drivers/fpga/Kconfig +0 -0
index d137ab2df1d7..1b3b03c8f938 100644

drivers/fpga/Kconfig config FPGA_SPARTAN2 · line 37

Quoted 10 lines

drivers/fpga/Kconfig +6 -0

@@ -28,4 +28,10 @@ config FPGA_SPARTAN2
 	depends on FPGA_XILINX
 	help
 	  Enable FPGA driver for Xilinx Spartan-II devices.
+
+config FPGA_PROG_FEEDBACK
+	bool "FPGA programming feedback"
+	help
+	  Enable printing of hash marks during FPGA configuration.
+
 endmenu

I would prefer if you can add depends on here because this feature is not available on newer drivers.

It means you have to add some Kconfig things for cyclone.

Thanks,
Michal

Signature · 14 lines

Michal Simek, Ing. (M.Eng), OpenPGP -> KeyID: FE3D1F91
w: www.monstr.eu p: +42-0-721842854
Maintainer of Linux kernel - Xilinx Microblaze
Maintainer of Linux kernel - Xilinx Zynq ARM and ZynqMP ARM64 SoCs
U-Boot custodian - Xilinx Microblaze/Zynq/ZynqMP SoCs


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Chris Packham

author

2016-11-25 00:10 UTC #15 lore raw

RFC PATCH 5/7 fpga: add Kconfig for CONFIG_FPGA_PROG_FEEDBACK

Quoted 27 lines · Michal Simek

Quoted 12 lines · Chris Packham
Signed-off-by Chris Packham <[email protected]>
---
 drivers/fpga/Kconfig | 6 ++++++
 1 file changed, 6 insertions(+)
drivers/fpga/Kconfig +0 -0
index d137ab2df1d7..1b3b03c8f938 100644
drivers/fpga/Kconfig config FPGA_SPARTAN2 · line 37
Quoted 10 lines
drivers/fpga/Kconfig +6 -0
@@ -28,4 +28,10 @@ config FPGA_SPARTAN2
      depends on FPGA_XILINX
      help
        Enable FPGA driver for Xilinx Spartan-II devices.
+
+config FPGA_PROG_FEEDBACK
+     bool "FPGA programming feedback"
+     help
+       Enable printing of hash marks during FPGA configuration.
+
 endmenu
I would prefer if you can add depends on here because this feature is not available on newer drivers.

Quoted 1 line

It means you have to add some Kconfig things for cyclone.

Cyclone, virtex and ACEX1K. I'll see if can do it. Guess I need to start playing with buildman (and/or travis).

Quoted 13 lines

Thanks,
Michal
--
Michal Simek, Ing. (M.Eng), OpenPGP -> KeyID: FE3D1F91
w: www.monstr.eu p: +42-0-721842854
Maintainer of Linux kernel - Xilinx Microblaze Maintainer of Linux kernel - Xilinx Zynq ARM and ZynqMP ARM64 SoCs U-Boot custodian - Xilinx Microblaze/Zynq/ZynqMP SoCs

Michal Simek

2016-11-25 06:58 UTC #16 lore raw

RFC PATCH 5/7 fpga: add Kconfig for CONFIG_FPGA_PROG_FEEDBACK

Quoted 28 lines · Chris Packham

Quoted 27 lines · Michal Simek
Quoted 12 lines · Chris Packham
Signed-off-by Chris Packham <[email protected]>
---
 drivers/fpga/Kconfig | 6 ++++++
 1 file changed, 6 insertions(+)
drivers/fpga/Kconfig +0 -0
index d137ab2df1d7..1b3b03c8f938 100644
drivers/fpga/Kconfig config FPGA_SPARTAN2 · line 37
Quoted 10 lines
drivers/fpga/Kconfig +6 -0
@@ -28,4 +28,10 @@ config FPGA_SPARTAN2
      depends on FPGA_XILINX
      help
        Enable FPGA driver for Xilinx Spartan-II devices.
+
+config FPGA_PROG_FEEDBACK
+     bool "FPGA programming feedback"
+     help
+       Enable printing of hash marks during FPGA configuration.
+
 endmenu
I would prefer if you can add depends on here because this feature is not available on newer drivers.

Quoted 4 lines

Quoted 1 line
It means you have to add some Kconfig things for cyclone.
Cyclone, virtex and ACEX1K. I'll see if can do it. Guess I need to start playing with buildman (and/or travis).

I was playing with travis recently and it is easy to use too. You can use it but for start buildman running on your PC should be fine.

Thanks,
Michal

Chris Packham

author

2016-11-22 08:49 UTC #17 lore raw

RFC PATCH 6/7 Move FPGA_PROG_FEEDBACK to defconfig

In reply to Chris Packham

Signed-off-by Chris Packham <[email protected]>

---

 configs/apf27_defconfig          | 1 +
 configs/astro_mcf5373l_defconfig | 1 +
 configs/mt_ventoux_defconfig     | 1 +
 include/configs/apf27.h          | 1 -
 include/configs/astro_mcf5373l.h | 1 -
 include/configs/mt_ventoux.h     | 2 --
 6 files changed, 3 insertions(+), 4 deletions(-)

configs/apf27_defconfig +1 -0

index f8f177ad56ce..4e0810a2064f 100644
@@ -23,4 +23,5 @@ CONFIG_CMD_FAT=y
 CONFIG_CMD_UBI=y
 CONFIG_FPGA_XILINX=y
 CONFIG_FPGA_SPARTAN3=y
+CONFIG_FPGA_PROG_FEEDBACK=y
 CONFIG_OF_LIBFDT=y

configs/astro_mcf5373l_defconfig +1 -0

index 5ea1b66e5b2a..188a2ae6d0b7 100644
@@ -11,3 +11,4 @@ CONFIG_CMD_I2C=y
 CONFIG_CMD_CACHE=y
 CONFIG_FPGA_XILINX=y
 CONFIG_FPGA_SPARTAN3=y
+CONFIG_FPGA_PROG_FEEDBACK=y

configs/mt_ventoux_defconfig +1 -0

index d4e58395cf22..10e5ebc20945 100644
@@ -26,6 +26,7 @@ CONFIG_CMD_FAT=y
 CONFIG_CMD_UBI=y
 CONFIG_FPGA_XILINX=y
 CONFIG_FPGA_SPARTAN3=y
+CONFIG_FPGA_PROG_FEEDBACK=y
 CONFIG_SYS_NS16550=y
 CONFIG_USB=y
 CONFIG_USB_ULPI_VIEWPORT_OMAP=y

include/configs/apf27.h +0 -1

index 00798fa1027f..df0dde0cdcd2 100644
@@ -262,7 +262,6 @@
  */
 #define CONFIG_FPGA_COUNT		1
 #define CONFIG_SYS_FPGA_WAIT		250 /* 250 ms */
-#define CONFIG_FPGA_PROG_FEEDBACK
 #define CONFIG_SYS_FPGA_CHECK_CTRLC
 #define CONFIG_SYS_FPGA_CHECK_ERROR

include/configs/astro_mcf5373l.h +0 -1

index d5d6540ec9b9..e5eaec238af7 100644
@@ -206,7 +206,6 @@
 #define CONFIG_FPGA_COUNT	1
 #define CONFIG_FPGA_ALTERA
 #define CONFIG_FPGA_CYCLON2
-#define CONFIG_FPGA_PROG_FEEDBACK
 #define CONFIG_SYS_FPGA_WAIT		1000
 
 /* End of user parameters to be customized */

include/configs/mt_ventoux.h +0 -2

index b6198dbdf6d3..97fe785ef957 100644
@@ -42,11 +42,9 @@
  * FPGA
  */
 #define CONFIG_CMD_FPGA_LOADMK
-#define CONFIG_FPGA_PROG_FEEDBACK
 #define CONFIG_SYS_FPGA_WAIT	10000
 #define CONFIG_MAX_FPGA_DEVICES	1
 #define CONFIG_FPGA_DELAY() udelay(1)
-#define CONFIG_FPGA_PROG_FEEDBACK
 
 #define CONFIG_SPLASH_SCREEN
 #define CONFIG_VIDEO_BMP_RLE8

Signature · 1 line

2.10.2

Michal Simek

2016-11-23 12:16 UTC #18 lore raw

RFC PATCH 6/7 Move FPGA_PROG_FEEDBACK to defconfig

Please put some description here.

Thanks,
Michal

Quoted 83 lines · Chris Packham

Signed-off-by Chris Packham <[email protected]>

---

 configs/apf27_defconfig          | 1 +
 configs/astro_mcf5373l_defconfig | 1 +
 configs/mt_ventoux_defconfig     | 1 +
 include/configs/apf27.h          | 1 -
 include/configs/astro_mcf5373l.h | 1 -
 include/configs/mt_ventoux.h     | 2 --
 6 files changed, 3 insertions(+), 4 deletions(-)

configs/apf27_defconfig +1 -0

index f8f177ad56ce..4e0810a2064f 100644
@@ -23,4 +23,5 @@ CONFIG_CMD_FAT=y
 CONFIG_CMD_UBI=y
 CONFIG_FPGA_XILINX=y
 CONFIG_FPGA_SPARTAN3=y
+CONFIG_FPGA_PROG_FEEDBACK=y
 CONFIG_OF_LIBFDT=y

configs/astro_mcf5373l_defconfig +1 -0

index 5ea1b66e5b2a..188a2ae6d0b7 100644
@@ -11,3 +11,4 @@ CONFIG_CMD_I2C=y
 CONFIG_CMD_CACHE=y
 CONFIG_FPGA_XILINX=y
 CONFIG_FPGA_SPARTAN3=y
+CONFIG_FPGA_PROG_FEEDBACK=y

configs/mt_ventoux_defconfig +1 -0

index d4e58395cf22..10e5ebc20945 100644
@@ -26,6 +26,7 @@ CONFIG_CMD_FAT=y
 CONFIG_CMD_UBI=y
 CONFIG_FPGA_XILINX=y
 CONFIG_FPGA_SPARTAN3=y
+CONFIG_FPGA_PROG_FEEDBACK=y
 CONFIG_SYS_NS16550=y
 CONFIG_USB=y
 CONFIG_USB_ULPI_VIEWPORT_OMAP=y

include/configs/apf27.h +0 -1

index 00798fa1027f..df0dde0cdcd2 100644
@@ -262,7 +262,6 @@
  */
 #define CONFIG_FPGA_COUNT		1
 #define CONFIG_SYS_FPGA_WAIT		250 /* 250 ms */
-#define CONFIG_FPGA_PROG_FEEDBACK
 #define CONFIG_SYS_FPGA_CHECK_CTRLC
 #define CONFIG_SYS_FPGA_CHECK_ERROR

include/configs/astro_mcf5373l.h +0 -1

index d5d6540ec9b9..e5eaec238af7 100644
@@ -206,7 +206,6 @@
 #define CONFIG_FPGA_COUNT	1
 #define CONFIG_FPGA_ALTERA
 #define CONFIG_FPGA_CYCLON2
-#define CONFIG_FPGA_PROG_FEEDBACK
 #define CONFIG_SYS_FPGA_WAIT		1000
 
 /* End of user parameters to be customized */

include/configs/mt_ventoux.h +0 -2

index b6198dbdf6d3..97fe785ef957 100644
@@ -42,11 +42,9 @@
  * FPGA
  */
 #define CONFIG_CMD_FPGA_LOADMK
-#define CONFIG_FPGA_PROG_FEEDBACK
 #define CONFIG_SYS_FPGA_WAIT	10000
 #define CONFIG_MAX_FPGA_DEVICES	1
 #define CONFIG_FPGA_DELAY() udelay(1)
-#define CONFIG_FPGA_PROG_FEEDBACK
 
 #define CONFIG_SPLASH_SCREEN
 #define CONFIG_VIDEO_BMP_RLE8

Signature · 14 lines

Michal Simek, Ing. (M.Eng), OpenPGP -> KeyID: FE3D1F91
w: www.monstr.eu p: +42-0-721842854
Maintainer of Linux kernel - Xilinx Microblaze
Maintainer of Linux kernel - Xilinx Zynq ARM and ZynqMP ARM64 SoCs
U-Boot custodian - Xilinx Microblaze/Zynq/ZynqMP SoCs


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Chris Packham

author

2016-11-22 08:49 UTC #19 lore raw

RFC PATCH 7/7 fpga/spartan3: add reverse bitstream mode

In reply to Chris Packham

The Xilinx tools we use appear to give us a bitstream with the bits reversed (compared to what the existing code expects) add a new CONFIG_FPGA_REVERSE_BITSTREAM option which tells the spartan3 driver to output the serial stream with the leftmost bit first.

Signed-off-by Chris Packham <[email protected]>

---

 drivers/fpga/Kconfig    | 7 +++++++
 drivers/fpga/spartan3.c | 8 ++++++++
 2 files changed, 15 insertions(+)

drivers/fpga/Kconfig +7 -0

index 1b3b03c8f938..26b7c864d275 100644
@@ -29,6 +29,13 @@ config FPGA_SPARTAN2
 	help
 	  Enable FPGA driver for Xilinx Spartan-II devices.
 
+config FPGA_REVERSE_BITSTREAM
+	bool "Reverse bitstream when programming"
+	depends on FPGA_SPARTAN3
+	help
+	  Some Xilinx tools generate programs that need to be uploaded LSb
+	  first. Set this option if your fpga binary requires this.
+
 config FPGA_PROG_FEEDBACK
 	bool "FPGA programming feedback"
 	help

drivers/fpga/spartan3.c +8 -0

index 34aa097ab6c2..2a57c8ab77b5 100644
@@ -392,12 +392,20 @@ static int spartan3_ss_load(xilinx_desc *desc, const void *buf, size_t bsize)
 					(*fn->clk) (false, true, cookie);
 					CONFIG_FPGA_DELAY ();
 					/* Write data */
+#ifdef CONFIG_FPGA_REVERSE_BITSTREAM
+					(*fn->wr) ((val & 0x01), true, cookie);
+#else
 					(*fn->wr) ((val & 0x80), true, cookie);
+#endif
 					CONFIG_FPGA_DELAY ();
 					/* Assert the clock */
 					(*fn->clk) (true, true, cookie);
 					CONFIG_FPGA_DELAY ();
+#ifdef CONFIG_FPGA_REVERSE_BITSTREAM
+					val >>= 1;
+#else
 					val <<= 1;
+#endif
 					i --;
 				} while (i > 0);

Signature · 1 line

2.10.2

Michal Simek

2016-11-23 12:16 UTC #20 lore raw

RFC PATCH 7/7 fpga/spartan3: add reverse bitstream mode

Quoted 17 lines · Chris Packham

The Xilinx tools we use appear to give us a bitstream with the bits reversed (compared to what the existing code expects) add a new CONFIG_FPGA_REVERSE_BITSTREAM option which tells the spartan3 driver to output the serial stream with the leftmost bit first.
Signed-off-by Chris Packham <[email protected]>
---
 drivers/fpga/Kconfig    | 7 +++++++
 drivers/fpga/spartan3.c | 8 ++++++++
 2 files changed, 15 insertions(+)
drivers/fpga/Kconfig +0 -0
index 1b3b03c8f938..26b7c864d275 100644

drivers/fpga/Kconfig config FPGA_SPARTAN2 · line 37

Quoted 9 lines

drivers/fpga/Kconfig +6 -0

@@ -29,6 +29,13 @@ config FPGA_SPARTAN2
 	help
 	  Enable FPGA driver for Xilinx Spartan-II devices.
 
+config FPGA_REVERSE_BITSTREAM
+	bool "Reverse bitstream when programming"
+	depends on FPGA_SPARTAN3
+	help
+	  Some Xilinx tools generate programs that need to be uploaded LSb
+	  first. Set this option if your fpga binary requires this.

I am not aware about that option because this is pretty ancient. Isn't there just a flag somewhere?

Quoted 20 lines

drivers/fpga/Kconfig +1 -0

+
 config FPGA_PROG_FEEDBACK
 	bool "FPGA programming feedback"
 	help

drivers/fpga/spartan3.c +4 -0

index 34aa097ab6c2..2a57c8ab77b5 100644
@@ -392,12 +392,20 @@ static int spartan3_ss_load(xilinx_desc *desc, const void *buf, size_t bsize)
 					(*fn->clk) (false, true, cookie);
 					CONFIG_FPGA_DELAY ();
 					/* Write data */
+#ifdef CONFIG_FPGA_REVERSE_BITSTREAM
+					(*fn->wr) ((val & 0x01), true, cookie);
+#else
 					(*fn->wr) ((val & 0x80), true, cookie);
+#endif
 					CONFIG_FPGA_DELAY ();
 					/* Assert the clock */

drivers/fpga/spartan3.c static int spartan3_ss_load(xilinx_desc *desc, const void *buf, size_t bsize) · line 411

Quoted 10 lines

drivers/fpga/spartan3.c +4 -0

 					(*fn->clk) (true, true, cookie);
 					CONFIG_FPGA_DELAY ();
+#ifdef CONFIG_FPGA_REVERSE_BITSTREAM
+					val >>= 1;
+#else
 					val <<= 1;
+#endif
 					i --;
 				} while (i > 0);

Acked-by Michal Simek <[email protected]>

Thanks,
Michal

Signature · 14 lines

Michal Simek, Ing. (M.Eng), OpenPGP -> KeyID: FE3D1F91
w: www.monstr.eu p: +42-0-721842854
Maintainer of Linux kernel - Xilinx Microblaze
Maintainer of Linux kernel - Xilinx Zynq ARM and ZynqMP ARM64 SoCs
U-Boot custodian - Xilinx Microblaze/Zynq/ZynqMP SoCs


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